TW200529712A - Fabricating process of circuit board with embedded passive component - Google Patents

Abstract

A fabricating process of circuit board with embedded passive component is described. The process comprises few steps. First, a conductive layer including a first surface and a second surface opposing to the first surface is provided. Moreover, the conductive layer has first through holes, which are passing through the conductive layer, respectively. At least one material layer is forming on the first surface. A multi-layer circuit unit including second through holes is provided, and the locations of the second through holes are corresponding to the locations of the first through holes, respectively. The conductive layer and the multi-layer circuit unit are orientating with each other by the first through holes and the second through holes, while the first surface of the conductive layer is facing a surface of the multi-layer circuit unit, and the material layer is between the multi-layer circuit unit and the conductive layer. The conductive layer is laminated to the multi-layer circuit unit. The conductive layer is patterning to form a conductive pattern.

Description

200529712 V. Description of the invention (1) * [Technical field to which the invention belongs] The present invention relates to a circuit board manufacturing process, and more particularly to a circuit board manufacturing method with embedded passive components. [Previous technology] The integration level of electronic products is getting higher and higher. For circuit boards used in high-integration electronic products, the circuit layer is also changed from a single layer to two layers to six layers and eight layers. Layer, or even more than 10 layers, so that the electronic elements can be installed on the printed circuit board later. Generally speaking, the most common field is the lamination process. When using FH Field Gas > v *. To print f ^ bits ί ^ to make circuit boards, each circuit layer and insulation layer The alignment between ς 2 must be well controlled. Therefore, a number of alignment marks or two layers of lines are formed on the insulation layer where each circuit layer is located on the circuit board process number = ^: some alignment marks are used to locate these insulation layers and one of their surfaces i:] : Then, these insulation layers and these circuit layers are laminated to make the product. 9 No insulation layer becomes a semi-processed section of a multilayer circuit board or circuit board; exhausted! 1B, which is made of a conventional multilayer printed circuit board and an inner layer substrate. Please refer to FIG. 1A. First, an inner layer substrate 10, 16 is provided. Two edges: 二 η edge layer 12, two circuit layers 14 and -alignment. The mark alignment marks are arranged on both surfaces of the insulating layer 12 and on both surfaces of the board. Then, the inner substrate-the substrate 20-the first substrate 20 and the second substrate 30-and the first and second substrates 30 have insulating layers 22 and 32 and the circuit layer 24 respectively.

200529712 V. Description of the invention (2) and 34 and the first registration mark 26 and the second registration mark 36 (the registration mark 16, the first registration mark 26 and the second registration mark 3 6 Shown in the shape area), and the circuit layer 24 and the first alignment mark 26 are arranged on one surface of the first substrate 20, and the circuit layer 34 and the second alignment mark 36 are arranged on the second One of the substrates 30 is on the surface. Thereafter, the X-ray and the alignment mark 16 of the inner substrate 10, the first alignment mark 26 of the first substrate 20 and the second alignment mark 36 of the second substrate 30 complete the inner substrate 10, the first substrate 20, and An alignment step of the second substrate 30. Referring to FIG. 1B, the inner substrate 10, the first substrate 20, and the second substrate 30 that have been aligned are thermally pressed and cured to form a multilayer printed circuit board or a semi-finished printed circuit board. It is worth mentioning that the registration mark 16, the first registration mark 26 and the second registration mark 36 are all formed by printing with ink, so the registration mark 16 and the circuit layer 14 and the first A pair of bit marks 26 and the line layer 24, and a second bit mark 36 and the line layer 34 each have a pair of bit errors. When using X-rays and alignment marks 16, 6, first alignment marks 26, and second alignment marks 36 to perform the alignment process of the inner substrate 10, the first substrate 20, and the second substrate 30 (such as As shown by the circular area in FIG. 1B), the registration errors generated by the above-mentioned registration marks will continuously accumulate. If the number of circuit layers on the circuit board increases, the accumulated errors of the alignment marks on these substrates with the circuit layer will increase by 0. In addition, as the number of circuit board layers increases, the electrical properties of the circuit board (such as RC delay) Effect) also gradually decreased, so passive components must be added to the circuit board to improve the electrical properties of the circuit board. However, normalized passive components with specific electrical values may not fully meet specific circuit design requirements.

12914twf.ptd Page 8 200529712 V. Description of the invention (3) design, so passive components can be made directly inside the circuit board. Therefore, the passive components inside the circuit board can be selected according to the wiring design and material selection of the circuit board. Wait to adjust the electrical value of the circuit board. [Summary of the Invention] In view of this, the object of the present invention is to provide a circuit board manufacturing process with embedded passive components to increase the alignment accuracy of a multilayer circuit board. Based on the foregoing or other objectives, the present invention provides a circuit board manufacturing process with embedded passive components, which includes, for example, the following steps. First, a conductive layer is provided, which has, for example, a first surface and a corresponding second surface, wherein the first surface has at least one element region, and the conductive layer further has a plurality of first through holes, respectively. Conductive layer. Then, at least one material layer is formed on the element area of the first surface. Thereafter, a multilayer circuit unit is provided, which has, for example, a plurality of second through holes, the positions of which correspond to the positions of the first through holes, respectively. The first through holes and the second through holes are used to locate the conductive layer and the multilayer circuit unit. The first side of the conductive layer faces a surface of the multilayer circuit unit, and the material layer is located between the multilayer circuit unit and the conductive layer. . Then, the conductive layer is laminated to the multilayer circuit unit. Finally, the conductive layer is patterned to form a first conductive pattern. According to the manufacturing process of the circuit board with the embedded passive device according to the preferred embodiment of the present invention, the conductive layer is, for example, a copper box layer (c 0 p p r r f 0 i 1). According to the manufacturing process of the circuit board with embedded passive components according to the preferred embodiment of the present invention, the above-mentioned method for forming the material layer includes, for example, screen printing. Of passive components

12914twf.ptd Page 9 200529712 V. Description of the invention (4) For the circuit board process, for example, the first conductive pattern has a first electrode and a second electrode electrically isolated from each other, which are respectively connected to the material layer, and the material The material of the layer includes, for example, a capacitor material. According to the manufacturing process of the circuit board with the embedded passive device according to the preferred embodiment of the present invention, after the step of forming the material layer, for example, the method further includes forming at least a first electrode layer on the material layer and the device region, and The first conductive pattern further has, for example, a first electrode and a second electrode, wherein the first electrode system is connected to the electrode layer, and at least part of the electrode layer and at least part of the second electrode system overlap each other, and the material of the material layer is, for example, Including dielectric materials. The method of forming the electrode layer includes, for example, screen printing. According to the process for manufacturing a circuit board with embedded passive components according to a preferred embodiment of the present invention, the above-mentioned multilayer circuit unit has, for example, a second conductive pattern, which is disposed on the surface of the multilayer circuit unit, and the conductive layer is laminated to The step of the multilayer circuit unit further includes, for example, providing an insulating layer, disposing the insulating layer between the conductive layer and the multilayer circuit unit, and pressing the conductive layer to the surface of the multilayer circuit unit through the insulating layer. In addition, the insulating layer is, for example, a prepreg. Based on the above, the manufacturing process of the circuit board with embedded passive components of the present invention directly uses the first through hole as the first electrode and a second electrode for alignment during screen printing, and directly uses the through hole during lamination. Holes are used as alignment marks of each layer to perform the alignment process of each layer. Therefore, the present invention can reduce the accumulation of alignment errors caused by the alignment marks in each layer. In addition, the present invention can also manufacture embedded resistance elements, inductance elements or capacitor elements to meet the circuit design of the circuit board.

12914twf.ptd Page 10 200529712 V. Description of the invention (5) > In order to make the above and other objects, features and advantages of the present invention more comprehensible, 'a preferred embodiment is given below, in conjunction with the accompanying drawings As detailed below. '[Embodiment] Please refer to FIG. 2A to FIG. 2E, which are schematic cross-sectional views showing a manufacturing process of a circuit board with embedded passive components according to a preferred embodiment of the present invention. Please refer to FIG. 2A # First, a conductive layer 110 is provided, and the conductive layer 110 has, for example, a plurality of first through holes 110d, a first surface 110a, and a corresponding second surface 110b. The first surface n0a has, for example, At least one device region 110c, and the first beaker holes 110d pass through the conductive layer, respectively. Then, at least one material layer is formed on the device region 110c of the first surface 110a (as shown in FIG. 2B). ί 罝 罝 Twenty-one / dagger layer circuit unit 130 (as shown in the figure), and the multi-layer through hole 1 301 is better than eight * There are multiple second through holes 13〇a, of which these two are worth one The enhancement β does not correspond to the positions of the first through holes 110d. In this example, one surface 13015 of the circuit unit 130 between the first through hole 110d and the 8th layer is placed between the conductive layer 1 10 and the multilayer circuit unit 130, and the side 110a is Facing between the multilayer units 130. In turn, the pressure-conducting material layer 120 is located on a multilayer circuit (as shown in FIG. 2D). Finally, the graph is shown in FIG. 10 to the multilayer circuit unit. The 30th conductive pattern H2 (as shown in FIG. 2E) is formed to form the conductive layer 110. 凊 Continue to refer to FIG. 2E to complete the first hole 1 30a. Positioning methods such as through holes n and this second system. Compared to the counterpoint of the conventional technology? Lu fguang or other image positioning system τ m ‘now (as shown in Figure 丨 β), this implementation

200529712 V. Description of the invention (6) ------ For example, the first through hole l10d and the second through hole i3〇a ^^ ^ ^ ^ ί = accumulation of bismuth difference. In addition, the conductive layer 110 is, for example, a copper or other conductive material layer, and the element area 110 c is, for example, a configuration area of a passive component. It is worth noting that the forming material 〇

Methods such as screen printing. The multilayer wiring unit 13 is, for example, a semi-finished product of a printed circuit board. In addition, the method of forming the first through-holes is, for example, mechanical drilling (laser drilling) or laser drilling, and the method of forming the material layer 12 is, for example, screen printing, screen printing = to The first through-holes 11 Od are screen-printing counter-holes. Prior to the press-alignment process, these second through-holes 130 a have been formed in the multilayer circuit 130 ′ and a plated metal layer can be formed therein (not shown) Makes this the first

The through hole 130a can be electrically connected to at least two circuit layers (not shown) located inside the multi-layer wire unit. π υ ϋ U Please refer to FIG. 3 ′, which is a schematic cross-sectional view illustrating a process of manufacturing a circuit board of a passive passive device according to a preferred embodiment of the present invention. In this figure, the content of 2C is similar. The difference lies in the multilayer circuit in this figure. If it has a second conductive pattern 132, it is arranged on the surface 130b of the multilayer circuit unit 13o, and the conductive layer 11 is laminated to In the step of the multilayer circuit unit 130, for example, it further includes providing an insulating layer 140, and disposing the insulating layer 140 between the conductive layer 110 and the multilayer circuit unit 130, and then the conductive layer 1 110. It is pressed onto the surface of the multilayer circuit unit 130 via the insulating layer 140 (301). It is worth noting that, in the step of laminating, this embodiment also uses the first through hole 110 d and the corresponding second through hole 130 a to locate the conductive layer 11 and the multilayer wire stomach.

12914twf.ptd

Page 12 V. Description of the invention (7) Relative position between the road units 130. In addition, J11 ° C in this figure is a resistive, inductive, or capacitive element area, for example. ❹ Jun0 Please refer to FIG. 4 ′, which illustrates a schematic cross-sectional view of a resistive element applied in accordance with the preferred solid board manufacturing process of the present invention. . The inner valley in this figure intersects with Figure 2E; heart, sweet. The-conductive pattern H2 is more similar, for example, is it different from the first place? 9 lies in:-the first lead U 2a and mutual electrical properties in this figure = .., Yi's first wires 1 1 2b, which are respectively connected to the material layer i 3〇. The material of the material layer 120 includes, for example, a resistive material. Therefore, the lead, the f-line, and the material layer 120 can be formed-the resistance element can form an inductive element and the same principle is used for the inductive material, which has: m5 #! To Fig. 5B 'which shows that according to the present invention, The best example is shown in the F1 field f circuit board process applied to the cross-section of the capacitive element; i two examples are similar 'The difference is that after the shape of the material, it includes at least-the electrode layer 150 Figure 5B] Area U ° C (as shown in Figure 5A). Please refer to Β the first conductive pattern 112 has, for example, a first second electrode 1 12b and sends a snow trick! t 9 # 士 Λ ^ and at least Qiu Bazhi;; = the first electrode 112a is connected to the electrode layer 150, mutual weight 22L; layer 15 0 and at least part of the second electrode 1 1 2 b is a material example : Including the material with a capacitance layer of 12 ° and the material layer 12 ° includes the grid second power; the first power d; the method of the layer 150 * Therefore, the thunder is invalidated. ^ The first through hole H 〇d is the screen printing registration hole. . °, (first electrode 112a, second electrode 1121) and materials

200529712 V. Description of the invention (8) Layer 1 2 0 can form a capacitor. In summary, the process of the present invention has the following advantages: 1. Compared with the electrical through-holes with embedded passive components adopted in the conventional technology as the alignment marks of the various layers, the embedded type of the present invention has the embedded type. Accumulation of passive component errors. 2. The embedded electrical parts of the present invention are embedded to conform to the circuit design of the circuit board. 3. To form a resistance element, inductance element or electrical printing on the embedded resistance element, first drill ( First through-hole) After completing the first through-hole, it is used as the accumulation of circuit bit errors with embedded passive components in each screen. Therefore, the present invention reduces the manufacturing cost of the printed circuit board. Although the present invention has been limited by the preferred implementation, anyone familiar with this technique and scope can make a few changes when considering the alignment marks used in the patented scope of the embedded passive component circuit board. Method, the board layout process directly uses the alignment process of each layer on each layer, so the circuit board process can reduce the process of aligning passive components, and the circuit board process can be more resistive, inductive or capacitive, or inductive or capacitive. In the device, the method of accommodating the material layer of the device is the screen printing method, that is, the printed alignment holes have been drilled before the screen printing. Therefore, the board process of the present invention can reduce the screen printing pair and can reduce the embedded passive components. As above, however, it is not intended to be used without departing from the spirit and decoration of the present invention, so what is defined by the protection of the present invention shall prevail.

12914twf.ptd Page 14 200529712 Brief Description of Drawings Figures 1A to 1B are schematic cross-sectional views of a conventional multilayer printed circuit board manufacturing process. 2A to 2E are schematic cross-sectional views illustrating a process of manufacturing a circuit board with an embedded passive component according to a preferred embodiment of the present invention. FIG. 3 is a schematic cross-sectional view of a circuit board manufacturing process with embedded passive components according to a preferred embodiment of the present invention. FIG. 4 is a schematic cross-sectional view illustrating a process of applying a circuit board process with embedded passive elements to a resistive element according to a preferred embodiment of the present invention. 5A to 5B are schematic cross-sectional views showing a process of applying a circuit board with embedded passive elements to a capacitor element according to a preferred embodiment of the present invention. [Illustration of Graphical Indications] 1 0: Inner substrate 12, 2 2, 3 2, 4 0, 1 4 0: Insulating layer 1 4, 2 4, 3 4: Circuit layer 1 6: Registration mark 2 0: First Substrate 2 6: First alignment mark 3 0: Second substrate 3 6: Second alignment mark 1 1 0: Conductive layer 1 1 0 a · First surface 1 1 Ob: Second surface 1 1 0 c: Element area 1 1 0 d: first through hole

12914twf.ptd Page 15 200529712 Brief description of the drawings 1 1 2: First conductive pattern 1 1 2 a: First electrode 1 1 2 b: Second electrode 1 2 0: Material layer 1 3 0: Multilayer circuit unit 1 32 : Second conductive pattern 1 3 0 a: second through hole 1 3 0 b: surface 1 5 0: electrode layer

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Claims (1)

200529712 6. Scope of patent application 1. A circuit board manufacturing process with embedded passive components, including: providing a conductive layer having a first surface and a corresponding second surface, wherein the first surface has at least one component area Moreover, the conductive layer further has a plurality of first through holes, which respectively penetrate the conductive layer. The production method is, for example, screen printing, and the method of drilling first and then printing is adopted, that is, the first through-hole is drilled before screen printing, as the registration hole of each layer of screen printing, and the screen printing process is sequentially completed; forming at least one material layer On the element area of the first side; providing a multi-layer circuit unit having a plurality of second through holes, the positions of which correspond to the positions of the first through holes respectively; via the first through holes and The conductive layer and the multilayer circuit unit are positioned corresponding to the second through holes, and the first side of the conductive layer faces a surface of the multilayer circuit unit, and the material layer is located between the multilayer circuit unit and the multilayer circuit unit. Between the conductive layers; laminating the conductive layer to the multilayer circuit unit; and patterning the conductive layer to form a first conductive pattern. 2. The process for manufacturing a circuit board with an embedded passive component as described in item 1 of the scope of the patent application, wherein the conductive layer is a copper foil layer. 3. The circuit board process with embedded passive components as described in item 1 of the scope of patent application, wherein the method of forming the material layer includes screen printing. 4. The process for manufacturing a circuit board with an embedded passive component as described in item 1 of the scope of the patent application, wherein the first conductive pattern further has a first electrode and a second electrode electrically isolated from each other, which are respectively connected to The material layer, and the material of the material layer includes a resistive material. 5. With embedded passive components as described in item 1 of the scope of patent application 12914twf.ptd Page 17 200529712 VI. Patented circuit board process, wherein after the step of forming the material layer, it further includes forming at least one electrode layer on the material layer and the element area, and the first conductive pattern It further has a first electrode and a second electrode, wherein the first electrode system is connected to the electrode layer, and at least part of the electrode layer and at least part of the second electrode system are mutually enriched, and the material of the material layer Including dielectric materials. 6. The circuit board process with embedded passive components as described in item 5 of the scope of patent application, wherein the method of forming the electrode layer includes screen printing. 7. The process for manufacturing a circuit board with an embedded passive component as described in item 1 of the scope of the patent application, wherein the multilayer circuit unit has a second conductive pattern, which is disposed on the surface of the multilayer circuit unit and is laminated. The step from the conductive layer to the multilayer circuit unit further includes providing an insulating layer, disposing the insulating layer between the conductive layer and the multilayer circuit unit, and pressing the conductive layer to the conductive layer via the insulating layer. The surface of the multilayer circuit unit. 8. The process for manufacturing a circuit board with an embedded passive component as described in item 7 of the scope of patent application, wherein the insulating layer is a semi-cured resin sheet. 12914twf.ptd Page 18