TW201508954A - Optoelectronic semiconductor device and fabricating method thereof - Google Patents

Abstract

An optoelectronic semiconductor device comprises a substrate, a first solid via plug, an optoelectronic semiconductor chip, a phosphor layer and a molding body. The first solid via plug penetrates through the substrate. The optoelectronic semiconductor chip has a first electrode aligned to and electrically connected with the first solid via plug. The phosphor layer is coated on at least one surface of the optoelectronic semiconductor chip. The molding body encapsulates the substrate, the optoelectronic semiconductor chip and the phosphor layer.

Description

Photoelectric semiconductor component and manufacturing method thereof

The present invention relates to a semiconductor package structure and a method of fabricating the same, and more particularly to an optoelectronic semiconductor component and a method of fabricating the same.

The light-emitting semiconductor element has good photoelectric characteristics such as low power consumption, low heat generation, long operating life, impact resistance, small volume, fast reaction speed, no mercury, and color light which can emit stable wavelength. With the advancement of photoelectric technology, it has been One of the better choices for new generation light sources.

For example, a white light emitting diode (LED) component is conventionally used in a package design in which wire bonding is performed for wire bonding. However, due to limitations in the wire bonding process, the wire bonding distance must be reserved between the wafer and the wafer, which not only causes a large increase in the size of the package structure, but also limits the number of wafer matrix structures, which is disadvantageous for miniaturization of components. Furthermore, when a wafer matrix is used for multi-chip packaging, since the wafer arrangement is relatively dispersed, it is more likely to affect the uniformity of the coating of the phosphor layer, which not only causes a problem that the yield of the subsequent processing of the component is low, but also because of the fluorescence. The layer is mixed unevenly, causing problems of polarized or color cast of the white light emitting diode element.

Therefore, there is a need to provide an advanced optoelectronic semiconductor chip package structure and a method of fabricating the same that solves the problems faced by the prior art.

One aspect of the present invention is to provide an optoelectronic semiconductor component, including a substrate Materials, first solid via plugs, optoelectronic semiconductor wafers, phosphor layers, and encapsulants. Wherein, the first solid interlayer plug penetrates the substrate. The optoelectronic semiconductor wafer has a first electrode that is aligned and in electrical contact with the first solid via plug. The phosphor layer covers at least one surface of the optoelectronic semiconductor wafer. The encapsulant encapsulates the substrate, the optoelectronic semiconductor wafer, and the phosphor layer.

In an embodiment of the invention, the optoelectronic semiconductor component further comprises: a first patterned metal layer on the first surface of the substrate, and a second patterned metal layer on the second surface of the substrate. Wherein the second surface is on the opposite side of the substrate relative to the first surface. a first patterned metal layer having at least one first pad aligned and directly in contact with the first solid via plug; the second patterned metal layer having at least one second pad aligned and aligned A solid via plug is in direct contact.

In an embodiment of the invention, the first electrode is via the first pad The first solid via plug is electrically connected.

In an embodiment of the invention, the optoelectronic semiconductor component further comprises: The substrate is bonded to a carrier substrate, and the substrate, the LED wafer, and the phosphor layer are separated from the outside air by the carrier substrate and the encapsulant.

In an embodiment of the invention, the carrier substrate has a straight line with the second pad Contact the metal line.

In an embodiment of the invention, the optoelectronic semiconductor component further comprises: A second solid via plug of the substrate is aligned and in electrical contact with the second electrode of the optoelectronic semiconductor wafer.

Another aspect of the present invention is to provide an optoelectronic semiconductor component The method comprises the steps of first providing a substrate and a first solid via plug extending through the substrate. Next, the first electrode of the optoelectronic semiconductor wafer is aligned and in electrical contact with the first solid via plug. Then, coating the phosphor on at least one surface of the optoelectronic semiconductor wafer Floor. Subsequently, the substrate, the light-emitting semiconductor wafer, and the phosphor layer are coated with a sealant.

In an embodiment of the invention, a substrate and a first solid interlayer are provided The step of plugging further includes: forming a first patterned metal layer having at least one first pad on the first surface of the substrate, aligning the first pad and directly interfacing with the first solid via Contacting; and forming a second patterned metal layer having at least one second pad on the second surface of the substrate, aligned and in direct contact with the first solid via plug, wherein the second surface is on the substrate The opposite side of the first surface.

In an embodiment of the invention, a substrate and a first solid interlayer are provided The plugging step is further included on the first patterned metal layer to form a patterned insulating layer to expose the first bonding pad.

In an embodiment of the invention, the first electricity of the optoelectronic semiconductor wafer The step of aligning and electrically contacting the first solid via plug includes using a solder ball to connect the first electrode to the first pad.

In an embodiment of the invention, a method of fabricating an optoelectronic semiconductor component The method further includes bonding a carrier substrate to the substrate and electrically connecting the second pad to the metal line of the carrier substrate.

In an embodiment of the invention, the step of bonding the carrier substrate to the substrate The method includes using a solder ball to connect the metal line of the carrier substrate with the second pad.

In an embodiment of the invention, the encapsulant is coated on the substrate, and the photoelectric half The step of the conductor wafer and the phosphor layer includes covering the substrate, the optoelectronic semiconductor wafer, the phosphor layer, and a portion of the carrier substrate with the encapsulant, thereby isolating the substrate, the optoelectronic semiconductor wafer, and the phosphor layer from the outside air.

In an embodiment of the invention, a method of fabricating an optoelectronic semiconductor component Furthermore, a second solid via plug is provided through the substrate such that at least one second electrode of the optoelectronic semiconductor wafer is aligned and electrically connected to the second solid via plug.

According to the above embodiment, the present invention provides an optoelectronic semiconductor element The device is formed by flip chip bonding, and the electrodes of at least one of the optoelectronic semiconductor wafers are aligned and electrically connected to the solid via plugs of the substrate. Thereafter, the phosphor layer is overlaid on at least one surface of the optoelectronic semiconductor wafer, and the substrate, the optoelectronic semiconductor wafer, and the phosphor layer are coated with an encapsulant.

Compared with the conventional wire-bonding technology, when the optoelectronic semiconductor chip is packaged, the package structure must be laterally extended to electrically connect the wire to the pad of the substrate. The optoelectronic semiconductor wafer adopting the flip chip package structure is in contact with the solid via plug under the longitudinal alignment of the wafer electrode system, and the required package size is small, which is advantageous for miniaturization of the optoelectronic semiconductor component.

In addition, due to the small package size, the optoelectronic semiconductor wafer can be arranged more closely. When the phosphor layer is coated and packaged, the uniformity of the phosphor layers of the respective optoelectronic semiconductor components can be increased, and the polarized light of the conventional optoelectronic semiconductor components can be solved. Or the problem of color cast. In addition, the flip chip packaging technology of the present invention uses a solid via plug to efficiently transfer the heat generated by the optoelectronic semiconductor wafer to the back surface of the substrate, compared to conventional wire bonding technology. The heat dissipation effect is better, and the performance of the optoelectronic semiconductor component can be improved.

100‧‧‧Optoelectronic semiconductor components

101‧‧‧Substrate

101a‧‧‧ First surface of the substrate

101b‧‧‧Second surface of the substrate

102a‧‧‧solid interlayer plug

102b‧‧‧solid interlayer plug

103‧‧‧ patterned metal layer

103a‧‧‧ pads

103b‧‧‧ solder pads

104‧‧‧ patterned metal layer

104a‧‧‧ pads

104b‧‧‧ solder pads

105‧‧‧patterned insulation

106‧‧‧Optoelectronic semiconductor wafer

106a‧‧‧Electroelectric semiconductor wafer electrodes

106b‧‧‧electrodes of optoelectronic semiconductor wafers

106c‧‧‧ upper surface of optoelectronic semiconductor wafer

106d‧‧‧ sidewalls of optoelectronic semiconductor wafers

107‧‧‧ solder balls

108‧‧‧Loading substrate

108a‧‧‧Metal lines

109‧‧‧Fluorescent layer

110‧‧‧ solder balls

111‧‧‧Insulating adhesive

112‧‧‧ Sealant

201‧‧‧Substrate

209‧‧‧Fluorescent layer

212‧‧‧ Wafer cutting steps

300‧‧‧Optoelectronic semiconductor components

308‧‧‧bearing substrate

312‧‧‧ Sealing body

1A to 1G are cross-sectional views showing the structure of an optoelectronic semiconductor device 100 according to an embodiment of the present invention.

2 is a cross-sectional view showing a structure in which a phosphor layer is coated on a plurality of optoelectronic semiconductor wafers in accordance with another embodiment of the present invention.

3 is a cross-sectional view showing the structure of an optoelectronic semiconductor device according to an embodiment of the invention.

The present invention is to provide an optoelectronic semiconductor having a small package size The device and the method for fabricating the same can increase the uniformity of the phosphor layer of the optoelectronic semiconductor device, and solve the problems of polarized light or color cast caused by uneven light mixing of the fluorescent layer. The above and other objects, features and advantages of the present invention will become more <RTIgt;

1A to 1G, FIGS. 1A to 1G are diagrams according to an embodiment of the present invention. A cross-sectional view showing the structure of the photo-electric semiconductor device 100 is shown. The method of fabricating the optoelectronic semiconductor component 100 includes the steps of first providing a substrate 101 having a first surface 101a and a second surface 101b (as shown in FIG. 1A). The second surface 101b is located on the substrate 101 opposite to the first surface 101a. In some embodiments of the present invention, the substrate 101 may be a lead frame, a printed circuit board (PCB), a flexible circuit board, a ceramic substrate, or any other die carrier (die carrier) ). In the present embodiment, the substrate 101 is a printed circuit board, and the material thereof may be, for example, bismaleimide-triazine resin (BT), or other similar materials.

Thereafter, at least one of the through substrates 101 is formed in the substrate 101. Cardiac interlayer plugs, such as solid via plugs 102a and 102b, extend from first surface 101a of substrate 101 to second surface 101b (as depicted in Figure IB). In some embodiments of the invention, the solid via plugs 102a and 102b are metal (e.g., copper or aluminum) plugs that extend through the substrate 101.

Then, on the first surface 101a of the substrate 101, a patterned gold is formed. a layer 103 in which the patterned metal layer 102 includes at least one pad (e.g., pads 103a and 103b) and the pads 103a and 103b are aligned with the solid via plugs 102a and 102b, respectively, and with a solid via plug 102a and 102b are directly connected. And forming another patterned metal layer 104 on the second surface 101b of the substrate 101, wherein the patterned metal layer 103 comprises at least one Pads (such as pads 104a and 104b), such that pads 104a and 104b are aligned with solid via plugs 102a and 102b, respectively, and are directly connected to solid via plugs 102a and 102b (as shown in FIG. 1B). .

It is worth noting that although in this embodiment, the solid interlayer plug 102a and 102b are formed prior to the patterned metal layers 103 and 104. However, in other embodiments, the formation of the solid via plugs 102a and 102b and the patterned metal layer 103 or 104 are not limited thereto. It is also possible to form the patterned metal layer 103 or 104 on the surface of the substrate 101 such that the pads 103a and 103b are aligned with the pads 104a and 104b, respectively. Thereafter, solid via plugs 102a and 102b are formed through the substrate 101 to align and directly connect the pads 103a, 103b, 104a and 104b.

Then, selectively forming a pattern on the metal layer 103 The edge layer 105 exposes the pads 103a and 103b to the outside (as shown in FIG. 1C). In some embodiments of the present invention, the material constituting the patterned insulating layer 105 may be, for example, ceria, tantalum nitride, hafnium oxynitride, epoxy resin or the like. In other embodiments of the present invention, the insulating layer 105 may not be formed, and the patterned metal layer 103 may be exposed to directly define the range of the pads 103a and 103 to save cost.

Subsequently, at least one optoelectronic semiconductor wafer 106 is provided, and the photo-electric half The electrodes 106a and 106b of the conductor wafer 104 are aligned with the solid via plugs 102a and 102b, respectively, and are in electrical contact with the solid via plugs 102a and 102b (as shown in FIG. 1D). In some embodiments of the present invention, the optoelectronic semiconductor wafer 106 may be a Light-Emitting Diode (LED) wafer, an Organic Light-Emitting Diode (OLED) wafer, or a laser diode. Laser diode wafer, photodiode wafer, charge-coupled device (CCD) wafer or solar cell wafer. In the present embodiment, the optoelectronic semiconductor wafer 106 is a light emitting diode wafer, and the cathode and anode electrodes (ie, the electrodes 104a and 104b) of the light emitting diode wafer are located on the same side of the optoelectronic semiconductor wafer 106. .

The electrodes 106a and 106b of the optoelectronic semiconductor wafer 106 are aligned, respectively. And electrically contacting the solid via plugs 102a and 102b, the optoelectronic semiconductor wafer 106 is placed on the patterned insulating layer 105, and the electrodes 106a and 106b of the semiconductor wafer 106 are exposed to the outside using the solder balls 107. The pads 103a and 103b are coupled. Since the pads 103a and 103b are respectively aligned and directly connected to the solid via plugs 102a and 102b; the electrodes 106a and 106b coupled to the pads 103a and 103b are respectively aligned and aligned with the solid via plugs 102a and 102b electrical contact.

Then, on at least one surface of the optoelectronic semiconductor wafer 106, a firefly is coated Light layer 109. In some embodiments of the present invention, an insulating paste 111 is preferably formed around the solder balls 107 and the electrodes 106a and 106b before the phosphor layer 109 is applied. Thereafter, a phosphor layer 109 (as shown in FIG. 1E) is applied over the upper surface 106c and the sidewall 106d of the optoelectronic semiconductor wafer 106 that is not covered by the insulating paste 111.

It should be noted that the aforementioned coating step of the phosphor layer 109 can be simultaneously performed. Applied to a plurality of optoelectronic semiconductor wafers 106. Referring to FIG. 2, FIG. 2 is a cross-sectional view showing a structure in which a phosphor layer 209 is coated on a plurality of optoelectronic semiconductor wafers 106 in accordance with another embodiment of the present invention. First, a plurality of optoelectronic semiconductor wafers 106 are arranged in an array pattern and fixed on a substrate 101 by wafer-level processing using steps as shown in FIGS. 1A to 1D. The phosphor layer 209 coating step as shown in FIG. 1E is performed on a plurality of optoelectronic semiconductor wafers 106 in synchronization. Subsequently, a wafer dicing step 212 is performed to form a structure similar to that shown in FIG. 1E. Due to the wafer level process, a plurality of optoelectronic semiconductor wafers 106 can be closely arranged on the substrate 101 to shorten the spacing between adjacent two optoelectronic semiconductor wafers 106. Therefore, the uniformity of the fluorescent layer 109 of each of the optoelectronic semiconductor elements 106 can be increased when the step of applying the phosphor layer 109 is performed.

Next, referring again to FIG. 1E, the base combined with the optoelectronic semiconductor wafer 106 will be used. The material 101 is fixed on the carrier substrate 108. In some embodiments of the present invention, the pads 104a and 104b of the second surface 101 of the substrate 101 are placed on the carrier substrate 108 using solder balls 110. The metal lines 108a are connected and electrically contact the optoelectronic semiconductor wafer 106 and the carrier substrate 108 (as shown in FIG. 1F). In some embodiments of the present invention, the carrier substrate 108 may be a metal core printed circuit board (MCPCB), a ceramic circuit board, or a substrate having good heat conduction effects.

Since the embodiment of the present invention adopts a flip chip package structure to optoelectronic The semiconductor wafer 106 is packaged. That is, the solder balls 107 and 110 which are longitudinally aligned and directly in contact with the solid via plugs 102a and 102b are used to fix the optoelectronic semiconductor wafer 106 to the carrier substrate 108 and to the metal trace 108a of the carrier substrate 108. Electrical connection. Therefore, the package structure does not need to be laterally extended, and the required package size is small, which is advantageous for miniaturization of the optoelectronic semiconductor device 100. Further, more optoelectronic semiconductor wafers 106 can be closely arranged on the carrier substrate 108, thereby greatly increasing the packaging density of the optoelectronic semiconductor device 100.

Subsequently, the substrate 101, the optoelectronic semiconductor wafer 106, and the encapsulant 112 are coated. The phosphor layer 109 and a portion of the carrier substrate 108 are used to isolate the substrate 101, the light-emitting semiconductor crystal 106, and the phosphor layer 109 from the outside air to form the optoelectronic semiconductor chip package structure 100 as shown in FIG. 1G.

Wherein, the optoelectronic semiconductor component 100 comprises a substrate 101, a solid via plug 102a and 102b, optoelectronic semiconductor wafer 106, phosphor layer 109, carrier substrate 108, and encapsulant 112. Among them, the solid via plugs 102a and 102b penetrate the substrate 101. Optoelectronic semiconductor wafer 106, having electrodes 106a and 106b, is aligned and in electrical contact with solid via plugs 102a and 102b. The phosphor layer 109 covers the upper surface 106c of the optoelectronic semiconductor wafer 106 and the sidewall 106d. The substrate 101 is fixed on the carrier substrate 108. The encapsulant 112 covers the substrate 101, the optoelectronic semiconductor wafer 106, the phosphor layer 109, and a portion of the carrier substrate 108, thereby isolating the substrate 101, the light-emitting semiconductor crystal 106, and the phosphor layer 109 from the outside air.

In some embodiments of the present invention, the material of the encapsulant 112 is preferably It is a transparent Molding Compounds such as epoxy resin, silicone rubber or polyimide (PI). The solidified encapsulant 112, in addition to protecting the optoelectronic semiconductor component 100, can form a hemispherical transparent microlens structure for enhancing the optical efficiency of the optoelectronic semiconductor component 100.

Although in the present embodiment, the encapsulant 112 has a single transparent microlens structure, Only one substrate 101 and the light-emitting semiconductor crystal 106 are coated, but other embodiments of the present invention are not limited thereto. For example, please refer to FIG. 3. FIG. 3 is a cross-sectional view showing the structure of an optoelectronic semiconductor device 300 according to an embodiment of the invention. The structure of the optoelectronic semiconductor component 300 is substantially similar to that of the optoelectronic semiconductor component 100. The difference is that in the optoelectronic semiconductor component 300, the single transparent microlens structure composed of the encapsulant 312 can be coated at the same time and fixed in plurality. The light-emitting semiconductor crystals 106 on the substrate 208 are carried.

According to the above embodiment, the present invention provides an optoelectronic semiconductor component, The electrode of the at least one optoelectronic semiconductor wafer is directly bonded to the solid via plug through the substrate by a flip chip bonding method. Thereafter, the phosphor layer is overlaid on at least one surface of the optoelectronic semiconductor wafer, and the substrate, the optoelectronic semiconductor wafer, and the phosphor layer are coated with an encapsulant.

Optoelectronic semiconductor wafers are packaged compared to conventional wire packaging technology When the package structure has to be extended laterally, the wire can be electrically connected to the pad of the substrate. The optoelectronic semiconductor wafer adopting the flip chip package structure is in contact with the solid via plug under the longitudinal alignment of the wafer electrode system, and the required package size is small, so that the optoelectronic semiconductor wafer arrangement is more tight and the optoelectronic semiconductor component is small. Chemical.

In addition, when performing phosphor layer coating and packaging, it is possible to increase each photoelectric The uniformity of the phosphor layer of the semiconductor element solves the problem of polarized or color cast of the conventional optoelectronic semiconductor element. In addition, the flip chip packaging technology of the present invention uses a solid via plug to efficiently fan the heat generated by the optoelectronic semiconductor wafer to the back surface of the substrate, compared to conventional wire bonding technology. , its heat dissipation effect is better, which can improve the efficiency of optoelectronic semiconductor components can.

While the invention has been described above in the preferred embodiments, it is not intended to limit the invention. Anyone having ordinary knowledge in the field can make some changes and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100‧‧‧Optoelectronic semiconductor components

101‧‧‧Substrate

102a‧‧‧solid interlayer plug

102b‧‧‧solid interlayer plug

104a‧‧‧ pads

104b‧‧‧ solder pads

105‧‧‧patterned insulation

106‧‧‧Optoelectronic semiconductor wafer

106a‧‧‧Electroelectric semiconductor wafer electrodes

106b‧‧‧electrodes of optoelectronic semiconductor wafers

106c‧‧‧ upper surface of optoelectronic semiconductor wafer

106d‧‧‧ sidewalls of optoelectronic semiconductor wafers

107‧‧‧ solder balls

108‧‧‧Loading substrate

108a‧‧‧Metal lines

109‧‧‧Fluorescent layer

110‧‧‧ solder balls

112‧‧‧ Sealant

Claims (14)

An optoelectronic semiconductor chip package structure comprising: a substrate; a first solid via plug extending through the substrate; an optoelectronic semiconductor wafer having a first electrode aligned with the first solid via plug Electrically connecting; a phosphor layer covering at least one surface of the optoelectronic semiconductor wafer; and a gel covering the substrate, the optoelectronic semiconductor wafer, and the phosphor layer. The optoelectronic semiconductor chip package structure of claim 1, further comprising: a first patterned metal layer on a first surface of the substrate, having at least one first pad, aligned and The first solid via plug is in direct contact; and a second patterned metal layer is disposed on a second surface of the substrate, having at least one second pad aligned and interposed with the first solid via The plug is in direct contact; wherein the second surface is on the opposite side of the substrate relative to the first surface. The optoelectronic semiconductor chip package structure of claim 2, wherein the first electrode is electrically connected to the first solid via plug via the first pad. The optoelectronic semiconductor chip package structure of claim 2, further comprising a carrier substrate coupled to the substrate; the substrate, the LED chip, and the LED substrate and the encapsulant The phosphor layer is isolated from the outside air. The optoelectronic semiconductor chip package structure of claim 4, wherein the The carrier substrate has a metal line in direct contact with the second pad. The optoelectronic semiconductor chip package structure of claim 1, further comprising a second solid via plug extending through the substrate and electrically aligned with a second electrode of the optoelectronic semiconductor wafer. A method of packaging an optoelectronic semiconductor wafer, comprising the steps of: providing a substrate and a first solid via plug extending through the substrate; aligning a first electrode of an optoelectronic semiconductor wafer with the first a solid via plug is electrically contacted; a phosphor layer is coated on at least one surface of the optoelectronic semiconductor wafer; and the substrate, the light emitting semiconductor wafer, and the phosphor layer are coated with a gel. The method for packaging an optoelectronic semiconductor wafer according to claim 7, wherein the step of providing the substrate and the first solid via plug further comprises: forming on a first surface of the substrate a first patterned metal layer having at least one first bonding pad, the first bonding pad is aligned and in direct contact with the first solid via plug; and formed on a second surface of the substrate a second patterned metal layer having at least one second pad aligned and in direct contact with the first solid via plug, wherein the second surface is located on the substrate opposite the first surface One side. The method for packaging an optoelectronic semiconductor wafer according to claim 8, wherein the step of providing the substrate and the first solid via plug is further included on the patterned first metal layer to form a The insulating layer is patterned to expose the first pad to the outside. The method of claim 3, wherein the step of aligning and electrically contacting the first electrode of the optoelectronic semiconductor wafer with the first solid via plug comprises using one A solder ball connects the first electrode and the first pad. The method for packaging an optoelectronic semiconductor chip according to claim 8, further comprising: bonding a carrier substrate to the substrate, and electrically connecting the second pad to a metal line of the carrier substrate. The method of claim 31, wherein the step of bonding the carrier substrate to the substrate comprises using a solder ball to connect the metal line to the second pad. The method for packaging an optoelectronic semiconductor wafer according to claim 11, wherein the step of coating the encapsulant with the substrate, the luminescent semiconductor wafer and the phosphor layer comprises coating the substrate with the encapsulant The material, the optoelectronic semiconductor wafer, the phosphor layer, and a portion of the carrier substrate are used to isolate the substrate, the optoelectronic semiconductor wafer, and the phosphor layer from outside air. The method of claim 3, further comprising: providing a second solid via plug, through the substrate, aligning at least a second electrode of the optoelectronic semiconductor wafer Electrically connected to the second solid via plug.