TW201508884A - Semiconductor structure including conductive film - Google Patents

Abstract

One embodiment of the present invention provides a semiconductor structure including: a semiconductor substrate having pads facing outward; a protective layer covered the semiconductor substrate and having openings for exposing the pads; a printed circuit board formed with external circuits; and a conductive film between the semiconductor substrate and the printed circuit board for electrically connecting the pads with the external circuits.

Description

Semiconductor structure with conductive film

This invention relates to a semiconductor structure, and more particularly to a semiconductor structure having a conductive film.

The content described in this section is merely a background for providing an embodiment of the present invention and does not constitute prior art.

In a semiconductor process, after a wafer is fabricated, a wafer can be patterned by optical processing to provide a semiconductor substrate. Since the electrode pattern of the wafer thus processed, that is, the semiconductor substrate, is extremely small, it is difficult to directly contact the PCB printed circuit board. Therefore, in order to electrically connect the semiconductor substrate to the PCB substrate, a package substrate (Packing Substrate) is generally used.

The package substrate is a PCB substrate having an inner lead. In order to electrically connect the electrode pattern of the semiconductor substrate to the inner lead of the package substrate, a wire bonding method or a Flip Chip Bonding method may be used. . The wire bonding method is a method in which a thin metal wire is used to connect between a semiconductor substrate and a package substrate, and a flip chip method is a method in which a protruding portion is provided on an electrode pattern of a semiconductor substrate, and then the protruding portion is connected. Such a projection is referred to as a solder ball or a bump, and such a structure is referred to as a bumping structure. In this manner, after the electrode pattern of the semiconductor substrate is connected to the inner leads of the package substrate by wire bonding or flip chip bonding, a packaging process is performed in order to fix the structure.

On the other hand, the semiconductor process and the semiconductor structure formed therefrom will vary depending on the size of the bumps. In the case where the size of the bump is small, such as the case where the diameter of the bump is about 60 μm to 100 μm, the package substrate structure is required, but in the case where the size of the bump is large, for example, the diameter of the bump At about 300 microns, there is no need to package substrate junctions The semiconductor substrate can be directly connected to the PCB substrate due to the size of the bump itself. The latter is referred to as a wafer level wafer size package WLCSP (Wafer Level Chip Size Packaging) structure.

Figure 1 is a schematic diagram showing the pre-stage for preparing separate die in a semiconductor process, which is a bumping structure without rearrangement. That is, Fig. 1 shows a structure in which a semiconductor 14 having a smaller diameter of 100 μm or less is bonded to the semiconductor at the level of the bumping structure. Figure 2 illustrates the bump structure rearranged in the semiconductor process. Generally, the pitch of the pads 11 on the semiconductor substrate 10 is very narrow. Therefore, in order to adhere the bumps 15 having a diameter of about 300 μm in order to use the WLCSP structure, it is necessary to appropriately use the protective layer 12 to rearrange the pitch of the pads 11. Fig. 2 is a view showing a structure in which the large bumps 15 are adhered to the pads 11 rearranged in order to use the WLCSP structure.

Bumping and WLCSP manufacturing method A photomask is used to form a protective layer 12 on the semiconductor substrate 10 to expose the bonding pad 11 to the outside, and is formed by electroplating or reactive sputtering. After the UBM 13 (Under Bump Metallurgy) structure is formed thereon, a bump or bump attach method is used to adhere the bumps 14, 15 thereto.

However, such bumping and WLCPS fabrication methods require expensive photomasks and Stencil Masks for ball attachment, and are produced due to complicated processes, resulting in a lot of losses. Time and cost. As a result, development time has become longer, process accidents have increased, and quality problems have frequently occurred.

In particular, the unit price of the products required by the market continues to decline, so there is a more urgent need for a technology that can reduce the unit price of the product.

In order to solve the above-mentioned problems, the main object of the present invention is to provide a new method different from the conventional wafer bump and WLCSP manufacturing method, which greatly reduces the number of process steps, thereby greatly reducing initial mask fabrication, etc. Development costs and wafer bumps for manufacturing unit price and WLCSP fabrication methods and their corresponding semiconductor package structures.

The technical problem to be attained by the present invention is not limited by the technical problems described above, and other technical problems that are not mentioned can be made by the following description. Those skilled in the art are well understood.

An embodiment of the present invention provides a semiconductor structure including: a semiconductor substrate with a plurality of pads exposed to the outside; a protective layer covering the semiconductor substrate and forming a plurality of openings for exposing the pads to the outside; A PCB substrate having an outer lead formed between the semiconductor substrate and the PCB substrate for electrically connecting the conductive pad to the outer lead.

Moreover, another embodiment of the present invention provides a semiconductor manufacturing method including the steps of: providing a plurality of pads to expose a semiconductor substrate; and having a plurality of openings for exposing the pads to the outside. a step of forming a protective layer on the semiconductor substrate; providing a step of forming a PCB substrate with a plurality of outer leads; and providing a conductive film, wherein the conductive film comprises: electrically connecting the pad and the outer lead a plurality of conductors and an insulating portion for insulating the protective layer from the PCB substrate; a step of adhering the conductive film to the protective layer; and a step of adhering the PCB substrate to the conductive film.

According to the semiconductor structure and the manufacturing method of an embodiment of the present invention, wafer bumps or WLCSP are not required, so that high early development costs such as equipment investment can be reduced.

Moreover, the complicated process can be omitted, so that the production time of the product can be shortened, thereby improving the productivity, and the process can be simplified, thereby reducing the defect rate of the process, and the product price of the product can be greatly reduced.

Moreover, the underfill process required in the flip chip method can be omitted due to the insulating portion.

Further, the effects of the present invention have various effects such as excellent durability as in the embodiment, and such effects will be described in the description of the embodiments to be described later.

10‧‧‧Semiconductor substrate

11‧‧‧ solder pads

12‧‧‧Protective layer

13‧‧‧UBM layer

14,15‧‧‧Bumps

16‧‧‧ solder layer

20‧‧‧Electrical film

21‧‧‧Conductor

22‧‧‧Insulation

X‧‧‧ length direction

C‧‧‧ center axis

Figure 1 is a schematic diagram showing the pre-stage for preparing the individual die (Die) in the semiconductor process, which is a bumping structure without rearrangement; and Figure 2 is a diagram showing the preparation of the independent crystal in the semiconductor process. The pre-stage of the pellet is a bump structure that is rearranged; the 3a, 3b, and 3c diagrams show a conductive film having various structures. The semiconductor structure; FIG. 4 is a view showing a semiconductor manufacturing method according to another embodiment of the present invention; and FIGS. 5a, 5b, and 5c are diagrams illustrating that the conductive film according to the second embodiment is adhered to the semiconductor substrate, and is pasted with The semiconductor substrate of the conductive film is subjected to a step of singulation.

Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings. However, this is not intended to limit the scope of the invention.

When reference numerals are attached to constituent elements of the respective drawings, the same components are denoted by the same reference numerals as long as they are indicated on different drawings. Further, in the description of the present invention, if it is determined that the specific description of the related conventional configuration or function may affect the gist of the present invention, the detailed description thereof will be omitted.

Further, the size, shape, and the like of the constituent elements shown in the drawings are exaggerated in accordance with the clarity and convenience of the description. Further, the terms that are specifically defined in consideration of the constitution and function of the present invention are merely illustrative of the embodiments of the present invention and are not intended to limit the scope of the present invention.

3a to 3c are semiconductor structures illustrating a conductive film having various structures. Please refer to FIGS. 3a to 3c and explain.

The semiconductor structure according to an embodiment of the present invention may include a semiconductor substrate 10 in which a plurality of pads 11 are exposed to the outside.

Further, the semiconductor substrate 10 is covered, and may include a protective layer 12 formed with a plurality of openings for allowing the bonding pad 11 to be exposed to the outside.

Further, a PCB substrate (printed circuit board, not shown) formed with a plurality of outer leads may be included.

Moreover, it may include a conductive film 20 interposed between the semiconductor substrate 10 and the PCB substrate for electrically connecting the pad 11 and the outer leads.

First, the pad 11 is used to expand the circuit function contained inside the semiconductor element. The pad 11 may be made of aluminum according to an embodiment. The semiconductor substrate 10 may be a wafer base in which a plurality of semiconductor wafers are formed in a matrix form and separated from each other according to a scribe line. board. Further, the semiconductor substrate 10 can be formed into a circuit portion in the germanium substrate by a wafer process, and the solder pad 11 can be exposed to the outside through the protective layer 12, such as a passivation layer.

On the other hand, the semiconductor substrate 10 has a structure in which a plurality of bumps 14, 15 (bump) can be formed, and the conductive film 20 according to the present embodiment can be adhered regardless of any function. For example, the semiconductor substrate 10 may be a dynamic random access memory (DRAM) component, a flash memory component, an LSI component of a microcontroller, a logic component, an analog component, a digital signal processor component, or a system on chip component. Or various components such as individual components.

Further, two or more wafers may be stacked on the semiconductor substrate 10, and the pads 11 may be connected in the vertical direction by a TSV (Through Silicon Via).

The conductive film 20 may include a plurality of conductors 21, and an insulating portion 22 for fixing the conductor 21 and insulating the protective layer 12 and the PCB substrate, according to an embodiment. The conductor 21 includes a first surface and a second surface, and the first surface is in contact with the solder pad 11 and the second surface is in contact with the outer lead. The second side may be the opposite side of the first side. In the conductive film 20, a surface other than the first surface and the second surface of the conductor 21 may be surrounded by the insulating portion 22.

The insulating portion 22 may be a soft material. According to an embodiment, a resin or polymer material may be included. In order to electrically connect the conductor 21 and the pad 11, the insulating portion 22 can function to fix the conductor 21 at an appropriate position.

According to an embodiment of the invention, a solder layer 16 may be formed on the first side and the second side of the conductor 21. The material of the solder layer 16 may be tin. The solder layer 16 may be formed on the first surface and the second surface of the conductor 21 by electroless plating or electroplating.

According to the embodiment, the conductive film 20 can be adhered to the semiconductor substrate 10 by adhering a bonding agent to the side of the semiconductor substrate 10 and then performing a curing process.

In the bump structure, the plurality of bumps 14 and 15 are usually made of tin or the like. In order to form the bumps 14 and 15 on the pad 11 of the semiconductor substrate 10, the pads 11 are formed with a paste. A UBM layer 13 of force is formed on the UBM layer 13 to form the bumps 14, 15. and, In order to protect the bumps 14, 15 formed on the pad 11, an underfill process for forming a protective layer 12 around the bumps 14, 15 is performed using an epoxy resin or the like.

The structure of the electroconductive thin film 20 according to the present embodiment is such that the insulating portion 22 fixes the conductor 21, and since the solder layer 16 is formed in a size smaller than that of the conventional bump structure, unlike the conventional bump, the UBM layer is not required. Thereby, it is not necessary to perform the process for forming the UBM layer, and it is also unnecessary to perform the filling primer process for protecting and fixing the bumps 14, 15, so that the number of semiconductor fabrication processes can be reduced. As a result, the semiconductor manufacturing time can be shortened, the manufacturing unit price can be lowered, and the productivity can be improved.

A first embodiment of the electroconductive thin film 20 is illustrated in Fig. 3a. Fig. 3c illustrates a third embodiment of the electroconductive thin film 20.

In the first embodiment and the third embodiment, the conductors 21 may be located on the conductive film 20 at positions corresponding to the positions of the pads 11 on the semiconductor substrate 10. That is, the conductor 21 is placed on the pad 11 corresponding to the conductor 21 so as to be electrically connectable to the first surface of the conductor 21. When the pad 11 has a positional pattern, the conductor 21 also has a position pattern corresponding thereto. For example, in the case where the pads 11 are arranged in a line along any first direction, the conductors 21 are also arranged in a row along the first direction.

The conductor 21 can include a first face that faces the pad 11. Moreover, it may further include an opposite surface formed on the first surface and facing the second surface of the PCB substrate. The first side may be a portion that is electrically connected to the pad 11. The second side may be a structure electrically connected to the package substrate in the first embodiment, and may be a structure electrically connected to the PCB substrate in the third embodiment. The contour of the first side and the contour of the second side may be of various shapes. The peripheral faces extending from the contour of the first face to the contour of the second face may also be of various shapes. The area of the first side may be less than or equal to the area of the pad 11.

In the first embodiment, the area of the first surface and the area of the second surface may be the same. However, in the third embodiment, the area of the second surface is larger than the area of the first surface. That is, the inside of the peripheral surface extending from the contour of the first surface to the contour of the second surface is filled, and the area perpendicular to the central axis C is centered on the central axis C of the conductor 21, from the first surface to the second surface. Gradually increasing form.

The third embodiment is provided as a WLCSP function by utilizing a junction of the conductor 21 which enlarges the area of the second face to be larger than the area of the first face to which the pad 11 is pasted. Structure. Therefore, in the case of implementing the third embodiment, the conductive film 20 is required to be rearranged by the area Array in the wafer fabrication process for the WLCSP. That is, in the third embodiment, in order to apply the conductive film 20, it is necessary to form the pad 11 in a wide range in the preparation process.

Fig. 3b is a view showing a second embodiment of the electroconductive thin film 20. Hereinafter, description will be made with reference to Fig. 3b. In the second embodiment of the electroconductive thin film 20, the conductor 21 may be disposed in the electroconductive thin film 20 at a certain interval along the longitudinal direction (X direction).

In the second embodiment, unlike the first embodiment and the third embodiment, a plurality of conductors 21 may be closely arranged in the insulating portion 22. A part of the plurality of conductors 21 of the plurality of conductors 21 may be disposed on a portion of the semiconductor substrate 10 where a pad 11 is not exposed.

Fig. 4 is a view showing a method of fabricating a semiconductor according to another embodiment of the present invention.

Fig. 5 is a view showing a step in which the second embodiment of the electroconductive thin film 20 of the present invention is adhered to the semiconductor substrate 10, and the semiconductor substrate 10 to which the electroconductive thin film 20 is adhered is subjected to isolation. The description will be made with reference to FIGS. 4 and 5.

The semiconductor manufacturing method according to other embodiments of the present invention may include a step of providing a plurality of pads 11 to the outside of a semiconductor substrate 10 (S100); in order to enable the pads 11 to be exposed to the outside, the semiconductor substrate 10 a step of forming a protective layer 12 having a plurality of openings; (S200); providing a step of forming a PCB substrate having a plurality of outer leads (S300); providing a conductive film 20 for electrically connecting the pads a plurality of conductors 21 with the outer leads, and a step (S400) for insulating the protective layer 12 and the insulating portion 22 of the PCB substrate; a step of adhering the conductive film 20 to the protective layer 12 (S500); The step of adhering the PCB substrate to the conductive film 20 (S600).

In the first embodiment and the third embodiment of the conductive film 20, the step of adhering the conductive film 20 (S500) may further include: the conductive film 20 or the semiconductor substrate 10 for the pad 11 to face the conductor 21. The steps to arrange. This is to electrically connect the pad 11 to the conductor 21 corresponding to the pad 11.

In contrast, in the second embodiment, the conductor 21 can be disposed at any position on the conductive film 20. That is, in the conductive film 20, a plurality of conductors 21 may be the same as the pad 11 The position is inserted into the insulating portion 22 at a certain pitch and in a pattern regardless of the position.

Thus, the step of aligning the conductive film 20 or the semiconductor substrate 10 in order to cause the pad 11 to face the conductor 21 can be omitted in the process of attaching the conductive film 20 (S500) in the second embodiment.

In the second embodiment, when the conductive film 20 is pasted on the semiconductor substrate 10, the conductive film 20 can be adhered without considering the position of the bonding pad 11, thereby omitting the alignment process and simplifying the semiconductor fabrication method. The improvement in performance has the advantage of reducing the manufacturing unit price.

In the first embodiment and the second embodiment of the conductive film 20, the process of adhering the PCB substrate (S600) includes: attaching a process for electrically connecting the conductor 21 and the package substrate of the PCB substrate on the conductive film 20, And the process of adhering the PCB substrate on the package substrate.

That is, the semiconductor structure in this case may be such that a package substrate is laminated on the upper surface of the PCB substrate, and the conductive film 20 is laminated on the upper surface of the package substrate, and the semiconductor is laminated on the conductive film 20. The structure of the substrate 10.

5a to 5c are views showing a process in which the electroconductive thin film 20 according to the second embodiment is adhered to the semiconductor substrate 10, and the semiconductor substrate 10 to which the electroconductive thin film 20 is pasted is subjected to isolation. FIG. 5a is a schematic view showing the conductive film 20 adhered to the semiconductor substrate 10. In the fifth step, after the solder layer 16 is melted by a reflow process, the conductor 21 of the conductive film 20 is adhered to the pad 11, and the adhesive of the insulating portion 22 is performed. Schematic diagram of the process of curing (Cure).

Figure 5c is a schematic diagram of cutting into individual cells by a separation process. Referring to FIGS. 5a to 5c, in the second embodiment of the conductive film 20, an alignment process for aligning the formation position of the pad 11 and the position of the conductor 21 is not required, and the insulating portion 22 is densely inserted therein. The conductive film 20 of the conductor 21 is adhered to the semiconductor substrate 10, and is pasted by a reflow process to be cut by a separation process.

The above description is only for the purpose of illustrating the technical concept of the present invention, and various modifications and changes can be made without departing from the spirit and scope of the invention.

Therefore, the illustrated embodiment of the present invention is not intended to limit the technical idea of the present invention. It is intended to be illustrative, and the embodiments do not limit the scope of the technical scope of the invention. The scope of the present invention is to be construed as the following claims, and all the technical scopes within the scope of the invention are construed as the scope of the invention.

10‧‧‧Semiconductor substrate

11‧‧‧ solder pads

12‧‧‧Protective layer

16‧‧‧ solder layer

20‧‧‧Electrical film

21‧‧‧Conductor

22‧‧‧Insulation

X‧‧‧ length direction

Claims (12)

A semiconductor structure comprising: a semiconductor substrate having a plurality of pads exposed to the outside; a protective layer covering the semiconductor substrate and forming a plurality of openings for exposing the pads to the outside; a printed circuit board, Forming a plurality of outer leads; and a conductive film interposed between the semiconductor substrate and the printed circuit board for electrically connecting the pad and the outer lead. The semiconductor structure of claim 1, wherein the conductive film further comprises: a plurality of conductors; and an insulating portion for fixing the conductor and insulating between the protective layer and the printed circuit board. The semiconductor structure of claim 2, wherein the conductor comprises a first surface and a second surface, and the first surface is in contact with the solder pad, and the second surface is in contact with the outer lead. The semiconductor structure of claim 3, wherein the first surface and the second surface are formed with a solder layer. The semiconductor structure of claim 2, wherein the insulating portion comprises a resin or a polymer material. The semiconductor structure of claim 2, wherein the conductors are arranged at a certain interval within the conductive film. The semiconductor structure of claim 6, wherein the plurality of conductors are electrically connected to the pad at the same time. The semiconductor structure of claim 2, wherein the conductors are located at positions corresponding to locations of the pads on the conductive film. The semiconductor structure of claim 8, wherein the conductor comprises: a first face facing the pad, and a second face formed on the opposite side of the first face and facing the printed circuit board, and The area of the second side is larger than the area of the first side. A method of fabricating a semiconductor structure, comprising the steps of: providing a semiconductor substrate with a plurality of pads exposed to the outside; forming a protective layer having a plurality of openings for exposing the pads to the outside; forming a protective layer on the semiconductor substrate; Forming a printed circuit board having a plurality of outer leads; providing a conductive film, wherein the conductive film comprises: a plurality of conductors for electrically connecting the solder pads to the outer leads, and for insulating the protective layer and the printing An insulating portion of the circuit substrate; the conductive film is adhered to the protective layer; and the printed circuit substrate is adhered to the conductive film. The method of fabricating a semiconductor structure according to claim 10, wherein the step of adhering the conductive film further comprises the step of arranging the conductive film or the semiconductor wafer for the pad to face the conductor. The method of manufacturing a semiconductor structure according to claim 10, wherein the step of pasting the printed circuit board comprises the steps of: attaching a package substrate for electrically connecting the conductor and the printed circuit board to the conductive film; And attaching the printed circuit board to the package substrate.