JP2008028081A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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JP2008028081A
JP2008028081A JP2006197983A JP2006197983A JP2008028081A JP 2008028081 A JP2008028081 A JP 2008028081A JP 2006197983 A JP2006197983 A JP 2006197983A JP 2006197983 A JP2006197983 A JP 2006197983A JP 2008028081 A JP2008028081 A JP 2008028081A
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acf
substrate
tft substrate
conductive particles
resin paste
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Hiroshi Ueda
上田　　宏
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive

Abstract

<P>PROBLEM TO BE SOLVED: To prevent short circuits between adjacent electrodes by increasing the number of conductive particles trapped between the electrodes connected to each other via an anisotropic conductive film (ACF). <P>SOLUTION: The ACF 8 is pasted to a TFT substrate 10 whereon ITO electrodes 5 (first electrodes) are formed, and then a thermosetting resin paste 11 is applied onto the ACF 8. The thermosetting resin paste 11 is in an uncured state, and has a lower viscosity than the ACF 8. Thereafter, a driving IC 7 having bumps 6 (second electrodes) are thermocompression-bonded to the TFT substrate 10 via the ACF 8 and the thermosetting resin paste 11. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

本発明は、半導体装置およびその製造方法に関し、特に、異方性導電膜を用いて電極同士を接続するための技術に関するものである。   The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly to a technique for connecting electrodes using an anisotropic conductive film.

絶縁性の接着樹脂中に導電性の微細粒子（導電粒子）を分散させた異方性導電膜（ＡＣＦ：Anisotropic Conductive Film）は、基板と半導体素子、あるいは基板同士の接続に広く使用されている。ＡＣＦを用いて形成される代表的なデバイスの一つとして液晶表示装置が挙げられる。液晶表示装置は、２枚の透明な絶縁性基板の間に液晶を挟持した表示パネルに駆動回路を接続し、当該表示パネルを照明装置上に重ねたものである。   Anisotropic conductive film (ACF) in which conductive fine particles (conductive particles) are dispersed in an insulating adhesive resin is widely used for connection between a substrate and a semiconductor element or between substrates. . One of typical devices formed using ACF is a liquid crystal display device. In the liquid crystal display device, a driving circuit is connected to a display panel in which liquid crystal is sandwiched between two transparent insulating substrates, and the display panel is stacked on a lighting device.

例えばアクティブ素子として薄膜トランジスタ（ＴＦＴ：Thin-Film Transistor）を用いた液晶表示装置では、２枚の透明な絶縁性基板の一方の基板（ＴＦＴ基板）上に複数のＴＦＴがマトリクス状に配列される。通常、ＴＦＴ基板はもう一方の基板（ＣＦ（Color filter）基板）よりも大きく、それらを重ね合わせる際には、ＴＦＴ基板の一部がＣＦ基板から張り出したかたちになる。ＴＦＴ基板上の複数のＴＦＴの各々には１つずつ画素が接続しており、駆動回路がそれら各ＴＦＴのＯＮ／ＯＦＦを制御することによって特定の画素に画像信号を送ることができる。   For example, in a liquid crystal display device using a thin film transistor (TFT) as an active element, a plurality of TFTs are arranged in a matrix on one substrate (TFT substrate) of two transparent insulating substrates. Usually, the TFT substrate is larger than the other substrate (CF (Color filter) substrate), and when they are overlapped, a part of the TFT substrate protrudes from the CF substrate. One pixel is connected to each of a plurality of TFTs on the TFT substrate, and an image signal can be sent to a specific pixel by controlling ON / OFF of each TFT by the drive circuit.

またＴＦＴ基板上には、各ＴＦＴのソース電極に接続し、画像信号を入力するためのソース配線が形成される。一般にソース配線は、ＴＦＴ基板の短辺に対して平行に、ＴＦＴ基板の長辺側の端部（ＣＦ基板からから張り出した部分）にまで引き出され、その端部付近においてソース用の駆動回路（ソースドライバ）を接続するための電極パッド（以下、単に「パッド」と称することもある）を有している。ＴＦＴ基板上にはさらに、各ＴＦＴのゲート電極に接続し、ＴＦＴをＯＮ／ＯＦＦを切り替える制御信号を入力するためのゲート配線が形成される。当該ゲート配線は、ＴＦＴ基板の長辺に平行に（即ち、上記のソース配線に対して直交するように）、ＴＦＴ基板の短辺側の端部（ＣＦ基板からから張り出した部分）にまで引き出され、その端部付近においてゲート用の駆動回路（ゲートドライバ）を接続するためのパッドが形成されている。   On the TFT substrate, source wiring for inputting an image signal is formed so as to be connected to the source electrode of each TFT. In general, the source wiring is led out to the end on the long side of the TFT substrate (portion protruding from the CF substrate) in parallel with the short side of the TFT substrate, and the source driving circuit ( It has an electrode pad (hereinafter also simply referred to as “pad”) for connecting a source driver. On the TFT substrate, there is further formed a gate wiring for connecting a gate electrode of each TFT and inputting a control signal for switching the TFT ON / OFF. The gate wiring is extended to the end of the TFT substrate on the short side (the portion protruding from the CF substrate) parallel to the long side of the TFT substrate (that is, perpendicular to the source wiring). A pad for connecting a gate driving circuit (gate driver) is formed in the vicinity of the end.

例えば、ＴＦＴ基板上にＣＯＧ（Chip On Glass）実装方式により駆動回路を実装する場合には、上記のパッド上にＡＣＦを介して駆動回路のＩＣ（Integrated Circuit ）が実装される。ＡＣＦは、駆動回路のＩＣ（駆動ＩＣ）をＴＦＴ基板上に機械的に固定すると共に、当該駆動ＩＣの下面に形成されたバンプ（突起電極）とＴＦＴ基板上面のパッドと間を電気的に接続する。先に述べたように、ＡＣＦは絶縁性の接着樹脂とその中に分散した導電粒子とから成っており、ＴＦＴ基板と駆動ＩＣとの機械的な接続が接着樹脂により行われる一方で、駆動ＩＣのバンプと基板上のパッドとの間に導電粒子が挟まれて捕捉されることによりバンプとパッドとの間の電気的接続が成されるのである。   For example, when a driving circuit is mounted on a TFT substrate by a COG (Chip On Glass) mounting method, an IC (Integrated Circuit) of the driving circuit is mounted on the pad via the ACF. The ACF mechanically fixes the drive circuit IC (drive IC) on the TFT substrate and electrically connects the bump (projection electrode) formed on the lower surface of the drive IC and the pad on the upper surface of the TFT substrate. To do. As described above, the ACF is composed of an insulating adhesive resin and conductive particles dispersed therein, and mechanical connection between the TFT substrate and the driving IC is performed by the adhesive resin, while the driving IC is provided. The conductive particles are sandwiched and captured between the bumps and the pads on the substrate, thereby establishing an electrical connection between the bumps and the pads.

近年、表示画像の高精細化の要求から、表示パネルに搭載される駆動ＩＣの出力ピン数は急速に増加している。また駆動ＩＣの製造コストの削減を図るため駆動ＩＣの外形はシュリンクされており、ピン数の増加と相まってバンプの狭ピッチ化はいっそう進んでいる。また駆動ＩＣのバンプの狭ピッチ化が進むにつれ、バンプの面積は小さいものへと変化してきた。そうなると、ＡＣＦ内の導電粒子が駆動ＩＣのバンプと基板上のパッドとの間に捕捉される数が少なくなるため、バンプとパッドとの間の接続不良が発生しやすくなる。   In recent years, the number of output pins of drive ICs mounted on a display panel is rapidly increasing due to the demand for higher definition of display images. In order to reduce the manufacturing cost of the driving IC, the outer shape of the driving IC is shrunk, and coupled with the increase in the number of pins, the bump pitch is further reduced. Further, as the pitch of the bumps of the driving IC is reduced, the area of the bumps has changed to a smaller one. As a result, the number of conductive particles in the ACF captured between the bumps of the driving IC and the pads on the substrate is reduced, so that poor connection between the bumps and the pads tends to occur.

その対策としては、ＡＣＦ中の導電粒子の密度を高くし、導電粒子がバンプとパッドとの間に捕捉される確率を上げることが考えられる。しかし導電粒子の密度を高くすると、今度はＡＣＦ中で導電粒子の凝集が発生し、凝集した導電粒子を通して隣接バンプ間がショートするといった不具合が発生する。   As a countermeasure, it is conceivable to increase the density of the conductive particles in the ACF and increase the probability that the conductive particles are trapped between the bump and the pad. However, when the density of the conductive particles is increased, the conductive particles agglomerate in the ACF, and there is a problem that adjacent bumps are short-circuited through the aggregated conductive particles.

この導電粒子の捕捉確率の向上と導電粒子の凝集の防止とを両立させる手法としては、導電粒子が配合された第１層と導電粒子を含まない（接着樹脂のみの）第２層とから成る２層構造のＡＣＦを用いる手法がある（例えば、特許文献１）。   As a method for achieving both improvement of the trapping probability of the conductive particles and prevention of aggregation of the conductive particles, the first layer in which the conductive particles are blended and a second layer that does not include the conductive particles (only the adhesive resin) are included. There is a technique using a two-layer ACF (for example, Patent Document 1).

例えばＴＦＴ基板と駆動ＩＣとの接続に２層構造のＡＣＦを用いる場合、導電粒子を含む第１層がＴＦＴ基板側、導電粒子を含まない第２層が駆動ＩＣ側になるように、当該ＡＣＦをＴＦＴ基板に貼り付け、それを介して駆動ＩＣをＴＦＴ基板に熱圧着する。このとき第２層は、駆動ＩＣのバンプにより押し出されて当該バンプとＴＦＴ基板上のパッドとの間から排出される。その結果、バンプとパッドとの間に第１層中の導電粒子が捕捉される。また上記の第２層の排出に伴って、バンプ同士の間の余剰な導電粒子の一部も排出されるので、隣接バンプ間のショートは防止される。   For example, when an ACF having a two-layer structure is used to connect the TFT substrate and the driving IC, the ACF is arranged so that the first layer containing conductive particles is on the TFT substrate side and the second layer not containing conductive particles is on the driving IC side. Is attached to the TFT substrate, and the drive IC is thermocompression-bonded to the TFT substrate through it. At this time, the second layer is pushed out by the bump of the driving IC and discharged from between the bump and the pad on the TFT substrate. As a result, the conductive particles in the first layer are captured between the bump and the pad. Further, as the second layer is discharged, a part of the excessive conductive particles between the bumps is also discharged, so that a short circuit between adjacent bumps is prevented.

このように２層構造のＡＣＦを採用することによって、接着樹脂中の導電粒子の密度を過度に高くすることなく、バンプとパッド間の導電粒子の捕捉数を向上させることができるので、バンプとパッド間の接続不良の防止と隣接バンプ間のショートの防止の両立させることができる。   By adopting the ACF having the two-layer structure in this way, the number of conductive particles captured between the bump and the pad can be improved without excessively increasing the density of the conductive particles in the adhesive resin. It is possible to achieve both prevention of poor connection between pads and prevention of short circuit between adjacent bumps.

再表００／０３３３７５号公報No. 00/033375

しかし２層構造のＡＣＦを採用した場合であっても、駆動ＩＣをＴＦＴ基板に圧着する際、導電粒子を含まない第２層を介して導電粒子を含む第１層に圧力が加わると、第１層が薄く広がってバンプとパッドとの間の導電粒子の数が減少する。その結果、バンプとパッド間における導電粒子の捕捉数が減少し、導電粒子の密度が低い場合と同様に接続不良の問題が生じ得る。   However, even when the ACF having the two-layer structure is adopted, when pressure is applied to the first layer including the conductive particles via the second layer not including the conductive particles when the driving IC is pressure-bonded to the TFT substrate, One layer spreads thin and the number of conductive particles between the bump and the pad decreases. As a result, the number of conductive particles trapped between the bump and the pad is reduced, and the problem of poor connection may occur as in the case where the density of the conductive particles is low.

本発明は以上のような課題を解決するためになされたものであり、基板上にＡＣＦを用いて半導体素子あるいは他の基板を熱圧着する際に、当該ＡＣＦを介して電気的に接続させる電極間の導電粒子の捕捉数を向上させるとともに、隣接する電極間のショートを防止することを目的とする。   The present invention has been made to solve the above-described problems. When a semiconductor element or another substrate is thermocompression-bonded using ACF on the substrate, the electrode is electrically connected via the ACF. An object is to improve the number of trapped conductive particles between them and to prevent a short circuit between adjacent electrodes.

本発明に係る半導体装置の製造方法は、（ａ）表面上に電極が形成された第１基板に、異方性導電膜を貼り付ける工程と、（ｂ）前記異方性導電膜上に硬化性樹脂ペーストを塗布する工程と、（ｃ）前記第１基板に第２基板あるいは半導体素子を重ね合わせ、前記硬化性樹脂ペーストを硬化する工程とを備えるものである。   The method for manufacturing a semiconductor device according to the present invention includes: (a) a step of attaching an anisotropic conductive film to a first substrate having electrodes formed on the surface; and (b) curing on the anisotropic conductive film. A step of applying a curable resin paste, and (c) a step of superposing a second substrate or a semiconductor element on the first substrate and curing the curable resin paste.

本発明によれば、第１基板に第２基板あるいは半導体素子を重ね合わせる際に、異方性導電膜が押し広げられることがないので、電極上に捕捉される異方性導電膜中の導電粒子の数の減少が抑制される。従って、良好な電気的接続が得られるため、隣接電極の間のショートも防止することができる。また、硬化性樹脂ペーストの硬化後においては、第１基板と第２基板あるいは半導体素子との間に、異方性導電膜が硬化した層と硬化性樹脂ペーストが硬化した樹脂層との２層構造が介在することになる。従って、２層構造のＡＣＦを用いた場合と同様の作用により、隣接電極の間のショートを防止する効果が得られる。   According to the present invention, since the anisotropic conductive film is not spread when the second substrate or the semiconductor element is overlaid on the first substrate, the conductivity in the anisotropic conductive film trapped on the electrode is prevented. Reduction in the number of particles is suppressed. Therefore, since a good electrical connection can be obtained, a short circuit between adjacent electrodes can be prevented. In addition, after curing of the curable resin paste, two layers of a layer in which the anisotropic conductive film is cured and a resin layer in which the curable resin paste is cured are interposed between the first substrate and the second substrate or the semiconductor element. The structure will be interposed. Therefore, the effect of preventing short-circuiting between adjacent electrodes can be obtained by the same action as when the two-layer ACF is used.

図１〜図３は、本発明の実施の形態に係る半導体装置の製造方法の工程図である。これらの図を参照し、本発明に係る半導体装置の製造方法について説明する。ここでは、ＡＣＦを用いて、表面に電極パッドが形成された絶縁基板上に、バンプ（突起電極）を有する半導体素子を熱圧着する例を説明する。図１〜図３においてはより具体的な例として、液晶表示パネルを構成するＴＦＴ基板上のソース配線の電極パットに、半導体素子である駆動ＩＣ（ソースドライバＩＣ）を熱圧着する場合を示している。即ち、図１〜図３は、ＴＦＴ基板の長辺側の端部の断面を示している。   1 to 3 are process diagrams of a method for manufacturing a semiconductor device according to an embodiment of the present invention. With reference to these drawings, a method for manufacturing a semiconductor device according to the present invention will be described. Here, an example will be described in which a semiconductor element having bumps (projection electrodes) is thermocompression bonded onto an insulating substrate having an electrode pad formed on the surface using ACF. 1 to 3, as a more specific example, a case where a driver IC (source driver IC) as a semiconductor element is thermocompression bonded to an electrode pad of a source wiring on a TFT substrate constituting a liquid crystal display panel is shown. Yes. That is, FIG. 1 to FIG. 3 show a cross section of the end portion on the long side of the TFT substrate.

まず、電極パッドを有するソース配線が形成されたＴＦＴ基板１０を用意する。図１の如く、この例のＴＦＴ基板１０においては、絶縁基板１上に第１絶縁膜２を介してソース配線３が形成されている。ソース配線３上は、それを保護するための第２絶縁膜４に覆われているが、ソース配線３と駆動ＩＣとの接続領域上の第２絶縁膜４はエッチングにより除去されており、その領域にソース配線３が露出している。このソース配線３の露出部分の上に透明導電膜であるＩＴＯ（Indium Tin Oxide）５が形成され、当該ＩＴＯ５が絶縁基板１側の電極パッド（第１電極）となる。以下、電極パッドとしてのＩＴＯ５を「ＩＴＯ電極」と称する。   First, a TFT substrate 10 on which a source wiring having electrode pads is formed is prepared. As shown in FIG. 1, in the TFT substrate 10 of this example, a source wiring 3 is formed on an insulating substrate 1 via a first insulating film 2. The source wiring 3 is covered with a second insulating film 4 for protecting the source wiring 3, but the second insulating film 4 on the connection region between the source wiring 3 and the driving IC is removed by etching. The source wiring 3 is exposed in the region. A transparent conductive film ITO (Indium Tin Oxide) 5 is formed on the exposed portion of the source wiring 3, and the ITO 5 serves as an electrode pad (first electrode) on the insulating substrate 1 side. Hereinafter, the ITO 5 as the electrode pad is referred to as an “ITO electrode”.

本実施の形態においては図１の如く、用意したＴＦＴ基板１０の上面（ＩＴＯ５が形成されている側の面）に異方性導電膜（ＡＣＦ）８を貼り付ける。先に述べたように、ＡＣＦ８は接着樹脂８０内に導電粒子８１が分散されて成っている。本発明でいうＡＣＦとしては、接着樹脂の中に微細粒子を分散させたものに限定されることなく、導電性の貫通孔を有する多孔質フッ素樹脂フィルムなども適用することができる。   In this embodiment, as shown in FIG. 1, an anisotropic conductive film (ACF) 8 is attached to the upper surface (surface on which ITO 5 is formed) of the prepared TFT substrate 10. As described above, the ACF 8 is formed by dispersing the conductive particles 81 in the adhesive resin 80. The ACF referred to in the present invention is not limited to those in which fine particles are dispersed in an adhesive resin, and a porous fluororesin film having conductive through holes can also be applied.

次いで図２に示すように、ＡＣＦ８の上に、導電粒子を含んでいないペースト状の熱硬化性樹脂（熱硬化性樹脂ペースト）１１を塗布する。この熱硬化性樹脂ペースト１１としては、その未硬化状態での粘度がＡＣＦ８の未硬化状態での粘度（実質的には接着樹脂８０の未硬化状態での粘度）よりも低いもの（即ち流動性が高いもの）が使用される。本実施の形態においては、硬化性樹脂ペーストとして熱硬化性のものを用いた例について示したが、例えば光硬化性の樹脂ペーストを用いることも可能であり、その場合も同様の効果を奏することができる。   Next, as shown in FIG. 2, a paste-like thermosetting resin (thermosetting resin paste) 11 not containing conductive particles is applied on the ACF 8. The thermosetting resin paste 11 has a viscosity in the uncured state lower than the viscosity of the ACF 8 in the uncured state (substantially the viscosity of the adhesive resin 80 in the uncured state) (that is, fluidity). Is used). In the present embodiment, an example in which a thermosetting resin paste is used as the curable resin paste has been shown. However, for example, a photocurable resin paste can be used, and in that case, the same effect can be obtained. Can do.

そして、塗布された熱硬化性樹脂ペースト１１の上から、図３のようにバンプ６（第２電極）を有する駆動ＩＣ７を、ＴＦＴ基板１０に圧着させる。上記のように、ＡＣＦ８および熱硬化性樹脂ペースト１１の未硬化状態では、熱硬化性樹脂ペースト１１がＡＣＦ８よりも粘度が低い。そのため、駆動ＩＣ７をＴＦＴ基板１０に押圧するときには、ＡＣＦ８が（バンプ６が圧入する部分を除いて）押し広げられることなく、余剰の熱硬化性樹脂ペースト１１が駆動ＩＣ７の下から外へ排出され、その残りが駆動ＩＣ８とＡＣＦ８との間に残る。このときバンプ６とＩＴＯ電極５間にＡＣＦ８中の導電粒子８１が挟まれることにより電気的な導通が発現する。そして加熱ツール（不図示）により加熱、加圧することにより、ＡＣＦ８の接着樹脂８０および熱硬化性樹脂ペースト１１が硬化する。その結果、バンプ６とＩＴＯ電極５間に導電粒子８１が捕捉された状態で、駆動ＩＣ７がＴＦＴ基板１０上に保持されるので、ＩＴＯ電極５とバンプ６との間の導通が保たれる。以上により、駆動ＩＣ７のＴＦＴ基板１０への熱圧着工程が完了する。   Then, a driving IC 7 having bumps 6 (second electrodes) as shown in FIG. 3 is pressure-bonded to the TFT substrate 10 from above the applied thermosetting resin paste 11. As described above, in the uncured state of ACF 8 and thermosetting resin paste 11, thermosetting resin paste 11 has a lower viscosity than ACF 8. Therefore, when the driving IC 7 is pressed against the TFT substrate 10, the surplus thermosetting resin paste 11 is discharged from the bottom of the driving IC 7 without the ACF 8 being expanded (except for the portion where the bump 6 is press-fitted). The rest remains between the driving IC 8 and the ACF 8. At this time, when the conductive particles 81 in the ACF 8 are sandwiched between the bump 6 and the ITO electrode 5, electrical conduction is developed. The ACF 8 adhesive resin 80 and the thermosetting resin paste 11 are cured by heating and pressing with a heating tool (not shown). As a result, the drive IC 7 is held on the TFT substrate 10 in a state where the conductive particles 81 are captured between the bump 6 and the ITO electrode 5, so that conduction between the ITO electrode 5 and the bump 6 is maintained. Thus, the thermocompression bonding process of the driving IC 7 to the TFT substrate 10 is completed.

上記のように本実施の形態においては、駆動ＩＣ７をＴＦＴ基板１０に押圧するときには、ＡＣＦ８が押し広げられることなく、余剰の熱硬化性樹脂ペースト１１がＩＣの下から外へ排出される。つまりＡＣＦ８の膜厚は、駆動ＩＣ７がＴＦＴ基板１０に圧着される前後でほぼ同じに保たれる。よって、バンプ６とＩＴＯ電極５との間の導電粒子８１の数の減少が防止され、その間での導電粒子８１の捕捉数の減少が抑えられる。従って、ＡＣＦ８内の導電粒子８１の密度を極度に上げることなく、バンプ６とＩＴＯ電極５との間で良好な電気的接続が得られるため、隣接するバンプ６の間のショートも防止することができる。   As described above, in this embodiment, when the driving IC 7 is pressed against the TFT substrate 10, the surplus thermosetting resin paste 11 is discharged from below the IC without the ACF 8 being spread. That is, the film thickness of the ACF 8 is kept substantially the same before and after the driving IC 7 is pressure-bonded to the TFT substrate 10. Therefore, a decrease in the number of conductive particles 81 between the bump 6 and the ITO electrode 5 is prevented, and a decrease in the number of captured conductive particles 81 between them is suppressed. Therefore, since a good electrical connection can be obtained between the bump 6 and the ITO electrode 5 without extremely increasing the density of the conductive particles 81 in the ACF 8, it is possible to prevent a short circuit between the adjacent bumps 6. it can.

また、熱圧着後においては、図３のようにＴＦＴ基板１０上のＡＣＦ８と駆動ＩＣ７との間に熱硬化性樹脂ペースト１１が硬化した樹脂層が残存する。つまり駆動ＩＣ７とＴＦＴ基板１０との間が、全てＡＣＦ８によって充填されるのではなく、導電粒子８１を含むＡＣＦ８の層と導電粒子８１を含まない熱硬化性樹脂ペースト１１の層の２層の樹脂層により充填されることになる。従って、結果的に２層構造のＡＣＦを用いた場合と同様に、隣接するバンプ６間の導電粒子８１の数は１層構造のＡＣＦの場合に比べて少ない。本発明ではその点においても、隣接するバンプ６の間のショートを防止する効果が得られる。熱硬化性樹脂ペースト１１の端面はＡＣＦ８の端面と揃える必要はないため、塗布の仕方に熟練が要求されない。またここでは、塗布された熱硬化性樹脂ペースト１１の面積は、駆動ＩＣ７の面積と同程度であり、熱硬化性樹脂ペースト１１の使用量を少量で済ますことができる。   Further, after thermocompression bonding, a resin layer in which the thermosetting resin paste 11 is cured remains between the ACF 8 on the TFT substrate 10 and the drive IC 7 as shown in FIG. That is, the space between the driving IC 7 and the TFT substrate 10 is not completely filled with the ACF 8, but the two-layer resin of the ACF 8 layer including the conductive particles 81 and the thermosetting resin paste 11 layer not including the conductive particles 81. It will be filled by the layer. Therefore, as a result, the number of conductive particles 81 between adjacent bumps 6 is smaller than that in the case of the ACF having the single layer structure, as in the case of using the ACF having the two layer structure. In the present invention, the effect of preventing a short circuit between adjacent bumps 6 can be obtained also in this respect. Since the end face of the thermosetting resin paste 11 does not need to be aligned with the end face of the ACF 8, skill is not required in the application method. Here, the area of the applied thermosetting resin paste 11 is almost the same as the area of the driving IC 7, and the amount of the thermosetting resin paste 11 used can be reduced.

図４は、本発明を用いたＣＯＧ実装方式により駆動ＩＣを実装する小型のＴＦＴ液晶表示装置の構成例を示す図である。同図において、図３に示したものと同様の機能を有する要素には同一符号を付してある。ＴＦＴ基板１０とＣＦ基板１２との間に液晶が挟まれている。ＣＦ基板１２表面およびＴＦＴ基板１０裏面には、偏光板１３が貼られている。ＴＦＴ基板１０上には、画素へ信号を供給するための配線が形成されており、パネル端部におけるＴＦＴ基板１０が張り出した部分に当該配線に信号を入力するためのパネル電極（パッド）が配置され、当該パネル電極上にＡＣＦ８が貼られる。そして当該ＡＣＦ８の上に熱硬化性樹脂ペースト１１が塗布され、この熱硬化性樹脂ペースト１１の上に駆動ＩＣ７が実装されている。駆動ＩＣ７のパネル端側には、駆動ＩＣ７へ信号を入力するためのＦＰＣ（Flexible Printed Circuit）１４が配置されている。ＦＰＣ１４は、ＡＣＦ１５を介してＴＦＴ基板１０上の配線と接続されている。図示は省略するが、ＴＦＴ基板１０の張り出し部分には、これら駆動ＩＣ７、ＡＣＦ８，１５およびＦＰＣ１４の上から防湿樹脂を塗布してもよい。ここでは、熱硬化性樹脂ペースト１１を、ＡＣＦ８よりも広い面積にわたって塗布した。ＡＣＦ８からはみ出た部分の熱硬化性樹脂ペースト１１は駆動ＩＣ７とＴＦＴ基板１０との固定を強固なものにする。この場合も、ＡＣＦ８の端面と熱硬化性樹脂ペースト１１の端面とは揃える必要がなく、塗布に熟練を要しない。   FIG. 4 is a diagram showing a configuration example of a small TFT liquid crystal display device in which a driving IC is mounted by a COG mounting method using the present invention. In the figure, elements having the same functions as those shown in FIG. A liquid crystal is sandwiched between the TFT substrate 10 and the CF substrate 12. A polarizing plate 13 is attached to the front surface of the CF substrate 12 and the back surface of the TFT substrate 10. A wiring for supplying a signal to the pixel is formed on the TFT substrate 10, and a panel electrode (pad) for inputting a signal to the wiring is arranged at a portion where the TFT substrate 10 protrudes at the end of the panel. Then, ACF8 is stuck on the panel electrode. A thermosetting resin paste 11 is applied on the ACF 8, and the driving IC 7 is mounted on the thermosetting resin paste 11. An FPC (Flexible Printed Circuit) 14 for inputting a signal to the drive IC 7 is disposed on the panel end side of the drive IC 7. The FPC 14 is connected to the wiring on the TFT substrate 10 via the ACF 15. Although illustration is omitted, a moisture-proof resin may be applied to the overhanging portion of the TFT substrate 10 from above the driving IC 7, ACF 8, 15 and FPC 14. Here, the thermosetting resin paste 11 was applied over a larger area than the ACF 8. The portion of the thermosetting resin paste 11 protruding from the ACF 8 makes the drive IC 7 and the TFT substrate 10 firmly fixed. Also in this case, the end face of the ACF 8 and the end face of the thermosetting resin paste 11 do not need to be aligned, and skill is not required for application.

以上のように、本発明によればＴＦＴ基板１０上にＡＣＦ８を用いて駆動ＩＣ７を熱圧着する際に、バンプ６上のＩＴＯ電極５と駆動ＩＣ７のバンプ６との間の導電粒子の捕捉数を向上させることができると共に、隣接するバンプ６間のショートを防止することができる。   As described above, according to the present invention, the number of trapped conductive particles between the ITO electrode 5 on the bump 6 and the bump 6 of the drive IC 7 when the drive IC 7 is thermocompression bonded on the TFT substrate 10 using the ACF 8. Can be improved, and a short circuit between adjacent bumps 6 can be prevented.

なお、本実施の形態においては、液晶表示パネルのＴＦＴ基板と駆動ＩＣとの熱圧着工程を例にして説明したが、本発明の適用はこれに限られるものではない。例えば、液晶表示パネルではなくエレクトロルミネセンス（ＥＬ）素子を用いた表示パネルの製造工程に適用してもよい。また半導体素子と絶縁基板間の接続に限らず、半導体素子と回路基板間の接続や、回路基板同士の接続など、電極間をＡＣＦを用いた熱圧着工程が含まれるあらゆる技術に応用することが可能である。   In the present embodiment, the thermocompression bonding process between the TFT substrate of the liquid crystal display panel and the driving IC has been described as an example, but the application of the present invention is not limited to this. For example, you may apply to the manufacturing process of the display panel using an electroluminescent (EL) element instead of a liquid crystal display panel. Moreover, the present invention is not limited to the connection between a semiconductor element and an insulating substrate, but can be applied to any technology including a thermocompression bonding process using an ACF between electrodes, such as a connection between a semiconductor element and a circuit board or a connection between circuit boards. Is possible.

本発明の実施の形態に係る半導体装置の製造方法の工程図である。It is process drawing of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の製造方法の工程図である。It is process drawing of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の製造方法の工程図である。It is process drawing of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明に係る半導体装置の製造方法を用いて形成されるＴＦＴ液晶表示装置の構成例を示す図である。It is a figure which shows the structural example of the TFT liquid crystal display device formed using the manufacturing method of the semiconductor device which concerns on this invention.

符号の説明Explanation of symbols

１ 絶縁基板、２ 第１絶縁膜、３ ソース配線、４ 第２絶縁膜、５ ＩＴＯ（電極パッド）、６ バンプ、７ 駆動ＩＣ、８，１５ ＡＣＦ、１０ ＴＦＴ基板、１１ 熱硬化性樹脂ペースト、１２ ＣＦ基板、１３ 偏光板、１４ ＦＰＣ、８０ 接着樹脂、８１ 導電粒子。
DESCRIPTION OF SYMBOLS 1 Insulating substrate, 2 1st insulating film, 3 Source wiring, 4 2nd insulating film, 5 ITO (electrode pad), 6 Bump, 7 Drive IC, 8,15 ACF, 10 TFT substrate, 11 Thermosetting resin paste, 12 CF substrate, 13 polarizing plate, 14 FPC, 80 adhesive resin, 81 conductive particles.

Claims (3)

（ａ）表面上に電極が形成された第１基板に、異方性導電膜を貼り付ける工程と、
（ｂ）前記異方性導電膜上に硬化性樹脂ペーストを塗布する工程と、
（ｃ）前記第１基板に第２基板あるいは半導体素子を重ね合わせ、前記硬化性樹脂ペーストを硬化する工程とを備える
ことを特徴とする半導体装置の製造方法。 (A) attaching an anisotropic conductive film to a first substrate having an electrode formed on the surface;
(B) applying a curable resin paste on the anisotropic conductive film;
(C) A method of manufacturing a semiconductor device comprising: a step of superposing a second substrate or a semiconductor element on the first substrate and curing the curable resin paste. 前記硬化性樹脂ペーストの粘度が、前記異方性導電膜の粘度よりも低い
ことを特徴とする請求項１記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 1, wherein the viscosity of the curable resin paste is lower than the viscosity of the anisotropic conductive film. 表面上に電極が形成された第１基板と、
前記第１基板上に形成された異方性導電膜と、
前記異方性導電膜上に、硬化性樹脂ペーストを塗布して実装された第２基板あるいは半導体素子とを備える
ことを特徴とする半導体装置。
A first substrate having an electrode formed on the surface;
An anisotropic conductive film formed on the first substrate;
A semiconductor device comprising: a second substrate or a semiconductor element mounted by applying a curable resin paste on the anisotropic conductive film.
JP2006197983A 2006-07-20 2006-07-20 Semiconductor device and its manufacturing method Pending JP2008028081A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101509425B1 (en) * 2013-08-29 2015-04-08 (주)에프씨아이 Semiconductor Structure Including Conductive Film

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101509425B1 (en) * 2013-08-29 2015-04-08 (주)에프씨아이 Semiconductor Structure Including Conductive Film

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