TW201507085A - Power controller device and fabricating method thereof - Google Patents

Power controller device and fabricating method thereof Download PDF

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TW201507085A
TW201507085A TW102128297A TW102128297A TW201507085A TW 201507085 A TW201507085 A TW 201507085A TW 102128297 A TW102128297 A TW 102128297A TW 102128297 A TW102128297 A TW 102128297A TW 201507085 A TW201507085 A TW 201507085A
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pin
pins
wafer
carrier
row
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TW102128297A
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TWI518860B (en
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薛彥迅
哈姆紮 耶爾馬茲
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萬國半導體股份有限公司
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  • Power Engineering (AREA)
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Abstract

The present invention is directed to a method for forming power controller components integrating a low side MOSFET and a high side MOSFET and a control IC. Bonding a first chip and a second chip onto a metal paddle of a installation unit, and bonding the control IC onto a first row support leads and a second row support leads, while a main electrode of the first chip is configured to be connect to a first lead near the paddle through a metal clip and a main electrode of the second chip is configured to be connect to a second lead near the paddle through another metal clip.

Description

功率控制器件及其製備方法Power control device and preparation method thereof

本發明一般涉及一種電源管理器件，尤其是涉及高端、低端MOSFET集成控制IC的功率控制器件及其製備方法。
The present invention generally relates to a power management device, and more particularly to a power control device for a high-end, low-side MOSFET integrated control IC and a method of fabricating the same.

在DC-DC之類的電源控制器件中，處於工作態的晶片的功耗比較大，往往要求晶片的源極端或漏極端能具有較好的熱量消散效果，而使得部分引線框架裸露至塑封體之外。例如在圖1所示的一種含有高端MOSFET 11和低端MOSFET 13的DC-DC變換器10，變換器10還包含有一個控制晶片12，控制晶片12輸出PWM或PFM信號至MOSFET 11、13並接收它們的回饋信號，所以MOSFET 11、13的一部分電極焊墊與控制晶片12的I/O焊墊之間還通過多條鍵合線實施電性連接。其中，MOSFET 11、13分別粘貼在分隔開的基座21、23上，MOSFET 11的源極端通過金屬片15連接到基座23上，MOSFET 13的源極通過金屬片16連接到引腳24上，而控制晶片12則粘貼在另一孤立的基座22上，基座21、23底面將裸露在圖中未示意出的塑封體的之外，用作與外部電路進行電性接觸的埠和散熱的主要途徑。較為明顯的是，基座21、22、23佔有較大的面積，這不僅導致成本不菲而且抑制了市場對器件的輕小化的主流要求。此外，美國專利申請US2012061813A1亦公開了一種DC-DC轉換器，其並排的高端、低端MOSFET位於基座上，而將控制器件完全疊加至高端、低端MOSFET之上，這就要求下方的MOSFET的引線必須有較低的線弧高度值，否則控制晶片容易觸及到其下方的金屬引線，其另一個不良後果是，高端、低端MOSFET在各自上方一側的散熱途徑被控制晶片完全隔斷。
正是基於以上問題的考慮，提出了本申請後續的各種實施方式。

In a power control device such as a DC-DC, the power consumption of a wafer in an active state is relatively large, and the source terminal or the drain terminal of the wafer is required to have a good heat dissipation effect, so that part of the lead frame is exposed to the plastic body. Outside. For example, in a DC-DC converter 10 including a high-side MOSFET 11 and a low-side MOSFET 13 shown in FIG. 1, the converter 10 further includes a control wafer 12 that outputs a PWM or PFM signal to the MOSFETs 11, 13 and The feedback signals are received, so that a part of the electrode pads of the MOSFETs 11, 13 and the I/O pads of the control wafer 12 are electrically connected by a plurality of bonding wires. The MOSFETs 11 and 13 are respectively attached to the separated pedestals 21 and 23, the source terminal of the MOSFET 11 is connected to the susceptor 23 through the metal piece 15, and the source of the MOSFET 13 is connected to the pin 24 through the metal piece 16. Above, the control wafer 12 is pasted on another isolated pedestal 22, and the bottom surfaces of the pedestals 21, 23 are exposed outside the molding body not shown in the figure, and are used as electrical contacts with external circuits. And the main way of cooling. More obviously, the pedestals 21, 22, and 23 occupy a large area, which not only causes costly but also suppresses the mainstream demand for the device to be lighter. In addition, U.S. Patent Application No. US2012061813A1 also discloses a DC-DC converter in which the side-by-side high-side, low-side MOSFET is placed on the pedestal and the control device is completely superimposed on the high-side, low-side MOSFET, which requires the underlying MOSFET. The leads must have a lower line arc height value, otherwise the control chip can easily reach the metal leads underneath it. Another negative consequence is that the heat dissipation paths of the high-side, low-side MOSFETs on the respective upper sides are completely blocked by the control wafer.
Based on the above considerations, various embodiments subsequent to the present application have been proposed.

在一種實施方式中，功率控制器件包括：一晶片安裝單元和一控制晶片及第一、第二晶片，該晶片安裝單元包括一基座和基座附近的第一、第二引腳及第一、第二排承載引腳；基座具有相對的一組第一、第二橫向邊緣及相對的一組第一、第二縱向邊緣，其中，第一引腳鄰近第一橫向邊緣並且其條狀鍵合區沿第一橫向邊緣長度方向延伸，第二引腳鄰近第二橫向邊緣並且其條狀鍵合區沿第二橫向邊緣長度方向延伸；第一、第二排承載引腳位於基座的第二縱向邊緣的一側，且第一排承載引腳中的每一個承載引腳皆平行於第二縱向邊緣並由第一引腳的橫向延長線上向第一、第二橫向邊緣之間的對稱中心線延伸，及第二排承載引腳中的每一個承載引腳皆平行於第二縱向邊緣並由第二引腳的橫向延長線上向所述對稱中心線延伸；第一、第二晶片均安裝在基座之上，控制晶片安裝在第一、第二排承載引腳之上，並且第一晶片正面的一個主電極通過一第一金屬片電性連接到第一引腳上，第二晶片正面的一個主電極通過一第二金屬片電性連接到第二引腳上。
上述功率控制器件，基座具有一個連接部，從基座位於第二縱向邊緣的一側的頂部向第一排承載引腳中最內側的一個承載引腳延伸，並與其連接。第一、第二晶片均粘附在基座的頂面上，使第一、第二晶片各自背面的背部電極均粘附在基座的頂面。
第一、第二排承載引腳各自的每個承載引腳均皆包括相互連接的一個上置引腳和一個下置引腳，承載引腳的上置引腳的頂面均與第一、第二晶片各自的正面共面；控制晶片以向第一、第二晶片偏移的方式倒裝安裝在第一、第二排承載引腳上，偏移程度為使其具有與第一、第二晶片形成交疊的交疊部分，使交疊部分正面的多個焊墊上相應設置的多個金屬凸塊分別對準並電性連接至第一、第二晶片各自正面的主電極、副電極；控制晶片餘下的焊墊上設置的金屬凸塊分別對準並電性連接至相應的各上置引腳上。
上述功率控制器件，還包括一個將晶片安裝單元、第一和第二晶片、控制晶片、第一和第二金屬片及各金屬凸塊予以包覆的塑封體，其包覆方式至少使各下置引腳的底面、基座的底面、第一和第二引腳各自的底面從塑封體的底面中外露。
上述功率控制器件，其特徵在於，在基座的頂面上設置有一個凹槽，第一、第二晶片均位於在凹槽內，使第一、第二晶片各自的背部電極均粘附在凹槽的底部，且第一、第二排承載引腳各自的每個承載引腳的頂面均與第一、第二晶片各自的正面共面。
上述功率控制器件，控制晶片以向第一、第二晶片偏移的方式倒裝安裝在第一、第二排承載引腳上，偏移程度為使其具有與第一、第二晶片形成交疊的交疊部分，使交疊部分正面的多個焊墊上設置的多個金屬凸塊分別對準並電性連接至第一、第二晶片各自正面的主電極、副電極；控制晶片餘下的焊墊上設置的金屬凸塊分別對準並電性連接至相應的各承載引腳上。
上述功率控制器件，還包括一個將晶片安裝單元、第一和第二晶片、控制晶片、第一和第二金屬片及各金屬凸塊予以包覆的塑封體，其包覆方式至少使各承載引腳的底面、基座的底面、第一和第二引腳各自的底面從塑封體的底面中外露。
上述功率控制器件，第一、第二金屬片各包括一個主平板部分和連接在其一側的相對主平板部分具有高度落差的一個副平板部分，以及第一、第二金屬片各自的主平板部分的底面上均設置有一個垂直向下延伸的端部；其中，第一、第二金屬片各自的端部的底端面分別與第一、第二晶片的主電極焊接，第一、第二金屬片各自的副平板部分分別與第一、第二引腳的鍵合區焊接。
上述功率控制器件，還包括一個將晶片安裝單元、第一和第二晶片、控制晶片、第一和第二金屬片及各金屬凸塊予以包覆的塑封體；其中控制晶片的背面與第一、第二金屬片各自的主平板部分的頂面共面，並且所述塑封體的包覆方式至少使各承載引腳的底面、基座的底面、第一和第二引腳各自的底面從塑封體的底面外露，和使第一、第二金屬片各自主平板部分的頂面、控制晶片的背面從塑封體的頂面外露。
上述的功率控制器件，第一、第二晶片均粘附在基座的頂面上，使第一、第二晶片各自背面的背部電極均粘附在基座的頂面；控制晶片倒裝安裝在第一、第二排承載引腳上，其正面的各焊墊上設置的金屬凸塊分別對準並電性連接至相應的各承載引腳上。
上述功率控制器件，第一、第二引腳各自沿第一、第二橫向邊緣的長度方向延伸的長度值分別小於第一、第二橫向邊緣的長度值；晶片安裝單元包括在第一引腳的長度方向的延長線上設置的一個靠近第一橫向邊緣的第一旁路引腳，位於第一排承載引腳的最內側的承載引腳和第一引腳之間，第一旁路引腳帶有一個連接部，從第一旁路引腳靠近第一排承載引腳中最內側的承載引腳的一側的頂部向該承載引腳延伸，並與其連接；晶片安裝單元包括在第二引腳的長度方向的延長線上設置的一個靠近第二橫向邊緣的第二旁路引腳，位於第二排承載引腳的最內側的承載引腳和第二引腳之間，第二旁路引腳帶有一個連接部，從第二旁路引腳靠近第二排承載引腳中最內側的承載引腳的一側的頂部向該承載引腳延伸，並與其連接；第一、第二晶片正面的副電極分別通過導電結構電性連接到第一、第二旁路引腳上；晶片安裝單元還包括一個L形的連接結構，將第一、第二排承載引腳中除了各自最內側的承載引腳之外的任意一承載引腳電性連接至基座的第二縱向邊緣上。
上述功率控制器件，利用鍵合引線，將第一晶片的正面的副電極電性連接至第一排承載引腳中任意一承載引腳上，將第二晶片正面的副電極、基座的頂面分別電性連接至第二排承載引腳中任意兩個不同的承載引腳上。
上述功率控制器件，第一、第二晶片均粘附在基座的頂面上，使第一、第二晶片各自背面的背部電極均粘附在基座的頂面；控制晶片的背面粘附在第一、第二排承載引腳上，利用鍵合引線，將第一、第二晶片各自正面的副電極和基座的頂面分別電性連接至控制晶片正面的相應焊墊上，將控制晶片正面餘下的多個焊墊分別電性連接至相對應的各承載引腳的頂面上。
在一種實施方式中，功率控制器件包括：一晶片安裝單元和一控制晶片及第一、第二晶片，該晶片安裝單元包括相鄰的第一、第二基座，並包括第一基座附近的第一引腳及第一排承載引腳，和包括第二基座附近的第二引腳及第二排承載引腳；第一、第二基座各自均具有相對的一組第一、第二橫向邊緣及相對的一組第一、第二縱向邊緣，第一引腳靠近第一基座的第一橫向邊緣並且其條狀鍵合區沿第一基座的第一橫向邊緣長度方向延伸，第二引腳靠近第二基座的第二橫向邊緣並且其條狀鍵合區沿第二基座的第二橫向邊緣長度方向延伸；第一排承載引腳位於第一基座的第二縱向邊緣的一側，且第一排承載引腳中的每一個承載引腳均平行於第一基座的第二縱向邊緣，並由第一引腳的橫向延長線上向第一基座、第二基座之間的分割線延伸；第二排承載引腳位於第二基座的第二縱向邊緣的一側，且第二排承載引腳中的每一個承載引腳均平行於第二基座的第二縱向邊緣，並由第二引腳的橫向延長線上向所述分割線延伸；其中，第一、第二晶片分別安裝在第一、第二基座之上，使第一、第二晶片各自背面的背部電極分別粘附在第一、第二基座的頂面，通過一金屬片將第一、第二晶片各自正面的主電極與第二引腳進行電性連接，控制晶片安裝在第一、第二排承載引腳之上。
上述功率控制器件，第二引腳帶有一個連接部，從第二引腳的鍵合區的頂部靠近第二排承載引腳中最內側的承載引腳的一側向該最內側的承載引腳延伸，並與其連接；第一、第二排承載引腳各自的每個承載引腳均皆包括相互連接的一個上置引腳和一個下置引腳，並且所有承載引腳的上置引腳的頂面均與第一、第二晶片各自的正面共面；控制晶片以向第一、第二晶片偏移的方式倒裝安裝在第一、第二排承載引腳上，偏移程度為使其具有與第一、第二晶片形成交疊的交疊部分，使交疊部分正面的多個焊墊上設置的多個金屬凸塊分別對準並電性連接至第一、第二晶片各自正面的主電極、副電極；控制晶片餘下的焊墊上設置的金屬凸塊分別對準並電性連接至相應的各上置引腳上。
上述功率控制器件，第一基座具有一個連接部，從第一基座的頂部位於其第一橫向邊緣的一側向第一引腳延伸，並與其連接。
上述功率控制器件，控制晶片倒裝安裝在第一、第二排承載引腳上，其正面的多個焊墊上相應設置的多個金屬凸塊分別對準並電性連接至各相應的承載引腳上；所述金屬片還電性連接到第一引腳上。
上述功率控制器件，第一引腳沿第一基座的第一橫向邊緣的長度方向延伸的長度值小於第一基座的第一橫向邊緣的長度值，第二引腳沿第二基座的第二橫向邊緣的長度方向延伸的長度值小於第二基座的第二橫向邊緣的長度值；晶片安裝單元包括在第一引腳的延長線上設置的一個靠近第一橫向邊緣的第一旁路引腳，位於第一排承載引腳的最內側的一個承載引腳和第一引腳之間，並且第一旁路引腳帶有一個連接部，從第一旁路引腳靠近第一排承載引腳的最內側的承載引腳的一側的頂部向該承載引腳延伸，並與其連接；晶片安裝單元包括在第二引腳的延長線上設置的一個靠近第二橫向邊緣的第二旁路引腳，位於第二排承載引腳的最內側的一個承載引腳和第二引腳之間，並且第二旁路引腳帶有一個連接部，從第二旁路引腳靠近第二排承載引腳的最內側的一個承載引腳的一側的頂部向該承載引腳延伸，並與其連接；第一、第二晶片正面的副電極分別通過導電結構電性連接到第一、第二旁路引腳上，並利用鍵合引線將第二引腳或第二晶片的主電極電性連接到第二排承載引腳中除最內側的承載引腳以外的任意一承載引腳上。
上述功率控制器件，利用鍵合引線，將第一晶片的副電極電性連接至第一排承載引腳中任意一承載引腳上，將第二晶片的正、副電極分別相對應的電性連接至第二排承載引腳中任意兩個不同的承載引腳上。
上述功率控制器件，控制晶片的背面粘附在第一、第二排承載引腳上；利用鍵合引線，將第一、第二晶片各自的副電極、第二晶片的主電極分別電性連接至控制晶片正面的相對應的焊墊上，將控制晶片正面餘下的多個焊墊分別連接至相對應的各承載引腳的頂面上。
在一種實施方式中，功率控制器包括：一晶片安裝單元和一控制晶片及第一、第二晶片，該晶片安裝單元包括相鄰的第一、第二基座，並包括第一基座附近的第一引腳及第一排承載引腳，和包括第二基座附近的第二引腳及第二排承載引腳；第一、第二基座各自均具有相對的一組第一、第二橫向邊緣及相對的一組第一、第二縱向邊緣，第一引腳靠近第一基座的第一橫向邊緣且其條狀鍵合區沿第一基座的第一橫向邊緣的長度方向延伸，第二引腳靠近第二基座的第二橫向邊緣且其條狀鍵合區沿第二基座的第二橫向邊緣的長度方向延伸；第一排承載引腳位於第一基座的第二縱向邊緣的一側，且第一排承載引腳中的每一個承載引腳均平行於第一基座的第二縱向邊緣，並由第一引腳的具有第一方向（例如X正軸）的橫向延長線上向第一基座和第二基座之間的分割線延伸；及第二排承載引腳位於第二基座的第二縱向邊緣的一側，且第二排承載引腳中的每一個承載引腳均平行於第二基座的第二縱向邊緣，並由第二引腳的與第一方向同向的橫向延長線上向所述分割線延伸；實質為矩形狀的第二基座在其第一橫向邊緣與第二縱向邊緣交叉的拐角處具有一個矩形切口而使第二基座形成L形結構，並在該切口中嵌入有一個基島；第一晶片安裝在第一基座上使其背面的背部電極粘附至第一基座的頂面，第二晶片倒裝安裝在第二基座和基島之上使其主、副電極分別粘附在第二基座、基島的頂面上，控制晶片安裝在第一、第二排承載引腳之上；利用一金屬片將第一晶片正面的主電極和第二晶片背面的背部電極電性連接第二引腳上。
上述功率控制器件，所述第一基座具有一個連接部，從第一基座的頂部位於第一橫向邊緣的一側向第一引腳延伸，並與其連接。
上述的功率控制器件，其特徵在於，第一、第二排承載引腳各自的每個承載引腳均皆包括相互連接的一個上置引腳和一個下置引腳，所有承載引腳的上置引腳的頂面均與第一晶片的正面、第二晶片的背面共面；晶片安裝單元包括一連接結構，該連接結構的水平延伸段對接在除第二排承載引腳最內側的承載引腳以外的第一、第二排承載引腳中任意一個承載引腳的上置部分上，其與水平面成夾角的傾斜延伸段垂直于水平延伸段並連接在水平延伸段和基島之間；控制晶片以向第一、第二晶片偏移的方式倒裝安裝在第一、第二排承載引腳上，偏移程度為使其具有與第一、第二晶片形成交疊的交疊部分，使交疊部分正面的多個焊墊上設置的多個金屬凸塊分別對準並電性連接至第一晶片的主、副電極和第二晶片的背部電極；控制晶片餘下的焊墊上設置的金屬凸塊分別對準並電性連接至各相應的上置引腳上。
上述的功率控制器件，第一引腳沿第一基座的第一橫向邊緣的長度方向延伸的長度值小於第一基座的第一橫向邊緣的長度值；晶片安裝單元包括在第一引腳的橫向延長線上設置的一個靠近第一基座的第一橫向邊緣的第一旁路引腳，位於第一排承載引腳的最內側的一個承載引腳和第一引腳之間，並且第一旁路引腳帶有一個連接部，從第一旁路引腳靠近該最內側的一個承載引腳的一側的頂部向該承載引腳延伸，並與其連接，從而第一晶片的副電極通過一個導電結構電性連接在第一旁路引腳上；晶片安裝單元包括一L形連接結構，該連接結構的縱向延伸段對接在除第一、第二排承載引腳中各自最內側的承載引腳之外的任意一承載引腳上，其橫向延伸段垂直于縱向延伸段並連接在縱向延伸段和基島之間；以及控制晶片倒裝安裝在第一、第二排承載引腳之上，控制晶片的焊墊上設置的金屬凸塊分別對準並電性連接至各相應的承載引腳上。
上述的功率控制器件，控制晶片倒裝安裝在第一、第二排承載引腳之上，第一晶片的副電極通過鍵合引線電性連接在第一排承載引腳中的任意一承載引腳上；晶片安裝單元包括一L形連接結構，該連接結構的縱向延伸段對接在除第二排承載引腳中最內側的承載引腳之外和除第一排承載引腳中連接至第一晶片的副電極的承載引腳以外的第一、第二承載引腳中的餘下的任意一承載引腳上，其橫向延伸段垂直于縱向延伸段並連接在縱向延伸段和基島之間。
上述的功率控制器件，控制晶片的背面粘附在第一、第二排承載引腳上；利用鍵合引線，將第一晶片的副電極、基島分別電性連接至控制晶片正面的相對應的焊墊上，同時利用鍵合引線將控制晶片正面餘下的多個焊墊分別連接至第一、第二排承載引腳中相應的各承載引腳的頂面上。
上述的功率控制器件，第二引腳具有一個連接部，從第二引腳的鍵合區的頂部靠近第二排承載引腳中最內側的一個承載引腳的一側向該最內側的一個承載引腳延伸，並與其連接；所述金屬片還電性連接在第一引腳上。
在一種實施方式中，一種功率控制器件的製備方法，包括以下步驟：步驟S1、提供一晶片安裝單元，包括一基座和基座附近的第一、第二引腳及第一、第二排承載引腳；基座具有相對的一組第一、第二橫向邊緣及相對的一組第一、第二縱向邊緣，第一引腳鄰近第一橫向邊緣並且其條狀鍵合區沿第一橫向邊緣長度方向延伸，第二引腳鄰近第二橫向邊緣並且其條狀鍵合區沿第二橫向邊緣長度方向延伸；第一、第二排承載引腳位於基座的第二縱向邊緣的同一側，且第一排承載引腳中的每個承載引腳均平行於第二縱向邊緣並由第一引腳的橫向延長線上向第一、第二橫向邊緣之間的對稱中心線延伸，及第二排承載引腳中的每一個承載引腳均平行於第二縱向邊緣並由第二引腳的橫向延長線上向所述對稱中心線延伸；步驟S2、將一第一晶片和一第二晶片並排安裝在基座之上，並將一控制晶片安裝在第一、第二排承載引腳之上；步驟S3、利用一個第一金屬片將第一晶片正面的一個主電極電性連接到第一引腳上，利用一個第二金屬片將第二晶片正面的一個主電極電性連接到第二引腳上。
上述的方法，基座具有一個連接部，從基座位於第二縱向邊緣的一側的頂部向第一排承載引腳中靠近第二縱向邊緣的最內側的一個承載引腳延伸，並與其連接。上述的方法，在步驟S2中，將第一、第二晶片粘附在基座的頂面上，使第一、第二晶片各自背面的背部電極均粘附在基座的頂面，其中第一、第二晶片各自的副電極位於各自的正面。
上述的方法，第一、第二排承載引腳各自的每個承載引腳均皆包括相互連接的一個上置引腳和一個下置引腳；在步驟S2中，先使第一、第二晶片各自的正面均與所有承載引腳的上置引腳的頂面共面；然後使控制晶片以向第一、第二晶片偏移的方式倒裝安裝在第一、第二排承載引腳上，使其具有與第一、第二晶片形成交疊的交疊部分，使交疊部分正面的多個焊墊上相應設置的多個金屬凸塊分別對準並電性連接至第一、第二晶片各自的主電極、副電極；同時使控制晶片餘下的焊墊上設置的金屬凸塊分別對準並電性連接至相應的各上置引腳上。
上述的方法，完成步驟S3之後，還包括利用一個塑封體將晶片安裝單元、第一和第二晶片、控制晶片、第一和第二金屬片及各金屬凸塊予以包覆的步驟，其包覆方式至少使各下置引腳的底面、基座的底面、第一和第二引腳各自的底面從塑封體的底面中外露。
上述的方法，預先在基座的頂面上設置一個凹槽，在步驟S2中，第一、第二晶片被安裝在凹槽內，使第一、第二晶片各自背面的背部電極均粘附在凹槽的底部，第一、第二晶片各自的副電極位於各自的正面，使第一、第二晶片各自的正面均與第一、第二排承載引腳各自的每個承載引腳的頂面共面。
上述的方法，在步驟S2中，使控制晶片以向第一、第二晶片偏移的方式倒裝安裝在第一、第二排承載引腳上，使其具有與第一、第二晶片形成交疊的交疊部分，使交疊部分正面的多個焊墊上設置的多個金屬凸塊分別對準並電性連接至第一、第二晶片各自的主電極、副電極；同時使控制晶片餘下的焊墊上設置的金屬凸塊分別對準並電性連接至第一、第二排承載引腳的相應各承載引腳上。
上述的方法，完成步驟S3之後，還包括利用一個塑封體將晶片安裝單元、第一和第二晶片、控制晶片、第一和第二金屬片及各金屬凸塊予以包覆的步驟，其包覆方式至少使各承載引腳的底面、基座的底面、第一和第二引腳各自的底面從塑封體的底面中外露。
上述方法，第一、第二金屬片各包括一個主平板部分和連接在主平板部分一側的一個副平板部分，第一、第二金屬片各自的主平板部分的底面上均設置有一個垂直向下延伸的端部；在步驟S3中，使第一、第二金屬片各自的端部的底端面分別與第一、第二晶片的主電極焊接，第一、第二金屬片各自的副平板部分分別與第一、第二引腳的鍵合區焊接。
上述方法，在步驟S2中，使控制晶片的背面與第一、第二金屬片各自的主平板部分的頂面共面；在完成步驟S3之後，還包括利用一個塑封體將晶片安裝單元、第一和第二晶片、控制晶片、第一和第二金屬片及各金屬凸塊予以包覆的步驟，包覆方式至少使各承載引腳的底面、基座的底面、第一和第二引腳各自的底面從塑封體的底面外露，和使第一、第二金屬片各自主平板部分的頂面、控制晶片的背面從塑封體的頂面外露。
上述的方法，第一引腳沿第一橫向邊緣的長度方向延伸的長度值小於第一橫向邊緣的長度值第二引腳沿第二橫向邊緣的長度方向延伸的長度值小於第二橫向邊緣的長度值；晶片安裝單元包括在第一引腳的橫向延長線上設置的一個靠近第一橫向邊緣的第一旁路引腳，位於第一排承載引腳的最內側的承載引腳和第一引腳之間，第一旁路引腳帶有一個連接部，從第一旁路引腳靠近該最內側的承載引腳的一側的頂部向該承載引腳延伸，並與其連接；晶片安裝單元包括還包括在第二引腳的橫向延長線上設置的一個靠近第二橫向邊緣的第二旁路引腳，位於第二排承載引腳的最內側的承載引腳和第二引腳之間，第二旁路引腳帶有一個連接部，從第二旁路引腳靠近該最內側的承載引腳的一側的頂部向該承載引腳延伸，並與其連接；晶片安裝單元還包括一個L形的連接結構，將第一、第二排承載引腳中除各自最內側的承載引腳以外的任意一承載引腳電性連接至基座上；在步驟S2中，控制晶片倒裝安裝在第一、第二排承載引腳上，其正面的多個焊墊上相應設置的多個金屬凸塊分別對準並電性連接至各相應的承載引腳上；從而在步驟S3中，利用導電結構，將第一、第二晶片各自正面的副電極分別電性連接到第一、第二旁路引腳上。
上述的方法，其特徵在於，在步驟S2中，控制晶片倒裝安裝在第一、第二排承載引腳上，其正面的多個焊墊上相應設置的多個金屬凸塊分別對準並電性連接至各相應的承載引腳上；步驟S3還包括利用鍵合引線，將第一晶片的副電極電性連接至第一排承載引腳中任意一承載引腳上，將第二晶片的副電極、基座的頂面分別電性連接至第二排承載引腳中任意兩個不同承載引腳上的步驟。
上述的方法，在步驟S2中，將控制晶片的背面粘附在第一、第二排承載引腳上；步驟S3還包括，利用鍵合引線，將第一、第二晶片各自的副電極、基座的頂面分別電性連接至控制晶片正面的相對應的焊墊上，同時利用鍵合引線將控制晶片正面餘下的多個焊墊分別連接至相對應的各承載引腳的頂面上。
在一種實施方式中，功率控制器件的製備方法，包括以下步驟：步驟S1、提供一晶片安裝單元，包括相鄰的第一、第二基座，並包括第一基座附近的第一引腳及第一排承載引腳，和包括第二基座附近的第二引腳及第二排承載引腳；第一、第二基座各自均具有相對的一組第一、第二橫向邊緣及相對的一組第一、第二縱向邊緣，第一引腳靠近第一基座的第一橫向邊緣並且其條狀鍵合區沿第一基座的第一橫向邊緣長度方向延伸，第二引腳靠近第二基座的第二橫向邊緣並且其條狀鍵合區沿第二基座的第二橫向邊緣長度方向延伸；第一排承載引腳位於第一基座的第二縱向邊緣的一側，且第一排承載引腳中的每一個承載引腳均平行於第一基座的第二縱向邊緣，並由第一引腳的橫向延長線上向第一基座、第二基座之間的分割線延伸；及第二排承載引腳位於第二基座的第二縱向邊緣的一側，且第二排承載引腳中的每一個承載引腳均平行於第二基座的第二縱向邊緣，並由第二引腳的橫向延長線上向所述分割線延伸；步驟S2、將一第一晶片和一第二晶片分別安裝在第一、第二基座之上，將一控制晶片安裝在第一、第二排承載引腳之上；步驟S3、將一金屬片焊接至第一、第二晶片各自正面的主電極和第二引腳上。
上述的方法，第二引腳具有一個連接部，從第二引腳的鍵合區的頂部靠近第二排承載引腳中最內側的一個承載引腳的一側向該最內側的一個承載引腳延伸，並與其連接；第一、第二排承載引腳各自的每個承載引腳均皆包括相互連接的一個上置引腳和一個下置引腳；在步驟S2中，先使第一、第二晶片各自的正面均與所有承載引腳的上置引腳的頂面共面；然後使控制晶片以向第一、第二晶片偏移的方式倒裝安裝在第一、第二排承載引腳上，使其具有與第一、第二晶片形成交疊的交疊部分，使交疊部分正面的多個焊墊上設置的多個金屬凸塊分別對準並電性連接至第一、第二晶片各自的主電極、副電極，同時使控制晶片餘下的焊墊上設置的金屬凸塊分別對準並電性連接至相應的各上置引腳上。
上述的方法，第一基座具有一個連接部，從第一基座的頂部位於其第一橫向邊緣的一側向第一引腳延伸，並與其連接。
上述的方法，第一引腳沿第一橫向邊緣的長度方向延伸的長度值分別小於第一橫向邊緣的長度值，第二引腳沿第二橫向邊緣的長度方向延伸的長度值分別小於第二橫向邊緣的長度值；晶片安裝單元包括在第一引腳的延長線上設置的一個靠近第一橫向邊緣的第一旁路引腳，位於第一排承載引腳的最內側的承載引腳和第一引腳之間，第一旁路引腳帶有一個連接部，從第一旁路引腳靠近該最內側的承載引腳的一側的頂部向該承載引腳延伸，並與其連接；晶片安裝單元還包括在第二引腳的延長線上設置有一個靠近第二橫向邊緣的第二旁路引腳，位於第二排承載引腳的最內側的承載引腳和第二引腳之間，第二旁路引腳帶有一個連接部，從第二旁路引腳靠近該最內側的一個承載引腳的一側的頂部向該承載引腳延伸，並與其連接；在步驟S2中，將控制晶片倒裝安裝在第一、第二排承載引腳上，其正面的多個焊墊上相應設置的多個金屬凸塊分別對準並電性連接至各相應的承載引腳上；在步驟S3中，金屬片同時還電性連接到第一引腳上，同時利用導電結構將第一、第二晶片的副電極分別電性連接到第一、第二旁路引腳上，並利用鍵合引線將第二引腳電性連接到第二排承載引腳中除最內側的承載引腳以外的任意一承載引腳上。
上述的方法，在步驟S2中，將控制晶片倒裝安裝在第一、第二排承載引腳上，其正面的多個焊墊上相應設置的多個金屬凸塊分別對準並電性連接至各相應的承載引腳上；在步驟S3中，金屬片還電性連接到第一引腳上，並利用鍵合引線，將第一晶片的副電極電性連接至第一排承載引腳中任意一承載引腳上，將第二晶片的正、副電極分別相對應的電性連接至第二排承載引腳中任意兩個不同的承載引腳上。
上述方法，步驟S2中，使控制晶片的背面粘附在第一、第二排承載引腳上；在步驟S3中，金屬片同時還被電性連接到第一引腳上，之後利用鍵合引線，將第一、第二晶片各自的副電極、第二晶片的主電極分別電性連接至控制晶片正面的相對應的焊墊上，同時利用鍵合引線將控制晶片正面餘下的多個焊墊分別連接至相對應的各承載引腳的頂面上。
在一種實施方式中，一種功率控制器件的製備方法包括以下步驟：步驟S1、提供一晶片安裝單元，該晶片安裝單元包括相鄰的第一、第二基座，並包括第一基座附近的第一引腳及第一排承載引腳，和包括第二基座附近的第二引腳及第二排承載引腳；第一、第二基座各自均具有相對的一組第一、第二橫向邊緣及相對的一組第一、第二縱向邊緣，第一引腳靠近第一基座的第一橫向邊緣並且其條狀鍵合區沿第一基座的第一橫向邊緣的長度方向延伸，第二引腳靠近第二基座的第二橫向邊緣並且其條狀鍵合區沿第二基座的第二橫向邊緣的長度方向延伸；第一排承載引腳位於第一基座的第二縱向邊緣的一側，且第一排承載引腳中的每一個承載引腳均平行於第一基座的第二縱向邊緣，並由第一引腳的橫向延長線上向第一基座和第二基座之間的分割線延伸；及第二排承載引腳位於第二基座的第二縱向邊緣的一側，且第二排承載引腳中的每一個承載引腳均平行於第二基座的第二縱向邊緣，並由第二引腳的橫向延長線上向所述分割線延伸；其中，實質為矩形狀的第二基座在其第一橫向邊緣與第二縱向邊緣交叉的拐角處具有一個矩形切口而使第二基座形成L形結構，並在該切口中嵌入有一個基島；步驟S2、將一第一晶片安裝在第一基座上，將一第二晶片倒裝安裝在第二基座和基島之上，將一控制晶片安裝在第一、第二排承載引腳之上；步驟S3、利用一金屬片將第一晶片正面的一個主電極電性連接到第二晶片背面的一個背部電極和第二引腳上。
上述的方法，所述第一基座具有一個連接部，從第一基座的頂部位於第一橫向邊緣的一側向第一引腳延伸，並與其連接。
上述的方法，第一、第二排承載引腳各自的每個承載引腳均皆包括相互連接的一個上置引腳和一個下置引腳；晶片安裝單元包括一連接結構，其水平延伸段對接在除第二排承載引腳最內側的承載引腳之外的第一、第二排承載引腳中任意一承載引腳的上置部分，其與水平面成夾角設置的傾斜延伸段垂直于水平延伸段並連接在水平延伸段和基島之間；在步驟S2中，使第一晶片的正面、第二晶片的背面與所有承載引腳的上置引腳的頂面均共面；然後使控制晶片以向第一、第二晶片偏移的方式倒裝安裝在第一、第二排承載引腳上，使其具有與第一、第二晶片形成交疊的交疊部分，使交疊部分正面的多個焊墊上設置的多個金屬凸塊分別對準並電性連接至第一晶片的主、副電極和第二晶片的背部電極，使控制晶片餘下的焊墊上設置的金屬凸塊分別對準並電性連接至各相應的上置引腳上。
上述方法，第一引腳沿第一基座的第一橫向邊緣的長度方向延伸的長度值分別小於第一基座的第一橫向邊緣的長度值；晶片安裝單元包括在第一引腳的延長線上設置的一個靠近第一基座的第一橫向邊緣的第一旁路引腳，位於第一排承載引腳的鄰近第二縱向邊緣的最內側的一個承載引腳和第一引腳之間，並且第一旁路引腳帶有一個連接部，從第一旁路引腳靠近該最內側的一個承載引腳的一側的頂部向該承載引腳延伸，並與其連接；晶片安裝單元包括一L形連接結構，連接結構的縱向延伸段對接在除第一、第二排承載引腳中各自最內側的承載引腳之外的任意一承載引腳上，其橫向延伸段垂直于縱向延伸段並連接在縱向延伸段和基島之間；步驟S2中，使控制晶片倒裝安裝在第一、第二排承載引腳之上，控制晶片的焊墊上設置的金屬凸塊分別對準並電性連接至各相應的承載引腳上；步驟S3還包括利用一個導電結構將第一晶片的副電極電性連接在第一旁路引腳上的步驟。
上述的方法，晶片安裝單元包括一L形連接結構，該連接結構的縱向延伸段對接在除第二排承載引腳中最內側的承載引腳之外的第一、第二承載引腳中的任意一承載引腳上，其橫向延伸段垂直于縱向延伸段並連接在縱向延伸段和基島之間；在步驟S2中，使控制晶片倒裝安裝在第一、第二排承載引腳之上；步驟S還包括利用鍵合引線將第一晶片的副電極電性連接在第一排承載引腳中的沒有與所述L形連接結構連接在一起的任意一承載引腳上的步驟。
上述的方法，在步驟S2中，將控制晶片的背面粘附在第一、第二排承載引腳上；步驟S3包括利用鍵合引線，將第一晶片的副電極、基島分別電性連接至控制晶片正面的相對應的焊墊上，同時利用鍵合引線將控制晶片正面餘下的多個焊墊分別連接至第一、第二排承載引腳中相應的各承載引腳的頂面上的步驟。
上述的方法，第二引腳具有一個連接部，從第二引腳的鍵合區的頂部靠近第二排承載引腳中最內側的一個承載引腳的一側向該最內側的一個承載引腳延伸，並與其連接；在步驟S3中，還將所述金屬片電性連接在第一引腳上。


In one embodiment, the power control device includes: a wafer mounting unit and a control chip and first and second wafers, the wafer mounting unit including a first and second pins and a first portion near the base and the base a second row carrying pins; the base having an opposing set of first and second lateral edges and an opposite set of first and second longitudinal edges, wherein the first pin is adjacent to the first lateral edge and has a strip The bonding region extends along the length of the first lateral edge, the second pin is adjacent to the second lateral edge and the strip-shaped bonding region extends along the length of the second lateral edge; the first and second rows of carrying pins are located at the base One side of the second longitudinal edge, and each of the first row of carrying pins is parallel to the second longitudinal edge and is between the first and second lateral edges by a lateral extension of the first pin a symmetric centerline extending, and each of the second row of carrier pins is parallel to the second longitudinal edge and extends from the lateral extension of the second pin toward the symmetric centerline; the first and second wafers Installed on the base The control chip is mounted on the first and second rows of carrier pins, and a main electrode on the front surface of the first wafer is electrically connected to the first pin through a first metal piece, and a main electrode on the front surface of the second chip The second metal piece is electrically connected to the second pin.
In the above power control device, the base has a connecting portion extending from the top of one side of the second longitudinal edge of the base toward the innermost one of the first row of carrying pins and connected thereto. The first and second wafers are all adhered to the top surface of the pedestal such that the back electrodes of the respective back surfaces of the first and second wafers are adhered to the top surface of the susceptor.
Each of the first and second rows of carrier pins includes an upper pin and a lower pin connected to each other, and the top surface of the upper pin of the pin is the first The front faces of the second wafers are coplanar; the control wafers are flip-chip mounted on the first and second rows of carrier pins in such a manner as to be offset from the first and second wafers, such that the offsets are such that they have the first and the The two wafers form overlapping overlapping portions, and the plurality of metal bumps respectively disposed on the plurality of pads on the front surface of the overlapping portion are respectively aligned and electrically connected to the main electrode and the secondary electrode of the front surface of each of the first and second wafers The metal bumps disposed on the remaining pads of the control chip are respectively aligned and electrically connected to the respective upper pins.
The power control device further includes a molding body covering the wafer mounting unit, the first and second wafers, the control wafer, the first and second metal sheets, and the metal bumps, and the covering manner is at least The bottom surface of the pin, the bottom surface of the pedestal, and the bottom surfaces of the first and second pins are exposed from the bottom surface of the molding body.
The power control device is characterized in that a recess is disposed on a top surface of the base, and the first and second wafers are all located in the recess, so that the back electrodes of the first and second wafers are adhered to each other. The bottom of the recess, and the top surface of each of the first and second rows of carrier pins is coplanar with the respective front faces of the first and second wafers.
In the above power control device, the control wafer is flip-chip mounted on the first and second rows of carrier pins in such a manner as to be offset from the first and second wafers, such that the offset is such that they have a relationship with the first and second wafers. The overlapping portions of the stack are such that the plurality of metal bumps disposed on the plurality of pads on the front side of the overlap portion are respectively aligned and electrically connected to the main electrode and the sub-electrode of the front surface of each of the first and second wafers; and the remaining of the control wafer The metal bumps disposed on the solder pads are respectively aligned and electrically connected to the respective carrier pins.
The power control device further includes a molding body covering the wafer mounting unit, the first and second wafers, the control wafer, the first and second metal sheets, and the metal bumps, and the covering manner is at least for each bearing The bottom surface of the pin, the bottom surface of the pedestal, and the bottom surfaces of the first and second pins are exposed from the bottom surface of the molding body.
In the above power control device, the first and second metal sheets each include a main flat plate portion and a sub-plate portion having a height drop corresponding to the opposite main flat plate portion connected to one side thereof, and a main flat plate of the first and second metal sheets a bottom portion of the bottom portion is provided with a vertically downwardly extending end portion; wherein the bottom end faces of the respective ends of the first and second metal sheets are respectively soldered to the main electrodes of the first and second wafers, first and second The respective sub-plate portions of the metal sheets are respectively welded to the bonding regions of the first and second pins.
The power control device further includes a molding body covering the wafer mounting unit, the first and second wafers, the control wafer, the first and second metal sheets, and the metal bumps; wherein the back surface of the control wafer is first The top surface of each of the main flat plate portions of the second metal piece is coplanar, and the plastic sealing body is coated in such a manner that at least the bottom surface of each of the carrier pins, the bottom surface of the base, and the bottom surfaces of the first and second pins are The bottom surface of the molding body is exposed, and the top surface of each of the main flat plate portions of the first and second metal sheets and the back surface of the control wafer are exposed from the top surface of the molding body.
In the above power control device, the first and second wafers are all adhered to the top surface of the pedestal, so that the back electrodes of the back surfaces of the first and second wafers are adhered to the top surface of the susceptor; On the first and second rows of carrier pins, the metal bumps disposed on the pads on the front side are respectively aligned and electrically connected to the respective carrier pins.
In the above power control device, the length values of the first and second pins respectively extending along the length direction of the first and second lateral edges are smaller than the length values of the first and second lateral edges, respectively; the wafer mounting unit is included at the first pin a first bypass pin disposed adjacent to the first lateral edge on the extension line of the length direction, located between the innermost carrier pin of the first row carrying pin and the first pin, the first bypass pin a connection portion extending from the top of the first bypass pin adjacent to the side of the innermost carrier pin of the first row of carrier pins and connected thereto; the wafer mounting unit is included in the second a second bypass pin disposed adjacent to the second lateral edge on the extension of the length of the pin, between the innermost carrier pin and the second pin of the second row of carrying pins, the second bypass The pin has a connection portion extending from the top of the second bypass pin adjacent to the side of the innermost carrier pin of the second row of carrier pins and connected thereto; first and second The secondary electrodes on the front side of the wafer are respectively connected The conductive structure is electrically connected to the first and second bypass pins; the wafer mounting unit further includes an L-shaped connection structure, except for the innermost carrier pins of the first and second rows of carrying pins Any one of the carrying pins is electrically connected to the second longitudinal edge of the base.
The power control device electrically connects the sub-electrode of the front surface of the first wafer to any one of the first row of carrier pins by using a bonding wire, and the top electrode of the second wafer and the top of the pedestal The faces are electrically connected to any two different carrier pins of the second row of carrier pins, respectively.
In the above power control device, the first and second wafers are all adhered to the top surface of the pedestal such that the back electrodes of the respective back surfaces of the first and second wafers are adhered to the top surface of the susceptor; On the first and second rows of carrying pins, the top surfaces of the front side of the first and second wafers and the top surface of the pedestal are respectively electrically connected to the corresponding pads on the front side of the control wafer by using bonding wires, which will be controlled The remaining plurality of pads on the front side of the wafer are electrically connected to the top surfaces of the corresponding carrier pins.
In one embodiment, the power control device includes: a wafer mounting unit and a control wafer and first and second wafers, the wafer mounting unit including adjacent first and second pedestals, and including the first pedestal a first pin and a first row of carrying pins, and a second pin and a second row of carrying pins adjacent to the second base; the first and second bases each have an opposite set of first, a second lateral edge and an opposite set of first and second longitudinal edges, the first pin being adjacent to the first lateral edge of the first pedestal and the strip-shaped bonding region along the length of the first lateral edge of the first pedestal Extending, the second pin is adjacent to the second lateral edge of the second base and the strip-shaped bonding region extends along the length of the second lateral edge of the second base; the first row of bearing pins is located at the first base One side of the two longitudinal edges, and each of the first row of carrying pins is parallel to the second longitudinal edge of the first pedestal and extends from the lateral extension of the first pin to the first pedestal, The dividing line between the second pedestals extends; the second row carries the pin positions One side of the second longitudinal edge of the second pedestal, and each of the second row of carrying pins is parallel to the second longitudinal edge of the second pedestal and is laterally extended by the second pin Extending to the dividing line; wherein the first and second wafers are respectively mounted on the first and second pedestals, so that the back electrodes of the back surfaces of the first and second wafers are respectively adhered to the first and second bases The top surface of the socket is electrically connected to the second electrode of each of the first and second wafers through a metal piece, and the control wafer is mounted on the first and second rows of carrier pins.
In the above power control device, the second pin has a connection portion from the top of the bonding region of the second pin to the side of the innermost carrier pin of the second row of carrier pins to the innermost carrier The foot extends and is connected thereto; each of the first and second rows of carrier pins includes an upper pin and a lower pin connected to each other, and the upper pins of all the bearing pins The top surface of the foot is coplanar with the front surface of each of the first and second wafers; the control wafer is flip-chip mounted on the first and second rows of carrier pins in a manner offset from the first and second wafers, offset degree In order to have an overlapping portion overlapping the first and second wafers, the plurality of metal bumps disposed on the plurality of pads on the front side of the overlapping portion are respectively aligned and electrically connected to the first and second wafers The main electrodes and the sub-electrodes on the front side of the control chip are respectively aligned on the remaining pads of the control chip and electrically connected to the respective upper pins.
In the above power control device, the first pedestal has a connecting portion extending from the top of the first pedestal on a side of the first lateral edge thereof toward the first pin and connected thereto.
In the above power control device, the control wafer is flip-chip mounted on the first and second rows of carrying pins, and the plurality of metal bumps respectively disposed on the plurality of pads on the front side are respectively aligned and electrically connected to the respective carrying leads. The metal piece is electrically connected to the first pin.
In the above power control device, the length of the first pin extending along the length of the first lateral edge of the first pedestal is smaller than the length of the first lateral edge of the first pedestal, and the second pin is along the second pedestal a length value of the second lateral edge extending in a length direction is smaller than a length value of the second lateral edge of the second pedestal; the wafer mounting unit includes a first bypass disposed on an extension line of the first pin adjacent to the first lateral edge a pin located between the first inner carrier pin of the first row of carrying pins and the first pin, and the first bypass pin has a connection from the first bypass pin to the first row a top of one side of the innermost carrying pin carrying the pin extends toward and is connected to the carrying pin; the wafer mounting unit includes a second side disposed on the extension of the second pin adjacent to the second lateral edge The circuit pin is located between a carrier pin and the second pin of the innermost side of the second row carrying pin, and the second bypass pin has a connection portion from the second bypass pin to the second The innermost one of the row carrying pins a top of one side of the carrying pin extends to and is connected to the carrying pin; the secondary electrodes on the front side of the first and second wafers are electrically connected to the first and second bypass pins through the conductive structure, respectively, and utilized The bonding wire electrically connects the main electrode of the second pin or the second chip to any one of the second row of carrying pins except the innermost carrying pin.
The power control device electrically connects the secondary electrode of the first wafer to any one of the first row of carrying pins by using a bonding wire, and the electrical properties of the positive and secondary electrodes of the second wafer are respectively corresponding. Connect to any two different carrier pins on the second row of carrier pins.
In the above power control device, the back surface of the control wafer is adhered to the first and second rows of load-bearing pins; and the main electrodes of the first and second wafers and the main electrodes of the second wafer are electrically connected by the bonding wires. To the corresponding pads on the front side of the control wafer, a plurality of solder pads remaining on the front surface of the control wafer are respectively connected to the top surfaces of the corresponding carrier pins.
In one embodiment, the power controller includes: a wafer mounting unit and a control wafer and first and second wafers, the wafer mounting unit including adjacent first and second pedestals, and including the first pedestal a first pin and a first row of carrying pins, and a second pin and a second row of carrying pins adjacent to the second base; the first and second bases each have an opposite set of first, a second lateral edge and an opposite set of first and second longitudinal edges, the first pin being adjacent to the first lateral edge of the first pedestal and the length of the strip-shaped bonding region along the first lateral edge of the first pedestal Extending direction, the second pin is adjacent to the second lateral edge of the second base and the strip-shaped bonding region extends along the length of the second lateral edge of the second base; the first row of carrier pins is located at the first base One side of the second longitudinal edge, and each of the first row of carrying pins is parallel to the second longitudinal edge of the first pedestal and has a first direction by the first pin (eg, X Splitting between the first base and the second base on the lateral extension line of the positive axis) a line extension; and a second row of carrier pins on one side of the second longitudinal edge of the second pedestal, and each of the second row of carrier pins is parallel to the second longitudinal edge of the second pedestal And extending to the dividing line by a lateral extension line of the second pin that is in the same direction as the first direction; the substantially rectangular second base has a corner at a corner where the first lateral edge intersects the second longitudinal edge a rectangular cutout forms the L-shaped structure of the second pedestal, and a base island is embedded in the slit; the first wafer is mounted on the first pedestal such that the back electrode of the back surface is adhered to the top of the first pedestal The second wafer is flip-chip mounted on the second pedestal and the island so that the main and auxiliary electrodes are respectively adhered to the top surface of the second pedestal and the island, and the control wafer is mounted in the first and second rows. Above the carrying pin; the main electrode on the front side of the first wafer and the back electrode on the back side of the second chip are electrically connected to the second pin by a metal piece.
In the above power control device, the first base has a connecting portion extending from a side of the first base at a side of the first lateral edge toward the first pin and connected thereto.
The above power control device is characterized in that each of the first and second rows of carrier pins each includes an upper pin and a lower pin connected to each other, all of which are carried on the pin The top surface of the pin is coplanar with the front surface of the first wafer and the back surface of the second wafer; the wafer mounting unit includes a connection structure, and the horizontal extension of the connection structure is docked on the innermost side of the second row of the carrier pins. An upper portion of any one of the first and second rows of carrying pins other than the pin, the oblique extension at an angle to the horizontal plane is perpendicular to the horizontal extension and is connected between the horizontal extension and the base island The control wafer is flip-chip mounted on the first and second rows of carrier pins in such a manner as to be offset from the first and second wafers to have an offset such that they overlap with the first and second wafers a portion of the plurality of metal bumps disposed on the plurality of pads on the front side of the overlap portion are respectively aligned and electrically connected to the main electrodes of the first wafer and the back electrodes of the second wafer; and the remaining pads on the control wafer are disposed Metal convex They are aligned with and electrically connected to the respective pins on the opposite.
In the above power control device, the length of the first pin extending along the length of the first lateral edge of the first pedestal is smaller than the length of the first lateral edge of the first pedestal; the wafer mounting unit is included at the first pin a first bypass pin disposed on the lateral extension line adjacent to the first lateral edge of the first pedestal, between a carrier pin and the first pin of the innermost side of the first row of carrying pins, and a bypass pin having a connection portion extending from the top of the first bypass pin adjacent to the innermost one of the carrier pins and connected thereto, thereby connecting the secondary electrode of the first wafer Electrically connected to the first bypass pin through a conductive structure; the wafer mounting unit includes an L-shaped connection structure, the longitudinal extension of the connection structure is butted at the innermost side of each of the first and second rows of carrier pins a carrier pin other than the carrier pin, the lateral extension of which is perpendicular to the longitudinal extension and is connected between the longitudinal extension and the base island; and the control chip is flip-chip mounted on the first and second rows of carrier pins Above, The metal bumps disposed on the pads of the control wafer are respectively aligned and electrically connected to the respective carrier pins.
In the above power control device, the control chip is flip-chip mounted on the first and second rows of carrier pins, and the auxiliary electrodes of the first wafer are electrically connected to any one of the first row of carrier pins through the bonding wires. The wafer mounting unit includes an L-shaped connection structure, and the longitudinal extension of the connection structure is butted except for the innermost carrier pin of the second row of carrier pins and connected to the first row of carrier pins a remaining one of the first and second carrier pins other than the carrier pins of the secondary electrode of the wafer, the lateral extension of which is perpendicular to the longitudinal extension and is connected between the longitudinal extension and the island .
In the above power control device, the back surface of the control wafer is adhered to the first and second rows of load-bearing pins; and the secondary electrodes and the islands of the first wafer are electrically connected to the front surface of the control wafer by bonding wires respectively. On the solder pad, a plurality of solder pads remaining on the front surface of the control wafer are respectively connected to the top surfaces of the corresponding ones of the first and second rows of carrier pins by using bonding wires.
In the above power control device, the second pin has a connecting portion from a top of the bonding region of the second pin to a side of the innermost one of the second row of carrying pins to the innermost one The carrier pin extends and is connected thereto; the metal piece is also electrically connected to the first pin.
In one embodiment, a method for fabricating a power control device includes the following steps: Step S1, providing a wafer mounting unit including a first and second pins and first and second rows near a base and a base Carrying a pin; the base has an opposite set of first and second lateral edges and an opposite set of first and second longitudinal edges, the first pin being adjacent to the first lateral edge and the strip-shaped bonding region along the first The lateral edge extends in the length direction, the second pin is adjacent to the second lateral edge and the strip-shaped bonding region extends along the length of the second lateral edge; the first and second rows of carrying pins are located at the same second longitudinal edge of the base a side, and each of the first row of carrier pins is parallel to the second longitudinal edge and extends from a lateral extension of the first pin to a symmetrical centerline between the first and second lateral edges, and Each of the second row of carrier pins is parallel to the second longitudinal edge and extends from the lateral extension of the second pin toward the symmetric centerline; step S2, a first wafer and a second The wafers are mounted side by side Above the pedestal, and mounting a control chip on the first and second rows of carrier pins; step S3, electrically connecting a main electrode of the front surface of the first wafer to the first pin by using a first metal piece Upper, a main electrode of the front surface of the second wafer is electrically connected to the second pin by a second metal piece.
In the above method, the base has a connecting portion extending from the top of one side of the second longitudinal edge of the base toward one of the first row of carrying pins adjacent to the innermost edge of the second longitudinal edge and connected thereto . In the above method, in step S2, the first and second wafers are adhered to the top surface of the pedestal, so that the back electrodes of the respective back surfaces of the first and second wafers are adhered to the top surface of the pedestal, wherein 1. The respective secondary electrodes of the second wafer are located on the respective front sides.
In the above method, each of the first and second rows of carrier pins includes an upper pin and a lower pin connected to each other; in step S2, the first and second are first made. The front sides of the wafers are all coplanar with the top surface of all of the upper pins of the carrier pins; the control wafer is then flip-chip mounted to the first and second rows of carrier pins in a manner offset from the first and second wafers. And having an overlapping portion overlapping the first and second wafers, wherein the plurality of metal bumps disposed on the plurality of pads on the front surface of the overlapping portion are respectively aligned and electrically connected to the first and the second The main electrodes and the sub-electrodes of the two wafers are simultaneously aligned; and the metal bumps disposed on the remaining pads of the control wafer are respectively aligned and electrically connected to the respective upper pins.
After the step S3 is completed, the method further includes the steps of coating the wafer mounting unit, the first and second wafers, the control wafer, the first and second metal sheets, and the metal bumps by using a plastic package. The covering method exposes at least the bottom surface of each of the lower pins, the bottom surface of the pedestal, and the bottom surfaces of the first and second pins from the bottom surface of the molding body.
In the above method, a recess is provided on the top surface of the pedestal in advance, and in step S2, the first and second wafers are mounted in the recesses, so that the back electrodes of the back surfaces of the first and second wafers are adhered. At the bottom of the groove, the respective sub-electrodes of the first and second wafers are located on the respective front faces, so that the front faces of the first and second wafers are respectively associated with each of the first and second rows of carrier pins. The top surface is coplanar.
In the above method, in step S2, the control wafer is flip-chip mounted on the first and second rows of carrier pins in such a manner as to be offset from the first and second wafers to form the first and second wafers. Overlapped overlapping portions, wherein a plurality of metal bumps disposed on the plurality of pads on the front side of the overlapping portion are respectively aligned and electrically connected to respective main electrodes and sub-electrodes of the first and second wafers; and the control wafer is simultaneously The metal bumps disposed on the remaining pads are respectively aligned and electrically connected to respective carrier pins of the first and second rows of carrier pins.
After the step S3 is completed, the method further includes the steps of coating the wafer mounting unit, the first and second wafers, the control wafer, the first and second metal sheets, and the metal bumps by using a plastic package. The covering method exposes at least the bottom surface of each of the carrier pins, the bottom surface of the pedestal, and the bottom surfaces of the first and second pins from the bottom surface of the molding body.
In the above method, the first and second metal sheets each include a main flat plate portion and a sub-plate portion connected to one side of the main flat plate portion, and a vertical surface of each of the main flat plate portions of the first and second metal sheets is disposed vertically. a downwardly extending end portion; in step S3, the bottom end faces of the respective end portions of the first and second metal sheets are respectively soldered to the main electrodes of the first and second wafers, and the respective first and second metal sheets are respectively The flat plate portions are respectively welded to the bonding regions of the first and second pins.
In the above method, in step S2, the back surface of the control wafer is coplanar with the top surface of each of the first and second metal sheets; after completing step S3, the wafer mounting unit is further included by using a plastic package. a step of coating the first and second wafers, the control wafer, the first and second metal sheets, and the metal bumps, at least the bottom surface of each of the carrier pins, the bottom surface of the base, the first and second leads The bottom surfaces of the legs are exposed from the bottom surface of the molding body, and the top surfaces of the main flat plate portions of the first and second metal sheets and the back surface of the control wafer are exposed from the top surface of the molding body.
In the above method, the length value of the first pin extending along the length direction of the first lateral edge is smaller than the length value of the first lateral edge. The length of the second pin extending along the length of the second lateral edge is smaller than the length of the second lateral edge. a length value; the wafer mounting unit includes a first bypass pin disposed on a lateral extension line of the first pin adjacent to the first lateral edge, and an innermost carrier pin and a first reference on the first row of the carrier pin Between the feet, the first bypass pin has a connection portion extending from the top of the first bypass pin adjacent to the side of the innermost carrier pin and connected thereto; the wafer mounting unit The method further includes a second bypass pin disposed on the lateral extension of the second pin adjacent to the second lateral edge, between the innermost carrier pin and the second pin of the second row of the carrier pin, The second bypass pin has a connection portion extending from the top of the second bypass pin adjacent to the side of the innermost carrier pin and connected thereto; the wafer mounting unit further includes an L Shaped connection a structure, electrically connecting any one of the first and second rows of carrier pins except the innermost carrier pins to the pedestal; in step S2, the control chip is flip-chip mounted at the first a plurality of metal bumps respectively disposed on the plurality of pads on the front side of the second row of the carrier pins are respectively aligned and electrically connected to the respective carrier pins; thereby, in step S3, using the conductive structure, The sub-electrodes on the front sides of the first and second wafers are electrically connected to the first and second bypass pins, respectively.
The above method is characterized in that, in step S2, the control wafer is flip-chip mounted on the first and second rows of carrier pins, and the plurality of metal bumps respectively disposed on the plurality of pads on the front surface are respectively aligned and electrically connected. Connected to each of the corresponding carrier pins; step S3 further includes electrically connecting the secondary electrode of the first wafer to any one of the first row of carrier pins by using a bonding wire, the second wafer The top surface of the sub-electrode and the pedestal are electrically connected to any two different carrier pins of the second row of carrying pins, respectively.
In the above method, in step S2, the back surface of the control wafer is adhered to the first and second rows of carrier pins; and step S3 further includes: using the bonding wires, the respective sub-electrodes of the first and second wafers, The top surfaces of the pedestals are respectively electrically connected to corresponding pads on the front surface of the control wafer, and the plurality of solder pads remaining on the front surface of the control wafer are respectively connected to the top surfaces of the corresponding carrier pins by using bonding wires.
In one embodiment, a method of fabricating a power control device includes the following steps: Step S1, providing a wafer mounting unit, including adjacent first and second pedestals, and including a first pin adjacent to the first pedestal And a first row of carrying pins, and a second pin and a second row of carrying pins adjacent to the second base; the first and second bases each have an opposite set of first and second lateral edges and An opposite set of first and second longitudinal edges, the first pin being adjacent to the first lateral edge of the first base and the strip-shaped bonding region extending along the length of the first lateral edge of the first base, the second lead The foot is adjacent to the second lateral edge of the second base and its strip-shaped bonding region extends along the second lateral edge length of the second base; the first row of carrier pins is located at a second longitudinal edge of the first base a side, and each of the first row of carrying pins is parallel to the second longitudinal edge of the first pedestal and extends from the lateral extension of the first lead to the first pedestal and the second pedestal The dividing line extends between; and the second row of carrying pins is located at the second base One side of the second longitudinal edge, and each of the second row of carrying pins is parallel to the second longitudinal edge of the second pedestal and is split by the lateral extension of the second pin a step of extending a first wafer and a second wafer on the first and second pedestals, and mounting a control wafer on the first and second rows of carrier pins; and step S3; A metal piece is soldered to the main electrode and the second pin of each of the front surfaces of the first and second wafers.
In the above method, the second pin has a connecting portion from the top of the bonding area of the second pin to the side of the innermost one of the carrying pins of the second row of carrying pins to the innermost one. The foot extends and is connected thereto; each of the first and second rows of carrier pins includes an upper pin and a lower pin connected to each other; in step S2, first The front faces of the second wafers are all coplanar with the top surfaces of the upper pins of all the carrying pins; then the control wafer is flip-chip mounted in the first and second rows in a manner offset from the first and second wafers The carrier pin has an overlapping portion overlapping the first and second wafers, and the plurality of metal bumps disposed on the plurality of pads on the front surface of the overlapping portion are respectively aligned and electrically connected to the first The main electrodes and the sub-electrodes of the second wafer are simultaneously aligned and electrically connected to the respective upper pins of the remaining pads of the control wafer.
In the above method, the first base has a connecting portion extending from the top of the first base at a side of the first lateral edge thereof toward the first pin and connected thereto.
In the above method, the length values of the first pins extending along the length direction of the first lateral edge are respectively smaller than the length values of the first lateral edges, and the lengths of the second pins extending along the length of the second lateral edges are respectively smaller than the second values. a length value of the lateral edge; the wafer mounting unit includes a first bypass pin disposed on the extension line of the first pin adjacent to the first lateral edge, and the innermost carrier pin and the first row of the first row of the carrier pin Between a pin, the first bypass pin has a connection portion extending from the top of the first bypass pin adjacent to the side of the innermost carrier pin and connected thereto; The mounting unit further includes a second bypass pin disposed on the extension line of the second pin adjacent to the second lateral edge, between the innermost carrier pin and the second pin of the second row of the carrier pin, The second bypass pin has a connection portion extending from the top of the second bypass pin adjacent to the side of the innermost one of the carrier pins and connected thereto; in step S2, Control chip flip mount On the first and second rows of carrying pins, a plurality of corresponding metal bumps on the plurality of pads on the front side are respectively aligned and electrically connected to the respective carrying pins; in step S3, the metal piece is At the same time, it is electrically connected to the first pin, and electrically connects the secondary electrodes of the first and second wafers to the first and second bypass pins respectively, and uses the bonding wires to connect the second The pin is electrically connected to any one of the second row of carrier pins except the innermost carrier pin.
In the above method, in step S2, the control wafer is flip-chip mounted on the first and second rows of carrier pins, and a plurality of metal bumps respectively disposed on the plurality of pads on the front surface are respectively aligned and electrically connected to Each of the corresponding carrier pins; in step S3, the metal piece is further electrically connected to the first pin, and the secondary electrode of the first wafer is electrically connected to the first row of the carrier pins by using the bonding wire The positive and the secondary electrodes of the second wafer are electrically connected to any two different carrier pins of the second row of the carrier pins, respectively.
In the above method, in step S2, the back surface of the control wafer is adhered to the first and second rows of carrier pins; in step S3, the metal piece is also electrically connected to the first pin, and then bonded. Lead wires respectively electrically connecting the respective sub-electrodes of the first and second wafers and the main electrodes of the second wafer to corresponding pads on the front surface of the control wafer, and simultaneously controlling the remaining plurality of pads on the front side of the wafer by using the bonding wires They are respectively connected to the top surfaces of the corresponding carrier pins.
In one embodiment, a method of fabricating a power control device includes the following steps: Step S1, providing a wafer mounting unit including adjacent first and second pedestals, and including near the first pedestal a first pin and a first row of carrying pins, and a second pin and a second row of carrying pins adjacent to the second base; the first and second bases each have a relative set of first and second a lateral edge and an opposite set of first and second longitudinal edges, the first pin being adjacent to the first lateral edge of the first base and the strip-shaped bonding region along the length of the first lateral edge of the first base Extending, the second pin is adjacent to the second lateral edge of the second pedestal and the strip-shaped bonding region extends along the length of the second lateral edge of the second pedestal; the first row of carrying pins is located at the first pedestal One side of the second longitudinal edge, and each of the first row of carrier pins is parallel to the second longitudinal edge of the first pedestal and extends from the lateral extension of the first pin to the first pedestal a dividing line extending between the second base; and a second The carrier pin is located on one side of the second longitudinal edge of the second pedestal, and each of the second row of carrier pins is parallel to the second longitudinal edge of the second pedestal and is coupled by the second pin a lateral extension line extending toward the dividing line; wherein the substantially rectangular second base has a rectangular cutout at a corner where the first lateral edge intersects the second longitudinal edge to form the second base into an L shape Structure, and embedding a base island in the slit; step S2, mounting a first wafer on the first pedestal, flipping a second wafer on the second pedestal and the island, The control chip is mounted on the first and second rows of carrier pins; in step S3, a main electrode of the front surface of the first wafer is electrically connected to a back electrode and a second pin on the back surface of the second wafer by using a metal piece .
In the above method, the first base has a connecting portion extending from a side of the first base at a side of the first lateral edge toward the first pin and connected thereto.
In the above method, each of the first and second rows of carrier pins includes an upper pin and a lower pin connected to each other; the chip mounting unit includes a connection structure and a horizontal extension thereof Docking an upper portion of any one of the first and second rows of carrying pins except the carrying pin of the innermost side of the second row of carrying pins, the oblique extending portion at an angle to the horizontal plane is perpendicular to a horizontally extending section and connected between the horizontally extending section and the base island; in step S2, the front side of the first wafer, the back side of the second wafer, and the top surface of all the upper pins of the carrying pins are coplanar; The control wafer is flip-chip mounted on the first and second rows of carrier pins in such a manner as to be offset from the first and second wafers so as to have an overlapping portion overlapping the first and second wafers. A plurality of metal bumps disposed on the plurality of pads on the front side of the stack are respectively aligned and electrically connected to the main electrodes of the first wafer and the back electrodes of the second wafer, so as to control the metal bumps provided on the remaining pads of the wafer Blocks are aligned and electrically connected Corresponding to each pin on the opposite.
In the above method, the length values of the first pins extending along the length of the first lateral edge of the first pedestal are respectively smaller than the length values of the first lateral edges of the first pedestal; the wafer mounting unit includes an extension at the first lead a first bypass pin disposed on the line adjacent to the first lateral edge of the first pedestal between the first inner carrier pin adjacent the second longitudinal edge of the first row of carrying pins and the first pin And the first bypass pin has a connection portion extending from the top of the side of the first bypass pin adjacent to the innermost one of the carrier pins and connected thereto; the wafer mounting unit includes An L-shaped connection structure, the longitudinal extension of the connection structure is docked on any of the carrier pins except the innermost carrier pins of the first and second rows of carrier pins, and the lateral extension extends perpendicular to the longitudinal direction The segment is connected between the longitudinally extending segment and the base island; in step S2, the control wafer is flip-chip mounted on the first and second rows of carrier pins, and the metal bumps disposed on the pads of the control wafer are respectively aligned and Electrical connection Each respective bearing pin; step S3 further comprises the step of utilizing a conductive structure at the first bypass pin sub-electrode is electrically connected to the first wafer.
In the above method, the wafer mounting unit includes an L-shaped connection structure, and the longitudinal extension of the connection structure is docked in the first and second carrier pins except the innermost carrier pins of the second row of carrier pins. Any of the carrying pins, the lateral extending portion thereof is perpendicular to the longitudinal extending portion and connected between the longitudinal extending portion and the base island; in step S2, the control wafer is flip-chip mounted on the first and second rows of carrying pins The step S further includes the step of electrically connecting the secondary electrodes of the first wafer to any one of the first rows of carrier pins that are not connected to the L-shaped connection structure by using a bonding wire.
In the above method, in step S2, the back surface of the control wafer is adhered to the first and second rows of carrier pins; and the step S3 includes electrically connecting the sub-electrodes and the islands of the first wafer by using bonding wires. Up to the corresponding pads on the front side of the control wafer, and simultaneously bonding the remaining plurality of pads on the front side of the control wafer to the top surfaces of the corresponding ones of the first and second rows of carrier pins by using bonding wires step.
In the above method, the second pin has a connecting portion from the top of the bonding area of the second pin to the side of the innermost one of the carrying pins of the second row of carrying pins to the innermost one. The foot extends and is connected thereto; in step S3, the metal piece is also electrically connected to the first pin.


110‧‧‧基座
111‧‧‧第一引腳
112‧‧‧第二引腳
113‧‧‧第一排承載引腳
114‧‧‧第二排承載引腳
103‧‧‧控制晶片
101‧‧‧第一晶片
102‧‧‧第二晶片
110a‧‧‧第一橫向邊緣
110b‧‧‧第二橫向邊緣
110c‧‧‧第一縱向邊緣
110d‧‧‧第二縱向邊緣
111a‧‧‧鍵合區
112a‧‧‧鍵合區
112b‧‧‧外部引腳
113‧‧‧第一排承載引腳
114‧‧‧第二排承載引腳
111b‧‧‧外部引腳
115a‧‧‧連接部
115c‧‧‧連接部
280‧‧‧中心線
113-1‧‧‧承載引腳
114-1‧‧‧承載引腳
114-2‧‧‧承載引腳
211‧‧‧第一金屬片
212‧‧‧第二金屬片
113a‧‧‧上置引腳
113b‧‧‧下置引腳
114a‧‧‧上置引腳
114b‧‧‧下置引腳
201‧‧‧屬凸塊
101a‧‧‧主電極
101b‧‧‧副電極
102a‧‧‧主電極
102b‧‧‧副電極
121‧‧‧第一旁路引腳
122‧‧‧第二旁路引腳
215‧‧‧粘合材料
211b‧‧‧主平板部分
211a、211c‧‧‧副平板部分
212b‧‧‧主平板部分
212a、212c‧‧‧副平板部分
1100‧‧‧凹槽
2110b‧‧‧主平板部分
2110a‧‧‧副平板部分
2110c‧‧‧端部
2120‧‧‧第二金屬片
2120b‧‧‧主平板部分
2120a‧‧‧副平板部分
2120c‧‧‧端部
2110‧‧‧第一金屬片
2120‧‧‧第二金屬片
225‧‧‧塑封體
117‧‧‧連接結構
117a‧‧‧縱向延伸段
117b‧‧‧橫向延伸段
311‧‧‧導電結構
312‧‧‧導電結構
311b‧‧‧主平板部分
311a、311c‧‧‧的副平板部分
119‧‧‧鍵合引線
110-1‧‧‧第一基座
110-2‧‧‧第二基座
110-1a‧‧‧第一橫向邊緣
110-1b‧‧‧第二橫向邊緣
110-1c‧‧‧第一縱向邊緣
110-1d‧‧‧第二縱向邊緣
110-2a‧‧‧第一橫向邊緣
110-2b‧‧‧第二橫向邊緣
110-2c‧‧‧第一縱向邊緣
110-2d‧‧‧第二縱向邊緣
250‧‧‧金屬片
250b、250d‧‧‧主平板部分
250a、250c、250e‧‧‧副平板部分
251‧‧‧金屬片
251b、251d、251f‧‧‧主平板部分
251a、251c、251e、251g‧‧‧副平板部分
113c‧‧‧連接結構
113c-1‧‧‧水準延伸段
113c-2‧‧‧傾斜延伸段
115b‧‧‧連接部
117'‧‧‧連接結構
117'a‧‧‧縱向延伸段
117'b‧‧‧橫向延伸段
110‧‧‧Base
111‧‧‧First pin
112‧‧‧second pin
113‧‧‧First row of carrying pins
114‧‧‧Second row of carrying pins
103‧‧‧Control chip
101‧‧‧First chip
102‧‧‧second chip
110a‧‧‧first lateral edge
110b‧‧‧second lateral edge
110c‧‧‧ first longitudinal edge
110d‧‧‧second longitudinal edge
111a‧‧‧bonding zone
112a‧‧‧bonding area
112b‧‧‧External Pin
113‧‧‧First row of carrying pins
114‧‧‧Second row of carrying pins
111b‧‧‧External Pin
115a‧‧‧Connecting Department
115c‧‧‧Connecting Department
280‧‧‧ center line
113-1‧‧‧ Carrying Pin
114-1‧‧‧ Carrying pin
114-2‧‧‧ Carrying Pin
211‧‧‧First sheet metal
212‧‧‧Second metal piece
113a‧‧‧Top pin
113b‧‧‧Lower pin
114a‧‧‧Top pin
114b‧‧‧Lower pin
201‧‧‧ is a bump
101a‧‧‧Main electrode
101b‧‧‧Secondary electrode
102a‧‧‧Main electrode
102b‧‧‧Secondary electrode
121‧‧‧First Bypass Pin
122‧‧‧Second BYPASS pin
215‧‧‧Adhesive materials
211b‧‧‧Main tablet section
211a, 211c‧‧‧sub-plate parts
212b‧‧‧Main tablet section
212a, 212c‧‧‧sub-plate parts
1100‧‧‧ Groove
2110b‧‧‧Main tablet section
2110a‧‧‧Sub-plate part
2110c‧‧‧End
2120‧‧‧Second metal piece
2120b‧‧‧Main tablet section
2120a‧‧‧Sub-plate part
2120c‧‧‧End
2110‧‧‧First sheet metal
2120‧‧‧Second metal piece
225‧‧‧plastic body
117‧‧‧ Connection structure
117a‧‧‧Longitudinal extension
117b‧‧‧ horizontal extension
311‧‧‧Electrical structure
312‧‧‧Electrical structure
311b‧‧‧Main tablet section
Sub-plate part of 311a, 311c‧‧
119‧‧‧bonding leads
110-1‧‧‧First base
110-2‧‧‧Second base
110-1a‧‧‧ first lateral edge
110-1b‧‧‧ second lateral edge
110-1c‧‧‧ first longitudinal edge
110-1d‧‧‧second longitudinal edge
110-2a‧‧‧ first lateral edge
110-2b‧‧‧second lateral edge
110-2c‧‧‧ first longitudinal edge
110-2d‧‧‧second longitudinal edge
250‧‧‧metal pieces
250b, 250d‧‧‧ main flat section
250a, 250c, 250e‧‧‧ sub-plate parts
251‧‧‧metal piece
251b, 251d, 251f‧‧‧ main flat section
251a, 251c, 251e, 251g‧‧‧ sub-plate parts
113c‧‧‧ Connection structure
113c-1‧‧‧ Level extension
113c-2‧‧‧ oblique extension
115b‧‧‧Connecting Department
117'‧‧‧ Connection structure
117'a‧‧‧Longitudinal extension
117'b‧‧‧ horizontal extension

參考所附附圖，以更加充分的描述本發明的實施例。然而，所附附圖僅用於說明和闡述，並不構成對本發明範圍的限制。
圖1是背景技術的DC-DC變換器10的俯視結構。
圖2A~2H是形成本申請的功率控制器件的流程示意圖和結構示意圖。
圖3A~3E是在基座上形成凹槽的功率控制器。
圖4A~4C是在基座上形成凹槽並使金屬片的背面裸露在塑封體之外的功率控制器。
圖5A~5D是晶片安裝單元包含旁路引腳的示意圖。
圖6A是控制晶片倒裝但是使用一部分鍵合引線的示意圖。
圖6B是控制晶片不倒裝但是使用一部分鍵合引線的示意圖。
圖7A~7D是利用兩個基座而非一個基座的示意圖。
圖8A是利用兩個基座但晶片安裝單元包含旁路引腳的示意圖。
圖8B是利用兩個基座但使用鍵合引線的示意圖。
圖8C是利用兩個基座但控制晶片不倒裝的示意圖。
圖9A~9G是晶片安裝單元含有一個基島而使低端MOSFET倒裝的示意圖。
圖10A是低端MOSFET倒裝並且晶片安裝單元包含旁路引腳的示意圖。
圖10B是低端MOSFET倒裝並使用鍵合引線的示意圖。
圖11A~11B是低端MOSFET倒裝但控制晶片不倒裝的示意圖。

Embodiments of the present invention are described more fully with reference to the accompanying drawings. However, the attached drawings are for illustration and illustration only and are not intended to limit the scope of the invention.
1 is a top plan view of a DC-DC converter 10 of the background art.
2A-2H are schematic flow charts and structural diagrams of the power control device of the present application.
3A-3E are power controllers that form grooves on the base.
4A to 4C are power controllers in which grooves are formed on the susceptor and the back surface of the metal piece is exposed outside the molded body.
5A-5D are schematic views of a wafer mounting unit including a bypass pin.
Figure 6A is a schematic illustration of controlling wafer flip-chip but using a portion of bond wires.
Figure 6B is a schematic illustration of the control wafer not flipping but using a portion of the bond wires.
7A-7D are schematic views of the use of two pedestals instead of one pedestal.
Figure 8A is a schematic illustration of the use of two pedestals but with the wafer mounting unit including a bypass pin.
Figure 8B is a schematic illustration of the use of two pedestals but using bond wires.
Figure 8C is a schematic illustration of the use of two susceptors but controlling the wafer not to be flipped.
9A to 9G are schematic diagrams in which the wafer mounting unit includes a base island to flip the low-side MOSFET.
FIG. 10A is a schematic diagram of a low side MOSFET flip-chip and a wafer mounting unit including a bypass pin.
Figure 10B is a schematic illustration of a low-side MOSFET flip-chip mounted using bond wires.
11A-11B are schematic views of the low-side MOSFET flip-chip but the control wafer is not flipped.

如圖2A~2B的功率控制器件，包括圖2A展示的晶片安裝單元，晶片安裝單元包括一通常為方形的基座110和它附近的第一引腳111和第二引腳112，還包括第一排承載引腳113、第二排承載引腳114，和包括控制晶片103及第一晶片101、第二晶片102。為了便於敍述方便和理解晶片安裝單元的各個子部分的形狀及位置關係，定義基座所在的平面內，X軸的指向為橫向，垂直於X軸的Y軸的指向為縱向，而與基座所在平面正交的方向（Z軸）定義為垂直/豎直方向。藉此定義基座110的第一橫向邊緣110a、第二橫向邊緣110b，它們構成基座的相對的一組對邊，並定義基座110的第一縱向邊緣110c、第二縱向邊緣110d，它們構成基座的相對的另一組對邊。第一引腳111鄰近第一橫向邊緣110a，第一引腳111具有長條狀的鍵合區111a，其沿第一橫向邊緣110a的長度方向延伸，而第二引腳112鄰近第二橫向邊緣110c，第二引腳112也具有長條狀的鍵合區112a，其沿第二橫向邊緣110b的長度方向延伸。此外，第一引腳111還包含一些外部引腳111b，垂直于鍵合區111a，並以背離基座110的方向略微向外延伸，第二引腳112包含一些外部引腳112b，垂直于鍵合區112a，以背離基座110的方向略微向外延伸。
第一排承載引腳113是多個平行排列（可以呈等距離或非等距離排列）的承載引腳的集合，第二排承載引腳114同樣也如此。第一排承載引腳113、第二排承載引腳114皆位於基座110的第二縱向邊緣110d的同一側，且第一排承載引腳113的集合中的每一個承載引腳皆平行於第二縱向邊緣110d，並由第一引腳111的橫向延長線上（即其長度方向的延長線）向第一橫向邊緣110a、第二橫向邊緣110b之間的對稱中心線280延伸，同時，第二排承載引腳114中的每一個承載引腳皆平行於第二縱向邊緣110d並由第二引腳112的橫向延長線上向對稱中心線280延伸。在一些實施方式中，基座110具有一個佈置在第一橫向邊緣110a和第二縱向邊緣110d拐角處的連接部115a，連接部115a從基座110位於第二縱向邊緣110d的一側的頂部向第一排承載引腳113中最內側的靠近第二縱向邊緣110d的一個承載引腳113-1延伸，並與承載引腳113-1連接，以此形成基座110與承載引腳113-1之間的連接部115a，所以一般連接部115a的厚度較之基座110、承載引腳113-1要薄得多。為了便於說明，最內側的承載引腳指的是第一排承載引腳（或第二排承載引腳）中鄰近第二縱向邊緣的一個承載引腳，與之對應的是，最外側的承載引腳是指第一排承載引腳（或第二排承載引腳）中最遠離第二縱向邊緣的一個承載引腳。
如圖2B，第一晶片101、第二晶片102均先被並排地安裝在基座110的頂面之上，第一晶片101靠近第一橫向邊緣110a，第二晶片102靠近第二橫向邊緣110b，其後，控制晶片103被倒裝安裝在第一排承載引腳113、第二排承載引腳114之上，但控制晶片103向第一晶片101、第二晶片102整體偏移一段距離，但不能過度偏移以防止觸及到圖2D中示出的第一金屬片211或第二金屬片212。
在圖2C的實施方式中，第一晶片101是一個高端MOSFET，第二晶片102是一個低端MOSFET，第一晶片101是P溝道型MOSFET，第二晶片102是N溝道型MOSFET。第一晶片101的正面設置有一個主電極101a（作為源極）和一個副電極101b（作為柵極），其背面的未示意出的金屬化層構成背部電極（作為漏極），其背部電極通過導電的粘合材料粘附在基座110的頂面上。第二晶片102的正面設置有一個主電極102a（作為源極）和一個副電極102b（作為柵極），其背面的金屬化層構成背部電極（作為漏極），通過導電的粘合材料粘附在基座110的頂面上。
圖2F是沿著圖2D中虛線B1~B1的截面示意圖，第一排承載引腳113的每個承載引腳均皆包括相互連接的一個上置引腳113a和一個下置引腳113b，它們之間具有高度落差，，前者位置要高，同樣，第二排承載引腳114的每個承載引腳均皆包括相互連接的一個上置引腳114a和一個下置引腳114b，以保障完成第一、第二晶片的粘貼之後，第一排承載引腳113、第二排承載引腳114中所有的上置引腳113a或114a的頂面均與第一晶片101、第二晶片102各自的正面共面。
為了更詳盡的描述控制晶片103的倒裝形式，圖2C刻意將控制晶片103繪製成透明的，其正面的各個焊墊（焊墊的具體介紹將在圖6B中展現）上均設置有金屬凸塊201，如焊錫球等。控制晶片103的一組對邊中的一個邊緣附近的焊墊上所設置的金屬凸塊201分別對準相應的各上置引腳113a，每個金屬凸塊201和與其對準並焊接的上置引腳113a保持電性連接，該組對邊中的另一個相對的邊緣附近的焊墊上所設置的金屬凸塊201則對準相應的各上置引腳114a，每個金屬凸塊201和與其對準並接觸的上置引腳114a保持電性連接。同時，控制晶片103以向第一晶片101、第二晶片102偏移的方式倒裝安裝在第一、第二排承載引腳113、144上，其偏移程度為：使第二晶片102具有與第一排承載引腳113、第二晶片114形成交疊的交疊部分，使交疊部分正面的多個焊墊上設置的多個金屬凸塊201分別對準第一晶片101的主電極101a、副電極101b和第二晶片102的主電極102a、副電極102b，每個金屬凸塊201和與其對準並焊接的主電極101a（或201a）或副電極101b（或102b）保持電性連接，很顯然，該交疊部分正面的多個焊墊位於控制晶片103的另一組對邊中的一個邊緣附近。其中，要求上置引腳113a或114a的頂面與第一、第二晶片101、102各自的正面共面，可保障控制晶片103處於水平無傾斜的狀態，金屬凸塊201不易產生虛焊。
如圖2D，通過粘合材料，第一金屬片211被安裝在第一晶片101的正面和第一引腳111的鍵合區111a上，第二金屬片212被安裝在第二晶片102的正面和第二引腳112的鍵合區112a上。圖2E是沿著圖2D中虛線A1~A1的截面示意圖，第一晶片101、第二晶片102通過導電的粘合材料215粘附在基座110上。第一金屬片211、第二金屬片212皆為橋式結構，以匹配晶片和引腳之間的高度差，第一金屬片211包括一個主平板部分211b（橋部分）和分別連接在其兩側的兩個副平板部分211a、211c（谷部分），副平板部分211a、211c相對主平板部分211b具有高度落差，前者處於較低位，後者處於較高位，通過粘合材料，副平板部分211a粘附在第一引腳111的鍵合區111a的頂面，副平板部分211c粘附在第一晶片101的主電極101a上。同樣，第二金屬片212也包括一個主平板部分212b和分別連接在其兩側的兩個副平板部分212a、212c，副平板部分212a粘附在第二引腳112的鍵合區112a的頂面，副平板部分212c粘附在第二晶片102的主電極102a上。圖2G是沿著圖2D中虛線C1~C1的截面示意圖，展示了連接部115a的結構，從基座110位於第二縱向邊緣110d的一側的頂部向最內側的承載引腳113-1延伸並與其連接，所以連接部115a的厚度小於基座110及承載引腳的厚度。
如圖2H，利用環氧樹脂類的塑封材料，製備一個將晶片安裝單元、第一晶片101和第二晶片102、控制晶片103、第一金屬片211和第二金屬片212及各金屬凸塊201予以密封包覆的塑封體225，就塑封體225而言，其包覆方式至少使各下置引腳113b、114b的底面、基座110的底面、第一引腳111和第二引腳112各自的底面從塑封體225的底面中外露。作為對比，圖2A是從晶片安裝單元的正面一側俯視它，而在圖2H中，是從基座背面一側俯視它，只不過此時晶片安裝單元的絕大部分被塑封體225包覆起來，唯有下置引腳113b、114b的底面，基座110的底面，鍵合區111a、112a的底面及外部引腳111b、112b的底面皆裸露在塑封體之外，而從塑封體225的頂面觀察（俯視圖未示出），第一晶片101和第二晶片102、控制晶片103、第一金屬片211和第二金屬片212及各金屬凸塊201則完全被密封不可見。
在圖2G~2H的實施方式中，基座110與承載引腳113-1之間的連接部115a的厚度較之基座110、承載引腳113-1要薄得多，以致連接部115a在完成塑封工藝後被後續的塑封體225密封住。但在另一些未示出的可替代的實施方式中，連接部115a的厚度可以和基座110、承載引腳113-1的厚度相同，只不過連接部115a的底面將會從塑封體225的底面裸露出來不再被隱藏。
如圖3A，晶片安裝單元與圖2A中所示結構並無較大區別，唯獨在基座110的頂面上刻蝕或壓印有一個通常大致為方形的凹槽1100，另一個區別是，第一排承載引腳113、第二排承載引腳114中的每個承載引腳均皆不包含上置部分和下置部分，每個承載引腳皆是長條狀的平板結構。在這種情況下，只需要調整凹槽1100的深度，即調整基座110的剩餘厚度，便可使第一晶片101的正面、第二晶片102的正面與第一排承載引腳113、第二排承載引腳114中的每個承載引腳的頂面共面，即便承載引腳不設上置部分和下置部分，也可以很好的滿足控制晶片103實現倒裝安裝，正如圖3D沿圖3B中虛線B2~B2的截面所示。控制晶片103仍然是以向第一晶片102、第二晶片103偏移的方式倒裝安裝在第一排承載引腳113、第二排承載引腳114上，偏移程度為使其具有與第一晶片102、第二晶片103形成交疊的交疊部分，並使交疊部分正面的位於控制晶片103的一組對邊中一個邊緣附近的一些焊墊上設置的多個金屬凸塊201分別對準並電性連接至第一晶片101的主電極101a、副電極101b上，和對準並電性連接至第二晶片102正面的主電極102a、副電極102b上，同時，針對餘下的焊墊，使控制晶片103的位於另一組對邊中一個邊緣附近的焊墊上設置的金屬凸塊201對準並電性連接至第一排承載引腳113的各承載引腳上，使控制晶片103的位於所述另一組對邊中的另一個邊緣附近的焊墊上設置的金屬凸塊201對準並電性連接至第二排承載引腳114的各承載引腳上。圖3C是圖3B中沿虛線A2~A2的截面，第一晶片101、第二晶片102均位於在凹槽1100內，並通過粘合材料215使第一晶片101、第二晶片102各自的背部電極均粘附在凹槽1100的底部。此時，與圖2H中僅僅是承載引腳的下置部分113b、114b的底面從塑封體225的底面裸露出來不同，在圖3E中，第一排承載引腳113、第二排承載引腳114的每個承載引腳的底面直接從塑封體225的底面中完全裸露出來。但第一晶片101和第二晶片102、控制晶片103、第一金屬片211和第二金屬片212及各金屬凸塊201仍然被塑封體225完全密封而不可見。
在圖4A中，與圖3B的區別在於，第一金屬片2110、第二金屬片2120不再是橋式結構的第一金屬片211、第二金屬片212，如圖4B沿圖4A中虛線A3~A3的截面所示，第一金屬片2110包括一個主平板部分2110b和連接在其一側的一個具有高度落差的副平板部分2110a，而且在主平板部分2110b的底面上設置有一個垂直向下延伸的端部2110c，通過粘合材料215，端部2110c的底端面與第一晶片101的主電極101a焊接，副平板部分2110a與第一引腳111的鍵合區111a焊接。第二金屬片2120包括一個主平板部分2120b和連接在其一側的一個副平板部分2120a，而且在主平板部分2120b的底面上設置有一個垂直向下延伸的端部2120c，通過粘合材料215，端部2120c的底端面與第二晶片102的主電極102a焊接，副平板部分2120a與第二引腳112的鍵合區112a焊接。由於製備工藝的因素，例如衝壓成型，考慮到例如橋式結構的第一金屬片211（或第二金屬片212）的主平板部分211b（或212b）在很多時候略微呈現出是一個向上隆起的穹隆或拱頂狀，以致主平板部分211b的頂面在塑封工藝中難以完全外露，所以塑封料往往直接將第一金屬片211（或第二金屬片212）予以塑封在內。而第一金屬片2110、第二金屬片2120則很好的克服了這個問題，所以主平板部分2110b、主平板部分2120b各自的頂面均可以從塑封體225的頂面（即塑封體225的與圖3E中所示的的底面相反的另一面）中裸露出來，正如圖4C所示。此外，如果能確保主平板部分211b、212b的頂面是絕對的平整面，它們也可以從塑封體225的頂面外露出來。圖4A中沿虛線B3~B3的截面與圖3D完全相同，所以只要調節凹槽1100的深度（相當於調節主平板部分2110b、主平板部分2120b的高度），就可以使控制晶片103的背面與主平板部分2110b、主平板部分2120b各自的頂面處於同一平面，以至於倒裝的控制晶片103的背面亦可從塑封體225的頂面中裸露出來，這為功率器件的散熱途徑提供了更多的選擇。此時，塑封體225的包覆方式至少使第一排承載引腳113、第二排承載引腳114的每個承載引腳的底面、基座110的底面、第一引腳111和第二引腳112各自的底面從塑封體225的底面外露，這與圖3E沒有區別。在一些實施方式中，第一金屬片2110、第二金屬片2120和控制晶片103也可從選擇被塑封體225完全包覆。
如圖5A，第一引腳111沿第一橫向邊緣110a的長度方向延伸的長度值L1小於第一橫向邊緣110a的長度值L2，第二引腳112沿第二橫向邊緣110b的長度方向延伸的長度值L3小於第二橫向邊緣110b的長度值L4，以此來設置晶片安裝單元的第一旁路引腳121、第二旁路引腳122。第一旁路引腳121靠近第一橫向邊緣110a，並設置在第一引腳111的橫向延長線上（即其長度方向的延遲線上），位於第一排承載引腳113的最內側的一個承載引腳113-1和第一引腳111之間，第一旁路引腳121帶有一個連接部115c，該連接部115c從第一旁路引腳121靠近該最內側的承載引腳113-1的一側的頂部向該承載引腳113-1延伸，並與該承載引腳113-1連接在一起，連接部115c的厚度此時小於第一旁路引腳121的厚度，在一些未示意出的實施方式中，也可以使連接部115c的厚度等於第一旁路引腳121、承載引腳113-1的厚度。同樣，第二旁路引腳122靠近第二橫向邊緣110b，並設置在第二引腳112的橫向延長線上（即其長度方向的延遲線上），位於第二排承載引腳114的最內側的一個承載引腳114-1和第二引腳112之間，第二旁路引腳122帶有一個連接部115d，該連接部115d從第二旁路引腳122靠近最內側的承載引腳114-1的一側的頂部向該承載引腳114-1延伸，並與該承載引腳114-1連接在一起，通常連接部115d的厚度小於第二旁路引腳122的厚度，但也可以設計使連接部115d的厚度等於第二旁路引腳122、承載引腳114-1的厚度。在圖5A中，使第一晶片101、第二晶片102各自背面的背部電極均粘附在基座110的頂面，第一晶片101的主電極101a通過第一金屬片211電性連接到第一引腳111上，第二晶片102的主電極102a通過一第二金屬片212電性連接到第二引腳112上。控制晶片103倒裝安裝在第一排承載引腳113和第二排承載引腳114上，但是控制晶片103沒有向第一晶片102、第二晶片103的方向偏移，控制晶片103正面的、位於其一組對邊中的一個邊緣附近的一些焊墊上設置的金屬凸塊201對準並電性連接至第一排承載引腳113的各承載引腳上，位於其所述一組對邊中的另一個邊緣附近的一些焊墊上設置的金屬凸塊201對準並電性連接至第二排承載引腳114的各承載引腳上。
在圖5A中，利用L形的連接結構117，將基座110機械及電性連接到第一排承載引腳113或第二排承載引腳114中除最內側的承載引腳113-1或114-1以外的任意一個承載引腳上，例如連接到第二排承載引腳114中的與承載引腳114-1鄰近的並位於承載引腳114-1外側的一個承載引腳114-2上。連接結構117包含相互連接、位於同一平面的一橫向延伸段117b和一縱向延伸段117a。如圖5C~5D，分別是沿E1~E1和E2~E2的截面，橫向延伸段117b的一端連接在基座110位於第二縱向邊緣110d的一側的頂部，縱向延伸段117a的一端對接在承載引腳114-2的一端的頂部，橫向延伸段117b的另一端和縱向延伸段117a的另一端連接，所以通常連接結構117比基座110、承載引腳114-2要薄。在圖5C~5D的實施方式中，連接結構117在完成塑封工序之後會被塑封體225包覆在內被隱藏，而在一些可替代的實施方式中，連接結構117的厚度可以和基座110、承載引腳114-2的厚度相同，則此時連接結構117的底面將會從塑封體225的底面中裸露出來。第一晶片101正面的副電極101b通過導電結構311電性連接到第一旁路引腳121上，第二晶片102正面的副電極102b通過導電結構312電性連接到第二旁路引腳122上，導電結構311、312可以是金屬片、帶狀的導電帶、鍵合線等。圖5B是沿圖5A中虛線D2~D2的截面示意圖，仍以橋式結構的金屬片為例，導電結構311的主平板部分311b兩側的副平板部分311a、311c分別粘合在第一旁路引腳121的頂面和第一晶片101正面的副電極101b上，導電結構312的主平板部分312b兩側的副平板部分312a、312c分別粘合在第二旁路引腳122的頂面和第二晶片102正面的副電極102b上。在後續的塑封工藝中，基座110的底面和第一排承載引腳113、第二排承載引腳114中每個承載引腳的底面直接從塑封體225的底面中完全裸露出來，第一引腳111、第二引腳121的底面從塑封體225底面外露，第一旁路引腳121、第二旁路引腳122的底面也從塑封體225底面外露，但第一晶片101和第二晶片102、控制晶片103、第一金屬片211和第二金屬片212及各金屬凸塊201和導電結構311、312仍然被塑封體225完全密封。
在圖6A中，先將第一晶片101、第二晶片102粘附在基座110的頂面上，使第一晶片101、第二晶片102各自背面的背部電極均粘附在基座110的頂面，將控制晶片103倒裝安裝在第一排承載引腳113和第二排承載引腳114上，之後將第一晶片101的主電極101a通過第一金屬片211電性連接到第一引腳111上，將第二晶片102的主電極102a通過一第二金屬片212電性連接到第二引腳112上。控制晶片103沒有向第一晶片102、第二晶片103的方向偏移，位於控制晶片103的一組對邊中的一個邊緣附近的一些焊墊上設置的金屬凸塊201對準並電性連接至第一排承載引腳113的各承載引腳上，位於控制晶片103的該一組對邊中的另一個邊緣附近的一些焊墊上設置的金屬凸塊201對準並電性連接至第二排承載引腳114的各承載引腳上。
利用鍵合引線119，將第一晶片101的正面的副電極101b電性連接至第一排承載引腳113中任意一個承載引腳上，作為優選，最好將副電極101b電性連接至最內側的承載引腳113-1上，這樣鍵合引線119的路徑最短。類似的，將第二晶片102正面的副電極102b電性連接至第二排承載引腳114中任意一個承載引腳上，並將基座110的頂面利用鍵合引線119電性連接至第二排承載引腳114中沒有與副電極102b連接的其他餘下的任意一個承載引腳之上，例如副電極102b電性連接至最內側的承載引腳114-1上，基座110電性連接至與承載引腳114-1鄰近並位於承載引腳114-1外側的一個承載引腳114-2上，這同樣可以縮短鍵合引線119的路徑。在後續的塑封工藝中，基座110的底面和第一排承載引腳113、第二排承載引腳114中每個承載引腳的底面直接從塑封體225的底面中完全裸露出來，第一、第二引腳的底面從塑封體225底面外露，第一晶片101和第二晶片102、控制晶片103、第一金屬片211和第二金屬片212及各金屬凸塊201和鍵合引線119仍然被塑封體225完全密封。
與圖5A的差異在於，在圖6B中，控制晶片103沒有倒裝安裝在第一排承載引腳113和第二排承載引腳114上，控制晶片103的正面朝上，其背面通過非導電的粘合劑粘附在第一排承載引腳113和第二排承載引腳114上，而且控制晶片103也沒有向第一晶片102、第二晶片103的方向偏移。利用鍵合引線119，將第一晶片101正面的副電極101b、第二晶片102正面的副電極102b、基座110的頂面分別電性連接至控制晶片103正面的相應焊墊103a上，與控制晶片103執行倒裝的情形不同，控制晶片103的焊墊103a上無需再焊接金屬凸塊201，代之的是直接焊接鍵合引線119。針對所有的焊墊103a中，除了連接至副電極101b、102b、基座110以外的餘下的焊墊而言，位於控制晶片103的一組對邊中的一個邊緣附近的一些焊墊103a電性連接至第一排承載引腳113的各承載引腳的頂面上，位於控制晶片103的該一組對邊中的另一個邊緣附近的一些焊墊103a電性連接至第二排承載引腳114的各承載引腳的頂面上，為了縮短鍵合引線119的路徑，連接至副電極101b、102b、基座110的焊墊103a最好位於控制晶片103的另一組對邊中的一個邊緣附近（該邊緣鄰近基座110）。在後續的塑封工藝中，基座110的底面和第一排承載引腳113、第二排承載引腳114中每個承載引腳的底面直接從塑封體225的底面中完全裸露出來，第一、第二引腳的底面從塑封體225底面外露，第一晶片101和第二晶片102、控制晶片103、第一金屬片211和第二金屬片212及鍵合引線119被塑封體225完全密封。
在圖5A、6A、6B的實施方式中，第一晶片101是P溝道型MOSFET，第二晶片102是N溝道型MOSFET。主電極101a作為源極，副電極101b作為柵極，其背面的未示意出的金屬化層構成背部電極作為漏極。主電極102a作為源極，副電極102b作為柵極，其背面的金屬化層構成背部電極作為漏極。
如圖7A~7D，在功率控制器件中，包括晶片安裝單元和控制晶片103及第一晶片101、第二晶片102。圖7A展示的晶片安裝單元含有相鄰的第一基座110-1、第二基座110-2，它們通常是方形，並包括第一基座110-1附近的第一引腳111及第一排承載引腳113，和包括第二基座110-2附近的第二引腳112及第二排承載引腳114。第一基座110-1具有相對的一組第一橫向邊緣110-1a和第二橫向邊緣110-1b，及具有相對的一組第一縱向邊緣110-1c、第二縱向邊緣110-1d，構成其四個邊緣。同樣，第二基座110-2也具有相對的一組第一橫向邊緣110-2a和第二橫向邊緣110-2b，及具有相對的一組第一縱向邊緣110-2c、第二縱向邊緣110-2d，構成其四個邊緣。第一基座110-1與第二基座110-2並排設置，第二基座110-2的第一橫向邊緣110-2a靠近第一基座110-1的第二橫向邊緣110-1b，在一些可選實施方式中，第二縱向邊緣110-1d與第二縱向邊緣110-2d大致對齊，第一縱向邊緣110-1a與第二縱向邊緣110-2a大致對齊。如果將第一排承載引腳113看作是一個整體和將第二排承載引腳114看作是一個整體，可以認為第一排承載引腳113、第二排承載引腳114這兩者是以平行排列的方式設置。
如圖7C為圖7B中沿虛線A4-A4的截面，結合圖7A，可以獲悉，第一引腳111靠近第一基座110-1的第一橫向邊緣110-1a，第一引腳111的條狀鍵合區111a沿第一基座110-1的第一橫向邊緣110-1a的長度方向延伸。第二引腳112靠近第二基座110-2的第二橫向邊緣110-2b，第二引腳111的條狀鍵合區112a沿第二基座110-2的第二橫向邊緣110-2a的長度方向延伸。第一排承載引腳113位於第一基座110-1的第二縱向邊緣110-1d的一側，第一排承載引腳113中的每一個承載引腳均平行於第一基座110-1的第二縱向邊緣110-1d，並由第一引腳110-1的具有第一方向（X軸正軸）的橫向延長線上（長度方向的延長線上）向第一基座110-1和第二基座110-2之間的分割線380延伸。第二排承載引腳114位於第二基座110-2的第二縱向邊緣110-2d的一側，且第二排承載引腳114中的每一個承載引腳均平行於第二基座110-2的第二縱向邊緣110-2d，並由第二引腳112的與第一方向同向的橫向延長線上向分割線380延伸。其中，第一晶片101粘貼在第一基座110-1的頂面上，第二晶片102粘貼在第二基座110-2之上，第一晶片101、第二晶片102各自背面的背部電極分別粘附在第一基座110-1、第二基座110-2的頂面，而控制晶片103則倒裝安裝在第一排承載引腳113、第二排承載引腳114之上。
在圖7A中，第二引腳112帶有一個連接部115b，從第二引腳112的條狀鍵合區112a的頂部靠近第二排承載引腳114中最內側的承載引腳114-1的一側向該最內側的承載引腳114-1延伸，並與承載引腳114-1連接。圖7A與圖2F類似，第一排承載引腳113的每個承載引腳均皆包括相互連接的一個上置引腳113a和一個下置引腳113b，第二排承載引腳114的每個承載引腳均皆包括相互連接的一個上置引腳114a和一個下置引腳114b，在圖7B所示的完成晶片的粘貼工序之後，所有承載引腳的上置引腳113a、114a的頂面均與第一晶片101、第二晶片102各自的正面101a、102a共面，從而控制晶片103以向第一晶片101、第二晶片102偏移的方式倒裝安裝在第一排承載引腳113、第二排承載引腳114上，偏移程度為使控制晶片103具有與第一晶片101、第二晶片102形成交疊的交疊部分，使交疊部分正面的多個焊墊上設置的多個金屬凸塊201分別對準並焊接至第一晶片101正面的主電極101a、副電極101b，和對準並焊接至第二晶片102正面的主電極102a、副電極102b，除交疊部分以外，控制晶片103餘下的焊墊上設置的金屬凸塊201分別對準並電性連接至第一排承載引腳113、第二排承載引腳114中相應的各上置引腳上，這與圖2C完全相同。值得注意的是，控制晶片103不能過度偏移以防止接觸到金屬片250。圖7B~7C中，通過一金屬片250將第一晶片101的主電極101a、第二晶片102的主電極102a與第二引腳112進行電性連接，金屬片250為一體成型的波浪狀或方波結構，含多個主平板部分250b、250d（橋部分）和多個副平板部分250a、250c、250e（谷部分），主平板部分的所在平面的高度要高於任意一個副平板部分所在平面的高度，金屬片250內側的副平板部分250c、250e共面，其首端的副平板部分250a和內側的副平板部分250c、250e不共面並低於後者的高度。主平板部分和副平板部分相互相鄰交叉分佈，每個主平板部分的兩側分別連接有兩個副平板部分。其中，副平板部分250a通過導電的粘合材料焊接到第二引腳112的鍵合區112a的頂面，而副平板部分250c通過粘合材料焊接到第二晶片102的主電極102a，副平板部分250e通過粘合材料焊接到第一晶片101的主電極101a。
在圖7A、7C中，第一基座110-1具有一個連接部116，從第一基座110-1的頂部位於其第一橫向邊緣110-1a的一側向第一引腳111延伸，並與第一引腳111連接，通常連接部116的厚度小於第一基座110-1的厚度，用於對塑封體225的鎖模。如圖7D所示的塑封體225的底面示意圖，功率控制器件還包括一個將晶片安裝單元、第一晶片101和第二晶片102、控制晶片103、金屬片250及各金屬凸塊201予以包覆的塑封體225，塑封體225的包覆方式至少使各下置引腳113b、114b的底面、第一基座110-1和第二基座110-2的底面、第一引腳111和第二引腳112各自的底面從塑封體225的底面外露。
在圖8A中，控制晶片103倒裝安裝在第一排承載引腳113、第二排承載引腳114上，但沒有向第一晶片101、第二晶片102偏移，控制晶片103的一組對邊中的一個邊緣附近的焊墊上所設置的金屬凸塊201分別對準第一排承載引腳113的相應的各承載引腳，每個金屬凸塊201和與其對準並接觸的承載引腳實施焊接以保持電性連接。控制晶片103的該組對邊中的另一個相對的邊緣附近的焊墊上所設置的金屬凸塊201則對準相應的第二排承載引腳114的各承載引腳，每個金屬凸塊201和與其對準並接觸的承載引腳實施焊接並保持電性連接。第一基座110-1沒有類似圖7A所示的連接部116，第一基座110-1與第一引腳111之間是分割開的。
第一引腳111沿第一基座110-1的第一橫向邊緣110-1a的長度方向延伸的長度值小於第一橫向邊緣110-1a的長度值，第二引腳112沿第二基座110-2的第二橫向邊緣110-2b的長度方向延伸的長度值小於第二橫向邊緣110-2b的長度值。晶片安裝單元包含的第一旁路引腳121設置在第一引腳111的橫向延長線上（長度方向的延長線上），鄰近第一基座110-1的第一橫向邊緣110-1a，並位於第一排承載引腳113的最內側的一個承載引腳113-1和第一引腳111之間。第一旁路引腳121帶有一個連接部115c，從第一旁路引腳121靠近第一排承載引腳113的最內側的承載引腳113-1的一側的頂部向該承載引腳113-1延伸，並與其連接，這在圖5A中有詳細描述。與此同時，晶片安裝單元包含的第二旁路引腳122設置在第二引腳112的橫向延長線上（其長度方向的延長線上），鄰近第二基座110-2的第二橫向邊緣110-2b，並位於第二排承載引腳114的最內側的一個承載引腳114-1和第二引腳112之間。第二旁路引腳122帶有一個連接部115d，從第二旁路引腳122靠近第二排承載引腳114的最內側的承載引腳114-1的一側的頂部向該承載引腳114-1延伸，並與其連接，這同樣在圖5A中有詳細描述。第一晶片101正面的副電極101b通過導電結構311電性連接到第一旁路引腳121上，第二晶片102正面的副電極102b通過導電結構312電性連接到第二旁路引腳122上，可以參考圖5A。同時，利用鍵合引線119將第二引腳112或者第二晶片102的主電極102a電性連接到第二排承載引腳114中除最內側的承載引腳114-1以外的任意一承載引腳上，最佳是電性連接到與承載引腳114-1相鄰的並位於承載引腳114-1外側的承載引腳114-2上。此外，第一晶片101、第二晶片102各自正面的主電極101a、101b分別通過金屬片251電性連接到第一引腳111、第二引腳112上，關於金屬片251的結構，可觀察圖11B，金屬片251亦為一體成型的波浪狀或方波結構，含多個主平板部分251b、251d、251f（橋部分）和多個副平板部分251a、251c、251e、251g（谷部分），主平板部分所在平面的高度要高於任意一個副平板部分所在平面的高度，主平板部分和副平板部分相互相鄰交叉分佈，每個主平板部分的兩側分別連接有兩個副平板部分。金屬片251兩端的副平板部分251a、251g與其內側的副平板部分251c、251e不共面，但其內側的副平板部分251c、251e相互共面，兩端的副平板部分251a、251g共面並低於內側的副平板部分251c、251e的高度。在圖8A中，副平板部分251a通過導電的粘合材料焊接到第二引腳112的鍵合區112a的頂面，而副平板部分251c通過粘合材料焊接到第二晶片102的主電極102a，副平板部分251e通過粘合材料焊接到第一晶片101的主電極101a，副平板部分251g通過導電的粘合材料焊接到第一引腳111的鍵合區111a的頂面。功率控制器件還包括一個將晶片安裝單元、第一晶片101和第二晶片102、控制晶片103、金屬片251及各金屬凸塊201、鍵合引線119和導電結構311、312予以包覆的塑封體225（此實施方式中未示意出），塑封體225的包覆方式至少使各承載引腳的底面、第一基座110-1和第二基座110-2的底面、第一引腳111和第二引腳112各自的底面從塑封體225的底面外露，第一旁路引腳121、第二旁路引腳122的底面也從塑封體225底面外露，但第一晶片101和第二晶片102、控制晶片103、金屬片251、鍵合引線119及各金屬凸塊201和導電結構311、312仍然被塑封體225完全密封。
圖8B與8A的區別在於，無需考慮第一引腳111沿第一基座110-1的第一橫向邊緣110-1a的長度方向延伸的長度值與第一橫向邊緣110-1a的長度值之間的關係，也無需考慮第二引腳112沿第二基座110-2的第二橫向邊緣110-2b的長度方向延伸的長度值與第二橫向邊緣110-2b的長度值之間的關係，因為第一旁路引腳121、第二旁路引腳122被移除。此時，直接利用鍵合引線119，將第一晶片101的正面的副電極101b電性連接至第一排承載引腳113中任意一個承載引腳上，作為優選，最好將副電極101b電性連接至最內側的承載引腳113-1上，這樣鍵合引線119的路徑最短。類似的，將第二晶片102正面的副電極102b電性連接至第二排承載引腳114中任意一個承載引腳上，並將第二晶片102的主電極102a利用鍵合引線119電性連接至第二排承載引腳114中沒有與副電極102b連接的其他餘下的任意一個承載引腳之上，例如副電極102b電性連接至最內側的承載引腳114-1上，主電極102a電性連接至與承載引腳114-1鄰近並位於承載引腳114-1外側的一個承載引腳114-2上，可以縮短鍵合引線119的路徑。功率控制器件還包括一個將晶片安裝單元、第一晶片101和第二晶片102、控制晶片103、金屬片251及各金屬凸塊201、鍵合引線119予以包覆的塑封體225（此實施方式中未示意出），塑封體225的包覆方式至少使各承載引腳的底面、第一基座110-1和第二基座110-2的底面、第一引腳111和第二引腳112各自的底面從塑封體225的底面外露，但第一晶片101和第二晶片102、控制晶片103、金屬片251、鍵合引線119及各金屬凸塊201仍然被塑封體225完全密封。
圖8C與8B的區別在於，控制晶片103沒有倒裝安裝在第一排承載引腳113和第二排承載引腳114上，控制晶片103的背面通過非導電的粘合劑粘附在第一排承載引腳113和第二排承載引腳114上，而且控制晶片103也沒有向第一晶片102、第二晶片103的方向偏移。利用鍵合引線119，將第一晶片101正面的副電極101b、第二晶片102正面的主電極102a、副電極102b分別電性連接至控制晶片103正面的數個相應焊墊103a上，與圖8A~8B中控制晶片103執行倒裝的情形不同，控制晶片103的焊墊103a上無需再焊接金屬凸塊201，而是作為鍵合區來迎合鍵合引線119的鍵合。在控制晶片103的所有焊墊103a中，針對除了已經連接至副電極101b、102b、主電極102a以外的餘下的焊墊而言，位於控制晶片103的一組對邊中的一個邊緣附近的一些焊墊103a電性連接至第一排承載引腳113的各承載引腳上，位於控制晶片103的該一組對邊中的另一個邊緣附近的一些焊墊103a電性連接至第二排承載引腳114的各承載引腳上，為了縮短鍵合引線119的路徑，連接至副電極101b、102b、主電極102a上的這些焊墊103a最好位於控制晶片103的與前述一組對邊相對的另一組對邊中的一個邊緣附近，並使該邊緣鄰近基座110。在該實施方式中，功率控制器件還包括一個將晶片安裝單元、第一晶片101和第二晶片102、控制晶片103、金屬片251及各鍵合引線119予以包覆的塑封體225（此實施方式中未示意出），塑封體225的包覆方式至少使各承載引腳的底面、第一基座110-1和第二基座110-2的底面、第一引腳111和第二引腳112各自的底面從塑封體225的底面外露，但第一晶片101和第二晶片102、控制晶片103、金屬片251、鍵合引線119仍然被塑封體225完全密封。
在圖7B、8A~8C的實施方式中，第一晶片101是N溝道型MOSFET，第二晶片102是頂漏底源的N溝道型MOSFET。第一晶片101的主電極101a作為源極，副電極101b作為柵極，其背面的未示意出的金屬化層構成背部電極作為漏極。第二晶片102的主電極102a作為漏極，副電極102b作為柵極，其背面的金屬化層構成背部電極作為底部的源極。
圖9A展示了一種晶片安裝單元的詳細結構，其與圖7A的主要差異在於，實質為矩形狀的第二基座110-2在其第一橫向邊緣110-2a與第二縱向邊緣110-2d交叉的拐角處具有一個矩形切口而使第二基座110-2呈現為L形結構，並在該切口中嵌入有一個基島113d。晶片安裝單元還包括一連接結構113c，連接結構113c包括水平延伸段113c-1和垂直于水平延伸段113c-1的傾斜延伸段113c-2，其水平延伸段113c-1在水平面上沿縱向延伸（例如平行於第二縱向邊緣110-1d、110-2d）並對接在除第二排承載引腳114最內側的承載引腳114-1之外的第一排承載引腳113、第二排承載引腳114中任意一個承載引腳的上置部分上，例如優選將水平延伸段113c-1的一端對接在鄰近第二縱向邊緣110-1d的最內側的承載引腳113-1的一端並且該兩者共面。連接結構113c的傾斜延伸段113c-2則與水平面形成大於零的夾角，其一端連接在水平延伸段113c-1上，另一端則傾斜的向下延伸直至和基島113d連接，如圖9D為沿圖9A中虛線C2~C2的截面，所以連接結構113c並不是嚴格意義上的L形，因為水平延伸段113c-1、傾斜延伸段113c-2並不共面，傾斜延伸段113c-2相對水平延伸段113c-1是向下彎折的，這便於匹配基島113d和承載引腳之間的立體高度差。另外，第二引腳112帶有一個連接部115b，這如圖7A中的描述完全一致，第二引腳112通過連接部115b連接到第二排承載引腳114中的鄰近第二縱向邊緣110-2d的最內側的一個承載引腳114-1上，連接部115b從第二引腳112靠近最內側的承載引腳114-1的一側的頂部向該承載引腳114-1延伸，並與該承載引腳114-1連接在一起。通常連接部115b的厚度小於第二旁路引腳122的厚度（如圖9E是圖9B中沿著虛線C3~C3的截面），但也可以設計使連接部115b的厚度等於第二旁路引腳122、承載引腳114-1的厚度。
第一晶片101粘貼在第一基座110-1上，使其背面的背部電極粘附至第一基座110-1的頂面，第二晶片102倒裝安裝在第二基座110-2和基島113d之上，使其主電極101a粘附在第二基座110-2的頂面上、其副電極102b粘附在基島113d的頂面上，至此第一晶片101的正面、第二晶片102的背面均與所有承載引腳的上置引腳113a、114a的頂面共面，而方便控制晶片103以向第一晶片101、第二晶片102偏移的方式倒裝安裝在第一排承載引腳113、第二排承載引腳114之上。控制晶片103正面的各個焊墊上均設置有金屬凸塊201，其一組對邊（例如第一組對邊）中的一個邊緣附近的焊墊上所設置的金屬凸塊201分別對準第一排承載引腳113中相應的各上置引腳113a，每個金屬凸塊201和與其對準並接觸的上置引腳113a實施焊接以保持電性連接，該組對邊中的另一個邊緣附近的焊墊上所設置的金屬凸塊201則對準第二排承載引腳114中相應的各上置引腳114a，每個金屬凸塊201和與其對準並接觸的上置引腳114a實施焊接以保持電性連接。控制晶片103的倒裝步驟中，使控制晶片103具有與第一晶片101、第二晶片102形成交疊的交疊部分，使交疊部分正面的、位於控制晶片103的另一組對邊（例如與第一組對邊相對的第二組對邊）中的一個邊緣附近的多個焊墊上設置的金屬凸塊201分別對準第一晶片101的主電極101a、副電極101b和第二晶片102的背部電極102c，每個金屬凸塊201和與其對準並接觸的主電極101a或副電極101b或背部電極102c實施焊接以保持電性連接，圖9C是沿圖9B中虛線D1~D2的截面。
圖9F~9G中，利用一金屬片250將第一晶片101的主電極101a、第二晶片102的背部電極102c與第二引腳112進行電性連接，金屬片250的結構在前述內容中已經詳細介紹，不再贅述。唯獨需要注意的是，副平板部分250a通過導電的粘合材料焊接到第二引腳112的鍵合區112a的頂面，副平板部分250c通過粘合材料焊接到第二晶片102的背部電極102c（這與圖7B~7C不同），副平板部分250e通過粘合材料焊接到第一晶片101的主電極101a。功率控制器件還包括一個將晶片安裝單元、第一晶片101和第二晶片102、控制晶片103、金屬片250及各金屬凸塊201予以包覆的塑封體225（圖中未示出），塑封體225的包覆方式至少使各下置引腳113b、114b的底面、第一基座110-1和第二基座110-2的底面、第一引腳111和第二引腳112各自的底面、基島113d的底面從塑封體225的底面外露。
與圖9A的晶片安裝單元的差異在於，在圖10A中，第一引腳111沿第一基座110-1的第一橫向邊緣110-1a的長度方向延伸的長度值小於第一橫向邊緣110-1a的長度值，晶片安裝單元包含的第一旁路引腳121設置在第一引腳111的橫向延長線上（即長度方向的延長線上），鄰近第一基座110-1的第一橫向邊緣110-1a，並位於第一排承載引腳113的最內側的一個承載引腳113-1和第一引腳111之間。第一旁路引腳121帶有一個連接部115c，從第一旁路引腳121靠近第一排承載引腳113的最內側的承載引腳113-1的一側的頂部向該承載引腳113-1延伸，並與其連接，這在圖5A中有詳細描述，第一晶片101正面的副電極101b通過導電結構311電性連接到第一旁路引腳121上。並且第一排承載引腳113、第二排承載引腳114均無上置、下置引腳，其每個承載引腳皆是條狀的平板結構，同時，L形的連接結構117'將基島113機械並電性連接到除第一排承載引腳113、第二排承載引腳114中各自最內側的承載引腳113-1、114-1之外的任意一個承載引腳上。譬如圖10A中，橫向延伸段117'b的一端連接在基島113d的大致與第二基座110-2的第二縱向邊緣110-2d對齊的邊緣的頂部，縱向延伸段117'a的一端對接在承載引腳114-2的一端的頂部，橫向延伸段117'b的另一端和縱向延伸段117'a的另一端連接，通常連接結構117'的厚度小於基島113、承載引腳的厚度，則連接結構117'被後續的塑封體225包覆隱藏，但也可以設計它們的厚度相同，則連接結構117'的底面從後續的塑封體225的底面外露。此外，第一晶片101的主電極101a、第二晶片102的背部電極102c皆通過金屬片251電性連接到第一引腳111、第二引腳112上，關於金屬片251的結構，不再贅述。在圖10A中，副平板部分251a通過導電的粘合材料焊接到第二引腳112的鍵合區112a的頂面，副平板部分251c通過粘合材料焊接到第二晶片102的背部電極102c，副平板部分250e通過粘合材料焊接到第一晶片101的主電極101a，副平板部分251g通過導電的粘合材料焊接到第一引腳111的鍵合區111a的頂面。功率控制器件還包括一個將晶片安裝單元、第一晶片101和第二晶片102、控制晶片103、金屬片251及導電結構311、各金屬凸塊201、第一旁路引腳121予以包覆的塑封體225（圖中未示出），塑封體225的包覆方式至少使各承載引腳的底面、第一基座110-1和第二基座110-2的底面、第一引腳111和第二引腳112各自的底面、基島113d的底面、第一旁路引腳121的底面從塑封體225的底面外露。
圖10B與圖10A的差異在於，無需考慮第一引腳111沿第一基座110-1的第一橫向邊緣110-1a的長度方向延伸的長度值與第一橫向邊緣110-1a的長度值之間的關係，可省略第一旁路引腳121。此時，利用鍵合引線119，將第一晶片101的正面的副電極101b電性連接至第一排承載引腳113中任意一個承載引腳上，作為優選，最好將副電極101b電性連接至最內側的承載引腳113-1上，則塑封體225（圖中未示出）將鍵合引線119包覆而不是導電結構311。
圖11A與圖10B的差異在於，連接結構117'被省略，基島113d是孤立的，沒有連接到任何承載引腳上，而且控制晶片103的背面通過非導電材料粘附在第一排承載引腳113、第二排承載引腳114上，控制晶片103也沒有向第一晶片101、第二晶片102偏移。利用鍵合引線119，將第一晶片101的副電極101b、基島113d分別電性連接至控制晶片103正面的相對應的焊墊上。除了連接至副電極101b、基島113d以外的餘下的焊墊，位於控制晶片103的一組對邊（如第一組對邊）中的一個邊緣附近的一些焊墊103a通過鍵合引線119電性連接至第一排承載引腳113的各承載引腳上，位於控制晶片103的該一組對邊中的另一個邊緣附近的一些焊墊103a通過鍵合引線119電性連接至第二排承載引腳114的各承載引腳上，為了縮短鍵合引線119的路徑，連接至副電極101b、基島113d上的這些焊墊103a最好位於控制晶片103的與前述一組對邊相對的另一組對邊（如第二組對邊）中的一個邊緣附近（該邊緣鄰近基座110）。在圖11B中，副平板部分251a通過導電的粘合材料焊接到第二引腳112的鍵合區112a的頂面，副平板部分251c通過粘合材料焊接到第二晶片102的背部電極102c（這與圖8A~8C中副平板部分251c焊接在第二晶片102的主電極102a有所不同），副平板部分250e通過粘合材料焊接到第一晶片101的主電極101a，副平板部分251g通過導電的粘合材料焊接到第一引腳111的鍵合區111a的頂面。功率控制器件還包括一個將晶片安裝單元、第一晶片101和第二晶片102、控制晶片103、金屬片251及鍵合引線119予以包覆的塑封體225（圖中未示出），塑封體225的包覆方式至少使各承載引腳的底面、第一基座110-1和第二基座110-2的底面、第一引腳111和第二引腳112各自的底面、基島113d的底面從塑封體225的底面外露。
在圖9B、10A~10B、11A的實施方式中，第一晶片101是N溝道型MOSFET，第二晶片102是N溝道型MOSFET。第一晶片101的主電極101a作為源極，副電極101b作為柵極，其背面的未示意出的金屬化層構成背部電極作為漏極。第二晶片102的主電極102a作為源極，副電極102b作為柵極，其背面的金屬化層構成背部電極作為漏極。
對於本領域的技術人員而言，閱讀上述說明後，各種變化和修正無疑將顯而易見。因此，所附的申請專利範圍書應看作是涵蓋本發明的真實意圖和範圍的全部變化修正。在申請專利範圍書範圍內任何和所有等價的範圍與內容，都應認為仍屬本發明的意圖和範圍內。

2A-2B, including the wafer mounting unit shown in FIG. 2A, the wafer mounting unit includes a generally square pedestal 110 and a first pin 111 and a second pin 112 adjacent thereto, and further includes A row of carrying pins 113, a second row of carrying pins 114, and a control wafer 103 and a first wafer 101, a second wafer 102. In order to facilitate the description and to understand the shape and positional relationship of each sub-portion of the wafer mounting unit, the plane in which the pedestal is located is defined, the X-axis is oriented horizontally, and the Y-axis perpendicular to the X-axis is oriented longitudinally, and the pedestal The direction in which the plane is orthogonal (Z-axis) is defined as the vertical/vertical direction. Thereby defining a first lateral edge 110a and a second lateral edge 110b of the base 110, which form an opposite set of opposite sides of the base, and define a first longitudinal edge 110c, a second longitudinal edge 110d of the base 110, which The opposite pair of opposite sides that make up the pedestal. The first pin 111 is adjacent to the first lateral edge 110a, the first pin 111 has an elongated bonding area 111a extending along the length of the first lateral edge 110a, and the second pin 112 is adjacent to the second lateral edge 110c, the second pin 112 also has an elongated bonding region 112a that extends along the length of the second lateral edge 110b. In addition, the first pin 111 further includes some external pins 111b perpendicular to the bonding region 111a and extending slightly outward in a direction away from the susceptor 110. The second pin 112 includes some external pins 112b perpendicular to the keys. The junction 112a extends slightly outwardly away from the susceptor 110.
The first row of carrier pins 113 is a collection of a plurality of carrier pins arranged in parallel (which may be arranged equidistantly or non-equidially), as is the second row of carrier pins 114. The first row of carrier pins 113 and the second row of carrier pins 114 are all located on the same side of the second longitudinal edge 110d of the pedestal 110, and each of the carrier pins of the first row of carrier pins 113 is parallel to a second longitudinal edge 110d extending from a transverse extension line of the first pin 111 (ie, an extension of its length direction) toward a symmetrical centerline 280 between the first lateral edge 110a and the second lateral edge 110b, and Each of the two rows of carrier pins 114 is parallel to the second longitudinal edge 110d and extends from the lateral extension of the second pin 112 to the symmetric centerline 280. In some embodiments, the base 110 has a connecting portion 115a disposed at a corner of the first lateral edge 110a and the second longitudinal edge 110d, the connecting portion 115a being from the top of the side of the base 110 at one side of the second longitudinal edge 110d A carrier pin 113-1 of the first row of the carrier pins 113 adjacent to the second longitudinal edge 110d extends and is connected to the carrier pin 113-1 to form the pedestal 110 and the carrier pin 113-1. There is a connection portion 115a therebetween, so the thickness of the general connection portion 115a is much thinner than that of the susceptor 110 and the carrier pin 113-1. For ease of illustration, the innermost carrier pin refers to a carrier pin adjacent to the second longitudinal edge of the first row of carrier pins (or the second row of carrier pins), corresponding to the outermost carrier A pin is one of the first row of carrying pins (or the second row of carrying pins) that is furthest from the second longitudinal edge.
2B, the first wafer 101 and the second wafer 102 are first mounted side by side on the top surface of the susceptor 110, the first wafer 101 is adjacent to the first lateral edge 110a, and the second wafer 102 is adjacent to the second lateral edge 110b. Thereafter, the control wafer 103 is flip-chip mounted on the first row of the carrier pins 113 and the second row of the carrier pins 114, but the control wafer 103 is offset from the first wafer 101 and the second wafer 102 by a distance. However, it is not possible to excessively offset to prevent access to the first metal piece 211 or the second metal piece 212 shown in FIG. 2D.
In the embodiment of FIG. 2C, the first wafer 101 is a high side MOSFET, the second wafer 102 is a low side MOSFET, the first wafer 101 is a P-channel MOSFET, and the second wafer 102 is an N-channel MOSFET. The front surface of the first wafer 101 is provided with a main electrode 101a (as a source) and a sub-electrode 101b (as a gate), and an unillustrated metallization layer on the back surface constitutes a back electrode (as a drain), and a back electrode thereof It is adhered to the top surface of the susceptor 110 by a conductive adhesive material. The front surface of the second wafer 102 is provided with a main electrode 102a (as a source) and a sub-electrode 102b (as a gate), and a metallization layer on the back surface constitutes a back electrode (as a drain), which is adhered by a conductive adhesive material. Attached to the top surface of the base 110.
2F is a schematic cross-sectional view along the broken line B1~B1 of FIG. 2D. Each of the carrier pins of the first row of carrying pins 113 includes an upper pin 113a and a lower pin 113b connected to each other. There is a height difference between the former, and the former position is high. Similarly, each of the carrier pins of the second row of carrying pins 114 includes an upper pin 114a and a lower pin 114b connected to each other to ensure completion. After the first and second wafers are pasted, the top surfaces of all the upper pins 113a or 114a of the first row of the carrier pins 113 and the second row of the carrier pins 114 are respectively associated with the first wafer 101 and the second wafer 102. The face is face to face.
For a more detailed description of the flip-chip form of the control wafer 103, FIG. 2C deliberately draws the control wafer 103 as transparent, and the respective pads on the front side (the specific description of the pads will be shown in FIG. 6B) are provided with metal bumps. Block 201, such as a solder ball or the like. The metal bumps 201 disposed on the pads near one of the pair of opposite sides of the control wafer 103 are respectively aligned with the respective upper pins 113a, and each of the metal bumps 201 is aligned with the solder and aligned thereon. The pin 113a remains electrically connected, and the metal bumps 201 disposed on the pads near the opposite edges of the pair of opposite sides are aligned with the respective upper pins 114a, each of the metal bumps 201 and The aligned and contacted upper pins 114a remain electrically connected. At the same time, the control wafer 103 is flip-chip mounted on the first and second rows of carrier pins 113, 144 in such a manner as to be offset from the first wafer 101 and the second wafer 102 by offsetting the second wafer 102. An overlapping portion overlapping the first row of the carrying pins 113 and the second wafer 114 is disposed such that the plurality of metal bumps 201 disposed on the plurality of pads on the front side of the overlapping portion are respectively aligned with the main electrode 101a of the first wafer 101 The sub-electrode 101b and the main electrode 102a and the sub-electrode 102b of the second wafer 102 are electrically connected to each of the metal bumps 201 and the main electrode 101a (or 201a) or the sub-electrode 101b (or 102b) aligned and soldered thereto. It is apparent that a plurality of pads on the front side of the overlap portion are located near one of the other pair of opposite sides of the control wafer 103. The top surface of the upper lead 113a or 114a is required to be coplanar with the front surface of each of the first and second wafers 101 and 102, so that the control wafer 103 can be horizontally tilted, and the metal bump 201 is less likely to be soldered.
As shown in FIG. 2D, the first metal piece 211 is mounted on the front surface of the first wafer 101 and the bonding area 111a of the first pin 111 by the bonding material, and the second metal piece 212 is mounted on the front surface of the second wafer 102. And a bonding area 112a of the second pin 112. 2E is a schematic cross-sectional view along the broken lines A1 to A1 of FIG. 2D, and the first wafer 101 and the second wafer 102 are adhered to the susceptor 110 by a conductive adhesive material 215. The first metal piece 211 and the second metal piece 212 are both bridge structures to match the height difference between the wafer and the lead, and the first metal piece 211 includes a main flat plate portion 211b (bridge portion) and is respectively connected to the two The two sub-plate portions 211a, 211c (valley portions) on the side, the sub-plate portions 211a, 211c have a height drop with respect to the main flat plate portion 211b, the former being at a lower position and the latter being at a higher position, passing the adhesive material, the sub-plate portion 211a Adhered to the top surface of the bonding region 111a of the first pin 111, the sub-plate portion 211c is adhered to the main electrode 101a of the first wafer 101. Similarly, the second metal piece 212 also includes a main flat plate portion 212b and two sub-plate portions 212a, 212c respectively connected to both sides thereof, and the sub-plate portion 212a is adhered to the top of the bonding portion 112a of the second pin 112. The sub-plate portion 212c is adhered to the main electrode 102a of the second wafer 102. 2G is a schematic cross-sectional view along the broken line C1 to C1 of FIG. 2D, showing the structure of the connecting portion 115a extending from the top of the side of the base 110 on the side of the second longitudinal edge 110d to the innermost carrying pin 113-1. And connected thereto, the thickness of the connecting portion 115a is smaller than the thickness of the susceptor 110 and the carrying pin.
As shown in FIG. 2H, a wafer mounting unit, a first wafer 101 and a second wafer 102, a control wafer 103, a first metal piece 211 and a second metal piece 212, and metal bumps are prepared by using an epoxy resin molding material. The sealing body 225 is sealed and covered. The sealing body 225 is covered in at least the bottom surface of each of the lower pins 113b and 114b, the bottom surface of the base 110, the first pin 111 and the second pin. The respective bottom surfaces of the 112 are exposed from the bottom surface of the molding body 225. In contrast, FIG. 2A is a plan view from the front side of the wafer mounting unit, and in FIG. 2H, it is viewed from the back side of the base, except that most of the wafer mounting unit is covered by the molded body 225 at this time. As a result, only the bottom surfaces of the lower pins 113b, 114b, the bottom surface of the susceptor 110, the bottom surfaces of the bonding regions 111a, 112a, and the bottom surfaces of the external leads 111b, 112b are exposed outside the molding body, and from the molding body 225 The top view (not shown in plan view), the first wafer 101 and the second wafer 102, the control wafer 103, the first metal piece 211 and the second metal piece 212, and the respective metal bumps 201 are completely sealed and invisible.
In the embodiment of FIGS. 2G to 2H, the thickness of the connection portion 115a between the susceptor 110 and the carrier pin 113-1 is much thinner than that of the susceptor 110 and the carrier pin 113-1, so that the connection portion 115a is After the molding process is completed, it is sealed by the subsequent molding body 225. However, in other alternative embodiments not shown, the thickness of the connecting portion 115a may be the same as the thickness of the base 110 and the carrying pin 113-1 except that the bottom surface of the connecting portion 115a will be from the molded body 225. The bottom is bare and no longer hidden.
As shown in FIG. 3A, the wafer mounting unit is not significantly different from the structure shown in FIG. 2A, except that a generally square-shaped recess 1100 is etched or embossed on the top surface of the susceptor 110, and the other difference is Each of the first row of carrying pins 113 and the second row of carrying pins 114 does not include an upper portion and a lower portion, and each of the carrying pins is a strip-shaped flat structure. In this case, only the depth of the recess 1100 needs to be adjusted, that is, the remaining thickness of the susceptor 110 is adjusted, so that the front surface of the first wafer 101, the front surface of the second wafer 102, and the first row of the carrying pins 113, The top surface of each of the two rows of carrying pins 114 is coplanar, and even if the carrying pins are not provided with an upper portion and a lower portion, the control wafer 103 can be satisfactorily mounted, as shown in FIG. 3D. Along the cross section of the broken line B2 to B2 in Fig. 3B. The control wafer 103 is still flip-chip mounted on the first row of the carrier pins 113 and the second row of the carrier pins 114 in such a manner as to be offset from the first wafer 102 and the second wafer 103, such that the offset is such that A wafer 102 and a second wafer 103 form overlapping overlapping portions, and a plurality of metal bumps 201 disposed on some of the pads adjacent to one of a pair of opposite sides of the control wafer 103 on the front side of the overlapping portion are respectively paired The second electrode 101 is electrically and electrically connected to the main electrode 101a and the sub-electrode 101b of the first wafer 101, and is electrically connected to the main electrode 102a and the sub-electrode 102b of the front surface of the second wafer 102, and at the same time, for the remaining pads. Aligning and electrically connecting the metal bumps 201 disposed on the pads of the control wafer 103 near one of the other pair of opposite sides to the respective carrier pins of the first row of the carrier pins 113, so that the control wafer 103 is The metal bumps 201 disposed on the pads near the other of the other pair of opposite sides are aligned and electrically connected to the respective carrier pins of the second row of carrier pins 114. 3C is a cross section along the broken lines A2 to A2 in FIG. 3B. The first wafer 101 and the second wafer 102 are both located in the recess 1100, and the backs of the first wafer 101 and the second wafer 102 are respectively made by the adhesive material 215. The electrodes are all adhered to the bottom of the groove 1100. At this time, unlike the bottom surface of the lower portion 113b, 114b of the bearing pin in FIG. 2H, which is exposed from the bottom surface of the molding body 225, in FIG. 3E, the first row carries the pin 113 and the second row carries the pin. The bottom surface of each of the carrier pins of 114 is completely exposed directly from the bottom surface of the molding body 225. However, the first wafer 101 and the second wafer 102, the control wafer 103, the first metal piece 211 and the second metal piece 212, and the respective metal bumps 201 are still completely sealed by the molding body 225 without being visible.
In FIG. 4A, the difference from FIG. 3B is that the first metal piece 2110 and the second metal piece 2120 are no longer the first metal piece 211 and the second metal piece 212 of the bridge structure, as shown in FIG. 4B along the dashed line in FIG. 4A. As shown in the cross section of A3 to A3, the first metal piece 2110 includes a main flat plate portion 2110b and a sub-plate portion 2110a having a height drop connected to one side thereof, and a vertical direction is provided on the bottom surface of the main flat plate portion 2110b. The lower extending end portion 2110c is welded to the main electrode 101a of the first wafer 101 by the adhesive material 215, and the bottom end surface of the end portion 2110c is welded to the bonding portion 111a of the first lead 111. The second metal piece 2120 includes a main flat plate portion 2120b and a sub-plate portion 2120a attached to one side thereof, and a vertically downwardly extending end portion 2120c is provided on the bottom surface of the main flat plate portion 2120b through the adhesive material 215. The bottom end surface of the end portion 2120c is soldered to the main electrode 102a of the second wafer 102, and the sub-plate portion 2120a is soldered to the bonding portion 112a of the second lead 112. Due to factors of the manufacturing process, such as press forming, it is considered that the main flat plate portion 211b (or 212b) of the first metal piece 211 (or the second metal piece 212) such as the bridge structure is slightly raised to an upward bulge in many cases. The dome or the dome is shaped such that the top surface of the main flat plate portion 211b is difficult to be completely exposed in the molding process, so that the molding compound tends to directly mold the first metal piece 211 (or the second metal piece 212). The first metal piece 2110 and the second metal piece 2120 can overcome this problem well, so the top surface of each of the main flat plate portion 2110b and the main flat plate portion 2120b can be from the top surface of the molded body 225 (ie, the molded body 225). It is exposed in the other side opposite to the bottom surface shown in Fig. 3E, as shown in Fig. 4C. Further, if it can be ensured that the top faces of the main flat plate portions 211b, 212b are absolutely flat faces, they may also be exposed from the top surface of the molded body 225. The cross section along the broken lines B3 to B3 in Fig. 4A is exactly the same as that of Fig. 3D, so that the back surface of the control wafer 103 can be made as long as the depth of the groove 1100 (corresponding to adjusting the height of the main flat plate portion 2110b and the main flat plate portion 2120b) is adjusted. The top surfaces of the main flat plate portion 2110b and the main flat plate portion 2120b are in the same plane, so that the back surface of the flip-chip control wafer 103 can also be exposed from the top surface of the molded body 225, which provides a more heat dissipation path for the power device. More choices. At this time, the molding body 225 is covered by at least the first row of the carrier pins 113, the bottom surface of each of the carrier pins of the second row of the carrier pins 114, the bottom surface of the susceptor 110, the first pins 111 and the second The bottom surface of each of the pins 112 is exposed from the bottom surface of the molding body 225, which is no different from FIG. 3E. In some embodiments, the first metal piece 2110, the second metal piece 2120, and the control wafer 103 can also be completely covered from the selected molded body 225.
As shown in FIG. 5A, the length value L1 of the first pin 111 extending along the length direction of the first lateral edge 110a is smaller than the length value L2 of the first lateral edge 110a, and the second pin 112 extends along the length direction of the second lateral edge 110b. The length value L3 is smaller than the length value L4 of the second lateral edge 110b, thereby setting the first bypass pin 121 and the second bypass pin 122 of the wafer mounting unit. The first bypass pin 121 is adjacent to the first lateral edge 110a and disposed on a lateral extension line of the first pin 111 (ie, a delay line in the longitudinal direction thereof), and is located at the innermost one of the first row of the carrier pins 113. Between the pin 113-1 and the first pin 111, the first bypass pin 121 has a connection portion 115c that is adjacent to the innermost carrier pin 113 from the first bypass pin 121- The top of one side of the 1 extends toward the carrier pin 113-1 and is coupled to the carrier pin 113-1. The thickness of the connection portion 115c is now smaller than the thickness of the first bypass pin 121, in some cases. In the illustrated embodiment, the thickness of the connecting portion 115c may be equal to the thickness of the first bypass pin 121 and the carrier pin 113-1. Similarly, the second bypass pin 122 is adjacent to the second lateral edge 110b and disposed on the lateral extension line of the second pin 112 (ie, the delay line in the length direction thereof) on the innermost side of the second row of carrier pins 114. Between a carrier pin 114-1 and a second pin 112, the second bypass pin 122 has a connection portion 115d that is adjacent to the innermost carrier pin 114 from the second bypass pin 122. The top of one side of the -1 extends toward the carrier pin 114-1 and is coupled to the carrier pin 114-1. Typically, the thickness of the connection portion 115d is smaller than the thickness of the second bypass pin 122, but The thickness of the connecting portion 115d is designed to be equal to the thickness of the second bypass pin 122 and the carrier pin 114-1. In FIG. 5A, the back electrodes of the respective back surfaces of the first wafer 101 and the second wafer 102 are adhered to the top surface of the susceptor 110, and the main electrode 101a of the first wafer 101 is electrically connected to the first metal sheet 211. On a pin 111, the main electrode 102a of the second wafer 102 is electrically connected to the second pin 112 through a second metal piece 212. The control wafer 103 is flip-chip mounted on the first row of carrier pins 113 and the second row of carrier pins 114, but the control wafer 103 is not offset in the direction of the first wafer 102 and the second wafer 103, and the front side of the wafer 103 is controlled. Metal bumps 201 disposed on some of the pads adjacent one of the pair of opposite sides are aligned and electrically connected to the respective carrier pins of the first row of carrier pins 113 on the opposite side of the set The metal bumps 201 disposed on some of the pads near the other edge are aligned and electrically connected to the respective carrier pins of the second row of carrier pins 114.
In FIG. 5A, the pedestal 110 is mechanically and electrically connected to the first row of carrier pins 113 or the second row of carrier pins 114 except for the innermost carrier pin 113-1 or by an L-shaped connection structure 117. Any one of the carrier pins other than 114-1, for example, connected to a carrier pin 114-2 adjacent to the carrier pin 114-1 and located outside the carrier pin 114-1 in the second row of carrier pins 114 on. The connecting structure 117 includes a laterally extending section 117b and a longitudinally extending section 117a that are connected to each other and are in the same plane. 5C to 5D are cross sections along E1 to E1 and E2 to E2, respectively, and one end of the laterally extending section 117b is connected to the top of one side of the base 110 at the second longitudinal edge 110d, and one end of the longitudinally extending section 117a is abutted at one end. The top end of one end carrying the pin 114-2, the other end of the laterally extending section 117b is connected to the other end of the longitudinally extending section 117a, so that the connection structure 117 is generally thinner than the pedestal 110 and the carrier pin 114-2. In the embodiment of FIGS. 5C-5D, the connection structure 117 is hidden by the molding body 225 after the molding process is completed, and in some alternative embodiments, the thickness of the connection structure 117 can be compared with the susceptor 110. The thickness of the carrier pin 114-2 is the same, and then the bottom surface of the connection structure 117 will be exposed from the bottom surface of the molding body 225. The sub-electrode 101b on the front surface of the first wafer 101 is electrically connected to the first bypass pin 121 through the conductive structure 311, and the sub-electrode 102b on the front surface of the second wafer 102 is electrically connected to the second bypass pin 122 through the conductive structure 312. The conductive structures 311, 312 may be metal sheets, strip-shaped conductive strips, bonding wires, or the like. 5B is a schematic cross-sectional view taken along the dashed line D2 to D2 of FIG. 5A. The metal plate of the bridge structure is still taken as an example. The sub-plate portions 311a and 311c on both sides of the main flat plate portion 311b of the conductive structure 311 are respectively bonded to the first side. On the top surface of the path pin 121 and the sub-electrode 101b on the front surface of the first wafer 101, the sub-plate portions 312a, 312c on both sides of the main plate portion 312b of the conductive structure 312 are bonded to the top surface of the second bypass pin 122, respectively. And on the secondary electrode 102b on the front side of the second wafer 102. In the subsequent molding process, the bottom surface of the pedestal 110 and the bottom surface of each of the first row of carrier pins 113 and the second row of carrier pins 114 are directly exposed from the bottom surface of the molding body 225, first The bottom surface of the pin 111 and the second pin 121 is exposed from the bottom surface of the molding body 225, and the bottom surfaces of the first bypass pin 121 and the second bypass pin 122 are also exposed from the bottom surface of the molding body 225, but the first wafer 101 and the first wafer 101 The two wafers 102, the control wafers 103, the first metal sheets 211 and the second metal sheets 212, and the metal bumps 201 and the conductive structures 311, 312 are still completely sealed by the molding body 225.
In FIG. 6A, the first wafer 101 and the second wafer 102 are first adhered to the top surface of the susceptor 110, so that the back electrodes of the respective back surfaces of the first wafer 101 and the second wafer 102 are adhered to the susceptor 110. On the top surface, the control wafer 103 is flip-chip mounted on the first row of carrier pins 113 and the second row of carrier pins 114, and then the main electrode 101a of the first wafer 101 is electrically connected to the first through the first metal piece 211. On the pin 111, the main electrode 102a of the second wafer 102 is electrically connected to the second pin 112 through a second metal piece 212. The control wafer 103 is not offset in the direction of the first wafer 102 and the second wafer 103, and the metal bumps 201 disposed on some of the pads near one of the pair of opposite sides of the control wafer 103 are aligned and electrically connected to On each of the carrier pins of the first row of carrying pins 113, metal bumps 201 disposed on some of the pads adjacent to the other of the pair of opposite sides of the control wafer 103 are aligned and electrically connected to the second row Each of the carrier pins of the pin 114 is carried.
The sub-electrode 101b of the front surface of the first wafer 101 is electrically connected to any one of the first row of the carrier pins 113 by using the bonding wires 119. Preferably, the sub-electrode 101b is preferably electrically connected to the most. The inner side of the carrier pin 113-1 is such that the path of the bonding wire 119 is the shortest. Similarly, the secondary electrode 102b on the front surface of the second wafer 102 is electrically connected to any one of the second row of carrier pins 114, and the top surface of the susceptor 110 is electrically connected to the first surface by the bonding wire 119. The other of the two rows of carrier pins 114 are not connected to any of the remaining carrier pins connected to the secondary electrode 102b. For example, the secondary electrode 102b is electrically connected to the innermost carrier pin 114-1, and the base 110 is electrically connected. To the carrier pin 114-2 adjacent to the carrier pin 114-1 and outside the carrier pin 114-1, this also shortens the path of the bond wire 119. In the subsequent molding process, the bottom surface of the pedestal 110 and the bottom surface of each of the first row of carrier pins 113 and the second row of carrier pins 114 are directly exposed from the bottom surface of the molding body 225, first The bottom surface of the second pin is exposed from the bottom surface of the molding body 225, the first wafer 101 and the second wafer 102, the control wafer 103, the first metal piece 211 and the second metal piece 212, and the metal bumps 201 and the bonding wires 119. Still completely sealed by the molded body 225.
The difference from FIG. 5A is that, in FIG. 6B, the control wafer 103 is not flip-chip mounted on the first row of carrier pins 113 and the second row of carrier pins 114, the front side of the control wafer 103 is upward, and the back side is non-conductive. The adhesive adheres to the first row of carrier pins 113 and the second row of carrier pins 114, and the control wafer 103 is also not offset in the direction of the first wafer 102 and the second wafer 103. The secondary electrode 101b on the front surface of the first wafer 101, the secondary electrode 102b on the front surface of the second wafer 102, and the top surface of the susceptor 110 are electrically connected to the corresponding pads 103a on the front surface of the control wafer 103 by using the bonding wires 119, respectively. In the case where the control wafer 103 is flip-chip mounted, it is not necessary to solder the metal bumps 201 on the pads 103a of the control wafer 103, and the bonding wires 119 are directly soldered. For all of the pads 103a, in addition to the remaining pads connected to the sub-electrodes 101b, 102b, the pedestal 110, some of the pads 103a located near one of a pair of opposite sides of the control wafer 103 are electrically Connected to the top surface of each of the carrier pins of the first row of carrier pins 113, some pads 103a adjacent to the other of the pair of opposite sides of the control wafer 103 are electrically connected to the second row of carrier pins On the top surface of each of the carrier pins 114, in order to shorten the path of the bonding wires 119, the pads 103a connected to the sub-electrodes 101b, 102b and the susceptor 110 are preferably located in one of the other opposite sides of the control wafer 103. Near the edge (the edge is adjacent to the pedestal 110). In the subsequent molding process, the bottom surface of the pedestal 110 and the bottom surface of each of the first row of carrier pins 113 and the second row of carrier pins 114 are directly exposed from the bottom surface of the molding body 225, first The bottom surface of the second pin is exposed from the bottom surface of the molding body 225, and the first wafer 101 and the second wafer 102, the control wafer 103, the first metal piece 211 and the second metal piece 212, and the bonding wire 119 are completely sealed by the molding body 225. .
In the embodiment of FIGS. 5A, 6A, and 6B, the first wafer 101 is a P-channel MOSFET, and the second wafer 102 is an N-channel MOSFET. The main electrode 101a serves as a source, the sub-electrode 101b serves as a gate, and the unillustrated metallization layer on the back surface constitutes a back electrode as a drain. The main electrode 102a serves as a source, the sub-electrode 102b serves as a gate, and the metallization layer on the back surface constitutes a back electrode as a drain.
7A to 7D, in the power control device, a wafer mounting unit and a control wafer 103, and a first wafer 101 and a second wafer 102 are included. The wafer mounting unit shown in FIG. 7A includes adjacent first pedestal 110-1 and second pedestal 110-2, which are generally square and include a first pin 111 and a first portion near the first pedestal 110-1. A row of carrying pins 113, and a second pin 112 and a second row of carrying pins 114 in the vicinity of the second pedestal 110-2. The first pedestal 110-1 has an opposite set of first lateral edges 110-1a and second lateral edges 110-1b, and has an opposite set of first longitudinal edges 110-1c, second longitudinal edges 110-1d, Forms its four edges. Likewise, the second pedestal 110-2 also has an opposing set of first lateral edges 110-2a and second lateral edges 110-2b, and an opposing set of first longitudinal edges 110-2c, second longitudinal edges 110 -2d, which constitutes its four edges. The first pedestal 110-1 is disposed side by side with the second pedestal 110-2, and the first lateral edge 110-2a of the second pedestal 110-2 is adjacent to the second lateral edge 110-1b of the first pedestal 110-1, In some alternative embodiments, the second longitudinal edge 110-1d is generally aligned with the second longitudinal edge 110-2d, the first longitudinal edge 110-1a being substantially aligned with the second longitudinal edge 110-2a. If the first row of carrier pins 113 is considered as a whole and the second row of carrier pins 114 is considered as a whole, it can be considered that both the first row of carrier pins 113 and the second row of carrier pins 114 are Set in a parallel arrangement.
7C is a cross section along the broken line A4-A4 in FIG. 7B. Referring to FIG. 7A, it can be seen that the first pin 111 is adjacent to the first lateral edge 110-1a of the first pedestal 110-1, and the first pin 111 is The strip bonding region 111a extends along the length direction of the first lateral edge 110-1a of the first pedestal 110-1. The second pin 112 is adjacent to the second lateral edge 110-2b of the second pedestal 110-2, and the strip-shaped bonding region 112a of the second pin 111 is along the second lateral edge 110-2a of the second pedestal 110-2 The length extends. The first row of carrier pins 113 are located on one side of the second longitudinal edge 110-1d of the first pedestal 110-1, and each of the first row of carrier pins 113 is parallel to the first pedestal 110- a second longitudinal edge 110-1d of 1 and directed to the first pedestal 110-1 by a lateral extension line (longitudinal extension line) of the first pin 110-1 having a first direction (X-axis positive axis) and A dividing line 380 between the second pedestals 110-2 extends. The second row of carrier pins 114 are located on one side of the second longitudinal edge 110-2d of the second pedestal 110-2, and each of the second row of carrier pins 114 is parallel to the second pedestal 110 The second longitudinal edge 110-2d of -2 extends from the lateral extension of the second pin 112 in the same direction as the first direction toward the dividing line 380. The first wafer 101 is pasted on the top surface of the first pedestal 110-1, and the second wafer 102 is pasted on the second pedestal 110-2. The back electrodes of the back surface of the first wafer 101 and the second wafer 102 are respectively The top surface of the first pedestal 110-1 and the second pedestal 110-2 are respectively adhered, and the control wafer 103 is flip-chip mounted on the first row of the carrying pins 113 and the second row of the carrying pins 114.
In FIG. 7A, the second pin 112 has a connection portion 115b from the top of the strip bonding region 112a of the second pin 112 near the innermost carrier pin 114-1 of the second row of carrier pins 114. One side extends toward the innermost carrier pin 114-1 and is coupled to the carrier pin 114-1. 7A is similar to FIG. 2F. Each of the carrier pins of the first row of carrier pins 113 includes an upper pin 113a and a lower pin 113b connected to each other, and the second row carries each of the pins 114. The carrier pins each include an upper pin 114a and a lower pin 114b connected to each other. After the bonding process of the completed wafer shown in FIG. 7B, the tops of the upper pins 113a, 114a of all the carrying pins are provided. The faces are coplanar with the front faces 101a, 102a of the first wafer 101 and the second wafer 102, thereby controlling the wafer 103 to be flip-chip mounted on the first row of carrier pins in such a manner as to be offset from the first wafer 101 and the second wafer 102. 113, the second row of carrying pins 114, the degree of offset is such that the control wafer 103 has overlapping portions that overlap with the first wafer 101 and the second wafer 102, such that a plurality of pads on the front side of the overlapping portion are disposed The plurality of metal bumps 201 are respectively aligned and soldered to the main electrode 101a, the sub-electrode 101b on the front surface of the first wafer 101, and the main electrode 102a and the sub-electrode 102b aligned and soldered to the front surface of the second wafer 102, except for the overlapping portion. In addition, the metal bumps provided on the remaining pads of the control wafer 103 are controlled. 201 are aligned with and electrically connected to a first row of the carrier pin 113, a second row of pins 114 carried in respective ones of the opposing pin, which is identical to FIG. 2C. It is worth noting that the control wafer 103 cannot be excessively offset to prevent contact with the metal piece 250. In FIGS. 7B-7C, the main electrode 101a of the first wafer 101 and the main electrode 102a of the second wafer 102 are electrically connected to the second lead 112 through a metal piece 250. The metal piece 250 is integrally formed into a wave shape or The square wave structure includes a plurality of main flat plate portions 250b, 250d (bridge portion) and a plurality of sub-plate portions 250a, 250c, 250e (valley portions), and the height of the plane of the main flat plate portion is higher than that of any one of the sub-plate portions The height of the plane, the sub-plate portions 250c, 250e on the inner side of the metal piece 250 are coplanar, and the sub-plate portion 250a at the head end and the sub-plate portions 250c, 250e at the inner side are not coplanar and lower than the latter. The main flat plate portion and the sub-plate portion are adjacently intersected with each other, and two sub-plate portions are respectively connected to both sides of each main flat plate portion. Wherein, the sub-plate portion 250a is soldered to the top surface of the bonding region 112a of the second pin 112 by a conductive bonding material, and the sub-plate portion 250c is soldered to the main electrode 102a of the second wafer 102 by the bonding material, the sub-plate The portion 250e is soldered to the main electrode 101a of the first wafer 101 by an adhesive material.
In FIGS. 7A and 7C, the first pedestal 110-1 has a connecting portion 116 extending from the top of the first pedestal 110-1 to the first pin 111 on a side of the first lateral edge 110-1a thereof. And connected to the first pin 111, generally the thickness of the connecting portion 116 is smaller than the thickness of the first pedestal 110-1 for clamping the molding body 225. As shown in the bottom surface of the molding body 225 shown in FIG. 7D, the power control device further includes a wafer mounting unit, a first wafer 101 and a second wafer 102, a control wafer 103, a metal piece 250, and respective metal bumps 201. The molding body 225, the molding body 225 is covered by at least the bottom surface of each of the lower pins 113b, 114b, the bottom surface of the first pedestal 110-1 and the second pedestal 110-2, the first pin 111 and the The bottom surfaces of the two pins 112 are exposed from the bottom surface of the molding body 225.
In FIG. 8A, the control wafer 103 is flip-chip mounted on the first row of carrier pins 113 and the second row of carrier pins 114, but is not offset from the first wafer 101 and the second wafer 102, and controls a group of wafers 103. The metal bumps 201 disposed on the pads near one edge of the pair are respectively aligned with the respective carrier pins of the first row of the carrier pins 113, and each of the metal bumps 201 and the carrier pin aligned with and in contact therewith The feet are welded to maintain an electrical connection. The metal bumps 201 disposed on the pads near the opposite edges of the pair of opposite sides of the control wafer 103 are aligned with the respective carrier pins of the corresponding second row of carrier pins 114, each of the metal bumps 201 Soldering and maintaining electrical connections to the carrier pins that are aligned and in contact therewith. The first pedestal 110-1 does not have a connection portion 116 similar to that shown in FIG. 7A, and the first pedestal 110-1 is separated from the first pin 111.
The length value of the first pin 111 extending along the length direction of the first lateral edge 110-1a of the first pedestal 110-1 is smaller than the length value of the first lateral edge 110-1a, and the second pin 112 is along the second pedestal The length value of the second lateral edge 110-2b of 110-2 extending in the length direction is smaller than the length value of the second lateral edge 110-2b. The first bypass pin 121 included in the wafer mounting unit is disposed on a lateral extension line (an extension line in the longitudinal direction) of the first pin 111, adjacent to the first lateral edge 110-1a of the first pedestal 110-1, and located at The first row carries the innermost one of the pins 113 between the carrier pin 113-1 and the first pin 111. The first bypass pin 121 has a connection portion 115c from the top of the first bypass pin 121 near the side of the innermost carrier pin 113-1 of the first row of carrier pins 113 to the carrier pin 113-1 extends and is connected thereto, which is described in detail in Figure 5A. At the same time, the second bypass pin 122 included in the wafer mounting unit is disposed on a lateral extension line of the second pin 112 (an extension line in the longitudinal direction thereof) adjacent to the second lateral edge 110 of the second pedestal 110-2. -2b, and located between the first inner carrier pin 114-1 and the second pin 112 of the second row of carrying pins 114. The second bypass pin 122 has a connection portion 115d from the top of the second bypass pin 122 near the side of the innermost carrier pin 114-1 of the second row of carrier pins 114 to the carrier pin 114-1 extends and is connected thereto, which is also described in detail in Figure 5A. The sub-electrode 101b on the front surface of the first wafer 101 is electrically connected to the first bypass pin 121 through the conductive structure 311, and the sub-electrode 102b on the front surface of the second wafer 102 is electrically connected to the second bypass pin 122 through the conductive structure 312. Above, reference can be made to Figure 5A. At the same time, the second lead 112 or the main electrode 102a of the second wafer 102 is electrically connected to any one of the second row of carrying pins 114 except the innermost carrying pin 114-1 by means of the bonding wire 119. Preferably, the pin is electrically connected to the carrier pin 114-2 adjacent to the carrier pin 114-1 and located outside the carrier pin 114-1. In addition, the main electrodes 101a and 101b of the front surface of each of the first wafer 101 and the second wafer 102 are electrically connected to the first pin 111 and the second pin 112 through the metal piece 251, respectively, and the structure of the metal piece 251 can be observed. 11B, the metal piece 251 is also an integrally formed wavy or square wave structure, and includes a plurality of main flat plate portions 251b, 251d, 251f (bridge portion) and a plurality of sub-plate portions 251a, 251c, 251e, 251g (valley portion). The height of the plane of the main flat plate portion is higher than the height of the plane of any one of the sub-plate portions, and the main flat plate portion and the sub-plate portion are adjacent to each other, and two sub-plate portions are respectively connected to two sides of each main flat plate portion. . The sub-plate portions 251a, 251g at both ends of the metal piece 251 are not coplanar with the inner sub-plate portions 251c, 251e, but the inner sub-plate portions 251c, 251e are coplanar with each other, and the sub-plate portions 251a, 251g at both ends are coplanar and low. The height of the sub-plate portions 251c, 251e on the inner side. In FIG. 8A, the sub-plate portion 251a is soldered to the top surface of the bonding region 112a of the second pin 112 by a conductive bonding material, and the sub-plate portion 251c is soldered to the main electrode 102a of the second wafer 102 by an adhesive material. The sub-plate portion 251e is welded to the main electrode 101a of the first wafer 101 by an adhesive material, and the sub-plate portion 251g is soldered to the top surface of the bonding region 111a of the first pin 111 by a conductive adhesive material. The power control device further includes a plastic package covering the wafer mounting unit, the first wafer 101 and the second wafer 102, the control wafer 103, the metal piece 251 and the metal bumps 201, the bonding wires 119, and the conductive structures 311, 312. The body 225 (not illustrated in this embodiment), the molding body 225 is covered by at least the bottom surface of each of the carrier pins, the bottom surface of the first pedestal 110-1 and the second pedestal 110-2, and the first pin The bottom surface of each of the 111 and the second pins 112 is exposed from the bottom surface of the molding body 225, and the bottom surfaces of the first bypass pin 121 and the second bypass pin 122 are also exposed from the bottom surface of the molding body 225, but the first wafer 101 and the first wafer 101 The two wafers 102, the control wafers 103, the metal sheets 251, the bonding wires 119, and the respective metal bumps 201 and the conductive structures 311, 312 are still completely sealed by the molding body 225.
8B and 8A are different in that it is not necessary to consider the length value of the first pin 111 extending along the length direction of the first lateral edge 110-1a of the first pedestal 110-1 and the length value of the first lateral edge 110-1a. The relationship between the two pins 112 along the length direction of the second lateral edge 110-2b of the second pedestal 110-2 and the length value of the second lateral edge 110-2b need not be considered. Because the first bypass pin 121 and the second bypass pin 122 are removed. At this time, the sub-electrode 101b of the front surface of the first wafer 101 is electrically connected to any one of the first-row carrying pins 113 by using the bonding wires 119. Preferably, the sub-electrode 101b is preferably electrically connected. The connection to the innermost carrier pin 113-1 is such that the path of the bonding wire 119 is the shortest. Similarly, the secondary electrode 102b on the front surface of the second wafer 102 is electrically connected to any one of the second row of carrier pins 114, and the main electrode 102a of the second wafer 102 is electrically connected by the bonding wire 119. Up to any of the remaining carrier pins of the second row of carrier pins 114 that are not connected to the secondary electrode 102b, for example, the secondary electrode 102b is electrically connected to the innermost carrier pin 114-1, and the main electrode 102a is electrically The connection to the carrier pin 114-2 adjacent to the carrier pin 114-1 and outside the carrier pin 114-1 can shorten the path of the bond wire 119. The power control device further includes a molding body 225 for covering the wafer mounting unit, the first wafer 101 and the second wafer 102, the control wafer 103, the metal piece 251, and each of the metal bumps 201 and the bonding wires 119 (this embodiment) The package body 225 is covered in at least the bottom surface of each of the carrier pins, the bottom surface of the first pedestal 110-1 and the second pedestal 110-2, the first pin 111 and the second pin. The respective bottom surfaces of the 112 are exposed from the bottom surface of the molding body 225, but the first wafer 101 and the second wafer 102, the control wafer 103, the metal piece 251, the bonding wires 119, and the respective metal bumps 201 are still completely sealed by the molding body 225.
8C and 8B differ in that the control wafer 103 is not flip-chip mounted on the first row of carrier pins 113 and the second row of carrier pins 114, and the back side of the control wafer 103 is adhered to the first by a non-conductive adhesive. The row carries pins 113 and the second row of carrier pins 114, and the control wafer 103 is also not offset in the direction of the first wafer 102 and the second wafer 103. The sub-electrode 101b on the front surface of the first wafer 101 and the main electrode 102a and the sub-electrode 102b on the front surface of the second wafer 102 are electrically connected to a plurality of corresponding pads 103a on the front surface of the control wafer 103, respectively. In the case where the control wafer 103 is flip-chip mounted in 8A to 8B, it is not necessary to solder the metal bump 201 on the pad 103a of the control wafer 103, but serves as a bonding region to cater for the bonding of the bonding wires 119. In all of the pads 103a of the control wafer 103, for the remaining pads other than the secondary electrodes 101b, 102b, the main electrode 102a, some of the edges of one of the opposite sides of the control wafer 103 are located. The pad 103a is electrically connected to each of the carrier pins of the first row of the carrier pins 113, and some of the pads 103a located near the other of the pair of opposite sides of the control wafer 103 are electrically connected to the second row of carriers. On each of the carrier pins of the pin 114, in order to shorten the path of the bonding wire 119, the pads 103a connected to the sub-electrodes 101b, 102b and the main electrode 102a are preferably located on the control wafer 103 opposite to the aforementioned pair of opposite sides. The other set of edges is adjacent to one of the edges and the edge is adjacent to the pedestal 110. In this embodiment, the power control device further includes a molding body 225 that covers the wafer mounting unit, the first wafer 101 and the second wafer 102, the control wafer 103, the metal piece 251, and the bonding wires 119. Not shown in the manner), the molding body 225 is covered by at least the bottom surface of each carrying pin, the bottom surface of the first pedestal 110-1 and the second pedestal 110-2, the first pin 111 and the second lead The bottom surface of each of the legs 112 is exposed from the bottom surface of the molding body 225, but the first wafer 101 and the second wafer 102, the control wafer 103, the metal piece 251, and the bonding wires 119 are still completely sealed by the molding body 225.
In the embodiment of FIGS. 7B and 8A to 8C, the first wafer 101 is an N-channel MOSFET, and the second wafer 102 is an N-channel MOSFET of a top-drain bottom source. The main electrode 101a of the first wafer 101 serves as a source, the sub-electrode 101b serves as a gate, and the unillustrated metallization layer on the back surface constitutes a back electrode as a drain. The main electrode 102a of the second wafer 102 serves as a drain, the sub-electrode 102b serves as a gate, and the metallization layer on the back surface constitutes a back electrode as a source of the bottom.
9A shows a detailed structure of a wafer mounting unit, which differs from FIG. 7A in that a substantially rectangular second base 110-2 is at its first lateral edge 110-2a and second longitudinal edge 110-2d. The corner of the intersection has a rectangular slit to make the second pedestal 110-2 appear as an L-shaped structure, and a base island 113d is embedded in the slit. The wafer mounting unit further includes a connection structure 113c including a horizontally extending section 113c-1 and an inclined extension 113c-2 perpendicular to the horizontally extending section 113c-1, the horizontally extending section 113c-1 extending longitudinally on a horizontal plane a first row of carrier pins 113, a second row (eg, parallel to the second longitudinal edges 110-1d, 110-2d) butside the carrier pins 114-1 that are the innermost of the second row of carrier pins 114 On an upper portion of any one of the carrying pins 114, for example, one end of the horizontally extending portion 113c-1 is preferably abutted at one end of the innermost carrying pin 113-1 adjacent the second longitudinal edge 110-1d and The two are in common. The inclined extension 113c-2 of the connecting structure 113c forms an angle greater than zero with the horizontal plane, one end of which is connected to the horizontally extending section 113c-1, and the other end of which extends obliquely downward until it is connected to the island 113d, as shown in FIG. 9D. Along the cross section of the broken line C2 to C2 in Fig. 9A, the connecting structure 113c is not L-shaped in a strict sense because the horizontally extending section 113c-1 and the inclined extending section 113c-2 are not coplanar, and the inclined extending section 113c-2 is opposite. The horizontally extending section 113c-1 is bent downward, which facilitates matching the stereoscopic height difference between the base island 113d and the carrier pin. In addition, the second pin 112 has a connection portion 115b which is completely identical as described in FIG. 7A, and the second pin 112 is connected to the adjacent second longitudinal edge 110 of the second row of carrier pins 114 through the connection portion 115b. On the innermost one of the carrier pins 114-1 of the -2d, the connection portion 115b extends from the top of the second pin 112 near the side of the innermost carrier pin 114-1 to the carrier pin 114-1, and Connected to the carrier pin 114-1. Generally, the thickness of the connecting portion 115b is smaller than the thickness of the second bypass pin 122 (as shown in FIG. 9E is a cross section along the broken lines C3 to C3 in FIG. 9B), but it may also be designed such that the thickness of the connecting portion 115b is equal to the second bypass. The thickness of the foot 122 and the carrying pin 114-1.
The first wafer 101 is pasted on the first pedestal 110-1 such that the back electrode on the back side is adhered to the top surface of the first pedestal 110-1, and the second wafer 102 is flip-chip mounted on the second pedestal 110-2. And the base island 113d, with its main electrode 101a adhered to the top surface of the second pedestal 110-2, and its sub-electrode 102b adhered to the top surface of the island 113d, to the front side of the first wafer 101, The back surface of the second wafer 102 is coplanar with the top surfaces of the upper pins 113a, 114a of all the carrying pins, and the control wafer 103 is conveniently flip-chip mounted in such a manner as to be offset from the first wafer 101 and the second wafer 102. The first row carries pins 113 and the second row carries pins 114. Each of the pads on the front surface of the control wafer 103 is provided with a metal bump 201, and the metal bumps 201 disposed on the pads near one edge of a pair of opposite sides (for example, the first pair of opposite sides) are respectively aligned with the first row Carrying respective upper pins 113a of the pins 113, each of the metal bumps 201 and the upper pins 113a aligned and in contact with them are soldered to maintain electrical connection, near the other edge of the pair of sides The metal bumps 201 disposed on the pads are aligned with the corresponding upper pins 114a of the second row of carrier pins 114, and each of the metal bumps 201 is soldered to the upper pins 114a aligned and in contact therewith. To maintain an electrical connection. In the flip-chip step of controlling the wafer 103, the control wafer 103 is provided with an overlapping portion overlapping the first wafer 101 and the second wafer 102, and the other overlapping side of the control wafer 103 is disposed on the front side of the overlapping portion ( For example, the metal bumps 201 disposed on the plurality of pads near one of the edges of the second pair of opposite sides of the first pair of opposite sides are respectively aligned with the main electrode 101a, the sub-electrode 101b, and the second wafer of the first wafer 101. The back electrode 102c of the 102, each of the metal bumps 201 and the main electrode 101a or the sub-electrode 101b or the back electrode 102c aligned and in contact with it are soldered to maintain electrical connection, and FIG. 9C is along the broken lines D1 to D2 in FIG. 9B. section.
In FIGS. 9F-9G, the main electrode 101a of the first wafer 101 and the back electrode 102c of the second wafer 102 are electrically connected to the second lead 112 by a metal piece 250. The structure of the metal piece 250 is already in the foregoing. Detailed introduction, no longer repeat them. It is only necessary to note that the sub-plate portion 250a is soldered to the top surface of the bonding region 112a of the second pin 112 by a conductive bonding material, and the sub-plate portion 250c is soldered to the back electrode of the second wafer 102 by an adhesive material. 102c (which is different from FIGS. 7B to 7C), the sub-plate portion 250e is soldered to the main electrode 101a of the first wafer 101 by an adhesive material. The power control device further includes a molding body 225 (not shown) for covering the wafer mounting unit, the first wafer 101 and the second wafer 102, the control wafer 103, the metal piece 250 and the metal bumps 201, and the plastic sealing The body 225 is covered by at least a bottom surface of each of the lower pins 113b, 114b, a bottom surface of the first pedestal 110-1 and the second pedestal 110-2, and a first pin 111 and a second pin 112. The bottom surface and the bottom surface of the base island 113d are exposed from the bottom surface of the molding body 225.
The difference from the wafer mounting unit of FIG. 9A is that, in FIG. 10A, the length value of the first pin 111 extending along the length direction of the first lateral edge 110-1a of the first pedestal 110-1 is smaller than the first lateral edge 110. a length value of -1a, the first bypass pin 121 included in the wafer mounting unit is disposed on a lateral extension line of the first pin 111 (ie, an extension line in the length direction), adjacent to the first lateral direction of the first pedestal 110-1 The edge 110-1a is located between a carrier pin 113-1 and the first pin 111 at the innermost side of the first row of carrying pins 113. The first bypass pin 121 has a connection portion 115c from the top of the first bypass pin 121 near the side of the innermost carrier pin 113-1 of the first row of carrier pins 113 to the carrier pin 113-1 extends and is connected thereto, which is described in detail in FIG. 5A, and the sub-electrode 101b on the front surface of the first wafer 101 is electrically connected to the first bypass pin 121 through the conductive structure 311. And the first row of the carrying pins 113 and the second row of the carrying pins 114 have no upper and lower pins, and each of the carrying pins is a strip-shaped flat structure, and the L-shaped connecting structure 117' will The island 113 is mechanically and electrically connected to any one of the carrier pins except the first inner carrier pin 113 and the innermost carrier pin 113-1, 114-1 of the second row of carrier pins 114. As shown in Fig. 10A, one end of the laterally extending section 117'b is attached to the top of the edge of the island 113d substantially aligned with the second longitudinal edge 110-2d of the second pedestal 110-2, one end of the longitudinally extending section 117'a Docking at the top of one end of the carrying pin 114-2, the other end of the laterally extending section 117'b is connected to the other end of the longitudinally extending section 117'a. Generally, the thickness of the connecting structure 117' is smaller than that of the island 113 and the carrying pin. For the thickness, the connecting structures 117' are covered by the subsequent molding body 225, but they may be designed to have the same thickness, and the bottom surface of the connecting structure 117' is exposed from the bottom surface of the subsequent molding body 225. In addition, the main electrode 101a of the first wafer 101 and the back electrode 102c of the second wafer 102 are electrically connected to the first pin 111 and the second pin 112 through the metal piece 251, and the structure of the metal piece 251 is no longer Narration. In FIG. 10A, the sub-plate portion 251a is soldered to the top surface of the bonding region 112a of the second lead 112 by a conductive adhesive material, and the sub-plate portion 251c is soldered to the back electrode 102c of the second wafer 102 by an adhesive material, The sub-plate portion 250e is welded to the main electrode 101a of the first wafer 101 by an adhesive material, and the sub-plate portion 251g is soldered to the top surface of the bonding region 111a of the first pin 111 by a conductive adhesive material. The power control device further includes a chip mounting unit, the first wafer 101 and the second wafer 102, the control wafer 103, the metal piece 251 and the conductive structure 311, the metal bumps 201, and the first bypass pins 121. a molding body 225 (not shown), the molding body 225 is covered by at least a bottom surface of each of the carrier pins, a bottom surface of the first pedestal 110-1 and the second pedestal 110-2, and a first pin 111 The bottom surface of each of the second pins 112, the bottom surface of the base island 113d, and the bottom surface of the first bypass pin 121 are exposed from the bottom surface of the molding body 225.
10B differs from FIG. 10A in that it is not necessary to consider the length value of the first pin 111 extending along the length direction of the first lateral edge 110-1a of the first pedestal 110-1 and the length value of the first lateral edge 110-1a. The relationship between the first bypass pin 121 can be omitted. At this time, the sub-electrode 101b of the front surface of the first wafer 101 is electrically connected to any one of the first-row carrying pins 113 by the bonding wires 119. Preferably, the sub-electrode 101b is preferably electrically connected. Connected to the innermost carrier pin 113-1, a molding body 225 (not shown) encloses the bonding wire 119 instead of the conductive structure 311.
11A is different from FIG. 10B in that the connection structure 117' is omitted, the island 113d is isolated, is not connected to any of the carrier pins, and the back surface of the control wafer 103 is adhered to the first row by the non-conductive material. On the leg 113 and the second row of carrier pins 114, the control wafer 103 is also not offset from the first wafer 101 and the second wafer 102. The sub-electrodes 101b and the islands 113d of the first wafer 101 are electrically connected to corresponding pads on the front surface of the control wafer 103 by bonding wires 119, respectively. In addition to the remaining pads connected to the sub-electrode 101b and the island 113d, some of the pads 103a located near one of the opposite sides of the control wafer 103 (e.g., the first pair of opposite sides) are electrically connected by the bonding wires 119. Connected to each of the carrier pins of the first row of carrying pins 113, some of the pads 103a located near the other of the pair of opposite sides of the control wafer 103 are electrically connected to the second row by bonding wires 119 The pads 103a connected to the sub-electrodes 101b and the islands 113d are preferably located on the respective bearing pins of the carrying pins 114, and the pads 103a connected to the sub-electrodes 101b and the islands 113d are located opposite to the pair of opposite sides of the control wafer 103. Another set of opposite sides (e.g., the second set of opposite sides) is adjacent to one of the edges (the edge is adjacent to the pedestal 110). In FIG. 11B, the sub-plate portion 251a is welded to the top surface of the bonding region 112a of the second pin 112 by a conductive bonding material, and the sub-plate portion 251c is soldered to the back electrode 102c of the second wafer 102 by an adhesive material ( This is different from the case where the sub-plate portion 251c of FIGS. 8A to 8C is soldered to the main electrode 102a of the second wafer 102, and the sub-plate portion 250e is soldered to the main electrode 101a of the first wafer 101 by the adhesive material, and the sub-plate portion 251g passes. A conductive adhesive material is soldered to the top surface of the bonding region 111a of the first pin 111. The power control device further includes a molding body 225 (not shown) for covering the wafer mounting unit, the first wafer 101 and the second wafer 102, the control wafer 103, the metal piece 251 and the bonding wires 119, and the plastic sealing body The covering manner of the 225 is at least a bottom surface of each of the carrying pins, a bottom surface of the first pedestal 110-1 and the second pedestal 110-2, a bottom surface of each of the first pin 111 and the second pin 112, and a base island 113d. The bottom surface is exposed from the bottom surface of the molding body 225.
In the embodiment of FIGS. 9B, 10A to 10B, and 11A, the first wafer 101 is an N-channel MOSFET, and the second wafer 102 is an N-channel MOSFET. The main electrode 101a of the first wafer 101 serves as a source, the sub-electrode 101b serves as a gate, and the unillustrated metallization layer on the back surface constitutes a back electrode as a drain. The main electrode 102a of the second wafer 102 serves as a source, the sub-electrode 102b serves as a gate, and the metallization layer on the back surface constitutes a back electrode as a drain.
Various changes and modifications will no doubt become apparent to those skilled in the <RTIgt; Accordingly, the appended claims are intended to cover all such modifications and Any and all equivalent ranges and contents within the scope of the claims are intended to be within the spirit and scope of the invention.

 

103‧‧‧控制晶片 103‧‧‧Control chip

201‧‧‧金屬凸塊 201‧‧‧Metal bumps

101a‧‧‧主電極 101a‧‧‧Main electrode

101b‧‧‧副電極 101b‧‧‧Secondary electrode

102a‧‧‧主電極 102a‧‧‧Main electrode

102b‧‧‧副電極 102b‧‧‧Secondary electrode

Claims (54)

一種功率控制器件，其特徵在於，包括：
一晶片安裝單元和一控制晶片及第一、第二晶片，該晶片安裝單元包括一基座和基座附近的第一、第二引腳及第一、第二排承載引腳；
基座具有相對的一組第一、第二橫向邊緣及相對的一組第一、第二縱向邊緣，其中，第一引腳鄰近第一橫向邊緣並且其條狀鍵合區沿第一橫向邊緣長度方向延伸，第二引腳鄰近第二橫向邊緣並且其條狀鍵合區沿第二橫向邊緣長度方向延伸；
第一、第二排承載引腳位於基座的第二縱向邊緣的一側，且第一排承載引腳中的每一個承載引腳皆平行於第二縱向邊緣並由第一引腳的橫向延長線上向第一、第二橫向邊緣之間的對稱中心線延伸，及第二排承載引腳中的每一個承載引腳皆平行於第二縱向邊緣並由第二引腳的橫向延長線上向所述對稱中心線延伸；
第一、第二晶片均安裝在基座之上，控制晶片安裝在第一、第二排承載引腳之上，並且還包括一第一金屬片，將第一晶片正面的一個主電極電性連接到第一引腳上，和包括一第二金屬片將第二晶片正面的一個主電極電性連接到第二引腳上。A power control device, comprising:
a chip mounting unit and a control chip and first and second wafers, the chip mounting unit includes a first and second pins and first and second rows of carrier pins adjacent to the base and the base;
The pedestal has an opposite set of first and second lateral edges and an opposite set of first and second longitudinal edges, wherein the first pin is adjacent to the first lateral edge and the strip-shaped bonding region is along the first lateral edge Extending in the length direction, the second pin is adjacent to the second lateral edge and the strip-shaped bonding region extends along the length of the second lateral edge;
The first and second rows of carrier pins are located on one side of the second longitudinal edge of the pedestal, and each of the first row of carrier pins is parallel to the second longitudinal edge and is laterally oriented by the first pin An extension line extends toward a symmetrical centerline between the first and second lateral edges, and each of the second row of carrier pins is parallel to the second longitudinal edge and is extended by a lateral extension of the second pin The symmetric centerline extends;
The first and second wafers are both mounted on the pedestal, the control wafer is mounted on the first and second rows of carrier pins, and further includes a first metal piece to electrically connect a main electrode on the front surface of the first wafer Connected to the first pin, and includes a second metal piece to electrically connect one main electrode of the front surface of the second chip to the second pin. 如申請專利範圍第1項所述的功率控制器件，其特徵在於，基座具有一個連接部，從基座位於第二縱向邊緣的一側的頂部向第一排承載引腳中最內側的一個承載引腳延伸，並與其連接。The power control device of claim 1, wherein the base has a connecting portion from a top of one side of the base at the second longitudinal edge to an innermost one of the first row of carrying pins The carrier pins extend and are connected to them. 如申請專利範圍第2項所述的功率控制器件，其特徵在於，第一、第二晶片各自背面的背部電極均粘附在基座的頂面。The power control device according to claim 2, wherein the back electrodes of the respective back surfaces of the first and second wafers are adhered to the top surface of the susceptor. 如申請專利範圍第3項所述的功率控制器件，其特徵在於，第一、第二排承載引腳各自的每個承載引腳均皆包括相互連接的一個上置引腳和一個下置引腳，所有承載引腳的上置引腳的頂面均與第一、第二晶片各自的正面共面；
控制晶片以向第一、第二晶片偏移的方式倒裝安裝在第一、第二排承載引腳上，偏移程度為使其具有與第一、第二晶片形成交疊的交疊部分，使交疊部分正面的多個焊墊上相應設置的多個金屬凸塊分別對準並電性連接至第一、第二晶片各自正面的主電極、副電極；
控制晶片餘下的焊墊上設置的金屬凸塊分別對準並電性連接至相應的各上置引腳上。The power control device of claim 3, wherein each of the first and second rows of carrier pins comprises an upper pin and a lower pin connected to each other. a top surface of all of the upper pins carrying the pins are coplanar with respective front sides of the first and second wafers;
The control wafer is flip-chip mounted on the first and second rows of carrier pins in such a manner as to be offset from the first and second wafers to have an offset such that they overlap the first and second wafers. Aligning and electrically connecting the plurality of metal bumps respectively disposed on the plurality of pads on the front surface of the overlapping portion to the main electrode and the sub-electrode on the front sides of the first and second wafers;
The metal bumps disposed on the remaining pads of the control chip are respectively aligned and electrically connected to the respective upper pins. 如申請專利範圍第4項所述的功率控制器件，其特徵在於，還包括一個將晶片安裝單元、第一和第二晶片、控制晶片、第一和第二金屬片及各金屬凸塊予以包覆的塑封體，其包覆方式至少使各下置引腳的底面、基座的底面、第一和第二引腳各自的底面從塑封體的底面外露。The power control device of claim 4, further comprising a package mounting unit, first and second wafers, control wafer, first and second metal sheets, and metal bumps. The covered plastic body is coated in such a manner that at least the bottom surface of each of the lower pins, the bottom surface of the base, and the bottom surfaces of the first and second pins are exposed from the bottom surface of the molding body. 如申請專利範圍第2項所述的功率控制器件，其特徵在於，在基座的頂面上設置有一個凹槽，第一、第二晶片均位於在凹槽內，使第一、第二晶片各自的背部電極均粘附在凹槽的底部，且第一、第二排承載引腳各自的每個承載引腳的頂面均與第一、第二晶片各自的正面共面。The power control device of claim 2, wherein a groove is disposed on a top surface of the base, and the first and second wafers are all located in the groove to make the first and second The respective back electrodes of the wafer are adhered to the bottom of the recess, and the top surfaces of each of the first and second rows of carrier pins are coplanar with the respective front faces of the first and second wafers. 如申請專利範圍第6項所述的功率控制器件，其特徵在於，控制晶片以向第一、第二晶片偏移的方式倒裝安裝在第一、第二排承載引腳上，偏移程度為使其具有與第一、第二晶片形成交疊的交疊部分，使交疊部分正面的多個焊墊上設置的多個金屬凸塊分別對準並電性連接至第一、第二晶片各自正面的主電極、副電極；
控制晶片餘下的焊墊上設置的金屬凸塊分別對準並電性連接至相應的各承載引腳上。The power control device of claim 6, wherein the control wafer is flip-chip mounted on the first and second rows of carrier pins in such a manner as to be offset from the first and second wafers. In order to have an overlapping portion overlapping the first and second wafers, the plurality of metal bumps disposed on the plurality of pads on the front side of the overlapping portion are respectively aligned and electrically connected to the first and second wafers Main electrode and secondary electrode on the front side;
The metal bumps disposed on the remaining pads of the control chip are respectively aligned and electrically connected to the respective carrier pins. 如申請專利範圍第7項所述的功率控制器件，其特徵在於，還包括一個將晶片安裝單元、第一和第二晶片、控制晶片、第一和第二金屬片及各金屬凸塊予以包覆的塑封體，其包覆方式至少使各承載引腳的底面、基座的底面、第一和第二引腳各自的底面從塑封體的底面外露。The power control device of claim 7, further comprising a package mounting unit, first and second wafers, control wafer, first and second metal sheets, and metal bumps. The covered plastic body is coated in such a manner that at least the bottom surface of each of the carrier pins, the bottom surface of the base, and the bottom surfaces of the first and second pins are exposed from the bottom surface of the molding body. 如申請專利範圍第7項所述的功率控制器件，其特徵在於，第一、第二金屬片各包括一個主平板部分和連接在其一側的相對主平板部分具有高度落差的一個副平板部分，以及第一、第二金屬片各自的主平板部分的底面上均設置有一個垂直向下延伸的端部；
第一、第二金屬片各自的端部的底端面分別與第一、第二晶片的主電極焊接，第一、第二金屬片各自的副平板部分分別與第一、第二引腳的鍵合區焊接。The power control device according to claim 7, wherein the first and second metal sheets each comprise a main flat plate portion and a sub-plate portion having a height difference between the opposite main flat plate portions connected to one side thereof And a bottom surface of each of the first and second metal sheets each having a vertically downwardly extending end portion;
The bottom end faces of the respective ends of the first and second metal sheets are respectively soldered to the main electrodes of the first and second wafers, and the sub-plate portions of the first and second metal sheets are respectively connected to the first and second pins. Joint welding. 如申請專利範圍第9項所述的功率控制器件，其特徵在於，還包括一個將晶片安裝單元、第一和第二晶片、控制晶片、第一和第二金屬片及各金屬凸塊予以包覆的塑封體；
控制晶片的背面與第一、第二金屬片各自的主平板部分的頂面共面，塑封體的包覆方式至少使各承載引腳的底面、基座的底面、第一和第二引腳各自的底面從塑封體的底面外露，和使第一、第二金屬片各自主平板部分的頂面、控制晶片的背面從塑封體的頂面外露。The power control device of claim 9, further comprising a package mounting unit, first and second wafers, control wafer, first and second metal sheets, and metal bumps. Covered plastic body;
The back surface of the control wafer is coplanar with the top surface of each of the first and second metal sheets, and the molding body is covered by at least the bottom surface of each of the carrier pins, the bottom surface of the base, and the first and second pins. The respective bottom surfaces are exposed from the bottom surface of the molding body, and the top surfaces of the main flat plate portions of the first and second metal sheets and the back surface of the control wafer are exposed from the top surface of the molding body. 如申請專利範圍第1項所述的功率控制器件，其特徵在於，第一、第二晶片各自背面的背部電極均粘附在基座的頂面；
控制晶片倒裝安裝在第一、第二排承載引腳上，其正面的各焊墊上設置的金屬凸塊分別對準並電性連接至相應的各承載引腳上。The power control device according to claim 1, wherein the back electrodes of the back surfaces of the first and second wafers are adhered to the top surface of the pedestal;
The control chip is flip-chip mounted on the first and second rows of carrier pins, and the metal bumps disposed on the pads on the front surface are respectively aligned and electrically connected to the respective carrier pins. 如申請專利範圍第11項所述的功率控制器件，其特徵在於，第一引腳沿第一橫向邊緣的長度方向延伸的長度值小於第一橫向邊緣的長度值，第二引腳沿第二橫向邊緣的長度方向延伸的長度值小於第二橫向邊緣的長度值；
晶片安裝單元包括在第一引腳的長度方向的延長線上設置的靠近第一橫向邊緣的第一旁路引腳，位於第一排承載引腳最內側的承載引腳和第一引腳之間並通過其帶有的一連接部與第一排承載引腳最內側的承載引腳連接；
和包括在第二引腳的長度方向的延長線上設置的靠近第二橫向邊緣的第二旁路引腳，位於第二排承載引腳的最內側的承載引腳和第二引腳之間，並通過其帶有的一連接部與第二排承載引腳中最內側的承載引腳連接；
第一、第二晶片正面的副電極分別通過導電結構電性連接到第一、第二旁路引腳上；
其中，晶片安裝單元還包括一個L形的連接結構，其一端對接在第一、第二排承載引腳中除了各自最內側的承載引腳之外的任意一承載引腳上，另一端連接在基座上。The power control device of claim 11, wherein the length of the first pin extending along the length of the first lateral edge is smaller than the length of the first lateral edge, and the second pin is along the second The length value of the lateral edge extending in the longitudinal direction is smaller than the length value of the second lateral edge;
The wafer mounting unit includes a first bypass pin disposed on an extension line of a length direction of the first pin adjacent to the first lateral edge, between the carrier pin and the first pin of the innermost side of the first row of the carrier pins And connected to the innermost carrier pin of the first row of carrying pins by a connecting portion thereof;
And a second bypass pin disposed adjacent to the second lateral edge on the extension line of the length direction of the second pin, between the innermost carrier pin and the second pin of the second row of the carrier pin, And connected by a connecting portion thereof with the innermost carrier pin of the second row of carrying pins;
The secondary electrodes on the front surface of the first and second wafers are electrically connected to the first and second bypass pins respectively through a conductive structure;
Wherein, the wafer mounting unit further comprises an L-shaped connecting structure, one end of which is connected to any one of the first and second rows of carrying pins except for the innermost carrying pins, and the other end is connected at On the pedestal. 如申請專利範圍第11項所述的功率控制器件，其特徵在於，還包括多條鍵合引線，將第一晶片的正面的副電極電性連接至第一排承載引腳中任意一承載引腳上，將第二晶片正面的副電極、基座的頂面分別電性連接至第二排承載引腳中任意兩個不同的承載引腳上。The power control device of claim 11, further comprising a plurality of bonding wires electrically connecting the secondary electrodes of the front surface of the first wafer to any one of the first row of carrying pins On the foot, the top surface of the front surface of the second wafer and the top surface of the base are electrically connected to any two different carrier pins of the second row of carrying pins. 如申請專利範圍第1項所述的功率控制器件，其特徵在於，第一、第二晶片各自背面的背部電極均粘附在基座的頂面，控制晶片的背面粘附在第一、第二排承載引腳上；
還包括鍵合引線，將第一、第二晶片各自正面的副電極和基座的頂面分別電性連接至控制晶片正面的相應焊墊上，將控制晶片正面餘下的多個焊墊分別電性連接至相對應的各承載引腳的頂面上。The power control device according to claim 1, wherein the back electrodes of the back surfaces of the first and second wafers are adhered to the top surface of the susceptor, and the back surface of the control wafer is adhered to the first and the Two rows of carrying pins;
Further comprising a bonding wire, the top surface of each of the front surface of the first and second wafers and the top surface of the pedestal are respectively electrically connected to corresponding pads on the front surface of the control wafer, and the plurality of solder pads remaining on the front surface of the control wafer are respectively electrically connected. Connect to the top surface of each corresponding carrier pin. 一種功率控制器件，其特徵在於，包括：
一晶片安裝單元和一控制晶片及第一、第二晶片，該晶片安裝單元包括相鄰的第一、第二基座，並包括第一基座附近的第一引腳及第一排承載引腳，和包括第二基座附近的第二引腳及第二排承載引腳；
第一、第二基座各自均具有相對的一組第一、第二橫向邊緣及相對的一組第一、第二縱向邊緣，第一引腳靠近第一基座的第一橫向邊緣並且其條狀鍵合區沿第一基座的第一橫向邊緣長度方向延伸，第二引腳靠近第二基座的第二橫向邊緣並且其條狀鍵合區沿第二基座的第二橫向邊緣長度方向延伸；
第一排承載引腳位於第一基座的第二縱向邊緣的一側，且第一排承載引腳中的每一個承載引腳均平行於第一基座的第二縱向邊緣，並由第一引腳的橫向延長線上向第一基座、第二基座之間的分割線延伸；
第二排承載引腳位於第二基座的第二縱向邊緣的一側，且第二排承載引腳中的每一個承載引腳均平行於第二基座的第二縱向邊緣，並由第二引腳的橫向延長線上向所述分割線延伸；
其中，第一、第二晶片分別安裝在第一、第二基座之上，使第一、第二晶片各自背面的背部電極分別粘附在第一、第二基座的頂面，控制晶片安裝在第一、第二排承載引腳之上；
還包括一金屬片，將第一、第二晶片各自正面的主電極與第二引腳進行電性連接。A power control device, comprising:
a wafer mounting unit and a control chip and first and second wafers, the wafer mounting unit includes adjacent first and second pedestals, and includes a first pin and a first row of carrier adjacent to the first pedestal a foot, and a second pin and a second row of carrying pins adjacent to the second base;
The first and second pedestals each have an opposite set of first and second lateral edges and an opposite set of first and second longitudinal edges, the first pin being adjacent to the first lateral edge of the first pedestal and a strip-shaped bonding region extending along a first lateral edge length of the first pedestal, a second pin adjacent the second lateral edge of the second pedestal and a strip-shaped bonding region along a second lateral edge of the second pedestal Extending in the length direction;
a first row of carrier pins on one side of a second longitudinal edge of the first pedestal, and each of the first row of carrier pins is parallel to a second longitudinal edge of the first pedestal and is a lateral extension line of one pin extends to a dividing line between the first base and the second base;
a second row of carrier pins on one side of a second longitudinal edge of the second pedestal, and each of the second row of carrier pins is parallel to a second longitudinal edge of the second pedestal and is a lateral extension line of the two pins extends toward the dividing line;
The first and second wafers are respectively mounted on the first and second pedestals, so that the back electrodes of the back surfaces of the first and second wafers are respectively adhered to the top surfaces of the first and second pedestals, and the control wafer is controlled. Installed on the first and second rows of carrier pins;
The utility model further comprises a metal piece electrically connecting the main electrode of the front surface of each of the first and second wafers with the second pin. 如申請專利範圍第15項所述的功率控制器件，其特徵在於，第二引腳通過其帶有的一連接部與第二排承載引腳中最內側的承載引腳連接；
第一、第二排承載引腳各自的每個承載引腳均皆包括相互連接的一個上置引腳和一個下置引腳，並且所有承載引腳的上置引腳的頂面均與第一、第二晶片各自的正面共面；
控制晶片以向第一、第二晶片偏移的方式倒裝安裝在第一、第二排承載引腳上，偏移程度為使其具有與第一、第二晶片形成交疊的交疊部分，使交疊部分正面的多個焊墊上設置的多個金屬凸塊分別對準並電性連接至第一、第二晶片各自正面的主電極、副電極；
控制晶片餘下的焊墊上設置的金屬凸塊分別對準並電性連接至相應的各上置引腳上。The power control device of claim 15, wherein the second pin is connected to the innermost carrier pin of the second row of carrier pins through a connection portion thereof;
Each of the first and second rows of carrier pins includes an upper pin and a lower pin connected to each other, and the top surface of the upper pin of all the bearing pins is the same as the first 1. The front faces of the second wafers are coplanar;
The control wafer is flip-chip mounted on the first and second rows of carrier pins in such a manner as to be offset from the first and second wafers to have an offset such that they overlap the first and second wafers. Aligning and electrically connecting the plurality of metal bumps disposed on the plurality of pads on the front side of the overlapping portion to the main electrode and the sub-electrode on the front sides of the first and second wafers;
The metal bumps disposed on the remaining pads of the control chip are respectively aligned and electrically connected to the respective upper pins. 如申請專利範圍第16項所述的功率控制器件，其特徵在於，第一基座具有一個連接部，從第一基座的頂部位於其第一橫向邊緣的一側向第一引腳延伸，並與其連接。The power control device of claim 16, wherein the first base has a connecting portion extending from a top of the first base on a side of the first lateral edge thereof toward the first pin, And connect with it. 如申請專利範圍第15項所述的功率控制器件，其特徵在於，控制晶片倒裝安裝在第一、第二排承載引腳上，其正面的多個焊墊上相應設置的多個金屬凸塊分別對準並電性連接至各相應的承載引腳上；
所述金屬片還電性連接到第一引腳上。The power control device of claim 15, wherein the control chip is flip-chip mounted on the first and second rows of carrier pins, and a plurality of metal bumps are disposed on the plurality of pads on the front surface thereof. Aligned and electrically connected to respective corresponding carrier pins;
The metal piece is also electrically connected to the first pin. 如申請專利範圍第18項所述的功率控制器件，其特徵在於，第一引腳沿第一基座的第一橫向邊緣的長度方向延伸的長度值小於第一基座的第一橫向邊緣的長度值，第二引腳沿第二基座的第二橫向邊緣的長度方向延伸的長度值小於第二基座的第二橫向邊緣的長度值；
晶片安裝單元包括在第一引腳的延長線上設置的一個靠近第一橫向邊緣的第一旁路引腳，位於第一排承載引腳的最內側的一個承載引腳和第一引腳之間，並通過其帶有的一個連接部與第一排承載引腳的最內側的承載引腳連接；
和包括在第二引腳的延長線上設置的一個靠近第二橫向邊緣的第二旁路引腳，位於第二排承載引腳的最內側的一個承載引腳和第二引腳之間，並通過其帶有的一個連接部與第二排承載引腳的最內側的一個承載引腳連接；
第一、第二晶片正面的副電極分別通過導電結構電性連接到第一、第二旁路引腳上，並利用鍵合引線將第二引腳或第二晶片的主電極電性連接到第二排承載引腳中除最內側的承載引腳以外的任意一承載引腳上。The power control device of claim 18, wherein the length of the first pin extending along a length of the first lateral edge of the first pedestal is smaller than the first lateral edge of the first pedestal a length value, a length value of the second pin extending along a length of the second lateral edge of the second pedestal is smaller than a length value of the second lateral edge of the second pedestal;
The chip mounting unit includes a first bypass pin disposed on an extension line of the first pin adjacent to the first lateral edge, between the one of the innermost one of the first row of the carrier pins and the first pin And connected to the innermost carrier pin of the first row of carrying pins by a connection portion thereof;
And a second bypass pin disposed on the extension line of the second pin adjacent to the second lateral edge, between the one of the innermost one of the second row of the carrier pin and the second pin, and Connected to one of the innermost one of the load pins of the second row of carrying pins by a connection portion thereof;
The secondary electrodes on the front surfaces of the first and second wafers are electrically connected to the first and second bypass pins through the conductive structures, respectively, and electrically connected to the main electrodes of the second or second wafer by using bonding wires. The second row carries the carrier pins on any of the carrier pins except the innermost carrier pins. 如申請專利範圍第18項所述的功率控制器件，其特徵在於，還包括鍵合引線，將第一晶片的副電極電性連接至第一排承載引腳中任意一承載引腳上，將第二晶片的正、副電極分別相對應的電性連接至第二排承載引腳中任意兩個不同的承載引腳上。The power control device of claim 18, further comprising a bonding wire electrically connecting the secondary electrode of the first wafer to any one of the first row of carrying pins, The positive and the secondary electrodes of the second wafer are respectively electrically connected to any two different carrier pins of the second row of carrier pins. 如申請專利範圍第15項所述的功率控制器件，其特徵在於，控制晶片的背面粘附在第一、第二排承載引腳上；
還包括鍵合引線，將第一、第二晶片各自的副電極、第二晶片的主電極分別電性連接至控制晶片正面的相對應的焊墊上，將控制晶片正面餘下的多個焊墊分別連接至相對應的各承載引腳的頂面上。The power control device of claim 15, wherein the back surface of the control wafer is adhered to the first and second rows of carrier pins;
The method further includes bonding wires, respectively electrically connecting the respective sub-electrodes of the first and second wafers and the main electrodes of the second wafer to corresponding pads on the front surface of the control wafer, and respectively controlling the remaining plurality of pads on the front surface of the wafer Connect to the top surface of each corresponding carrier pin. 一種功率控制器件，其特徵在於，包括：
一晶片安裝單元和一控制晶片及第一、第二晶片，該晶片安裝單元包括相鄰的第一、第二基座，並包括第一基座附近的第一引腳及第一排承載引腳，和包括第二基座附近的第二引腳及第二排承載引腳；
第一、第二基座各自均具有相對的一組第一、第二橫向邊緣及相對的一組第一、第二縱向邊緣，第一引腳靠近第一基座的第一橫向邊緣且其條狀鍵合區沿第一基座的第一橫向邊緣的長度方向延伸，第二引腳靠近第二基座的第二橫向邊緣且其條狀鍵合區沿第二基座的第二橫向邊緣的長度方向延伸；
第一排承載引腳位於第一基座的第二縱向邊緣的一側，且第一排承載引腳中的每一個承載引腳均平行於第一基座的第二縱向邊緣，並由第一引腳的橫向延長線上向第一基座和第二基座之間的分割線延伸；及
第二排承載引腳位於第二基座的第二縱向邊緣的一側，且第二排承載引腳中的每一個承載引腳均平行於第二基座的第二縱向邊緣，並由第二引腳的橫向延長線上向所述分割線延伸；
實質為矩形狀的第二基座在其第一橫向邊緣與第二縱向邊緣交叉的拐角處具有一個矩形切口而使第二基座形成L形結構，並在該切口中嵌入有一個基島；
第一晶片安裝在第一基座上使其背面的背部電極粘附至第一基座的頂面，第二晶片倒裝安裝在第二基座和基島之上使其主、副電極分別粘附在第二基座、基島的頂面上，控制晶片安裝在第一、第二排承載引腳之上；
還包括一金屬片，將第一晶片正面的主電極和第二晶片背面的背部電極電性連接第二引腳上。A power control device, comprising:
a wafer mounting unit and a control chip and first and second wafers, the wafer mounting unit includes adjacent first and second pedestals, and includes a first pin and a first row of carrier adjacent to the first pedestal a foot, and a second pin and a second row of carrying pins adjacent to the second base;
The first and second pedestals each have an opposite set of first and second lateral edges and an opposite set of first and second longitudinal edges, the first pin being adjacent to the first lateral edge of the first pedestal and a strip-shaped bonding region extending along a length of the first lateral edge of the first pedestal, a second pin adjacent to the second lateral edge of the second pedestal and a strip-shaped bonding region along the second lateral direction of the second pedestal The length of the edge extends;
a first row of carrier pins on one side of a second longitudinal edge of the first pedestal, and each of the first row of carrier pins is parallel to a second longitudinal edge of the first pedestal and is a lateral extension line of one pin extends toward a dividing line between the first base and the second base; and a second row of carrying pins is located on one side of the second longitudinal edge of the second base, and the second row carries Each of the pins is parallel to the second longitudinal edge of the second pedestal and extends from the lateral extension of the second pin toward the dividing line;
a substantially rectangular second base having a rectangular slit at a corner where the first lateral edge intersects the second longitudinal edge to form an L-shaped structure in the second base, and a base island is embedded in the slit;
The first wafer is mounted on the first pedestal such that the back electrode of the back surface is adhered to the top surface of the first pedestal, and the second wafer is flip-chip mounted on the second pedestal and the island to have the main and auxiliary electrodes respectively Adhering to the top surface of the second pedestal and the island, the control wafer is mounted on the first and second rows of bearing pins;
A metal piece is further included, and the main electrode on the front surface of the first wafer and the back electrode on the back surface of the second wafer are electrically connected to the second pin. 如申請專利範圍第22項所述的功率控制器件，其特徵在於，所述第一基座具有一個連接部，從第一基座的頂部位於第一橫向邊緣的一側向第一引腳延伸，並與其連接。The power control device of claim 22, wherein the first base has a connecting portion extending from a top of the first base to a first pin on a side of the first lateral edge And connect with it. 如申請專利範圍第22或23項所述的功率控制器件，其特徵在於，第一、第二排承載引腳各自的每個承載引腳均皆包括相互連接的一個上置引腳和一個下置引腳，第一晶片的正面、第二晶片的背面與所有承載引腳的上置引腳的頂面共面；
晶片安裝單元包括一連接結構，該連接結構的水平延伸段對接在除第二排承載引腳最內側的承載引腳以外的第一、第二排承載引腳中任意一個承載引腳的上置部分上，其與水平面成夾角設置的傾斜延伸段垂直于水平延伸段並連接在水平延伸段和基島之間；
控制晶片以向第一、第二晶片偏移的方式倒裝安裝在第一、第二排承載引腳上，偏移程度為使其具有與第一、第二晶片形成交疊的交疊部分，使交疊部分正面的多個焊墊上設置的多個金屬凸塊分別對準並電性連接至第一晶片的主、副電極和第二晶片的背部電極；
控制晶片餘下的焊墊上設置的金屬凸塊分別對準並電性連接至各相應的上置引腳上。The power control device of claim 22 or 23, wherein each of the first and second rows of carrier pins comprises an upper pin and a lower one connected to each other. Pinning, the front side of the first wafer, the back side of the second wafer is coplanar with the top surface of all the upper pins carrying the pins;
The chip mounting unit includes a connection structure, and the horizontal extension of the connection structure is docked on any one of the first and second rows of carrier pins except the carrier pin of the innermost side of the second row of carrier pins. Partially, the inclined extension disposed at an angle to the horizontal plane is perpendicular to the horizontal extension and connected between the horizontal extension and the base island;
The control wafer is flip-chip mounted on the first and second rows of carrier pins in such a manner as to be offset from the first and second wafers to have an offset such that they overlap the first and second wafers. Aligning and electrically connecting the plurality of metal bumps disposed on the plurality of pads on the front side of the overlap portion to the back electrodes of the main and auxiliary electrodes of the first wafer and the second wafer;
The metal bumps disposed on the remaining pads of the control chip are respectively aligned and electrically connected to the respective upper pins. 如申請專利範圍第22項所述的功率控制器件，其特徵在於，第一引腳沿第一基座的第一橫向邊緣的長度方向延伸的長度值小於第一基座的第一橫向邊緣的長度值；
晶片安裝單元包括在第一引腳的橫向延長線上設置的一個靠近第一基座的第一橫向邊緣的第一旁路引腳，位於第一排承載引腳的最內側的一個承載引腳和第一引腳之間，並通過其帶有的一個連接部與第一排承載引腳最內側的一個承載引腳連接，從而第一晶片的副電極通過一個導電結構電性連接在第一旁路引腳上；
晶片安裝單元包括一L形連接結構，該連接結構的縱向延伸段對接在除第一、第二排承載引腳中各自最內側的承載引腳之外的任意一承載引腳上，其橫向延伸段垂直于縱向延伸段並連接在縱向延伸段和基島之間；以及
控制晶片倒裝安裝在第一、第二排承載引腳之上，控制晶片的焊墊上設置的金屬凸塊分別對準並電性連接至各相應的承載引腳上。The power control device of claim 22, wherein the length of the first pin extending along the length of the first lateral edge of the first pedestal is smaller than the first lateral edge of the first pedestal Length value
The wafer mounting unit includes a first bypass pin disposed on a lateral extension line of the first pin adjacent to a first lateral edge of the first pedestal, and a carrier pin located at an innermost side of the first row of carrying pins and Between the first pins, and through a connection portion thereof, a connection pin is connected to the innermost one of the first row of the carrier pins, so that the secondary electrodes of the first wafer are electrically connected to the first side through a conductive structure On the road pin;
The wafer mounting unit includes an L-shaped connection structure, and the longitudinal extension of the connection structure is docked on any of the carrier pins except the innermost carrier pins of the first and second rows of carrier pins, and the lateral extension thereof The segments are perpendicular to the longitudinally extending segments and are connected between the longitudinally extending segments and the islands; and the control wafer is flip-chip mounted over the first and second rows of carrier pins, and the metal bumps disposed on the pads of the control wafer are respectively aligned And electrically connected to each corresponding carrier pin. 如申請專利範圍第22項所述的功率控制器件，其特徵在於，控制晶片倒裝安裝在第一、第二排承載引腳之上，第一晶片的副電極通過鍵合引線電性連接在第一排承載引腳中的任意一承載引腳上；
晶片安裝單元包括一L形連接結構，該連接結構的縱向延伸段對接在除第二排承載引腳中最內側的承載引腳之外和除第一排承載引腳中連接至第一晶片的副電極的承載引腳以外的第一、第二承載引腳中的餘下的任意一承載引腳上，其橫向延伸段垂直于縱向延伸段並連接在縱向延伸段和基島之間。The power control device of claim 22, wherein the control wafer is flip-chip mounted on the first and second rows of carrier pins, and the secondary electrodes of the first wafer are electrically connected by bonding wires. The first row of carrying pins is on any one of the carrying pins;
The wafer mounting unit includes an L-shaped connection structure, the longitudinal extension of the connection structure being butted in addition to the innermost carrier pin of the second row of carrier pins and connected to the first wafer except the first row of carrier pins On any of the remaining ones of the first and second carrier pins other than the carrier pins of the secondary electrode, the lateral extension is perpendicular to the longitudinal extension and is connected between the longitudinal extension and the island. 如申請專利範圍第22項所述的功率控制器件，其特徵在於，控制晶片的背面粘附在第一、第二排承載引腳上；
還包括鍵合引線，將第一晶片的副電極、基島分別電性連接至控制晶片正面的相對應的焊墊上，同時利用鍵合引線將控制晶片正面餘下的多個焊墊分別連接至第一、第二排承載引腳中相應的各承載引腳的頂面上。The power control device of claim 22, wherein the back surface of the control wafer is adhered to the first and second rows of carrier pins;
The utility model further includes a bonding wire, electrically connecting the auxiliary electrode and the island of the first wafer to the corresponding pads of the front surface of the control wafer, and simultaneously connecting the plurality of solder pads remaining on the front surface of the control wafer to the first by using the bonding wires 1. The second row carries the top surface of each of the corresponding carrier pins. 如申請專利範圍第25~27項中任意一項所述的功率控制器件，其特徵在於，第二引腳通過其具有的一個連接部將其與第二排承載引腳中最內側的一個承載引腳連接；
所述金屬片還電性連接在第一引腳上。The power control device according to any one of claims 25 to 27, wherein the second pin carries the innermost one of the second row of carrying pins through a connecting portion thereof Pin connection
The metal piece is also electrically connected to the first pin. 一種功率控制器件的製備方法，其特徵在於，包括以下步驟：
步驟S1、提供一晶片安裝單元，包括一基座和基座附近的第一、第二引腳及第一、第二排承載引腳；
基座具有相對的一組第一、第二橫向邊緣及相對的一組第一、第二縱向邊緣，第一引腳鄰近第一橫向邊緣並且其條狀鍵合區沿第一橫向邊緣長度方向延伸，第二引腳鄰近第二橫向邊緣並且其條狀鍵合區沿第二橫向邊緣長度方向延伸；
第一、第二排承載引腳位於基座的第二縱向邊緣的同一側，且第一排承載引腳中的每個承載引腳均平行於第二縱向邊緣並由第一引腳的橫向延長線上向第一、第二橫向邊緣之間的對稱中心線延伸，及第二排承載引腳中的每一個承載引腳均平行於第二縱向邊緣並由第二引腳的橫向延長線上向所述對稱中心線延伸；
步驟S2、將一第一晶片和一第二晶片並排安裝在基座之上，並將一控制晶片安裝在第一、第二排承載引腳之上；
步驟S3、利用一個第一金屬片將第一晶片正面的一個主電極電性連接到第一引腳上，利用一個第二金屬片將第二晶片正面的一個主電極電性連接到第二引腳上。A method for preparing a power control device, comprising the steps of:
Step S1, providing a wafer mounting unit, comprising a base and a first pin and a second pin and a first and second row of carrying pins;
The pedestal has an opposite set of first and second lateral edges and an opposite set of first and second longitudinal edges, the first pin being adjacent to the first lateral edge and the strip-shaped bonding region along the length of the first lateral edge Extending, the second pin is adjacent to the second lateral edge and the strip-shaped bonding region extends along the length of the second lateral edge;
The first and second rows of carrier pins are on the same side of the second longitudinal edge of the pedestal, and each of the first row of carrier pins is parallel to the second longitudinal edge and is laterally oriented by the first pin The extension line extends toward a symmetrical centerline between the first and second lateral edges, and each of the second row of carrier pins is parallel to the second longitudinal edge and is extended by a lateral extension of the second pin The symmetric centerline extends;
Step S2, mounting a first wafer and a second wafer side by side on the pedestal, and mounting a control wafer on the first and second rows of bearing pins;
Step S3, electrically connecting a main electrode of the front surface of the first wafer to the first lead by using a first metal piece, and electrically connecting a main electrode of the front surface of the second wafer to the second lead by using a second metal piece. On the feet. 如申請專利範圍第29項所述的方法，其特徵在於，基座具有一個連接部，從基座位於第二縱向邊緣的一側的頂部向第一排承載引腳中靠近第二縱向邊緣的最內側的一個承載引腳延伸，並與其連接。The method of claim 29, wherein the base has a connecting portion from a top of the base on one side of the second longitudinal edge toward the second longitudinal carrying edge of the first row of carrying pins The innermost one of the carrier pins extends and is connected thereto. 如申請專利範圍第30項所述的方法，其特徵在於，在步驟S2中，使第一、第二晶片各自背面的背部電極均粘附在基座的頂面，其中第一、第二晶片各自的副電極位於各自的正面。The method of claim 30, wherein in step S2, the back electrodes of the respective back sides of the first and second wafers are adhered to the top surface of the pedestal, wherein the first and second wafers The respective secondary electrodes are located on their respective front faces. 如申請專利範圍第31項所述的方法，其特徵在於，第一、第二排承載引腳各自的每個承載引腳均皆包括相互連接的一個上置引腳和一個下置引腳；
在步驟S2中，先使第一、第二晶片各自的正面均與所有承載引腳的上置引腳的頂面共面；
然後使控制晶片以向第一、第二晶片偏移的方式倒裝安裝在第一、第二排承載引腳上，使其具有與第一、第二晶片形成交疊的交疊部分，使交疊部分正面的多個焊墊上相應設置的多個金屬凸塊分別對準並電性連接至第一、第二晶片各自的主電極、副電極；
同時使控制晶片餘下的焊墊上設置的金屬凸塊分別對準並電性連接至相應的各上置引腳上。The method of claim 31, wherein each of the first and second rows of carrier pins comprises an upper pin and a lower pin connected to each other;
In step S2, first, the front sides of the first and second wafers are all coplanar with the top surface of the upper pins of all the carrying pins;
The control wafer is then flip-chip mounted on the first and second rows of carrier pins in such a manner as to be offset from the first and second wafers to have overlapping portions that overlap the first and second wafers. a plurality of metal bumps respectively disposed on the plurality of pads on the front surface of the overlapping portion are respectively aligned and electrically connected to the main electrodes and the sub-electrodes of the first and second wafers;
At the same time, the metal bumps disposed on the remaining pads of the control chip are respectively aligned and electrically connected to the corresponding upper pins. 如申請專利範圍第32項所述的方法，其特徵在於，完成步驟S3之後，還包括利用一個塑封體將晶片安裝單元、第一和第二晶片、控制晶片、第一和第二金屬片及各金屬凸塊予以包覆的步驟，其包覆方式至少使各下置引腳的底面、基座的底面、第一和第二引腳各自的底面從塑封體的底面中外露。The method of claim 32, further comprising, after completing step S3, further comprising: using a molding body to mount the wafer mounting unit, the first and second wafers, the control wafer, the first and second metal sheets, and The step of covering each of the metal bumps is performed by at least the bottom surface of each of the lower pins, the bottom surface of the pedestal, and the bottom surfaces of the first and second leads are exposed from the bottom surface of the molding body. 如申請專利範圍第30項所述的方法，其特徵在於，預先在基座的頂面上設置一個凹槽，在步驟S2中，第一、第二晶片被安裝在凹槽內，使第一、第二晶片各自背面的背部電極均粘附在凹槽的底部，第一、第二晶片各自的副電極位於各自的正面，使第一、第二晶片各自的正面均與第一、第二排承載引腳各自的每個承載引腳的頂面共面。The method of claim 30, wherein a groove is provided on the top surface of the base in advance, and in step S2, the first and second wafers are mounted in the groove to make the first The back electrodes on the back sides of the second wafer are all adhered to the bottom of the groove, and the respective sub-electrodes of the first and second wafers are located on the respective front faces, so that the front faces of the first and second wafers are respectively the first and second faces. The top surface of each of the carrier pins of the row carrying pins is coplanar. 如申請專利範圍第34項所述的方法，其特徵在於，在步驟S2中，使控制晶片以向第一、第二晶片偏移的方式倒裝安裝在第一、第二排承載引腳上，使其具有與第一、第二晶片形成交疊的交疊部分，使交疊部分正面的多個焊墊上設置的多個金屬凸塊分別對準並電性連接至第一、第二晶片各自的主電極、副電極；
同時使控制晶片餘下的焊墊上設置的金屬凸塊分別對準並電性連接至第一、第二排承載引腳的相應各承載引腳上。The method of claim 34, wherein in step S2, the control wafer is flip-chip mounted on the first and second rows of carrier pins in such a manner as to be offset from the first and second wafers. Having an overlapping portion overlapping the first and second wafers, respectively aligning and electrically connecting the plurality of metal bumps disposed on the plurality of pads on the front surface of the overlapping portion to the first and second wafers Respective main electrodes and secondary electrodes;
At the same time, the metal bumps disposed on the remaining pads of the control chip are respectively aligned and electrically connected to the corresponding carrier pins of the first and second rows of carrier pins. 如申請專利範圍第35項所述的方法，其特徵在於，完成步驟S3之後，還包括利用一個塑封體將晶片安裝單元、第一和第二晶片、控制晶片、第一和第二金屬片及各金屬凸塊予以包覆的步驟，其包覆方式至少使各承載引腳的底面、基座的底面、第一和第二引腳各自的底面從塑封體的底面中外露。The method of claim 35, further comprising, after completing step S3, further comprising: using a molding body to mount the wafer mounting unit, the first and second wafers, the control wafer, the first and second metal sheets, and The step of covering each of the metal bumps is performed by at least the bottom surface of each of the carrier pins, the bottom surface of the pedestal, and the bottom surfaces of the first and second pins are exposed from the bottom surface of the molding body. 如申請專利範圍第35項所述的方法，其特徵在於，第一、第二金屬片各包括一個主平板部分和連接在主平板部分一側的相對主平板部分具有高度差的一個副平板部分，以及第一、第二金屬片各自的主平板部分的底面上均設置有一個垂直向下延伸的端部；
在步驟S3中，使第一、第二金屬片各自的端部的底端面分別與第一、第二晶片的主電極焊接，第一、第二金屬片各自的副平板部分分別與第一、第二引腳的鍵合區焊接。The method of claim 35, wherein the first and second metal sheets each comprise a main flat plate portion and a sub-plate portion having a height difference from the opposite main flat plate portion connected to one side of the main flat plate portion. And a bottom surface of each of the first and second metal sheets each having a vertically downwardly extending end portion;
In step S3, the bottom end faces of the respective ends of the first and second metal sheets are respectively soldered to the main electrodes of the first and second wafers, and the sub-plate portions of the first and second metal sheets are respectively associated with the first The bonding area of the second pin is soldered. 如申請專利範圍第37項所述的方法，其特徵在於，在步驟S2中，使控制晶片的背面與第一、第二金屬片各自的主平板部分的頂面共面；
在完成步驟S3之後，還包括利用一個塑封體將晶片安裝單元、第一和第二晶片、控制晶片、第一和第二金屬片及各金屬凸塊予以包覆的步驟，包覆方式至少使各承載引腳的底面、基座的底面、第一和第二引腳各自的底面從塑封體的底面外露，和使第一、第二金屬片各自主平板部分的頂面、控制晶片的背面從塑封體的頂面外露。The method of claim 37, wherein in step S2, the back surface of the control wafer is coplanar with the top surface of each of the first and second metal sheets;
After the step S3 is completed, the method further comprises the steps of coating the wafer mounting unit, the first and second wafers, the control wafer, the first and second metal sheets, and the metal bumps by using a molding body, the covering manner is at least The bottom surface of each of the carrier pins, the bottom surface of the base, and the bottom surface of each of the first and second pins are exposed from the bottom surface of the molding body, and the top surface of each of the first and second metal sheets is controlled to be the top surface of the main flat plate portion, and the back surface of the control wafer Exposed from the top surface of the plastic body. 如申請專利範圍第29項所述的方法，其特徵在於，第一引腳沿第一橫向邊緣的長度方向延伸的長度值小於第一橫向邊緣的長度值，第二引腳沿第二橫向邊緣的長度方向延伸的長度值小於第二橫向邊緣的長度值；
晶片安裝單元包括在第一引腳的橫向延長線上設置的一個靠近第一橫向邊緣的第一旁路引腳，位於第一排承載引腳的最內側的承載引腳和第一引腳之間，並通過其帶有的一個連接部與第一排承載引腳中最內側的承載引腳連接；
晶片安裝單元包括還包括在第二引腳的橫向延長線上設置的一個靠近第二橫向邊緣的第二旁路引腳，位於第二排承載引腳的最內側的承載引腳和第二引腳之間，並通過其帶有的一個連接部與第二排承載引腳的最內側的承載引腳連接；
晶片安裝單元還包括一個L形的連接結構，其一端連接在第一、第二排承載引腳中除各自最內側的承載引腳以外的任意一承載引腳上，另一端連接在基座上；
在步驟S2中，控制晶片倒裝安裝在第一、第二排承載引腳上，其正面的多個焊墊上相應設置的多個金屬凸塊分別對準並電性連接至各相應的承載引腳上；從而
在步驟S3中，利用導電結構，將第一、第二晶片各自正面的副電極分別電性連接到第一、第二旁路引腳上。The method of claim 29, wherein the length of the first pin extending along the length of the first lateral edge is smaller than the length of the first lateral edge, and the second pin is along the second lateral edge. The length value extending in the length direction is smaller than the length value of the second lateral edge;
The wafer mounting unit includes a first bypass pin disposed on a lateral extension of the first pin adjacent to the first lateral edge, between the innermost carrier pin of the first row of carrier pins and the first pin And connected to the innermost carrier pin of the first row of carrier pins by a connection portion thereof;
The wafer mounting unit further includes a second bypass pin disposed on the lateral extension line of the second pin adjacent to the second lateral edge, and the innermost carrier pin and the second pin of the second row carrying pin Between and through a connection portion thereof with the innermost carrier pin of the second row of carrying pins;
The chip mounting unit further includes an L-shaped connecting structure, one end of which is connected to any one of the first and second rows of carrying pins except for the innermost carrying pins, and the other end is connected to the base. ;
In step S2, the control wafer is flip-chip mounted on the first and second rows of carrier pins, and a plurality of metal bumps respectively disposed on the plurality of pads on the front surface are respectively aligned and electrically connected to the respective carrier leads. On the foot; thus, in step S3, the secondary electrodes on the front sides of the first and second wafers are electrically connected to the first and second bypass pins, respectively, by using a conductive structure. 如申請專利範圍第29項所述的方法，其特徵在於，在步驟S2中，控制晶片倒裝安裝在第一、第二排承載引腳上，其正面的多個焊墊上相應設置的多個金屬凸塊分別對準並電性連接至各相應的承載引腳上；
步驟S3還包括，利用鍵合引線，將第一晶片的副電極電性連接至第一排承載引腳中任意一承載引腳上，將第二晶片的副電極和基座的頂面分別電性連接至第二排承載引腳中任意兩個不同承載引腳上。The method of claim 29, wherein in step S2, the control wafer is flip-chip mounted on the first and second rows of carrier pins, and the plurality of pads on the front surface are correspondingly disposed. Metal bumps are respectively aligned and electrically connected to respective bearing pins;
Step S3 further includes electrically connecting the secondary electrode of the first wafer to any one of the first row of carrying pins by using a bonding wire, respectively, and electrically electrically connecting the secondary electrode of the second wafer and the top surface of the base. Sexually connected to any two different carrier pins of the second row of carrying pins. 如申請專利範圍第29項所述的方法，其特徵在於，在步驟S2中，將控制晶片的背面粘附在第一、第二排承載引腳上；
步驟S3還包括，利用鍵合引線，將第一、第二晶片各自的副電極、基座的頂面分別電性連接至控制晶片正面的相對應的焊墊上，同時利用鍵合引線將控制晶片正面餘下的多個焊墊分別連接至相對應的各承載引腳的頂面上。The method of claim 29, wherein in step S2, the back side of the control wafer is adhered to the first and second rows of carrier pins;
Step S3 further includes electrically connecting the top surfaces of the sub-electrodes and the pedestals of the first and second wafers to the corresponding pads on the front surface of the wafer by using bonding wires, and simultaneously controlling the wafers by using bonding wires. A plurality of solder pads remaining on the front surface are respectively connected to the top surfaces of the corresponding carrier pins. 一種功率控制器件的製備方法，其特徵在於，包括以下步驟：
步驟S1、提供一晶片安裝單元，包括相鄰的第一、第二基座，並包括第一基座附近的第一引腳及第一排承載引腳，和包括第二基座附近的第二引腳及第二排承載引腳；
第一、第二基座各自均具有相對的一組第一、第二橫向邊緣及相對的一組第一、第二縱向邊緣，第一引腳靠近第一基座的第一橫向邊緣並且其條狀鍵合區沿第一基座的第一橫向邊緣長度方向延伸，第二引腳靠近第二基座的第二橫向邊緣並且其條狀鍵合區沿第二基座的第二橫向邊緣長度方向延伸；
第一排承載引腳位於第一基座的第二縱向邊緣的一側，且第一排承載引腳中的每一個承載引腳均平行於第一基座的第二縱向邊緣，並由第一引腳的橫向延長線上向第一基座、第二基座之間的分割線延伸；及
第二排承載引腳位於第二基座的第二縱向邊緣的一側，且第二排承載引腳中的每一個承載引腳均平行於第二基座的第二縱向邊緣，並由第二引腳的橫向延長線上向所述分割線延伸；
步驟S2、將一第一晶片和一第二晶片分別安裝在第一、第二基座之上，將一控制晶片安裝在第一、第二排承載引腳之上；
步驟S3、將一金屬片焊接至第一、第二晶片各自正面的主電極和第二引腳上。A method for preparing a power control device, comprising the steps of:
Step S1, providing a wafer mounting unit, including adjacent first and second pedestals, and including a first pin and a first row of carrying pins near the first pedestal, and including a second pedestal Two pins and a second row carrying pins;
The first and second pedestals each have an opposite set of first and second lateral edges and an opposite set of first and second longitudinal edges, the first pin being adjacent to the first lateral edge of the first pedestal and a strip-shaped bonding region extending along a first lateral edge length of the first pedestal, a second pin adjacent the second lateral edge of the second pedestal and a strip-shaped bonding region along a second lateral edge of the second pedestal Extending in the length direction;
a first row of carrier pins on one side of a second longitudinal edge of the first pedestal, and each of the first row of carrier pins is parallel to a second longitudinal edge of the first pedestal and is a lateral extension line of one pin extends toward a dividing line between the first base and the second base; and a second row of carrying pins is located on one side of the second longitudinal edge of the second base, and the second row carries Each of the pins is parallel to the second longitudinal edge of the second pedestal and extends from the lateral extension of the second pin toward the dividing line;
Step S2, mounting a first wafer and a second wafer on the first and second pedestals respectively, and mounting a control wafer on the first and second rows of carrier pins;
Step S3, soldering a metal piece to the main electrode and the second pin of each front surface of the first and second wafers. 如申請專利範圍第42項所述的方法，其特徵在於，第二引腳具有一個連接部，從第二引腳的鍵合區的頂部靠近第二排承載引腳中最內側的一個承載引腳的一側向該最內側的一個承載引腳延伸，並與其連接；
第一、第二排承載引腳各自的每個承載引腳均皆包括相互連接的一個上置引腳和一個下置引腳；
在步驟S2中，先使第一、第二晶片各自的正面均與所有承載引腳的上置引腳的頂面共面；然後
使控制晶片以向第一、第二晶片偏移的方式倒裝安裝在第一、第二排承載引腳上，使其具有與第一、第二晶片形成交疊的交疊部分，使交疊部分正面的多個焊墊上設置的多個金屬凸塊分別對準並電性連接至第一、第二晶片各自的主電極、副電極，同時使控制晶片餘下的焊墊上設置的金屬凸塊分別對準並電性連接至相應的各上置引腳上。The method of claim 42, wherein the second pin has a connecting portion from the top of the bonding region of the second pin to the innermost one of the second row of carrying pins. One side of the foot extends toward and is connected to the innermost one of the carrier pins;
Each of the first and second rows of carrier pins includes an upper pin and a lower pin connected to each other;
In step S2, the front sides of the first and second wafers are all coplanar with the top surface of the upper pins of all the carrier pins; then the control wafer is inverted to the first and second wafers. Mounting on the first and second rows of carrying pins to have overlapping portions overlapping the first and second wafers, so that the plurality of metal bumps disposed on the plurality of pads on the front side of the overlapping portion are respectively Aligning and electrically connecting to the main electrode and the sub-electrode of each of the first and second wafers, and simultaneously aligning and electrically connecting the metal bumps disposed on the remaining pads of the control wafer to the respective upper pins. . 如申請專利範圍第43項所述的方法，其特徵在於，第一基座具有一個連接部，從第一基座的頂部位於其第一橫向邊緣的一側向第一引腳延伸，並與其連接。The method of claim 43, wherein the first base has a connecting portion extending from a top of the first base at a side of the first lateral edge thereof toward the first pin, and connection. 如申請專利範圍第42項所述的方法，其特徵在於，第一引腳沿第一橫向邊緣的長度方向延伸的長度值分別小於第一橫向邊緣的長度值，第二引腳沿第二橫向邊緣的長度方向延伸的長度值分別小於第二橫向邊緣的長度值；
晶片安裝單元包括在第一引腳的延長線上設置的一個靠近第一橫向邊緣的第一旁路引腳，位於第一排承載引腳的最內側的承載引腳和第一引腳之間，第一旁路引腳帶有一個連接部，從第一旁路引腳靠近該最內側的承載引腳的一側的頂部向該承載引腳延伸，並與其連接；
還包括在第二引腳的延長線上設置有一個靠近第二橫向邊緣的第二旁路引腳，位於第二排承載引腳的最內側的承載引腳和第二引腳之間，第二旁路引腳帶有一個連接部，從第二旁路引腳靠近該最內側的一個承載引腳的一側的頂部向該承載引腳延伸，並與其連接；
在步驟S2中，將控制晶片倒裝安裝在第一、第二排承載引腳上，其正面的多個焊墊上相應設置的多個金屬凸塊分別對準並電性連接至各相應的承載引腳上；
在步驟S3中，金屬片同時還電性連接到第一引腳上，同時利用導電結構將第一、第二晶片的副電極分別電性連接到第一、第二旁路引腳上，並利用鍵合引線將第二引腳或第二晶片的主電極電性連接到第二排承載引腳中除最內側的承載引腳以外的任意一承載引腳上。The method of claim 42, wherein the length of the first pin extending along the length of the first lateral edge is smaller than the length of the first lateral edge, and the second pin is along the second lateral direction. The length values of the edges extending in the longitudinal direction are respectively smaller than the length values of the second lateral edges;
The chip mounting unit includes a first bypass pin disposed on an extension line of the first pin adjacent to the first lateral edge, between the innermost carrier pin of the first row of carrying pins and the first pin, The first bypass pin has a connection portion extending from the top of the first bypass pin adjacent to the side of the innermost carrier pin and connected thereto;
The method further includes a second bypass pin disposed adjacent to the second lateral edge on the extension line of the second pin, between the innermost carrier pin and the second pin of the second row carrying pin, and second The bypass pin has a connection portion extending from the top of the second bypass pin adjacent to the side of the innermost one of the carrier pins and connected thereto;
In step S2, the control wafer is flip-chip mounted on the first and second rows of carrier pins, and a plurality of metal bumps respectively disposed on the plurality of pads on the front surface are respectively aligned and electrically connected to the respective carriers. On the pin;
In step S3, the metal piece is electrically connected to the first pin at the same time, and the auxiliary electrodes of the first and second wafers are electrically connected to the first and second bypass pins respectively by using a conductive structure, and The main electrode of the second pin or the second chip is electrically connected to any one of the second row of carrying pins except the innermost carrying pin by a bonding wire. 如申請專利範圍第42項所述的方法，其特徵在於，在步驟S2中，將控制晶片倒裝安裝在第一、第二排承載引腳上，其正面的多個焊墊上相應設置的多個金屬凸塊分別對準並電性連接至各相應的承載引腳上；
在步驟S3中，金屬片還電性連接到第一引腳上，並利用鍵合引線，將第一晶片的副電極電性連接至第一排承載引腳中任意一承載引腳上，將第二晶片的正、副電極分別相對應的電性連接至第二排承載引腳中任意兩個不同的承載引腳上。The method of claim 42, wherein in step S2, the control wafer is flip-chip mounted on the first and second rows of carrier pins, and the plurality of pads on the front surface are correspondingly disposed. Metal bumps are respectively aligned and electrically connected to respective bearing pins;
In step S3, the metal piece is further electrically connected to the first pin, and the secondary electrode of the first wafer is electrically connected to any one of the first row of carrying pins by using a bonding wire, The positive and the secondary electrodes of the second wafer are respectively electrically connected to any two different carrier pins of the second row of carrier pins. 如申請專利範圍第42項所述的方法，其特徵在於，在步驟S2中，使控制晶片的背面粘附在第一、第二排承載引腳上；
在步驟S3中，金屬片同時還被電性連接到第一引腳上，之後利用鍵合引線，將第一、第二晶片各自的副電極、第二晶片的主電極分別電性連接至控制晶片正面的相對應的焊墊上，同時利用鍵合引線將控制晶片正面餘下的多個焊墊分別連接至相對應的各承載引腳的頂面上。The method of claim 42, wherein in step S2, the back surface of the control wafer is adhered to the first and second rows of carrier pins;
In step S3, the metal piece is also electrically connected to the first pin, and then the main electrode of the first and second wafers and the main electrode of the second chip are electrically connected to the control by the bonding wires. On the corresponding pads on the front side of the wafer, the plurality of pads remaining on the front side of the control wafer are respectively connected to the top surfaces of the corresponding carrier pins by using bonding wires. 一種功率控制器件的製備方法，其特徵在於，包括以下步驟：
步驟S1、提供一晶片安裝單元，該晶片安裝單元包括相鄰的第一、第二基座，並包括第一基座附近的第一引腳及第一排承載引腳，和包括第二基座附近的第二引腳及第二排承載引腳；
第一、第二基座各自均具有相對的一組第一、第二橫向邊緣及相對的一組第一、第二縱向邊緣，第一引腳靠近第一基座的第一橫向邊緣並且其條狀鍵合區沿第一基座的第一橫向邊緣的長度方向延伸，第二引腳靠近第二基座的第二橫向邊緣並且其條狀鍵合區沿第二基座的第二橫向邊緣的長度方向延伸；
第一排承載引腳位於第一基座的第二縱向邊緣的一側，且第一排承載引腳中的每一個承載引腳均平行於第一基座的第二縱向邊緣，並由第一引腳的橫向延長線上向第一基座和第二基座之間的分割線延伸；及
第二排承載引腳位於第二基座的第二縱向邊緣的一側，且第二排承載引腳中的每一個承載引腳均平行於第二基座的第二縱向邊緣，並由第二引腳的橫向延長線上向所述分割線延伸；
其中，實質為矩形狀的第二基座在其第一橫向邊緣與第二縱向邊緣交叉的拐角處具有一個矩形切口而使第二基座形成L形結構，並在該切口中嵌入有一個基島；
步驟S2、將一第一晶片安裝在第一基座上，將一第二晶片倒裝安裝在第二基座和基島之上，將一控制晶片安裝在第一、第二排承載引腳之上；
步驟S3、利用一金屬片將第一晶片正面的一個主電極和第二晶片背面的一個背部電極電性連接到第二引腳上。A method for preparing a power control device, comprising the steps of:
Step S1, providing a wafer mounting unit including adjacent first and second pedestals, and including a first pin and a first row of carrying pins near the first pedestal, and including a second base a second pin and a second row of pins adjacent to the socket;
The first and second pedestals each have an opposite set of first and second lateral edges and an opposite set of first and second longitudinal edges, the first pin being adjacent to the first lateral edge of the first pedestal and a strip-shaped bonding region extends along a length of the first lateral edge of the first pedestal, the second pin is adjacent to the second lateral edge of the second pedestal and the strip-shaped bonding region is along the second lateral direction of the second pedestal The length of the edge extends;
a first row of carrier pins on one side of a second longitudinal edge of the first pedestal, and each of the first row of carrier pins is parallel to a second longitudinal edge of the first pedestal and is a lateral extension line of one pin extends toward a dividing line between the first base and the second base; and a second row of carrying pins is located on one side of the second longitudinal edge of the second base, and the second row carries Each of the pins is parallel to the second longitudinal edge of the second pedestal and extends from the lateral extension of the second pin toward the dividing line;
Wherein the substantially second rectangular base has a rectangular cutout at a corner where the first lateral edge intersects the second longitudinal edge, the second base forms an L-shaped structure, and a base is embedded in the slit island;
Step S2: mounting a first wafer on the first pedestal, flip-chip mounting a second wafer on the second pedestal and the island, and mounting a control wafer on the first and second rows of carrying pins. Above
Step S3, electrically connecting a main electrode of the front surface of the first wafer and a back electrode of the back surface of the second wafer to the second pin by using a metal piece. 如申請專利範圍第48項所述的方法，其特徵在於，所述第一基座具有一個連接部，從第一基座的頂部位於第一橫向邊緣的一側向第一引腳延伸，並與其連接。The method of claim 48, wherein the first base has a connecting portion extending from a top of the first base on a side of the first lateral edge toward the first pin, and Connect with it. 如申請專利範圍第48或49項所述的方法，其特徵在於，第一、第二排承載引腳各自的每個承載引腳均皆包括相互連接的一個上置引腳和一個下置引腳；
晶片安裝單元包括一連接結構，其水平延伸段對接在除第二排承載引腳最內側的承載引腳之外的第一、第二排承載引腳中任意一承載引腳的上置部分，其與水平面成夾角設置的傾斜延伸段垂直于水平延伸段並連接在水平延伸段和基島之間；
在步驟S2中，使第一晶片的正面、第二晶片的背面與所有承載引腳的上置引腳的頂面均共面；然後
使控制晶片以向第一、第二晶片偏移的方式倒裝安裝在第一、第二排承載引腳上，使其具有與第一、第二晶片形成交疊的交疊部分，使交疊部分正面的多個焊墊上設置的多個金屬凸塊分別對準並電性連接至第一晶片的主、副電極和第二晶片的背部電極，使控制晶片餘下的焊墊上設置的金屬凸塊分別對準並電性連接至各相應的上置引腳上。The method of claim 48 or 49, wherein each of the first and second rows of carrier pins comprises an upper pin and a lower pin connected to each other. foot;
The chip mounting unit includes a connection structure, the horizontal extension portion of which is connected to an upper portion of any one of the first and second rows of carrier pins except the carrier pin of the innermost side of the second row of carrier pins. An inclined extension disposed at an angle to the horizontal plane is perpendicular to the horizontal extension and connected between the horizontal extension and the base island;
In step S2, the front surface of the first wafer, the back surface of the second wafer, and the top surface of all the upper pins of the carrier pins are coplanar; then the control wafer is shifted toward the first and second wafers. Flip-chip mounted on the first and second rows of carrier pins to have overlapping portions overlapping the first and second wafers, and a plurality of metal bumps disposed on the plurality of pads on the front side of the overlapping portion Aligning and electrically connecting to the main electrodes of the first wafer and the back electrodes of the second wafer, respectively, aligning and electrically connecting the metal bumps disposed on the remaining pads of the control wafer to respective corresponding upper leads On the feet. 如申請專利範圍第48項所述的方法，其特徵在於，第一引腳沿第一基座的第一橫向邊緣的長度方向延伸的長度值分別小於第一基座的第一橫向邊緣的長度值；
晶片安裝單元包括在第一引腳的延長線上設置的一個靠近第一基座的第一橫向邊緣的第一旁路引腳，位於第一排承載引腳的鄰近第二縱向邊緣的最內側的一個承載引腳和第一引腳之間，並且第一旁路引腳帶有一個連接部，從第一旁路引腳靠近該最內側的一個承載引腳的一側的頂部向該承載引腳延伸，並與其連接；
晶片安裝單元包括一L形連接結構，該連接結構的縱向延伸段對接在除第一、第二排承載引腳中各自最內側的承載引腳之外的任意一承載引腳上，其橫向延伸段垂直于縱向延伸段並連接在縱向延伸段和基島之間；
在步驟S2中，使控制晶片倒裝安裝在第一、第二排承載引腳之上，控制晶片的焊墊上設置的金屬凸塊分別對準並電性連接至各相應的承載引腳上；
步驟S3還包括利用一個導電結構將第一晶片的副電極電性連接在第一旁路引腳上的步驟。The method of claim 48, wherein the length of the first pin extending along the length of the first lateral edge of the first pedestal is less than the length of the first lateral edge of the first pedestal, respectively. value;
The wafer mounting unit includes a first bypass pin disposed on an extension of the first pin adjacent the first lateral edge of the first pedestal, located at an innermost side of the first row of carrying pins adjacent the second longitudinal edge a carrier pin and the first pin, and the first bypass pin has a connection portion from the top of the side of the first bypass pin adjacent to the innermost one of the carrier pins The foot extends and is connected thereto;
The wafer mounting unit includes an L-shaped connection structure, and the longitudinal extension of the connection structure is docked on any of the carrier pins except the innermost carrier pins of the first and second rows of carrier pins, and the lateral extension thereof The segment is perpendicular to the longitudinal extension and is connected between the longitudinal extension and the base island;
In step S2, the control wafer is flip-chip mounted on the first and second rows of carrier pins, and the metal bumps disposed on the pads of the control wafer are respectively aligned and electrically connected to the respective carrier pins;
Step S3 further includes the step of electrically connecting the secondary electrode of the first wafer to the first bypass pin using a conductive structure. 如申請專利範圍第48項所述的方法，其特徵在於，晶片安裝單元包括一L形連接結構，該連接結構的縱向延伸段對接在除第二排承載引腳中最內側的承載引腳之外的第一、第二承載引腳中的任意一承載引腳上，其橫向延伸段垂直于縱向延伸段並連接在縱向延伸段和基島之間；
在步驟S2中，使控制晶片倒裝安裝在第一、第二排承載引腳之上；
步驟S3還包括利用鍵合引線將第一晶片的副電極電性連接在第一排承載引腳中的沒有與所述L形連接結構連接在一起的任意一承載引腳上的步驟。The method of claim 48, wherein the wafer mounting unit comprises an L-shaped connection structure, and the longitudinal extension of the connection structure is butted to the innermost carrier pin of the second row of carrier pins. And any one of the first and second carrier pins, wherein the lateral extension is perpendicular to the longitudinal extension and is connected between the longitudinal extension and the base island;
In step S2, the control wafer is flip-chip mounted on the first and second rows of carrier pins;
Step S3 further includes the step of electrically connecting the secondary electrodes of the first wafer to any one of the first rows of carrier pins that are not connected to the L-shaped connection structure by means of bond wires. 如申請專利範圍第48項所述的方法，其特徵在於，在步驟S2中，將控制晶片的背面粘附在第一、第二排承載引腳上；
步驟S3還包括利用鍵合引線，將第一晶片的副電極、基島分別電性連接至控制晶片正面的相對應的焊墊上，同時利用鍵合引線將控制晶片正面餘下的多個焊墊分別連接至第一、第二排承載引腳中相應的各承載引腳的頂面上的步驟。The method of claim 48, wherein in step S2, the back side of the control wafer is adhered to the first and second rows of carrier pins;
Step S3 further includes electrically connecting the secondary electrode and the base island of the first wafer to the corresponding pads on the front surface of the control wafer by using the bonding wires, and simultaneously controlling the remaining plurality of solder pads on the front surface of the wafer by using the bonding wires. A step of connecting to the top surface of each of the first and second rows of carrier pins. 如申請專利範圍第51~53項中任意一項所述的方法，其特徵在於，第二引腳具有一個連接部，從第二引腳的鍵合區的頂部靠近第二排承載引腳中最內側的一個承載引腳的一側向該最內側的一個承載引腳延伸，並與其連接；
在步驟S3中，還將所述金屬片電性連接在第一引腳上。
The method of any one of claims 51 to 53, wherein the second pin has a connecting portion from the top of the bonding region of the second pin to the second row of the carrying pins One of the innermost one of the carrying pins extends toward and is connected to the innermost one of the carrying pins;
In step S3, the metal piece is also electrically connected to the first pin.
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Publication number Priority date Publication date Assignee Title
CN112117250A (en) * 2020-09-07 2020-12-22 矽磐微电子(重庆)有限公司 Chip packaging structure and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112117250A (en) * 2020-09-07 2020-12-22 矽磐微电子(重庆)有限公司 Chip packaging structure and manufacturing method thereof

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