TW201501447A - Active battery charge equalization circuit for electric vehicle - Google Patents

Abstract

An active battery charge equalization circuit is disclosed. The circuit comprises an inner charge equalization circuit and an outer charge equalization circuit. The inner charge equalization circuit is electrically connected to a certain number of batteries; and the outer charge equalization circuit is electrically connected to the inner charge equalization circuit on a single PCB. Therefore, the redundant charge of any battery is collaboratively released by the inner and outer charge equalization circuits to the other batteries, and thus achieving charge equalization effectively.

Description

Active battery balance circuit structure of electric vehicle battery pack

The invention relates to an application field of an electric vehicle, in particular to an active electric balance circuit structure of an electric vehicle battery pack.

For high power applications, such as electric vehicles, etc., it is common to have series connected battery modules to provide the required voltage. When the lithium battery module is in series, the power imbalance is caused, and the battery is easily damaged by overvoltage or undervoltage.

If the power balance circuit is provided, the problem of matching the battery module can be improved, and the safety and cycle life of the lithium battery are greatly improved. In order to cope with the situation of more series battery, if there is only a single-level architecture, the circuit structure will be too complicated and difficult to implement; in addition, due to the complicated energy transmission path, the conversion efficiency will be reduced; The architecture is not suitable for modular design, and it is not convenient for the expansion of the number of connected batteries in the future.

The invention provides an active power balance circuit structure of an electric vehicle battery pack, which has a two-level balanced circuit structure, and can easily achieve a modular design, facilitates the expansion of the number of serially connected batteries in the future, and can improve the lithium battery. The safety of the pool and the improvement of its cycle life.

Therefore, the object of the present invention is to solve the above problems and provide an active battery balancing circuit structure for an electric vehicle battery pack, comprising an inner layer cell balancing circuit electrically connected with a plurality of batteries; and an outer layer balancing circuit, The inner layer cell balancing circuit is electrically connected to a circuit board.

Thereby, the excess power of one of the batteries is released to the other battery through the inner layer balancing circuit and the outer layer balancing circuit.

Wherein, the inner layer balance voltage system is composed of several sets of step-down converters (buck-boost converter), each set of step-down converters includes a diode, a transistor, and an inductor, and each battery system is connected to a corresponding one group to reduce the voltage On the converter.

Wherein, the step-down converter is operated in a continuous conduction mode (CCM).

Wherein one transistor Q ₁ is turned on when the case, the case ₁ by a power line connected to one of the transistor Q ₁ cells B ₁ removed, and stored in the transistor Q is connected to the inductor L _1; When the transistor Q _{1 is} in the off state, the amount of electricity is distributed by the inductor L ₁ to the other battery through the corresponding diode D ₁ .

The outer cell balancing circuit OCE includes a plurality of sets of anti-parallel transistors (switches) and a plurality of capacitors, each of which is electrically connected to a corresponding one of a group of transistors (switches) that are connected in anti-parallel. Connected, the output ends of two adjacent sets of anti-parallel transistors (switches) are electrically connected to the two ends of one of the capacitors respectively, and the number of the capacitors is less than the reverse parallel transistors (switches The number of sets is one, and the number of such batteries is the same as the number of sets of transistors (switches) in the reverse parallel.

The transistor (switch) is a BJT or a MOSFET.

The above objects and advantages of the present invention will be readily understood from the following detailed description of the embodiments of the invention.

Of course, the invention may be varied on certain components, or in the arrangement of the components, but the selected embodiments are described in detail in the specification and their construction is shown in the drawings.

ICE‧‧‧ Inner layer cell balancing circuit

OCE‧‧‧Outer cell balance circuit

B ₁ ~B ₄ ‧‧‧Battery

B _m1 ~B _m4 ‧‧‧Battery

C ₁ ~ C ₃ ‧ ‧ capacitor

C _outside ‧‧‧ capacitor

D ₁ ~ D ₄ ‧‧‧ Dipole

i _B1 ~i _B2 ‧‧‧ Current

I _m1 ~I _m4 ‧‧‧current

I _pk ‧‧‧peak current

I _tr ‧‧‧ valley current

L ₁ ~L ₄ ‧‧‧Inductors

Line 5~13‧‧‧Connecting wire

Line A‧‧‧Connecting wire

MB ₁ ~MB ₄ ‧‧‧Battery Pack

Point1~3‧‧‧connection endpoint

Point5‧‧‧connection endpoint

pointA1‧‧‧connection endpoint

Q ₁ ~Q ₇ ‧‧‧Optoelectronics

Q _dis ‧‧‧released electricity

BQ _1a , BQ _1b , BQ _1c , BQ _2a , BQ _2b , BQ _2c , BQ _3a , BQ _3b , BQ _3c , BQ _4a , BQ _4b , BQ _4c ‧‧‧BJT

MQ _1a , MQ _1b , MQ _2a , MQ _2b , MQ _3a , MQ _3b , MQ _4a , MQ _4b ‧ ‧ MOSFET

T ₁ ~T ₂ ‧‧‧Transformer

T _s ‧‧‧ switching cycle

FIG. 1 is a schematic diagram showing a two-layer balanced circuit structure of an active power balance circuit structure of the battery pack of the present invention.

FIG. 2 is a circuit diagram showing the inner layer balance circuit of the present invention.

FIG. 3A is a schematic diagram showing the operation of the corresponding boost converter in FIG. 2 when the battery B _{4 has a} large amount of electricity and the transistor Q _{4 is} turned on.

FIG. 3B is a schematic diagram showing the operation of the corresponding boost converter in FIG. 2 when the battery B _{4 has a} large amount of electricity and the transistor Q ₄ is turned off.

4A is a schematic diagram showing the operation of the corresponding boost converter of FIG. 2 when the battery B _{1 has a} large amount of electricity and the transistor Q _{1 is} turned on.

FIG. 4B is a schematic diagram showing the operation of the corresponding boost converter in FIG. 2 when the battery B _{1 has a} large amount of electricity and the transistor Q ₁ is turned off.

FIG. 5A is a schematic diagram showing the operation of the corresponding boost converter when the battery B ₂ and the battery B _{3 are} electrically charged and the transistor Q ₂ and the transistor Q _{3 are} turned on in FIG. 2 .

FIG. 5B is a schematic diagram showing the operation of the corresponding boost converter when the battery B ₂ and the battery B _{3 are} large in power and the transistors Q ₂ and Q _{3 are} turned off in FIG. 2 .

Fig. 6A is a circuit diagram showing a first embodiment of an outer layer cell balancing circuit of the present invention.

Figure 6B is a circuit diagram showing a second embodiment of the outer layer cell balancing circuit of the present invention.

Fig. 7 is a circuit diagram showing the MOSFETs MQ _1a , MQ _2a , MQ _3a , and MQ _4a turned on in Fig. 6B.

Fig. 8 is a circuit diagram showing the MOSFETs MQ _1b , MQ _2b , MQ _3b , and MQ _4b turned on in Fig. 6B.

Fig. 9A is a simplified circuit diagram showing a state in which a transistor (switch) Qi of a boost converter is turned on.

Fig. 9B is a simplified circuit diagram showing the state in which the transistor (switch) Qi of the boost converter is turned off.

Fig. 10 is a view showing the correspondence relationship between the inductor current i _L and the time t on the boost converter.

Fig. 11 is a flow chart showing the calculation of the conduction rate.

Fig. 12 is a flow chart showing the calculation of the conduction ratio of the boost converter.

Figure 13 is a circuit diagram showing the main circuit block in the actual circuit.

Fig. 14 is a view showing the connection of the outer layer circuit.

Figure 15 is a circuit diagram showing the control and drive circuit.

Fig. 16 is a circuit diagram showing a power supply circuit.

Figure 17 is a diagram showing the connection of the third and fourth batteries in a circuit board. Waveform diagram of the drive signal and pole current of the converter.

Figure 18 is a graph showing the results of balancing a single circuit board with four batteries.

Figure 19 is a graph showing the results of balancing four batteries with respect to another single circuit board of Figure 18.

With regard to the technical means by which the present invention achieves the above objects, the following embodiments are described in detail below with reference to the drawings, which are well understood and recognized.

Please refer to FIG. 1 , which is a two-layer balanced circuit architecture diagram of the active battery balancing circuit structure of the battery pack of the present invention.

The active battery balance circuit structure 1 of the electric vehicle battery pack of the present invention includes an inner charge equalization circuit (ICE) and an outer charge equalization circuit (OCE), and an inner layer balance circuit ICE system. It is electrically connected to the outer cell balancing circuit OCE.

As shown in FIG. 1 , the inner layer balance circuit ICE and the outer layer balance circuit OCE can be disposed on the same circuit board (not shown), which can form a modular design and is suitable for more series battery packs. (For example, the application of the first battery pack MB ₁ , the second battery pack MB ₂ , the third battery pack MB _{3 ,} and the fourth battery pack MB ₄ in series).

FIG. 2 is a circuit diagram showing the inner layer balance circuit of the present invention.

Referring to FIG. 2, the inner layer balance circuit ICE can be composed of four sets of buck-boost converters, each of which includes a diode, a transistor, And an inductor, that is, the first group of step-down converters includes a diode D ₁ , a transistor Q _{1 ,} and an inductor L ₁ , and the second group of step-down converters includes a diode D ₂ The transistor Q ₂ and the inductor L ₂ , the third group of step-down converters includes a diode D ₃ , a transistor Q ₃ and an inductor L ₃ , and the fourth group of step-up converters includes two The polar body D ₄ , the transistor Q ₄ and the inductor L ₄ ; but not limited thereto. Each of the batteries B ₁ , B ₂ , B ₃ , B ₄ is connected to a set of step-down converters, wherein i _B1 and i _B2 represent currents flowing through battery B ₁ and battery B ₂ , respectively. The step-down converter is responsible for transferring too much power on the corresponding battery to other batteries; here the step-down converter is operated in continuous conduction mode (CCM) to provide comparison Large transfer current.

FIG. 3A is a schematic diagram showing the operation of the corresponding boost converter in FIG. 2 when the battery B _{4 has a} large amount of electricity and the transistor Q _{4 is} turned on. FIG. 3B is a schematic diagram showing the operation of the corresponding boost converter in FIG. 2 when the battery B _{4 has a} large amount of electricity and the transistor Q ₄ is turned off.

Please refer to FIG. 3A and FIG. 3B simultaneously. In FIG. 3A, the transistor Q ₄ is in the on state, at which time the power is taken out by the battery B ₄ and stored on the inductor L ₄ ; and in FIG. 3B , in FIG. 3B The crystal Q ₄ is in the off state, at which time the electric quantity is distributed by the inductor L ₄ through the diode D ₄ to the other batteries B ₁ , B ₂ and B ₃ .

FIG. 4A is a schematic diagram showing the operation of the corresponding step-down converter of FIG. 2 when the battery B _{1 has a} large amount of electricity and the transistor Q _{1 is} turned on. FIG. 4B is a schematic diagram showing the operation of the corresponding step-down converter of FIG. 2 when the battery B _{1 has a} large amount of electricity and the transistor Q ₁ is turned off.

Referring to FIG. 4A and FIG. 4B simultaneously, in FIG. 4A, the transistor Q ₁ is in the on state, at which time the power is taken out by the battery B ₁ and stored on the inductor L ₁ ; and in FIG. 4B , The crystal Q ₁ is in the off state, at which time the electric quantity is distributed by the inductor L ₁ through the diode D ₁ to the other batteries B ₂ , B ₃ and B ₄ .

FIG. 5A is a schematic diagram showing the operation of the corresponding step-down converter in FIG. 2 when the battery B ₂ and the battery B _{3 are} electrically charged and the transistors Q ₂ and Q _{3 are} turned on. FIG. 5B is a schematic diagram showing the operation of the corresponding step-down converter of FIG. 2 when the battery B ₂ and the battery B _{3 are} relatively large and the transistors Q ₂ and Q _{3 are} turned off.

Please refer to FIG. 5A and FIG. 5B simultaneously. In FIG. 5A, the transistor Q ₂ and the transistor Q ₃ are in the on state. At this time, the power is taken out from the battery B ₂ and the battery B ₃ and stored in the inductor L _{2 .} And in the inductor L ₃ ; in FIG. 5B, the transistor Q ₂ and the transistor Q ₃ are in an off state, at which time the power is passed from the inductor L ₂ and the inductor L ₃ through the diode D ₂ and the second The polar body D _{3 is} assigned to the other batteries B ₁ and B ₂ .

Fig. 6A is a circuit diagram showing a first embodiment of an outer layer cell balancing circuit of the present invention. Figure 6B is a circuit diagram showing a second embodiment of the outer layer cell balancing circuit of the present invention.

The outer cell balancing circuit OCE uses a capacitor as a medium for transferring electricity, as shown in FIG. The initial outer cell balancing circuit OCE uses reverse parallel BJT (component numbers BQ _1a , BQ _1b , BQ _1c , BQ _2a , BQ _2b , BQ _2c , BQ _3a , BQ _3b , BQ _3c , BQ _4a , BQ _{4b )} , BQ _4c ) as a switching element, as shown in FIG. 6A; and after considering the reduction of the number of components, the switching-on relationship can all be changed to MOSFETs (MQ _1a , MQ _1b , MQ _2a , MQ _2b , MQ _3a , MQ _{3b )} , MQ _4a , MQ _4b ), as shown in FIG. 6B. Both can achieve the effect of balance of electricity. This creation is illustrated by taking FIG. 6B as an example, but is not limited thereto.

Fig. 7 is a circuit diagram showing the MOSFETs MQ _1a , MQ _2a , MQ _3a , and MQ _4a turned on in Fig. 6B.

Referring to FIG. 7, the outer cell balancing circuit OCE includes a plurality of sets of anti-parallel transistor (switching) MOSFETs (MQ _1a -MQ _1b , MQ _2a -MQ _2b , MQ _3a -MQ _3b , MQ _4a -MQ _4b ) and a plurality of capacitors (C ₁ ~ C ₃ ), each battery system is electrically connected to an input end of a corresponding one of the reverse parallel transistors (switches), and two adjacent sets of reverse parallel transistors (switches) The output ends are electrically connected to the two ends of one of the capacitors respectively, that is, the battery B _m1 is electrically connected to the input terminals of the anti-parallel transistor (switch) MOSFETs MQ _1a -MQ _1b , and the battery B _m2 is connected. Electrically connected to the input terminals of the anti-parallel transistor (switch) MOSFET MQ _2a -MQ _2b , and the battery B _m3 is electrically connected to the input terminal of the anti-parallel transistor (switch) MOSFET MQ _3a -MQ _3b , The battery B _m4 is electrically connected to the input terminals of the anti-parallel transistor (switch) MOSFET MQ _4a -MQ _4b , the anti-parallel transistor (switch) MOSFETs MQ _1a -MQ _1b and the anti-parallel transistors ( The output of the MOSFET MQ _2a -MQ _2b is electrically connected to both ends of the capacitor C ₁ , and the transistor (switching) MOSFET is connected in anti-parallel. The output terminals of MQ _2a -MQ _2b and the anti-parallel transistor (switch) MOSFET MQ _3a -MQ _3b are respectively electrically connected to the two ends of the capacitor C ₂ , and the anti-parallel transistor (switching) MOSFET MQ _3a - The outputs of the MQ _3b and the anti-parallel transistor (switch) MOSFETs MQ _4a -MQ _4b are electrically connected to both ends of the capacitor C ₃ , respectively.

The number of capacitors is less than the number of sets of transistor (switching) MOSFETs connected in anti-parallel, and the number of phases is one. In this embodiment, the number of capacitors is three, and the number of capacitors in reverse parallel is (switching) MOSFET. The number of groups is four, and the number of batteries B _m1 ~ B _m4 is the same as the number of sets of transistor (switching) MOSFETs connected in anti-parallel. When the MOSFETs MQ _1a , MQ _2a , MQ _3a , and MQ _{4a are} turned on, the batteries B _m1 , B _m2 , and B _m3 are respectively connected to the capacitors C ₁ , C ₂ , and C ₃ ; that is, the three capacitors C ₁ , C ₂ , C ₃ is charged to voltage values V _Bm1 , V _Bm2 , V _Bm3 , _respectively ; in particular, MOSFETs MQ _2a and MQ _3a simultaneously _carry currents in both directions, that is, MOSFET MQ _2a simultaneously burdens current I _m1 and current I _M2 , while MOSFET MQ _3a simultaneously carries current I _m2 and current I _m3 ; therefore these two components can flow through a smaller net current to reduce the power loss on the switch.

Fig. 8 is a circuit diagram showing the MOSFETs MQ _1b , MQ _2b , MQ _3b , and MQ _4b turned on in Fig. 6B.

When the MOSFETs MQ _1b , MQ _2b , MQ _3b , and MQ _{4b are} turned on, the batteries B _m2 , B _m3 , and B _m4 are respectively connected to the capacitors C ₁ , C ₂ , and C ₃ ; if the voltage of the capacitor is high, then The battery is discharged to the battery; otherwise, the battery is recharged by the capacitor. Similarly, MOSFETs MQ _2a and MQ _3a simultaneously carry currents in both directions. The two modes of operation are repeated to continuously operate the circuit; that is, the adjacent two cells are powered by a capacitor to carry out the exchange of power until the charge of all the batteries is consistent.

In order to analyze the operation of the boost converter and the power discharged from the battery by the boost converter, the boost converter is represented by a simplified circuit, and FIG. 9A shows the transistor of the boost converter. A simplified circuit diagram when (switch) Qi is turned on, and FIG. 9B is a simplified circuit diagram when the transistor (switch) Qi of the boost converter is turned off. Wherein the subscript "i" represents the ith battery; E _i is the voltage sum of the other batteries that the boost converter faces when releasing energy; and Q _i represents the transistor (switch), and D _i represents Diode, L _i denotes an inductor, R _i denotes a resistor, and also represents all losses on the circuit.

If the boost converter is operated in CCM (Continuous Conduction Mode), the corresponding relationship between the inductor current i _L and the time t on the boost converter is as shown in FIG. 10, where I _tr and I _pk Represents valley current and peak current, respectively. When the transistor (switch) Q _{i is} turned on, the circuit equation can be expressed as:

When the transistor (switch) Q _i is turned off, the circuit equation can be expressed as:

Solving the above equation (1) and equation (2) is available:

Where T _s is the switching period of the transistor (switch) Q _i .

In order to calculate the battery power that can be released by the boost converter, considering that the transistor (switch) is turned on, the inductor current is the current released by the battery. Therefore, the Q _dis in Figure 10 is a transistor (switch). The discharged battery power when it is turned on. However, due to the special architecture of the circuit, when the transistor (switch) Q _i when turned off, the inductor current will flow into the other battery; i.e., each cell may obtain additional boost converter transistor (switch) Q _i is turned off The amount of electricity that came from the time. Therefore, when calculating the discharge capacity of individual batteries, in addition to considering the release power Q _d i _s of the boost converter itself, the power Q _ch transmitted by other boost converters should also be considered. The electric quantity Q _dis , Q _ch and the net electric quantity ΔQ _i released by the i-th battery can be expressed as the following equation:

If the equilibrium current is defined as the current that can be released by the battery and is obtained by the average value of equation (5), it will have different results depending on the voltage of other batteries. To reduce confusion and facilitate the definition of balancing current, the balancing current is defined as the current on the transistor (switch), ie Q _dis /T _s :

Based on the integrated equations (3) and (6), the required balance voltage can be calculated. The required inductance value.

In control, the most important task is to set the duty ratio of each boost converter transistor (switch). Please refer to Figure 11 for a flow chart for determining the conduction rate.

First, the voltage value of each battery is read (step SA1), and it is determined whether the voltage difference between the batteries (|Δ V | _max , which represents the maximum value of the voltage difference between the batteries) is less than a predetermined value δ (step SA2). If so, it means that the battery pack has reached equilibrium, so the operation of the balancing circuit is stopped (step SA6); if not, after the battery voltage is obtained, the relationship between the voltage and the battery SOC can be converted into the remaining capacity of the battery (step SA3). ). The conduction ratio required for each boost converter is calculated from the remaining power of each battery (step SA4); and the boost converter is operated for a balanced time T _eq with this conduction ratio (step SA5). Then, the boost converter is stopped for a short period of time T _vd (step SA7) to prepare to detect the battery voltage of the next timing, that is, return to step SA1.

Fig. 12 is a flow chart showing the calculation of the conduction ratio of the boost converter.

Since the battery power is passed on to each other, the calculation of the turn-on rate of each boost converter is related to other boost converters. The whole calculation process is a process of iterative operation, starting with an initial guess (step SB1), and then determining the gap between the two iterations by the function of each conduction rate and other conductivity (step SB2). Whether it is within a preset value ε (step SB3), if so, the calculation is stopped; if not, the process returns to step SB1. Thereby, the iterative operation is repeated several times until the gap resolution of the two iterations is within a preset value ε.

In terms of the implementation circuit, the main circuit, the control and drive circuit, the power supply circuit, the overall circuit, and the voltage detection circuit are described.

Figure 13 is a circuit diagram showing the main circuit block in the actual circuit.

The main circuit includes two parts: an inner layer circuit ICE and an outer layer circuit OCE; the inner layer circuit ICE includes four boost converters (inductors L ₁ to L ₄ , transistors (switches) Q ₁ to Q ₄ , and two poles The body D ₁ ~ D ₄ ), the outer layer circuit OCE includes a capacitor C _outside and two transistors (switches) Q ₆ and Q ₇ , and B ₁ ~ B ₄ represent the battery. The outer circuit OCE is connected as shown in Figure 14, which connects the outer circuits in series through two 2-pin power sockets (CON1 and CON2) on each board.

Figure 15 is a circuit diagram showing the control and drive circuit.

Referring to FIG. 15, the control and drive circuit block includes a dsPIC chip controller and a MOSFET drive circuit composed of a PC923. In addition to driving the four transistors (switches) Q ₁ to Q _{4 of the} inner layer circuit ICE and the two transistors (switches) Q ₆ and Q ₇ of the outer layer circuit ICE, the driving circuit is also used for the power transformer. Transistor (switch) (not shown).

Fig. 16 is a circuit diagram showing a power supply circuit.

Please refer to FIG. 16 , since both the single-chip controller and the PC 923 driving circuit require power, and the driving power supply has multiple groups and is not commonly grounded. Therefore, multiple sets of ungrounded power supplies need to be provided via transformers (T1 and T2). Since the number of secondary windings is large, it is divided into two identical transformers and used in parallel before requiring a smaller transformer core volume. The primary side of the transformer is connected to the four strings of batteries B ₁ ~ B ₄ , and the battery pack provides the circuit power, as shown in FIG. 16 . The supply voltage is switched via a MOSFET switch, supplying energy to a plurality of subsequent flyback converters, providing multiple sets of isolated power supplies. In addition, since the dsPIC chip controller and the transistor (switch) Q ₅ drive circuit require an initial power supply to start the operation of the flyback converter at startup, the battery pack is first connected to resistors R12 and R13 to line 13 and point 5, respectively. To provide initial power. (where line represents the connecting wire, point represents the connecting end point, and the numbers or texts at the respective rears indicate the serial number or code number respectively)

Figure 17 is a waveform diagram showing the driving signals and the pole currents of the converters to which the third and fourth batteries are connected in a circuit board.

Referring to FIG. 17, since the voltage of the fourth battery B ₄ is high, that is, its SOC (State of Charge) is large, the duty ratio of the converter is large. Therefore, the converter has a large inductor current, so that the fourth battery B ₄ releases more power.

Figure 18 is a graph showing the results of balancing a single circuit board with four batteries.

Referring to FIG. 18, initially, the respective battery voltages are 3.794V, 3.828V, 3.883V, and 4.001V, respectively; the maximum difference between battery voltages is 207mV. After 268 minutes, the battery voltage became 3.807V, 3.859V, 3.841V, and 3.852V; the difference between the battery voltages became 44mV.

Figure 19 is a graph showing the results of balancing four batteries with respect to another single circuit board of Figure 18.

Referring to FIG. 19, initially, the battery voltages are 3.667V, 3.797V, 3.829V, and 4.096V, respectively, and the maximum difference between battery voltages is 418mV. And after 268 After a minute, the battery voltage becomes 3.760V, 3.807V, 3.764V, and 3.784V, and the difference between the battery voltages becomes 47mV, and the difference can be reduced to less than 50mV to achieve the balance of power.

The above description of the embodiments is intended to be illustrative of the present invention and is not intended to limit the present invention, so any change in the value or substitution of equivalent elements should still fall within the scope of the present invention.

From the above detailed description, it will be apparent to those skilled in the art that the present invention can achieve the aforementioned objectives, and has been in compliance with the provisions of the Patent Law, and has filed a patent application.

ICE‧‧‧ Inner layer cell balancing circuit

OCE‧‧‧Outer cell balance circuit

MB ₁ ~MB ₄ ‧‧‧Battery Pack

Claims (6)

An active battery balancing circuit structure for an electric vehicle battery pack, comprising: an inner layer electric quantity balancing circuit electrically connected with a plurality of batteries; and an outer layer electric quantity balancing circuit and the inner layer electric quantity balancing circuit on a circuit board The power is connected; thereby, the excess power of one of the batteries is discharged to the other battery through the inner layer balancing circuit and the outer layer balancing circuit. According to the active battery balancing circuit structure of the electric vehicle battery pack according to claim 1, wherein the inner layer balancing electric system is composed of a plurality of buck-boost converters, each group The boost converter includes a diode, a transistor, and an inductor, and each battery is connected to a corresponding one of the boost converters. The active cell balancing circuit structure of the electric vehicle battery pack according to claim 2, wherein the boost converter is operated in a continuous conduction mode (CCM). The active cell balancing circuit structure of the electric vehicle battery pack according to claim 2, wherein one of the transistors Q _{1 is} in a conducting state, and the electric quantity is connected to the battery of the transistor Q ₁ B _{1 is} taken out and stored on the inductor L ₁ connected to the transistor Q ₁ ; and when the transistor Q _{1 is} in the off state, the amount of electricity is distributed by the inductor L ₁ through the corresponding diode D ₁ to the other battery. The active cell balancing circuit structure of the electric vehicle battery pack according to claim 2, wherein the outer cell balancing circuit OCE comprises a plurality of sets of anti-parallel transistors (switches) and a plurality of capacitors, each of the battery systems The input ends of the transistors (switches) connected in anti-parallel with one of the corresponding groups are electrically connected, and the output ends of the adjacent two groups of anti-parallel transistors (switches) are electrically connected to the two ends of one of the capacitors respectively Sexual connection, the number of such capacitors is less than the number of such anti-parallel transistors (switches), the number of phase differences is one, and the number of modified batteries is the same as the reverse parallel transistors (switches The number of groups is the same. The active cell balancing circuit structure of the electric vehicle battery pack according to claim 5, wherein the transistor (switch) is a BJT or a MOSFET.