TW201442247A - Thin film transistor array substrate and method for manufacturing the same - Google Patents

Abstract

A thin film transistor and a method for manufacturing the same are provided. The thin film transistor includes a substrate, an insulating layer, a power line, a data line and an initialization power line, a planarization layer and a pixel electrode. The insulating layer is formed on the substrate. The power line, the data line and the initialization power line are formed on the insulating layer. The planarization layer covers the power line, the data line and the initialization power line. The pixel electrode is formed on the planarization layer. The initialization power line and the data line are made of a same metal layer, and the initialization power line is not in a layer where the pixel electrode is disposed so as not to occupy a wiring space of the pixel electrode. Therefore, a pixel area can be maximized to increase an aperture ratio thereof and an effective light emitting area, such that product performance can be enhanced.

Description

Thin film transistor array substrate and manufacturing method thereof

The present invention relates to a thin film transistor array substrate and a method of fabricating the same.

The organic electroluminescent diode (OLED) display technology is different from the traditional LCD display mode, and has self-luminous characteristics, which can be made lighter and thinner, has a larger viewing angle, and has more vivid colors, and has the advantages that the LCD is incomparable. In recent years, OLED applications have become more widespread.

As shown in FIG. 1, a conventional thin film transistor array substrate for driving an organic light emitting diode includes a scan driving unit 11, a data line driving unit 12, and a plurality of pixels 13. Each of the pixel units 13 corresponds to an initialization power line 14. The initialization power line 14 is arranged in parallel with the scan line 15 and the illumination control line 16 (E1 to En). The initialization power line 14 is arranged vertically with the data line 17 and the power line 18. In the peripheral circuit, the initialization power line 14 and the cathode metal 19 are connected and grounded.

As shown in FIG. 2, the initialization power supply line 14 and the pixel electrode 21 are the same layer of metal, and the initialization power supply line 14 and the source of the sixth thin film transistor T6 are connected through the contact hole 20.

As shown in FIG. 3, the circuit connection of the initializing power supply line 14 and the sixth thin film transistor T6 is to first etch the first insulating layer 24a and the second insulating layer 24b of the semiconductor layer 23 deposited on the substrate 22, such as a low temperature polysilicon layer. A hole is then deposited with a metal layer 25, which is in the same layer as the data line 17 (see FIG. 2) and the power line 18, and then a planarization layer 26 is deposited on the metal layer 25 and is patterned in the planarization layer 26. The contact hole is etched, and finally, the pixel electrode 27 is deposited and photolithographically formed to form the initialization power supply line 14 and the pixel electrode 21 shown in FIG.

In the above conventional thin film transistor array, the initialization power supply line 14 and the pixel electrode 21 are the same layer of metal, and the pattern is formed by the same photolithography process. The main problem is that since the initialization power supply line 14 and the pixel electrode 21 are the same layer metal, The arrangement and area of the pixel electrodes 21 on the array substrate are limited, that is, the aperture ratio of the pixels is reduced; and the evaporation of the three materials of red, green and blue in the direction perpendicular to the initialization of the power supply line 14 is also limited, the product The brightness of the light is not maximized. At the same time, the structure of the contact hole 20 in the pixel is complicated, and the three-lithography process is required to realize the electrical connection. Since the hole size in the pixel is small, the pixel electrode 27 and the semiconductor are in poor contact. The problem affects the yield of the product.

An object of the present invention is to provide a thin film transistor array substrate having a high pixel aperture ratio and a method of fabricating the same to solve the problems in the prior art.

To achieve the above object, the present invention adopts the following technical solutions: The present invention provides a thin film transistor array substrate comprising a substrate, an insulating layer, a power supply line, a data line and an initialization power supply line, a planarization layer, and a pixel electrode. An insulating layer is formed on the substrate; a power line, a data line, and an initialization power line are formed on the insulating layer; a planarization layer covers the power line, the data line, and an initialization power line; and a pixel electrode is formed on the planarization layer .

According to an embodiment of the present invention, the thin film transistor array substrate further includes: a plurality of scan lines, a plurality of light emission control lines, a scan line driving unit, a data line driving unit, a first switching film transistor, and a second driving film a crystal, a first storage capacitor, a second storage capacitor, a third switching thin film transistor, a fourth switching thin film transistor, a fifth switching thin film transistor, and a sixth thin film transistor. The scan line driving unit is configured to provide a scan signal to the scan line, and provide an illumination control signal to the illumination control line; the data line drive unit is configured to provide a data signal to the data line; the source of the first switch film transistor is connected to the data line, Writing a control signal line signal; a source of the second driving thin film transistor is connected to a drain of the first switching thin film transistor; and a first storage capacitor is connected between the gate of the second driving thin film transistor and the power line; The second storage capacitor is connected between one of the gate and the scan line of the second driving film transistor; the source of the third switching film transistor is connected to the power line, and the gate is connected to one of the light-emitting control lines; The drain of the fourth switching thin film transistor is connected to the organic light emitting diode, the source is connected to the drain of the second driving thin film transistor; the source of the fifth switching thin film transistor and the gate of the second driving thin film transistor a pole connection for compensating for a threshold voltage change of the driving thin film transistor; a source of the sixth thin film transistor is connected with an initial power supply line for The gate voltage of the second driving thin film transistor is initialized.

According to an embodiment of the invention, the thin film transistor array substrate further comprises a semiconductor layer under the insulating layer.

According to an embodiment of the invention, a contact hole is formed in the insulating layer, and the initialization power line is electrically connected to the semiconductor layer through the contact hole.

According to an embodiment of the invention, the initialization power line is disposed in parallel with the data line.

According to an embodiment of the invention, the insulating layer comprises a first insulating layer made of yttrium oxide and a second insulating layer made of tantalum nitride on the first insulating layer.

According to an embodiment of the invention, the semiconductor layer is a low temperature polysilicon layer.

The invention provides a method for manufacturing a thin film transistor array substrate, comprising the steps of: step S1: providing a substrate; step S2: forming a semiconductor layer on the substrate; step S3: forming an insulating layer on the semiconductor; step S4: insulating A contact hole is formed in the layer; step S5: forming a power supply line, a data line, and an initialization power supply line on the insulating layer; step S6: forming a planarization layer on the resultant structure; and step S7: forming a pixel electrode on the planarization layer.

According to an embodiment of the invention, in the step S2, the semiconductor layer is formed by a magnetron sputtering process or a vapor deposition process or an evaporation process.

According to an embodiment of the invention, in the step S3, an insulating layer is formed on the semiconductor layer by a PECVD process or a spin coating process.

According to an embodiment of the invention, in the step S4, the contact hole is formed by a photolithography and etching process.

According to an embodiment of the invention, the initialization power line is electrically connected to the semiconductor layer through the contact hole.

According to an embodiment of the present invention, in the step S3, the insulating layer comprises a first insulating layer formed of yttrium oxide and a second insulating layer formed of tantalum nitride, after first forming a first insulating layer on the semiconductor And forming a second insulating layer on the first insulating layer.

According to an embodiment of the present invention, the forming a power line, a data line, and an initial power line on the insulating layer includes: forming a metal layer on the insulating layer; forming a mask pattern on the metal layer; using the mask pattern Etching the metal layer to form the power line, the data line, and the initialization power line.

According to an embodiment of the invention, the power line, the data line, and the initialization power line are formed by an etching process.

It can be seen from the above technical solutions that the advantages and positive effects of the present invention are: initializing the power line and the data line as the same metal layer, and initializing the power line not in the layer where the pixel electrode is located, so the initialization power line does not occupy the wiring space of the pixel electrode, and the pixel The area can be maximized, thereby greatly increasing the pixel aperture ratio, thereby increasing the effective light-emitting area and improving product performance.

The above and other objects, features and advantages of the present invention will become apparent from

11‧‧‧Scan Drive Unit

12‧‧‧Data line drive unit

13‧‧‧ pixels

14‧‧‧Initialize the power cord

15‧‧‧ scan line

16‧‧‧Lighting control line

17‧‧‧Data line

18‧‧‧Power cord

19‧‧‧Cathode metal

20‧‧‧Contact hole

21‧‧‧pixel electrode

22‧‧‧Substrate

23‧‧‧Semiconductor layer

24a‧‧‧first insulation

24b‧‧‧Second insulation

25‧‧‧metal layer

26‧‧‧Destivation layer

27‧‧‧pixel electrode

7‧‧‧ source electrode

8‧‧‧汲 electrode

9‧‧‧ Third organic layer

1 is a schematic structural view of a conventional thin film transistor array substrate; FIG. 2 is a plan view of a single pixel in a conventional thin film transistor array substrate; and FIG. 3 is an initial power supply line and a sixth thin film power in the conventional thin film transistor array substrate. 4 is a schematic structural view of a thin film transistor array substrate of the present invention; FIG. 5A is a plan view of a single pixel in the thin film transistor array of the present invention; and FIG. 5B is a thin film transistor of the present invention; FIG. 6 is a schematic structural view of a source contact hole of an initializing power supply line and a sixth thin film transistor in the thin film transistor array substrate of the present invention; FIG. 7 is a thin film transistor array substrate of the present invention; FIG. 8 is a cross-sectional view showing a peripheral connection structure in the thin film transistor array substrate of the present invention.

Specific embodiments of the present invention will be described in detail below. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the invention.

Thin film transistor array substrate

As shown in FIG. 4, the thin film transistor array substrate for driving an organic light emitting diode of the present invention comprises a substrate 22, and an insulation formed on the substrate 22 The layer, the power line 18, the data line 17 and the initialization power line 14 formed on the insulating layer cover the power line 18, the data line 17 and the planarization layer 26 of the initialization power line 14, and the pixels formed on the planarization layer 26. electrode.

Further, the thin film transistor array substrate of the present invention further includes a scan line driving unit 11, a data line driving unit 12, and a plurality of pixels 13.

The scanning line driving unit 11 includes a gate driving unit that supplies a driving signal to the scanning line 15, and an emission control unit that supplies an emission control signal to the emission control lines 16 (E1 to En). The scanning line 15 (G1~Gn) is a double-side driving, and the lighting control line 16 (E1~En) is divided into an odd-even one-side driving. The data line driving unit 12 supplies the data lines 17 (D1 to Dn) with analog or digital signals for controlling the gray scale of the thin film transistor. Each of the power supply lines 18 is connected together in a peripheral circuit to supply a power source ELVDD. The pixel unit 13 is distributed at a vertical intersection of the scanning lines 15 (G1 to Gn), the light emission control lines 16 (E1 to En), the initialization power supply line 14, the data line 17, and the power supply line 18.

In the present invention, the initialization power supply line 14 and the data lines 17 (D1 to Dn) are arranged in parallel and arranged perpendicularly to the scanning line 15, which is advantageous in that the initialization power supply line 14 and the pixel electrode 21 (see FIG. 5A) are not in the same layer, FIG. 5A The pattern of the pixel electrode 21 can be randomly arranged, and the aperture ratio of the pixel 13 is the largest, and the brightness and life of the product are effectively improved without increasing the number of photolithography.

See Figures 5A and 5B. Each of the pixel units 13 includes a first switching thin film transistor T1, a second driving thin film transistor T2, a first storage capacitor C1, a second storage capacitor C2, a third switching thin film transistor T3, and a fourth switching thin film transistor T4. The fifth switching film transistor T5 and the sixth film transistor T6.

The source of the first switching thin film transistor T1 is connected to the data line 17 for controlling the signal writing of the data line 17.

The source of the second driving thin film transistor T2 is connected to the drain of the first switching thin film transistor T1 for controlling the luminous intensity.

The first storage capacitor C1 is connected between the gate of the second driving thin film transistor T2 and the power supply line 18. The first storage capacitor C1 functions to maintain the gate of the second driving thin film transistor T2 during the organic electroluminescence. The pole voltage is constant. The second storage capacitor C2 is connected between the gate of the second driving thin film transistor T2 and the scan line.

The source of the third switching thin film transistor T3 is connected to the power supply line 18 for controlling the power line 18 switch.

The drain of the fourth switching thin film transistor T4 is connected to the organic light emitting diode, and the source thereof is connected to the drain of the second driving thin film transistor T2 for controlling the organic light emitting diode to emit light.

The source of the fifth switching thin film transistor T5 is connected to the gate of the second driving thin film transistor T2 for compensating for the threshold voltage variation of the driving thin film transistor.

The source of the sixth thin film transistor T6 is connected to the initialization power supply line 14 for initializing the gate voltage of the second driving thin film transistor T2.

As shown in FIG. 7, the gate line corresponding to the gate of the sixth thin film transistor T6 is the scan line of the pixel of the previous row, wherein the initialization power line 14 and the cathode 19 are connected together in the peripheral loop and then connected to the ELVSS. For example, as shown in FIG. 8, the planarization layer 26 on the data line metal layer 25 is removed, After that, the cathode metal 28 is directly vapor-deposited, and the initializing power supply line and the cathode ELVSS are directly connected, and finally led out to the flexible printed circuit board (FPC) and the peripheral driving circuit.

In the present invention, the wiring direction of the initialization power supply line 14 of the sixth thin film transistor T6 is parallel to the data line 17 and the power supply line 18, and the same metal layer is used for the data line 17. The initialization power supply line 14 is connected to the source of the thin film transistor T6 through the contact hole 20.

In the effective display area, the metal layer 25 is directly used as the Vint line, and the Vint line is taken out of the effective display area, and then the contact hole 20 is etched on the metal layer 25, and the pixel electrode 27 and the metal layer 25 are contacted to be connected to the peripheral circuit. Since the hole outside the effective display area is larger than the size of the hole in the display area, the process is easily controlled, and the upper metal 27 and the semiconductor layer 23 are easily contacted.

In the present invention, the initialization power line 14 and the data line 17 are the same metal layer, and the initialization power line 14 does not occupy the wiring space of the pixel electrode 21, so the pixel area can be maximized, thereby improving the effective light-emitting area and improving product performance. To increase market competitiveness.

Method for manufacturing thin film transistor array substrate

As shown in FIG. 6 , the manufacturing method of the thin film transistor array substrate of the present invention comprises the following steps:

Step S1: A glass substrate 22 is provided.

Step S2: forming a semiconductor layer 23 on the glass substrate 22 through a magnetron sputtering process or a vapor deposition process or an evaporation process, such as a low temperature polysilicon layer, and the semiconductor material at the semiconductor layer 23 and the thin film transistor channel are the same layer.

Step S3: After the first insulating layer 24a is formed on the semiconductor layer 23 by a PECVD process or a spin coating process, a second insulating layer 24b is formed on the first insulating layer 24a. The first insulating layer 24a is between the semiconductor layer 23 and the scanning line 15 shown in FIG. 5A, and the second insulating layer 24b is insulated between the scanning line 15 and the data line 17 shown in FIG. 5A. The material of the first insulating layer 24a may be, for example, yttrium oxide, and the material of the second insulating layer 24b may be, for example, tantalum nitride.

Step S4: The contact hole 20 is formed by a process such as photolithography or etching in the first insulating layer 24a and the second insulating layer 24b.

Step S5: The data line 17, the power supply line 18, and the initialization power supply line 14 are formed on the first insulating layer 24a and the second insulating layer 24b. Further, in the step S5, the metal layer 25 may be deposited on the second insulating layer 24b, the reticle pattern is formed on the metal layer 25, and the metal layer 25 is etched by the reticle pattern to form the power line 18 and the data. Line 17 and initialization power line 14. Further, the power line 18, the data line 17, and the initialization power line 14 are formed by an etching process. Therefore, in the present invention, the data line 17, the power supply line 18, and the initialization power supply line 14 are the same layer of metal.

Step S6: Next, a planarization layer 26 is deposited. The main purpose of this planarization layer 26 is to eliminate the unevenness of the pixel light-emitting area caused by the variation of the underlying pattern.

Step S7: Finally, after the pixel electrode 27 is formed on the planarization layer 26, the process related to the array process is completed.

In the method for manufacturing a thin film transistor array substrate of the present invention, The main advantage of drawing the initialization power supply line 14 in the pixel shown in FIG. 5A according to the line material, that is, the metal layer 25, is that the number of lithography times of the contact hole 20 in the pixel is reduced, and the pixel initialization power supply line 14 shown in FIG. 5A can be effectively prevented. Poor contact with the underlying semiconductor material.

Through the above description, the present invention can improve product yield and performance without increasing the number of lithography.

In the above description, many specific details are set forth in order to provide a sufficient understanding of the present invention. The present invention is not limited by the specific embodiments disclosed above. The drawings used in the present invention are not to be construed as being Amplification; Finally, the thin film transistor array substrate mentioned in the present invention includes, but is not limited to, a low temperature polycrystalline germanium thin film transistor array substrate.

While the invention has been described with respect to the exemplary embodiments illustrated embodiments The present invention may be embodied in a variety of forms without departing from the spirit and scope of the invention. It is to be understood that the above-described embodiments are not limited to the details of the foregoing, but are construed broadly within the spirit and scope of the appended claims. All changes and modifications that fall within the scope of the claims or their equivalents should therefore be covered by the accompanying claims.

11‧‧‧Scan Drive Unit

12‧‧‧Data line drive unit

13‧‧‧ pixels

14‧‧‧Initialize the power cord

15‧‧‧ scan line

16‧‧‧Lighting control line

17‧‧‧Data line

18‧‧‧Power cord

19‧‧‧Cathode metal

Claims (15)

A thin film transistor array substrate comprising: a substrate; an insulating layer formed on the substrate; a power line, a data line and an initialization power line formed on the insulating layer; a planarization layer covering the power line and the data line And the initialization power line; and the pixel electrode are formed on the planarization layer. The thin film transistor array substrate of claim 1, further comprising: a plurality of scan lines; a plurality of light emission control lines; and a scan line driving unit, configured to provide scan signals to the scan lines, and provide the scan lines to the light control lines a light-emitting control signal; a data line driving unit for providing a data signal to the data line; a first switching thin film transistor having a source connected to the data line for controlling data line signal writing; and a second driving thin film transistor The source is connected to the drain of the first switching thin film transistor; the first storage capacitor is connected between the gate of the second driving thin film transistor and the power line; and the second storage capacitor is connected to the first a second driving thin film transistor between the gate and one of the scan lines; a third switching thin film transistor having a source connected to the power line and a gate connected to one of the light emitting control lines ; a fourth switching thin film transistor, the drain of which is connected to the organic light emitting diode, the source of which is connected to the drain of the second driving thin film transistor; the fifth switching thin film transistor, the source thereof and the second driving film The gate of the transistor is connected to compensate for a threshold voltage change of the driving film transistor; the sixth thin film transistor has a source connected to the initializing power line for the gate voltage of the second driving thin film transistor Initialize. The thin film transistor array substrate of claim 1, further comprising a semiconductor layer under the insulating layer. The thin film transistor array substrate of claim 3, wherein a contact hole is formed in the insulating layer, and the initialization power supply line is electrically connected to the semiconductor layer through the contact hole. The thin film transistor array substrate of claim 1, wherein the initialization power supply line is disposed in parallel with the data line. The thin film transistor array substrate of claim 1, wherein the insulating layer comprises a first insulating layer made of yttrium oxide and a second insulating layer made of tantalum nitride on the first insulating layer. The thin film transistor array substrate of claim 3, wherein the semiconductor layer is a low temperature polysilicon layer. A method for manufacturing a thin film transistor array substrate, comprising the steps of: Step S1: providing a substrate; step S2: forming a semiconductor layer on the substrate; step S3: forming an insulating layer on the semiconductor; step S4: forming a contact hole in the insulating layer; step S5: on the insulating layer Forming a power supply line, a data line, and an initialization power supply line; Step S6: forming a planarization layer on the resultant structure; Step S7: forming a pixel electrode on the planarization layer. The manufacturing method according to claim 8, wherein in the step S2, the semiconductor layer is formed by a magnetron sputtering process or a vapor deposition process or an evaporation process. The manufacturing method according to claim 8, wherein in the step S3, the insulating layer is formed on the semiconductor layer by a PECVD process or a spin coating process. The manufacturing method according to claim 8, wherein in the step S4, the contact hole is formed by a photolithography and etching process. The manufacturing method according to claim 8, wherein the initialization power supply line is electrically connected to the semiconductor layer through the contact hole. The manufacturing method according to claim 8, wherein in the step S3, the insulating layer comprises a first insulating layer formed of yttrium oxide and a tantalum nitride And forming a second insulating layer, after forming the first insulating layer on the semiconductor layer, and then forming the second insulating layer on the first insulating layer. The manufacturing method of claim 8, wherein the forming the power line, the data line, and the initializing power line on the insulating layer comprises: forming a metal layer on the insulating layer; forming a mask pattern on the metal layer; The metal layer is etched using the mask pattern to form the power line, the data line, and the initialization power line. The manufacturing method of claim 14, wherein the power line, the data line, and the initialization power line are formed by an etching process.