CN103199096B - Thin film transistor array substrate and manufacturing method thereof - Google Patents
Thin film transistor array substrate and manufacturing method thereof Download PDFInfo
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- CN103199096B CN103199096B CN201310136120.XA CN201310136120A CN103199096B CN 103199096 B CN103199096 B CN 103199096B CN 201310136120 A CN201310136120 A CN 201310136120A CN 103199096 B CN103199096 B CN 103199096B
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Abstract
The invention provides a thin film transistor array substrate and a manufacturing method thereof. The thin film transistor array substrate comprises a substrate, an insulating layer, a power line, a data line, an initialized power line, a planarization layer and a pixel electrode, wherein the insulating layer is formed on the substrate; the power line, the data line and the initialized power line are all formed on the insulating layer; the planarization layer is covered on the power line, the data line and the initialized power line; and the pixel electrode is formed on the planarization layer. According to the invention, the initialized power line and the data line are on the same metal layer, while the initialized power line is not on the layer on which the pixel electrode is located, so that the initialized power line does not occupy the lining space of the pixel electrode, the pixel area can be maximized, thus the pixel aperture opening ratio can be improved greatly, the effective light-emitting area can be improved and the product performance can be improved.
Description
Technical field
The present invention relates to a kind of thin-film transistor array base-plate and manufacture method thereof.
Background technology
Organic electroluminescent LED (OLED) Display Technique is different from traditional LCD display mode, has self luminous characteristic, can do lighter and thinner, visible angle is larger, color is more bright-coloured, has the advantage that LCD is incomparable, and OLED application is in recent years more and more extensive.
As shown in Figure 1, the thin-film transistor array base-plate of existing driving Organic Light Emitting Diode, comprises scan drive cell 11, data line drive unit 12 and multiple pixel 13.The wherein corresponding initialize power line 14 of each pixel cell 13.Initialize power line 14 and scan line 15, light emitting control line 16 (E1 ~ En) are all arranged in parallel.Initialize power line 14 is arranged vertically with data wire 17 and power line 18.In peripheral circuit, initialize power line 14 is connected rear ground connection with cathodic metal 19.
As shown in Figure 2, initialize power line 14 and pixel electrode 21 are same layer metal, and initialize power line 14 and the source electrode of the 6th thin-film transistor T6 are connected by contact hole 20.
As shown in Figure 3, it is first the first insulating barrier 24a of semiconductor layer 23 such as low-temperature polycrystalline silicon layer and the second insulating barrier 24b that are deposited on substrate 22 are carved a hole that initialize power line 14 is connected with the circuit of the 6th thin-film transistor T6, then depositing metal layers 25 again, metal level 25 is same layer metal with data wire 17 (see Fig. 2) and power line 18, then deposited planarization layer 26 on metal level 25, and etching contact hole at planarization layer 26, after last pixel deposition electrode 27, photoetching forms the initialize power line 14 shown in Fig. 2 and pixel electrode 21.
In above-mentioned traditional thin film transistor (TFT) array, initialize power line 14 and pixel electrode 21 are same layer metal, pattern is formed with a photoetching process, there is following subject matter: because initialize power line 14 and pixel electrode 21 are with layer metal, limit the arrangement mode of pixel electrode 21 on array base palte and area, namely reduce the aperture opening ratio of pixel; And the evaporation of red, green, blue three kinds of materials is also restricted on the direction vertical with initialize power line 14, the luminosity of product can not maximize; Meanwhile, the complex structure of the contact hole 20 in pixel, carry out third photo etching technique and could realize being electrically connected, because the hole dimension in pixel is less, so easily have pixel electrode 27 and the bad problem of semiconductor contact, affects the yield of product.
Summary of the invention
One object of the present invention is to provide the thin-film transistor array base-plate and manufacture method thereof that a kind of pixel aperture ratio is high, to solve the problems of the prior art.
For achieving the above object, the present invention adopts following technical scheme:
The invention provides a kind of thin-film transistor array base-plate, comprise substrate, insulating barrier, power line, data wire and initialize power line, planarization layer and pixel electrode.Insulating barrier is formed on described substrate; Power line, data wire and initialize power line are all formed on described insulating barrier; Planarization layer covers described power line, data wire and initialize power line; Pixel electrode is formed on described planarization layer.
According to an embodiment of the present invention, described thin-film transistor array base-plate also comprises: multi-strip scanning line, many articles of light emitting control lines, scanning line driving unit, data line drive unit, the first switching thin-film transistors, second drive thin-film transistor, the first storage capacitance, the second storage capacitance, the 3rd switching thin-film transistor, the 4th switching thin-film transistor, the 5th switching thin-film transistor and the 6th thin-film transistor.Scanning line driving unit is used for providing sweep signal to scan line, provides LED control signal to light emitting control line; Data line drive unit is used for providing data-signal to data wire; The source electrode of the first switching thin-film transistor is connected with data wire, writes for control data line signal; Second drives the source electrode of thin-film transistor to be connected with the drain electrode of the first transistor; Between the grid that first storage capacitance is connected to the second driving thin-film transistor and power line; Between the grid that second storage capacitance is connected to the second driving thin-film transistor and scan line; The source electrode of the 3rd switching thin-film transistor is connected with power line, and grid connects light emitting control line; The drain electrode of the 4th switching thin-film transistor is connected with Organic Light Emitting Diode, and its source electrode and second drives the drain electrode of thin-film transistor to be connected; The source electrode and second of the 5th switching thin-film transistor drives the grid of thin-film transistor to be connected, and drives thin-film transistor threshold voltage variation for compensating; The source electrode of the 6th thin-film transistor is connected with initialize power line, for driving the grid voltage of thin-film transistor to carry out initialization to second.
According to an embodiment of the present invention, described thin-film transistor array base-plate also comprises the semiconductor layer be positioned at below described insulating barrier.
According to an embodiment of the present invention, be formed with contact hole in wherein said insulating barrier, described initialize power line is electrically connected with described semiconductor layer by described contact hole.
According to an embodiment of the present invention, described initialize power line and described data wire are arranged in parallel.
According to an embodiment of the present invention, described insulating barrier comprises the first insulating barrier of being made up of silica and is positioned at the second insulating barrier that the first insulating barrier is made up of silicon nitride.
According to an embodiment of the present invention, wherein said semiconductor layer is low-temperature polycrystalline silicon layer.
The invention provides a kind of manufacture method of thin-film transistor array base-plate, comprise the steps:
Step S1 a: substrate is provided;
Step S2: form semi-conductor layer on substrate;
Step S3: form insulating barrier on the semiconductor;
Step S4: form contact hole in a insulating layer;
Step S5: form power line, data wire and initialize power line on described insulating barrier;
Step S6: form planarization layer on resulting structures;
Step S7: form pixel electrode on planarization layer.
According to an embodiment of the present invention, wherein, in described step S2, described semiconductor layer is formed by magnetron sputtering technique or gas-phase deposition or evaporation process.
According to an embodiment of the present invention, wherein, in described step S3, pecvd process or spin coating proceeding is adopted to prepare insulating barrier on the semiconductor layer.
According to an embodiment of the present invention, wherein, in described step S4, described contact hole is formed with photoetching and etch process.
According to an embodiment of the present invention, wherein, described initialize power line is electrically connected with described semiconductor layer by described contact hole.
According to an embodiment of the present invention, wherein, in described step S3, insulating barrier comprises the first insulating barrier formed by silica and the second insulating barrier formed by silicon nitride, after first first forming the first insulating barrier on the semiconductor, then form the second insulating barrier on the first insulating barrier.
According to an embodiment of the present invention, on described insulating barrier, wherein form power line, data wire and initialize power line to comprise:
Described insulating barrier forms metal level;
Described metal level forms mask pattern;
Utilize described mask pattern, etch described metal level, form described power line, data wire and initialize power line.
According to an embodiment of the present invention, wherein said power line, data wire and initialize power line are formed by an etch process.
From technique scheme, advantage of the present invention and good effect are: initialize power line and data wire are same layer metal level, initialize power line is not at the layer at pixel electrode place, therefore initialize power line does not occupy the wiring space of pixel electrode, elemental area can be accomplished to maximize, thus increase substantially pixel aperture ratio, thus improve effective light-emitting area, improving product performance.
By referring to accompanying drawing description of a preferred embodiment, above-mentioned and other objects, features and advantages of the present invention will be more obvious.
Accompanying drawing explanation
Fig. 1 is the structural representation of existing thin-film transistor array base-plate;
Fig. 2 is the plane graph of single pixel in existing thin-film transistor array base-plate;
Fig. 3 is the structural representation of the source contact openings of initialize power line in existing thin-film transistor array base-plate and the 6th thin-film transistor;
Fig. 4 is the structural representation of thin-film transistor array base-plate of the present invention;
Fig. 5 A is the plane graph of single pixel in thin film transistor (TFT) array of the present invention;
Fig. 5 B is the pixel-driving circuit figure in thin film transistor (TFT) array of the present invention;
Fig. 6 is the structural representation of the source contact openings of initialize power line in thin-film transistor array base-plate of the present invention and the 6th thin-film transistor;
Fig. 7 is the peripheral syndeton plane graph in thin-film transistor array base-plate of the present invention;
Fig. 8 is the peripheral syndeton profile in thin-film transistor array base-plate of the present invention.
Primary clustering description of reference numerals:
11: scan drive cell
12: data line drive unit
13: pixel
14: initialize power line
15: scan line
16: light emitting control line
17: data wire
18: power line
19: cathodic metal
20: contact hole
21: pixel electrode
22: substrate
23: semiconductor layer
24a: the first insulating barrier
24b: the second insulating barrier
25: metal level
26: planarization layer
27: pixel electrode
7: source electrode
8: drain electrode
9: the three organic layers
Embodiment
Specific embodiments of the invention will be described in detail below.It should be noted that the embodiments described herein is only for illustrating, is not limited to the present invention.
Thin-film transistor array base-plate
As shown in Figure 4, the thin-film transistor array base-plate of driving Organic Light Emitting Diode of the present invention, comprise substrate 22, be formed in the insulating barrier on described substrate 22, form power line 18, data wire 17 and initialize power line 14 on the insulating layer, cover the planarization layer 26 of power line 18, data wire 17 and initialize power line 14, and be formed in the pixel electrode on planarization layer 26.
Further, thin-film transistor array base-plate of the present invention also comprises scanning line driving unit 11, data line drive unit 12 and multiple pixel 13.
Scanning line driving unit 11 comprises to be provided the grid line driver element of drive singal to scan line 15 and provides the luminous luminous controling unit for signal processed to light emitting control line 16 (E1 ~ En).Wherein scan line 15 (G1 ~ Gn) is that bilateral drives, light emitting control line 16 (E1 ~ En) point one-sided driving of odd even.Data line drive unit 12 provides the analog or digital signal controlling thin-film transistor GTG to data wire 17 (D1 ~ Dn).Power supply ELVDD is provided after each power line 18 is connected together in peripheral loop.Pixel cell 13 is distributed in square crossing place of scan line 15 (G1 ~ Gn), light emitting control line 16 (E1 ~ En) and initialize power line 14, data wire 17, power line 18.
In the present invention, initialize power line 14 and data wire 17 (D1 ~ Dn) arranged in parallel, and with scan line 15 vertical arrangement, its advantage is that initialize power line 14 and pixel electrode 21 (see Fig. 5 A) be not at same layer, in Fig. 5 A, the figure of pixel electrode 21 can arbitrarily arrange, the aperture opening ratio of pixel 13 is maximum, and under the prerequisite not increasing photoetching number of times, brightness and the life-span of product effectively improve.
See Fig. 5 A and Fig. 5 B.Each pixel cell 13 comprises the first switching thin-film transistor T1, second and drives thin-film transistor T2, the first storage capacitance C1, the second storage capacitance C2, the 3rd switching thin-film transistor T3, the 4th switching thin-film transistor T4, the 5th switching thin-film transistor T5 and the 6th thin-film transistor T6.
The source electrode of the first switching thin-film transistor T1 is connected with data wire 17, writes for control data line 17 signal.
Second drives the source electrode of thin-film transistor T2 to be connected with the drain electrode of the first transistor T1, for controlling luminous intensity.
Between the grid that first storage capacitance C1 is connected to the second driving thin-film transistor T2 and power line 18, the effect of the first storage capacitance C1 is during organic electroluminescent, keeps the grid voltage of second driving thin-film transistor T2 invariable.Between the grid that second storage capacitance C2 is connected to the second driving thin-film transistor T2 and scan line.
The source electrode of the 3rd switching thin-film transistor T3 is connected with power line 18, for controlling power line 18 switch.
The drain electrode of the 4th switching thin-film transistor T4 is connected with Organic Light Emitting Diode, and its source electrode and second drives the drain electrode of thin-film transistor T2 to be connected, for controlling organic light-emitting diode.
The source electrode and second of the 5th switching thin-film transistor T5 drives the grid of thin-film transistor T2 to be connected, and drives thin-film transistor threshold voltage variation for compensating.
The source electrode of the 6th thin-film transistor T6 is connected with initialize power line 14, for driving the grid voltage of thin-film transistor T2 to carry out initialization to second.
As shown in Figure 7, the scan line 15 that the grid of the 6th thin-film transistor T6 is corresponding is the scan line of lastrow pixel, and wherein initialize power line 14 and negative electrode 19 receive ELVSS after linking together in peripheral loop.Such as, as shown in Figure 8, the planarization layer 26 on data wire metal layer 25 is removed, then direct evaporation cathodic metal 28, initialize power line is directly connected with negative electrode ELVSS, is finally drawn out to flexible printed circuit board (FPC) and is connected with peripheral drive circuit.
In the present invention, the wiring direction of the initialize power line 14 of the 6th thin-film transistor T6 is parallel with power line 18 with data wire 17, and with data wire 17 same layer metal level.Initialize power line 14 is linked together by contact hole 20 with the source electrode of thin-film transistor T6.
Directly use metal level 25 as Vint line in territory, effective display area, Vint line line is drawn out to outside effective display area, then on metal level 25, contact hole 20 is carved, pixel electrode 27 is contacted with metal level 25, be connected with peripheral circuit, because the size in the hole in the boring ratio viewing area that effective display area is overseas is large, technique easily controls, and upper strata metal 27 easily contacts with semiconductor layer 23.
In the present invention, initialize power line 14 and data wire 17 are same layer metal level, and initialize power line 14 does not occupy the wiring space of pixel electrode 21, so elemental area can be accomplished to maximize, thus improve effective light-emitting area, improving product performance, increase the market competitiveness.
The manufacture method of thin-film transistor array base-plate
As shown in Figure 6, the manufacture method of thin-film transistor array base-plate of the present invention comprises the steps:
Step S1 a: glass substrate 22 is provided.
Step S2: on glass substrate 22, form semiconductor layer 23, such as low-temperature polycrystalline silicon layer by magnetron sputtering technique or gas-phase deposition or evaporation process, the semi-conducting material at semiconductor layer 23 and thin film transistor channel place is same layer.
Step S3: after adopting pecvd process or spin coating proceeding first to form the first insulating barrier 24a on semiconductor layer 23, then form the second insulating barrier 24b on the first insulating barrier 24a.Wherein the first insulating barrier 24a is between the scan line 15 shown in semiconductor layer 23 and Fig. 5 A, and the second insulating barrier 24b plays insulating effect between the scan line 15 shown in Fig. 5 A and data wire 17.The material of the first insulating barrier 24a can be such as silica, and the material of the second insulating barrier 24b can be such as silicon nitride.
Contact hole 20 is formed by the technique such as photoetching or etching in step S4: the first insulating barrier 24a and the second insulating barrier 24b.
Step S5: form data wire 17, power line 18 and initialize power line 14 at the first insulating barrier 24a and the second insulating barrier 24b afterwards.Further, in this step S5, can first depositing metal layers 25 on the second insulating barrier 24b, metal level 25 forms mask pattern, utilizes mask pattern, etch this metal level 25, form described power line 18, data wire 17 and initialize power line 14.Further, described power line 18, data wire 17 and initialize power line 14 is formed by an etch process.Therefore, in the present invention, data wire 17, power line 18 and initialize power line 14 is same layer metal.
Step S6: then deposited planarization layer 26, the main purpose of this layer of planarization layer 26 is pixel light emission area out-of-flatnesses that the offset eliminating lower floor's figure causes.
Step S7: the last processing procedure completing array processes after formation pixel electrode 27 and be correlated with on planarization layer 26.
In the manufacture method of thin-film transistor array base-plate of the present invention, reduce with the photoetching number of times that the major advantage that the initialize power line 14 in the pixel shown in Fig. 5 A is drawn is contact hole 20 in pixel by data wire material and metal level 25, effectively can prevent the problem of the pixel initialize power line 14 shown in Fig. 5 A and underlying semiconductor material loose contact.
By above-mentioned explanation, the present invention, can improving product yield and performance under the prerequisite not increasing photoetching number of times.
Set forth a lot of concrete details in superincumbent description so that understand the present invention fully, the present invention is not subject to the restriction of disclosed specific embodiment above; Secondly the legend used in the present invention for convenience of explanation, is disobeyed general ratio and is done equal proportion amplification; The thin-film transistor array base-plate mentioned in last the present invention includes but not limited to low-temperature polysilicon film transistor array base palte.
Although exemplary embodiment describe the present invention with reference to several, should be appreciated that term used illustrates and exemplary and nonrestrictive term.Spirit or the essence of invention is not departed from because the present invention can specifically implement in a variety of forms, so be to be understood that, above-described embodiment is not limited to any aforesaid details, and explain widely in the spirit and scope that should limit in claim of enclosing, therefore fall into whole change in claim or its equivalent scope and remodeling and all should be claim of enclosing and contained.
Claims (6)
1. a thin-film transistor array base-plate, for driving Organic Light Emitting Diode, comprising:
Substrate;
Insulating barrier, is formed on described substrate;
Power line, data wire and initialize power line, be formed on described insulating barrier;
Planarization layer, covers described power line, data wire and initialize power line; And
Pixel electrode, is formed on described planarization layer;
Multi-strip scanning line;
Many light emitting control lines;
Scanning line driving unit, for providing sweep signal to scan line, provides LED control signal to light emitting control line;
Data line drive unit, for providing data-signal to data wire;
First switching thin-film transistor, its source electrode is connected with data wire, writes for control data line signal;
Second drives thin-film transistor, and its source electrode is connected with the drain electrode of the first switching thin-film transistor;
First storage capacitance, between the grid being connected to the second driving thin-film transistor and power line;
Second storage capacitance, between the grid being connected to the second driving thin-film transistor and scan line;
3rd switching thin-film transistor, its source electrode is connected with power line, and grid connects light emitting control line;
4th switching thin-film transistor, its drain electrode is connected with Organic Light Emitting Diode, and its source electrode and second drives the drain electrode of thin-film transistor to be connected;
5th switching thin-film transistor, its source electrode and second drives the grid of thin-film transistor to be connected, for compensating the second driving thin-film transistor threshold voltage variation;
6th thin-film transistor, its source electrode is connected with initialize power line, for driving the grid voltage of thin-film transistor to carry out initialization to second.
2. thin-film transistor array base-plate as claimed in claim 1, also comprises the semiconductor layer be positioned at below described insulating barrier.
3. thin-film transistor array base-plate as claimed in claim 2, is formed with contact hole in wherein said insulating barrier, and described initialize power line is electrically connected with described semiconductor layer by described contact hole.
4. thin-film transistor array base-plate as claimed in claim 1, wherein, described initialize power line and described data wire are arranged in parallel.
5. thin-film transistor array base-plate as claimed in claim 1, wherein, described insulating barrier comprises the first insulating barrier of being made up of silica and is positioned at the second insulating barrier that the first insulating barrier is made up of silicon nitride.
6. thin-film transistor array base-plate as claimed in claim 2, wherein said semiconductor layer is low-temperature polycrystalline silicon layer.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310136120.XA CN103199096B (en) | 2013-04-18 | 2013-04-18 | Thin film transistor array substrate and manufacturing method thereof |
| TW102115257A TWI518918B (en) | 2013-04-18 | 2013-04-29 | Thin film transistor array substrate and method for manufacturing the same |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310136120.XA CN103199096B (en) | 2013-04-18 | 2013-04-18 | Thin film transistor array substrate and manufacturing method thereof |
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| CN103199096A CN103199096A (en) | 2013-07-10 |
| CN103199096B true CN103199096B (en) | 2014-12-17 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104134424A (en) * | 2014-05-27 | 2014-11-05 | 四川虹视显示技术有限公司 | AMOLED (Active Matrix Organic Light Emitting Diode) pixel structure and manufacturing method thereof |
| KR102272230B1 (en) * | 2014-10-29 | 2021-07-05 | 삼성디스플레이 주식회사 | Display panel for compensating negative power supply voltage, display module and mobile device including the same |
| CN106157882B (en) * | 2015-04-24 | 2019-01-15 | 上海和辉光电有限公司 | Dot structure |
| CN107871757B (en) * | 2016-09-23 | 2020-04-14 | 京东方科技集团股份有限公司 | Organic light emitting diode array substrate, preparation method thereof and display device |
| CN108305888B (en) * | 2017-01-12 | 2020-10-16 | 上海和辉光电股份有限公司 | Array substrate and display panel |
| CN106991968B (en) * | 2017-05-27 | 2020-11-27 | 京东方科技集团股份有限公司 | Pixel compensation circuit, pixel compensation method and display device |
| CN107274829B (en) | 2017-07-10 | 2020-04-14 | 上海天马有机发光显示技术有限公司 | Organic electroluminescent display panel and display device |
| CN109727531A (en) * | 2017-10-31 | 2019-05-07 | 云谷（固安）科技有限公司 | A kind of display panel and terminal |
| CN110136651B (en) * | 2019-06-12 | 2021-09-17 | 京东方科技集团股份有限公司 | Array substrate, OLED display panel and display device |
| US11348533B1 (en) | 2019-06-13 | 2022-05-31 | Apple Inc. | Methods and apparatus for accelerating scan signal fall time to reduce display border width |
| CN112951830B (en) * | 2021-02-01 | 2023-02-07 | 泉芯集成电路制造(济南)有限公司 | Integrated circuit device, memory, and electronic apparatus |
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| CN101334564A (en) * | 2007-06-28 | 2008-12-31 | 上海广电Nec液晶显示器有限公司 | LCD and making method thereof |
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| CN103199096A (en) | 2013-07-10 |
| TW201442247A (en) | 2014-11-01 |
| TWI518918B (en) | 2016-01-21 |
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