CN104393026A - OLED display substrate, manufacturing method of OLED display substrate, and display device adopting OLED display substrate - Google Patents
OLED display substrate, manufacturing method of OLED display substrate, and display device adopting OLED display substrate Download PDFInfo
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Abstract
The invention discloses an OLED (Organic Light Emitting Diode) display substrate, a manufacturing method of the OLED display substrate and a display device adopting the OLED display substrate, and belongs to the field of display. The OLED display substrate comprises a power supply electrode connected with internal voltage, at least one thin film transistor and at least one storage capacitor; a first electrode of the storage capacitor is a doped active layer of the thin film transistor; a second electrode of the storage capacitor is the power supply electrode. By adopting the technical scheme of the invention, power consumption of the display substrate can be reduced, a manufacturing process of the OLED display substrate can be simplified and manufacturing cost of the OLED display substrate is reduced.
Description
Technical field
The present invention relates to display field, particularly relate to a kind of oled display substrate and preparation method thereof, display unit.
Background technology
Low-temperature polysilicon silicon technology (Low Temperature Poly-silicon, LTPS) be that the technology enterprise of Japanese North America is in order to reduce the energy consumption of Note-PC display screen at first, make Note-PC seem the thinner lighter and technology of research and development, greatly about middle nineteen nineties this technology start to move towards the trial period.The organic light emission liquid crystal panel OLED of new generation derived by LTPS also formally went on the practical stage in 1998, its sharpest edges are ultra-thin, lightweight, low power consumption, the feature of himself luminescence simultaneously, thus more gorgeous color and image more clearly can be provided, and what is more important, production cost only has 1/3 of normal liquid crystal panel.AM-OLED (Active Matrix/Organic Light Emitting Diode) is active matrix organic light-emitting diode (AMOLED) panel, compare traditional liquid crystal panel, AM-OLED has the features such as reaction speed is very fast, contrast is higher, visual angle is wider.
Tradition AM-OLED adopts 2T1C (two transistors and an electric capacity) type of drive, one of them switching transistor, a driving transistors and a storage capacitance, time effective to scan line, switching transistor is opened, and data-signal is stored into storage capacitance; The voltage signal that storage capacitance stores controls the conducting of driving transistors, the data voltage signal of input is converted to the current signal of OLED luminescence needs to show different GTGs.Because of the radium-shine annealing technology that current LTPS processing procedure adopts, spatially there is uneven characteristic in the threshold voltage (Vth) of the transistor of making, causes each drive transistor threshold voltage (Vth) to there is larger difference.
The LTPS display base plate being applied to now AM-OLED adopts PMOS structure, traditional 2T1C structure can realize display, but because Silicon uniformity is bad, the fluctuating range of Vth is larger, thus display Mura (brightness irregularities) easily occurs in the display of 2T1C structure, in order to improve pixel display, develop 6T1C structure or 6T2C structure, the impact that the structure of 6T1C can effectively avoid Vth to fluctuate, improves display quality.But 6T1C structure adds process complexity, reduce production capacity and yield.
In addition, an electrode of the storage capacitance of existing oled display substrate adopts the active layer after adulterating to be formed, another electrode adopts grid metal level to be formed, the power electrode (ELVDD) connecing builtin voltage is connected with the grid metal layer image forming one of them electrode of storage capacitance by via hole, owing to usually having the big current of moment when storage capacitance is charged, for preventing big current by single via hole, usually design 2 to 3 via holes at a pixel region and connect grid metal layer image and ELVDD, add the probability that via hole is bad; Simultaneously due to the size in order to ensure storage capacitance, the Area comparison forming the grid metal layer image of one of them electrode of storage capacitance is large, the very large area that intersects is had with source and drain metal layer image, electric capacity is defined between grid metal layer image and source and drain metal level, cause very large load, add the power consumption of whole display base plate.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of oled display substrate and preparation method thereof, display unit, can reduce the power consumption of display base plate, and can simplify the manufacture craft of oled display substrate, reduces the cost of manufacture of oled display substrate.
For solving the problems of the technologies described above, embodiments of the invention provide technical scheme as follows:
On the one hand, a kind of oled display substrate is provided, comprise the power electrode, at least one thin-film transistor and at least one storage capacitance that are connected with builtin voltage, first electrode of described storage capacitance is the active layer of the described thin-film transistor after doping, and the second electrode of described storage capacitance is described power electrode.
Further, described oled display substrate also comprises:
The gate electrode of the described thin-film transistor between described active layer and described power electrode, is separated with gate insulation layer between described gate electrode and described active layer, is separated with intermediate insulating layer between described gate electrode and described power electrode.
Further, the source electrode of described power electrode and described thin-film transistor, drain electrode are positioned at same layer.
Further, described oled display substrate also comprises:
Be positioned at the flatness layer on described source electrode, drain electrode and power electrode.
Further, described oled display substrate also comprises:
Be positioned at the anode on described flatness layer, organic luminous layer and negative electrode, described anode is electrically connected by the via hole in described flatness layer and described drain electrode.
Further, described active layer is made for adopting polysilicon.
The embodiment of the present invention additionally provides a kind of display unit, comprises above-mentioned oled display substrate.
The embodiment of the present invention additionally provides a kind of manufacture method of above-mentioned oled display substrate, and described manufacture method comprises:
One substrate is provided;
Be formed with the figure of active layer on the substrate;
The substrate of figure being formed with described active layer forms gate insulation layer;
Described gate insulation layer is formed the figure of gate electrode, with the figure of gate electrode for mask, described active layer is adulterated, utilize the described active layer after doping to form the first electrode of described storage capacitance;
The substrate being formed with described gate electrode forms intermediate insulating layer;
Described intermediate insulating layer is formed the figure of described power electrode, utilizes described power electrode to form the second electrode of described storage capacitance.
Further, the described figure being formed with active layer on the substrate comprises:
Deposition of amorphous silicon layers on the substrate, carries out laser crystallization to described amorphous silicon layer, forms polysilicon layer;
Described polysilicon layer is utilized to form the figure of described active layer by a patterning processes.
Further, the described figure forming described power electrode on described intermediate insulating layer comprises:
Source and drain metal level is utilized to form described power electrode and source electrode, drain electrode by a patterning processes.
Embodiments of the invention have following beneficial effect:
In such scheme, the electrode of oled display substrate storage capacitance is formed by the active layer after power electrode and doping respectively, be compared in prior art the electrode of the active layer after utilizing doping and grid metal layer image formation storage capacitance, significantly decrease the area of grid metal layer image, thus decrease the area that intersects of grid metal layer image and source and drain metal layer image, decrease the load of display base plate, reduce the power consumption of display base plate; In addition, because the area of grid metal layer image significantly reduces, therefore, after utilizing grid metal level formation gate electrode, can be directly that mask adulterates to active layer with gate electrode, additionally need not carry out once special patterning processes to adulterate to active layer, simplify the manufacture craft of oled display substrate, reduce the cost of manufacture of oled display substrate; Further, owing to not needing to utilize grid metal layer image to form the electrode of storage capacitance, therefore, the via hole of grid metal layer image and power electrode need not be connected by bamboo product, decrease the probability that via hole is bad.
Accompanying drawing explanation
Fig. 1 is the floor map after the oled display substrate of the embodiment of the present invention is formed with active layer;
Fig. 2 is A-A ' the place schematic cross-section of Fig. 1;
Fig. 3 is the floor map after the oled display substrate formation gate electrode of the embodiment of the present invention;
Fig. 4 is A-A ' the place schematic cross-section of Fig. 3;
Fig. 5 is the floor map after the oled display substrate formation intermediate insulating layer of the embodiment of the present invention;
Fig. 6 is A-A ' the place schematic cross-section of Fig. 5;
Fig. 7 is the floor map after the oled display substrate of the embodiment of the present invention forms source electrode and drain electrode;
Fig. 8 is A-A ' the place schematic cross-section of Fig. 7;
Fig. 9 is the floor map after the oled display substrate formation flatness layer of the embodiment of the present invention;
Figure 10 is A-A ' the place schematic cross-section of Fig. 9;
Figure 11 is the floor map after the oled display substrate formation anode of the embodiment of the present invention;
Figure 12 is A-A ' the place schematic cross-section of Figure 11;
Figure 13 is B-B ' the place schematic cross-section of Figure 11;
Figure 14 is the dot structure schematic diagram of the oled display substrate of one embodiment of the invention;
Figure 15 is the electrical block diagram of the oled display substrate of the embodiment of the present invention;
Figure 16 is the signal timing diagram of the oled display substrate of the embodiment of the present invention;
Figure 17 is the floor map of existing oled display substrate;
Figure 18 is A-A ' the place schematic cross-section of Figure 17.
Reference numeral
1 substrate, 2 active layers, 3 gate insulation layers, 4 gate electrodes, 5 emission electrodes, 6 reset terminals, 7 intermediate insulating layers, 8 source electrodes and drain electrode, 9 power electrodes, 10 data wires, 11 flatness layers, 12 anodes, 13 public electrodes, 14 grid metal layer image.
Embodiment
For making the technical problem to be solved in the present invention, technical scheme and advantage clearly, be described in detail below in conjunction with the accompanying drawings and the specific embodiments.
Embodiment one
Present embodiments provide a kind of oled display substrate, comprise the power electrode, at least one thin-film transistor and at least one storage capacitance that are connected with builtin voltage, wherein, first electrode of described storage capacitance is the active layer of the described thin-film transistor after doping, and the second electrode of described storage capacitance is described power electrode.
The electrode of the oled display substrate storage capacitance of the present embodiment is formed by the active layer after power electrode and doping respectively, be compared in prior art the electrode of the active layer after utilizing doping and grid metal layer image formation storage capacitance, significantly decrease the area of grid metal layer image, thus decrease the area that intersects of grid metal layer image and source and drain metal layer image, decrease the load of display base plate, reduce the power consumption of display base plate; In addition, because the area of grid metal layer image significantly reduces, therefore, after utilizing grid metal level formation gate electrode, can be directly that mask adulterates to active layer with gate electrode, additionally need not carry out once special patterning processes to adulterate to active layer, simplify the manufacture craft of oled display substrate, reduce the cost of manufacture of oled display substrate; Further, owing to not needing to utilize grid metal layer image to form the electrode of storage capacitance, therefore, the via hole of grid metal layer image and power electrode need not be connected by bamboo product, decrease the probability that via hole is bad.
Further, described oled display substrate also comprises:
The gate electrode of the described thin-film transistor between described active layer and described power electrode, is separated with gate insulation layer between described gate electrode and described active layer, is separated with intermediate insulating layer between described gate electrode and described power electrode.
Further, the source electrode of described power electrode and described thin-film transistor, drain electrode are positioned at same layer.
Further, described oled display substrate also comprises:
Be positioned at the flatness layer on described source electrode, drain electrode and power electrode.
Further, described oled display substrate also comprises:
Be positioned at the anode on described flatness layer, organic luminous layer and negative electrode, described anode is electrically connected by the via hole in described flatness layer and described drain electrode.
Further, in order to ensure the performance of oled display substrate, described active layer is made for adopting polysilicon.
Embodiment two
Present embodiments provide a kind of display unit, comprise the oled display substrate as described in embodiment one.Described display unit can be: any product or parts with Presentation Function such as display floater, TV, display, DPF, mobile phone, panel computer.
Embodiment three
The present embodiment additionally provides a kind of manufacture method of above-mentioned oled display substrate, and described manufacture method comprises:
One substrate is provided;
Be formed with the figure of active layer on the substrate;
The substrate of figure being formed with described active layer forms gate insulation layer;
Described gate insulation layer is formed the figure of gate electrode, with the figure of gate electrode for mask, described active layer is adulterated, utilize the described active layer after doping to form the first electrode of described storage capacitance;
The substrate being formed with described gate electrode forms intermediate insulating layer;
Described intermediate insulating layer is formed the figure of described power electrode, utilizes described power electrode to form the second electrode of described storage capacitance.
The present embodiment is formed the electrode of oled display substrate storage capacitance respectively by the active layer after power electrode and doping, be compared in prior art the electrode of the active layer after utilizing doping and grid metal layer image formation storage capacitance, significantly decrease the area of grid metal layer image, thus decrease the area that intersects of grid metal layer image and source and drain metal layer image, decrease the load of display base plate, reduce the power consumption of display base plate; In addition, because the area of grid metal layer image significantly reduces, therefore, after utilizing grid metal level formation gate electrode, can be directly that mask adulterates to active layer with gate electrode, additionally need not carry out once special patterning processes to adulterate to active layer, simplify the manufacture craft of oled display substrate, reduce the cost of manufacture of oled display substrate; Further, owing to not needing to utilize grid metal layer image to form the electrode of storage capacitance, therefore, the via hole of grid metal layer image and power electrode need not be connected by bamboo product, decrease the probability that via hole is bad.
Further, the described figure being formed with active layer on the substrate comprises:
Deposition of amorphous silicon layers on the substrate, carries out laser crystallization to described amorphous silicon layer, forms polysilicon layer;
Described polysilicon layer is utilized to form the figure of described active layer by a patterning processes.
Further, the described figure forming described power electrode on described intermediate insulating layer comprises:
Source and drain metal level is utilized to form described power electrode and source electrode, drain electrode by a patterning processes.
Embodiment four
Below in conjunction with accompanying drawing, oled display substrate of the present embodiment and preparation method thereof is described in detail:
As shown in FIG. 17 and 18, an electrode of the storage capacitance of existing oled display substrate adopts the active layer 2 after adulterating to be formed, another electrode is for be formed by grid metal level, the power electrode (ELVDD) 9 connecing builtin voltage is connected with the grid metal layer image 14 forming one of them electrode of storage capacitance Cst by via hole, owing to usually having the big current of moment when storage capacitance is charged, for preventing big current by single via hole, usually design 2 to 3 via holes at a pixel region and connect grid metal layer image 14 and power electrode 9, add the probability that via hole is bad, simultaneously due to the size in order to ensure storage capacitance, the Area comparison forming the grid metal layer image 14 of one of them electrode of storage capacitance is large, the very large area that intersects is had with source and drain metal layer image, electric capacity is defined between grid metal layer image 14 and source and drain metal level, cause very large load, add the power consumption of whole display base plate, in addition, active layer 2 adopts polysilicon to make, polysilicon is still eigenstate, mobility is very low, can not as the electrode of storage capacitance, needing adulterates to active layer 2 forms the electrode of storage capacitance, but because the Area comparison of grid metal layer image 14 is large, most of region of active layer 2 block by grid metal layer image 14, therefore can not adulterate to active layer 2 for mask with grid metal layer image 2, need to carry out extra patterning processes to adulterate to active layer 2 specially, add the complexity of oled display substrate manufacture craft, improve the cost of manufacture of oled display substrate, in addition, as shown in figure 17, the spacing between the grid metal layer image 14 of intersecting with source and drain metal layer image and the grid metal layer image forming T1 and T2 is very little, and technological fluctuation probably causes these two grid metal layer image to be connected, T1, T2 were lost efficacy, causes occurring that display is bad.
In order to solve the problem, present embodiments provide a kind of oled display substrate and preparation method thereof, this manufacture method specifically comprises the following steps:
Step 1 a: substrate 1 is provided, and is formed with active layer 2 on substrate 1;
Substrate 1 can be quartz base plate or glass substrate, and particularly, substrate 1 can be the glass substrate of thickness between 0.4-0.7mm.Substrate 1 is cleaned, after substrate 1 cleaning is dustless, adopts CVD (Chemical Vapor Deposition, chemical vapour deposition (CVD)) method to deposit a layer thickness on substrate 1 and be
resilient coating, wherein, cushioning layer material can select oxide, nitride or nitrogen oxide, and resilient coating can be individual layer, bilayer or sandwich construction, and resilient coating can adopt SiNx, SiOx or Si (ON) x, and particularly, resilient coating can be for thickness
siNx and thickness be
siO
2the double-decker of composition.
Depositing a layer thickness is on the buffer layer
amorphous silicon layer a-Si:H, ELA (excimer laser) crystallization is carried out to amorphous silicon layer and forms polysilicon layer, apply photoresist on the polysilicon layer, carry out exposing, developing and dry etching, be formed with the figure of active layer 2 as shown in Figure 1, Fig. 2 is the A-A ' schematic cross-section of Fig. 1;
Step 2: form gate insulation layer 3, gate insulation layer 3 is formed the figure of gate electrode 4, emission electrode 5 and reset terminal 6, and with the figure of gate electrode 4 for mask, carries out heavy doping to active layer 2, forms the first electrode of storage capacitance;
Particularly, can strengthen chemical vapour deposition (CVD) (PECVD) method by using plasma, on the substrate 1 through step 1, deposit thickness is about
gate insulation layer 3, wherein, gate insulator layer material can select oxide, nitride or nitrogen oxide, gate insulation layer can be individual layer, bilayer or sandwich construction, and gate insulation layer can adopt SiNx, SiOx or Si (ON) x, particularly, gate insulation layer can be for thickness
siNx and thickness be
siO
2the double-decker of composition.
Afterwards, can adopt sputtering or the method for thermal evaporation on gate insulation layer 3, deposit a layer thickness to be
grid metal level, grid metal level can be Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, the alloy of the metals such as W and these metals, grid metal level can be single layer structure or sandwich construction, and sandwich construction is Cu Mo such as, Ti Cu Ti, Mo Al Mo etc.Grid metal level applies one deck photoresist, mask plate is adopted to expose photoresist, photoresist is made to form the non-reserve area of photoresist and photoresist reserve area, wherein, photoresist reserve area corresponds to the figure region of grid line, gate electrode 4, emission electrode 5 and reset terminal 6, and the non-reserve area of photoresist corresponds to the region beyond above-mentioned figure; Carry out development treatment, the photoresist of the non-reserve area of photoresist is completely removed, and the photoresist thickness of photoresist reserve area remains unchanged; Etched away the grid metallic film of the non-reserve area of photoresist by etching technics completely, peel off remaining photoresist, form the figure of grid line, gate electrode 4, emission electrode 5 and reset terminal 6, as shown in Figure 3, Fig. 4 is the A-A ' schematic cross-section of Fig. 3 to the structure of formation.
Then with the figure of gate electrode 4 for mask, heavy doping is carried out to active layer 2, forms the first electrode of storage capacitance;
Step 3: form the figure including the intermediate insulating layer 7 of insulating barrier via hole;
Particularly, magnetron sputtering, thermal evaporation, PECVD or other film build method deposit thickness can be adopted to be on the substrate 1 through step 2
intermediate insulation layer material, wherein, intermediate insulation layer material can select oxide, nitride or nitrogen oxide, and particularly, intermediate insulating layer can adopt SiNx, SiOx or Si (ON) x.Intermediate insulating layer can be single layer structure, and also can be the double-layer structure adopting silicon nitride and silica to form, particularly, intermediate insulating layer can be for thickness
siNx and thickness be
siO
2the double-decker of composition.
Intermediate insulation layer material applies one deck photoresist; Mask plate is adopted to expose photoresist, photoresist is made to form the non-reserve area of photoresist and photoresist reserve area, wherein, photoresist reserve area corresponds to the figure region of intermediate insulating layer 7, and the non-reserve area of photoresist corresponds to the region beyond above-mentioned figure; Carry out development treatment, the photoresist of the non-reserve area of photoresist is completely removed, and the photoresist thickness of photoresist reserve area remains unchanged; Etched away the intermediate insulation layer material of the non-reserve area of photoresist by etching technics completely, peel off remaining photoresist, form the figure comprising the intermediate insulating layer 7 of insulating barrier via hole, as shown in Figure 5, Fig. 6 is the A-A ' schematic cross-section of Fig. 5 to the structure of formation
Step 4: the figure forming power electrode 9, source electrode and drain electrode 8, data wire 10;
Particularly, can on the substrate 1 through step 3, adopt magnetron sputtering, thermal evaporation or other film build method to deposit a layer thickness to be about
source and drain metal level, source and drain metal level can be the alloy of the metals such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W and these metals.Source and drain metal level can be single layer structure or sandwich construction, sandwich construction such as Cu Mo, Ti Cu Ti, Mo Al Mo etc.Particularly, source and drain metal level can be for thickness
ti, thickness be
al, thickness be
ti composition three-decker.
Source and drain metal level applies one deck photoresist, mask plate is adopted to expose photoresist, photoresist is made to form the non-reserve area of photoresist and photoresist reserve area, wherein, photoresist reserve area corresponds to the figure region of power electrode 9, source electrode and drain electrode 8, data wire 10, and the non-reserve area of photoresist corresponds to the region beyond above-mentioned figure; Carry out development treatment, the photoresist of the non-reserve area of photoresist is completely removed, and the photoresist thickness of photoresist reserve area remains unchanged; The source and drain metallic film of the non-reserve area of photoresist is etched away completely by etching technics, peel off remaining photoresist, form power electrode 9, source electrode and drain electrode 8, data wire 10, the structure formed as shown in Figure 7 and Figure 8, source electrode is connected with active layer 2 by insulating barrier via hole with drain electrode 8, and power electrode 9 is as the second electrode of storage capacitance.
Step 5: form the flatness layer 11 including flatness layer via hole;
Particularly, can apply one deck resin material on the substrate 1 through step 4, wherein, the material of resin can be photosensitive resin, also can moral sense photopolymer resin; Adopt mask plate to expose resin material, then etched by development or dry etch process, form the figure comprising the flatness layer 11 of flatness layer via hole, the structure of formation as shown in Figure 9 and Figure 10.
Step 6: form anode 12 and public electrode 13;
Particularly, the substrate 1 through step 5 adopts magnetron sputtering, thermal evaporation or other film build method deposit a layer thickness to be about
conductive layer, conductive layer can adopt the materials such as ITO, IZO, Ag, and this conductive layer can be single layer structure or sandwich construction, and particularly, conductive layer can be for thickness
iTO, thickness be
ag, thickness be
iTO composition three-decker.
Apply one deck photoresist on the electrically conductive, mask plate is adopted to expose photoresist, photoresist is made to form the non-reserve area of photoresist and photoresist reserve area, wherein, photoresist reserve area corresponds to the figure region of anode 12 and public electrode 13, and the non-reserve area of photoresist corresponds to the region beyond above-mentioned figure; Carry out development treatment, the photoresist of the non-reserve area of photoresist is completely removed, and the photoresist thickness of photoresist reserve area remains unchanged; Etched away the conductive film of the non-reserve area of photoresist by etching technics completely, peel off remaining photoresist, form anode 12 and public electrode 13, the structure of formation is as shown in Figure 11,12 and Figure 13, and anode 12 is connected with drain electrode by flatness layer via hole.
Step 7: form pixel and define layer, organic luminous layer and negative electrode.
Particularly, the substrate 1 through step 6 applies PI (polyimides), and carries out exposure imaging, form pixel and define layer.On pixel defines between layer anode 12, form organic luminous layer afterwards, organic luminous layer generally includes hole injection layer, hole transmission layer, luminescent layer, hole blocking layer, electronic barrier layer, electron transfer layer, electron injecting layer etc.; Organic luminous layer forms negative electrode, thus finally defines OLED display device.
Because the luminous efficiency of OLED different materials is different, in order to reach best display effect, the sub-pixel size of red, green, blue three look can be carried out different settings.Simultaneously in order to improve PPI (Pixel Per Inch, resolution), the present embodiment using four sub-pixels as a unit, as shown in figure 14, using blue subpixels, green sub-pixels, red sub-pixel and green sub-pixels as a pixel cell, red sub-pixel and blue subpixels can give adjacent pixel cell public, utilize algorithm to improve PPI.
Be the circuit diagram of the oled display substrate of the present embodiment as shown in figure 15, this oled display substrate comprises five transistor T1-T5, driving transistors DTFT, storage capacitance Cst and an OLED display device, and the structure of circuit is identical with existing.Be that the data wire of the oled display substrate of the embodiment of the present invention, reset terminal, gate electrode, emission electrode are at the sequential chart of t1 (reseting stage), t2 (charging stage), t3 (keep stage) as shown in figure 16.
The present embodiment is formed the electrode of oled display substrate storage capacitance respectively by the active layer after power electrode and doping, be compared in prior art the electrode of the active layer after utilizing doping and grid metal layer image formation storage capacitance, significantly decrease the area of grid metal layer image, thus decrease the area that intersects of grid metal layer image and source and drain metal layer image, decrease the load of display base plate, reduce the power consumption of display base plate; In addition, because the area of grid metal layer image significantly reduces, therefore, after utilizing grid metal level formation gate electrode, can be directly that mask adulterates to active layer with gate electrode, additionally need not carry out once special patterning processes to adulterate to active layer, simplify the manufacture craft of oled display substrate, reduce the cost of manufacture of oled display substrate; Further, owing to not needing to utilize grid metal layer image to form the electrode of storage capacitance, therefore, the via hole of grid metal layer image and power electrode need not be connected by bamboo product, decrease the probability that via hole is bad; And because the area of grid metal layer image significantly reduces, effectively prevent the possibility that different grid metal layer image is connected, decrease the probability occurring that display is bad.
The above is the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the prerequisite not departing from principle of the present invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (10)
1. an oled display substrate, comprise the power electrode, at least one thin-film transistor and at least one storage capacitance that are connected with builtin voltage, it is characterized in that, first electrode of described storage capacitance is the active layer of the described thin-film transistor after doping, and the second electrode of described storage capacitance is described power electrode.
2. oled display substrate according to claim 1, is characterized in that, described oled display substrate also comprises:
The gate electrode of the described thin-film transistor between described active layer and described power electrode, is separated with gate insulation layer between described gate electrode and described active layer, is separated with intermediate insulating layer between described gate electrode and described power electrode.
3. oled display substrate according to claim 1, is characterized in that, source electrode, the drain electrode of described power electrode and described thin-film transistor are positioned at same layer.
4. oled display substrate according to claim 3, is characterized in that, described oled display substrate also comprises:
Be positioned at the flatness layer on described source electrode, drain electrode and power electrode.
5. oled display substrate according to claim 4, is characterized in that, described oled display substrate also comprises:
Be positioned at the anode on described flatness layer, organic luminous layer and negative electrode, described anode is electrically connected by the via hole in described flatness layer and described drain electrode.
6. the oled display substrate according to any one of claim 1-5, is characterized in that, described active layer is made for adopting polysilicon.
7. a display unit, is characterized in that, comprises the oled display substrate as described in any one of claim 1-6.
8. a manufacture method for the oled display substrate according to any one of claim 1-6, is characterized in that, described manufacture method comprises:
One substrate is provided;
Be formed with the figure of active layer on the substrate;
The substrate of figure being formed with described active layer forms gate insulation layer;
Described gate insulation layer is formed the figure of gate electrode, with the figure of gate electrode for mask, described active layer is adulterated, utilize the described active layer after doping to form the first electrode of described storage capacitance;
The substrate being formed with described gate electrode forms intermediate insulating layer;
Described intermediate insulating layer is formed the figure of described power electrode, utilizes described power electrode to form the second electrode of described storage capacitance.
9. the manufacture method of oled display substrate according to claim 8, is characterized in that, the described figure being formed with active layer on the substrate comprises:
Deposition of amorphous silicon layers on the substrate, carries out laser crystallization to described amorphous silicon layer, forms polysilicon layer;
Described polysilicon layer is utilized to form the figure of described active layer by a patterning processes.
10. the manufacture method of oled display substrate according to claim 8, is characterized in that, the described figure forming described power electrode on described intermediate insulating layer comprises:
Source and drain metal level is utilized to form described power electrode and source electrode, drain electrode by a patterning processes.
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| WO2016197524A1 (en) * | 2015-06-11 | 2016-12-15 | 京东方科技集团股份有限公司 | Organic electroluminescent display device, display apparatus, and manufacturing method therefor |
| CN107039466A (en) * | 2017-05-04 | 2017-08-11 | 京东方科技集团股份有限公司 | A kind of display base plate and preparation method thereof, display device |
| CN108052727A (en) * | 2017-12-08 | 2018-05-18 | 杭州电子科技大学 | A kind of metal gate Work function Change causes the method for estimation of gate capacitance statistical distribution |
| CN110391180A (en) * | 2019-06-13 | 2019-10-29 | 惠科股份有限公司 | Production method, array substrate and the display device of array substrate |
| CN111540777A (en) * | 2017-03-21 | 2020-08-14 | 群创光电股份有限公司 | Display panel |
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