TW201442079A - Structure of metal gate structure and manufacturing method of the same - Google Patents

Abstract

A manufacturing method of a metal gate structure is provided. First, a substrate covered by an interlayer dielectric is provided. A gate trench is formed in the interlayer dielectric, wherein a gate dielectric layer is formed in the gate trench. A silicon-containing work function layer is formed on the gate dielectric layer in the gate trench. Finally, the gate trench is filled up with a conductive metal layer.

Description

Metal gate structure and manufacturing method thereof

The invention relates to a metal gate structure and a manufacturing method thereof, in particular to a metal gate structure using a gate last process and a manufacturing method thereof.

As the size of semiconductor components continues to shrink, the conventional method utilizes a tunneling effect that reduces the thickness of the gate dielectric layer, such as reducing the thickness of the yttria layer, for optimization purposes. A physical limitation that causes excessive leakage current. In order to effectively extend the evolution of logic components, high dielectric constant (hereinafter referred to as high-k) materials have an effective reduction in physical limit thickness and the same equivalent oxide thickness (EOT). In order to effectively reduce the leakage current and achieve the equivalent capacitance to control the channel switch, it is used to replace the conventional ruthenium dioxide layer or the ruthenium oxynitride layer as the gate dielectric layer.

However, the conventional gate material polysilicon is faced with boron penetration effect, which leads to problems such as lower component efficiency; and the polysilicon gate encounters an inevitable depletion effect, making the equivalent gate dielectric layer The increase in thickness and the decrease in the gate capacitance value lead to difficulties such as the deterioration of the component driving capability. In response to this problem, the semiconductor industry has proposed to replace the traditional polysilicon gate with a new gate material, such as a metal gate with a work function metal layer, as a matching high-k gate dielectric layer. Control electrode.

However, even if a high-k gate dielectric layer is used in place of a conventional germanium dioxide or tantalum oxynitride dielectric layer, and a metal gate with a matching work function is substituted for a conventional polysilicon gate, how to continuously increase the performance of the semiconductor device, for example, When reducing the equivalent thickness of the gate dielectric layer, it is ensured that the metal gate of the P-type metal-oxide-semiconductor (PMOS) transistor has a potential of 4.9 eV to 5.2 eV. The left and right work functions have been the problem that the semiconductor industry has to solve.

Accordingly, it is an object of the present invention to provide a metal gate structure and a method of fabricating the same that can adjust the metal gate of a PMOS transistor to a desired work function.

In accordance with a preferred embodiment of the present invention, a metal gate structure is provided that includes a substrate, a gate trench, a gate dielectric layer, a germanium-containing function layer, and a conductive layer. The substrate is covered with an interlayer dielectric layer, and the interlayer dielectric layer has a gate trench. The gate dielectric layer, the germanium-containing function layer, and the conductive metal layer are sequentially disposed on the substrate in the gate trench. The conductive metal layer fills the gate trench.

According to another preferred embodiment of the present invention, a method of fabricating a metal gate structure is provided, including the following steps. A substrate is first provided which is covered with an interlevel dielectric layer. A gate trench is formed in the interlayer dielectric layer, and a gate dielectric layer is disposed in the gate trench. A germanium-containing function layer is formed on the gate dielectric layer in the gate trench. Finally, a conductive metal layer is filled in the gate trench.

10‧‧‧First area

12‧‧‧Second area

20‧‧‧First stack structure

30‧‧‧Second stacking structure

100‧‧‧Base

102‧‧‧Shallow trench isolation structure

104‧‧‧ dielectric layer

106‧‧‧gate dielectric layer

108‧‧‧Barrier layer

110‧‧‧etch stop layer

112‧‧‧First work function layer

116‧‧‧ patterned sacrificial layer

118‧‧‧ patterned hard mask

120‧‧‧First lightly doped bungee

122‧‧‧Second lightly doped bungee

124‧‧‧ Sidewall

130‧‧‧First source/bungee

132‧‧‧Second source/bungee

134‧‧‧metal telluride

140‧‧‧Contact hole etch stop layer

142‧‧‧Interlayer dielectric layer

146‧‧‧ patterned photoresist layer

150‧‧‧First Gate Ditch

152‧‧‧Second gate ditches

160‧‧‧second work function layer

162‧‧‧Top barrier layer

170‧‧‧metal layer

172‧‧‧ gate metal layer

180‧‧‧First metal gate structure

182‧‧‧Second metal gate structure

1 to 10 are schematic views showing a semiconductor device having a metal gate according to a preferred embodiment of the present invention.

Please refer to FIG. 1 to FIG. 10 . FIG. 1 to FIG. 10 are schematic diagrams showing a semiconductor device having a metal gate according to a preferred embodiment of the present invention. In this embodiment, the semiconductor device is preferably a complementary CMOS transistor, and the preferred embodiment uses a gate-last process with a front high-k dielectric layer. (high-K first) process. As shown in FIG. 1, a substrate 100 is first provided, such as a germanium substrate or a silicon-on-insulator (SOI) substrate. A first region 10 and a second region 12 are defined on the substrate 100. For example, a PMOS region and an NMOS region are respectively formed, and a plurality of shallow trench isolation (STI) 102 are formed in the substrate 100 for electricity. Sexual insulation of two adjacent areas.

Then, an interfacial layer 104 made of a dielectric material such as an oxide or a nitride is selectively formed on the surface of the substrate 100, and a gate dielectric layer 106 and a barrier layer 108 are sequentially formed. To form a stacked film on the dielectric layer 104. The gate dielectric layer 106 is preferably a high-k dielectric layer having a dielectric constant substantially greater than 20, and has one or more layers. According to an embodiment of the present invention, high-k dielectric layer may include a metal oxide layer, for example, a rare earth metal oxide layer, and optionally consisting of hafnium oxide (hafnium oxide, HfO _2), hafnium silicate oxide ( Hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), aluminum oxide (AlO), lanthanum oxide (La ₂ O ₃ ), lanthanum aluminum oxide (lanthanum aluminum oxide, LaAlO), tantalum oxide (Ta ₂ O ₃ ), zirconium oxide (ZrO ₂ ), zirconium silicon oxide (ZrSiO), hafnium zirconium oxide (HfZrO), antimony Strontium bismuth tantalate (SrBi ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (PbZr _x Ti _1-x O ₃ , PZT) and barium strontium titanate (BaxSr) a group consisting of _1-x TiO ₃ , BST) and the like. Further, the barrier layer 108 is preferably made of titanium nitride (TiN).

Then, as shown in FIG. 2, a sacrificial layer (not shown), such as a polysilicon layer, and a hard mask (not shown) are sequentially formed on the surface of the barrier layer 108, and then a patterned photoresist layer is used. (not shown) performing a pattern transfer process as a mask, and removing a portion of the hard mask, the sacrificial layer, the barrier layer 108, the gate dielectric layer 106, and the dielectric layer 104 by a single etching or successive etching step, A patterned sacrificial layer 116 and a patterned hard mask 118 are formed on the substrate 100. As shown in FIG. 2, finally, the patterned photoresist layer is stripped, and a first stacked structure 20 and a second stacked structure 30 are formed in the first region 10 and the second region 12, respectively. The stacked structures 20, 30 described above can be used as a dummy gate or a replacement gate structure in subsequent processes. Wherein, the material of the sacrificial layer may include a polycrystalline germanium material having no undoped, a polycrystalline germanium material having an N ⁺ dopant, and/or an amorphous germanium material. The hard mask is composed of cerium oxide (SiO ₂ ), cerium nitride (SiN), tantalum carbide (SiC), and/or cerium oxynitride (SiON).

Then, as shown in FIG. 3, sidewalls 124 are respectively formed on the sidewalls of the first stack structure 20 and the second stack structure 30, and a corresponding conductive type is formed in each of the substrates 100 on both sides of the sidewall spacer 124. Lightly doped drain (LDD) and source/drain. Specifically, the first lightly doped drain 120 and the first source/drain 130 may be formed in the first region 10 and each have a first conductivity type, such as a P-type. The second lightly doped drain 122 and the second source/drain 132 are formed in the second region 12, and each has a second conductivity type, such as an N-type.

Then, a selective epitaxial growth (SEG) process may be selectively performed, for example, an epitaxial layer is formed in the substrate 100 on both sides of the sidewalls 124 in the first region 10 and/or the second region 12. (not shown) to provide proper compressive stress in the carrier channel. For example, the material of the epitaxial layer in the first region 10 may include silicon germanium (SiGe), and the material of the epitaxial layer in the second region 12 may include silicon phosphous (SiP) or germanium carbon ( Silicon carbide, SiC). And each of the above epitaxial layers may be a single layer structure or a multilayer structure. In addition, the timing at which the epitaxial layer is formed is not limited to being formed in the substrate 100 preferentially after the source/drain electrodes 130, 132 are formed.

Then, a silicidation process may be performed. For example, a metal layer (not shown) composed of cobalt, titanium, nickel, platinum, palladium, molybdenum or the like is formed on the substrate 100 and covers the source/drain 130, 132, and then using at least one rapid thermal anneal (RTP) process to react the metal layer with the source/drain electrodes 130, 132 to surface the substrate 100 of the first region 10 and the second region 12, respectively A deuterated metal layer 134 is formed. Finally, the unreacted metal layer is removed. It should be noted that the timing of performing the germanium metallization process is not limited thereto, and it may be performed after the source/drain contact hole is formed subsequently and the source/drain is exposed.

Then, a contact etch stop layer (CESL) 140 and an interlayer dielectric layer 142 are sequentially formed on the surface of the substrate 100 to cover the first stacked structure 20 and the second stacked structure 30, respectively. Wherein, the contact hole etch stop layer 140 may have appropriate stress to enhance the mobility of the carrier. Finally, a planarization process, such as a chemical mechanical polishing process and/or an etching process, is performed to remove portions of the interlayer dielectric layer 142, portions of the contact hole etch stop layer 140, and portions of the hard mask 118 until exposed. The patterned sacrificial layer 116 is patterned. Then, an etching process is performed to hollow out the patterned sacrificial layer 116 in the first region 10 and the second region 12 to form a first gate in the interlayer dielectric layer 142 of the first region 10 and the second region 12, respectively. The trench 150 and a second gate trench 152.

It should be noted here that since the surface of the gate dielectric layer 106 is covered by the barrier layer 108, the gate dielectric layer 106 is not etched or hollowed out. Finally, an etch stop layer 110 is selectively deposited in a comprehensive manner to cover the first gate trench 150 and the inner wall of a second gate trench 152 in a compliant manner. The composition of the etch stop layer 110 is preferably different from the barrier layer 108, and may include, for example, tantalum nitride (TaN), but is not limited thereto.

In addition, please refer to FIG. 4, which is a schematic diagram of a variation of the preferred embodiment. As shown in Fig. 4, this variant uses a post-high-k last process integration. Specifically, the present modification needs to form a gate dielectric layer and a barrier layer before forming the first stacked structure (not shown) and the second stacked structure (not shown), so the first stage of the initial stage of this embodiment The stacked structure and the second stacked structure do not include a gate dielectric layer and a barrier layer. According to this embodiment, after the gate sacrificial layer (not shown) is removed to form the first gate trench 150 and the second gate trench 152, the first gate trench 150 and the second gate trench are exposed. The dielectric layer 104 at the bottom of the 152. The dielectric layer 104 may be composed of cerium oxide and may serve as an interface layer. A gate dielectric layer 106 is then formed over the substrate 100, which may comprise the high-k material described above. As shown in FIG. 4, the gate dielectric layer 106 in the first gate trench 150 and the second gate trench 152 has a U-shape covering the first gate trench 150 and the second gate trench 152 side and bottom. After forming the high-k gate dielectric layer 106, the aforementioned barrier layer (not shown) and the selective etch stop layer 110 may be formed thereon.

A first work function layer 112 is then formed as shown in FIG. 5 to laterally cover the interlayer dielectric layer 142 and the bottom and sidewalls of each of the gate trenches 150, 152. Therefore, the first work function layer 112 preferably includes a vertical portion and a horizontal portion, respectively located on the side wall and the bottom surface of the trench. It should be noted here that the composition of the first work function layer 112 of the present embodiment contains germanium atoms, and thus may be referred to as a germanium-containing work function layer. More specifically, the composition preferably includes titanium, ruthenium, and nitrogen, or further includes other atoms such as oxygen.

Preferably, the first work function layer 112 is formed by the present embodiment by using an atomic layer deposition (ALD) process, which includes a plurality of adsorption-purge-adsorption-clean cycles. Process. For example, for a first work function layer 112 comprising titanium, niobium, and nitrogen, each adsorption-clean-adsorption-clean process can correspond to providing a titanium precursor-providing a clean gas-providing a helium precursor. Matter and nitrogen precursor - provide clean gas. Thus, titanium precursors, such as titanium tetrachloride (TiCl _4), and silicon precursor, Silane (SiH _4), are alternately supplied onto the substrate 100, and the conformality cover the bottom of the gate trench 150, 152 And side walls. In addition, the above process may include heating or a plasma process to increase the reaction capacity.

In addition to the atomic layer deposition process described above, the first work function layer 112 can also be formed by other various methods, such as gas phase diffusion, ion implantation, solid phase diffusion. ) or a combination of the above deposition processes. For example, a layer of germanium, such as a polysilicon layer or an amorphous germanium layer, and a titanium metal layer may be deposited sequentially on the bottom and sidewalls of each of the gate trenches 150, 152. Then, a thermal process is performed to diffuse germanium atoms and/or titanium atoms to form a titanium telluride layer. Finally, vapor phase diffusion or ion implantation is used to freely diffuse or accelerate the impact of the nitrogen atoms into the metal layer, respectively.

Preferably, the work function value of the first work function layer 112 will be greater than 4.9 eV. The atomic ratio of titanium to tantalum will be between 1.5 and 4, and the percentage of germanium atoms will be between 10% and 30%. In the case where the ruthenium-containing function layer includes titanium, ruthenium, nitrogen and oxygen, the ratio of the number of atoms between them is preferably 28.9:13.2:46.8:10. In addition, the first work function layer 112 may also be a metal compound doped with antimony. The metal compound includes titanium nitride (TiN), titanium carbide (TiC), and tantalum nitride (TaN). , tantalum carbide (TaC), tungsten carbide (WC) or aluminum titanium nitride (TiAlN), but is not limited thereto. In addition, the first work function layer 112 can also be a single layer structure or a composite layer structure.

One feature of the invention is the doping of germanium atoms into the P-type work function layer to adjust its work function value. In contrast to the case where the value of the P-type work function layer work function is generally adjusted using nitrogen or oxygen, the ruthenium-containing work function layer of the present invention can increase the electric power without increasing the gate leakage current (J _g ). The electrical behavior of the crystal structure, such as increasing the flat band voltage (V _fb ) and reducing the equivalent oxidation thickness.

Next, as shown in FIG. 6, a photolithography process is performed to form a patterned photoresist layer 146 having a single layer or a multilayer structure on the substrate 100. The patterned photoresist layer 146 may expose the first work function layer 112 located in the second region 12. The first work function layer 112, which is not protected by the patterned photoresist layer 146, is removed by a suitable etchant to expose the etch stop layer 108 within the second gate trench 152. When the first work function layer 112 is removed, the etch stop layer 108 prevents the barrier layer 108 and the gate dielectric layer 106 from being further etched underneath.

In addition, as shown in FIG. 7 , in order to improve the filling result of the subsequent gate metal layer, only the patterned photoresist layer 146 may be formed in the first gate trench 150 . The surface is slightly lower than the opening of the first gate trench 150. Therefore, in the subsequent etching process, in addition to the first work function layer 112 in the second gate trench 152 being etched away, the first work function layer 112 at the opening of the first gate trench 150 may also be stripped. Thin or removed. Therefore, the first work function layer 112 will only remain in the first gate trench 150, especially the bottom and sidewalls of the first gate trench 150. In this case, the sidewalls near the opening of the first gate trench 150 are not covered by the first work function layer 112, thereby increasing the filling ability of the subsequent gate metal layer.

Please continue to see Figure 8. Removing the first work in the second gate trench 152 After the function layer 112, a CVD process or a PVD process is performed to form a second work function layer 160 on the substrate 100. The second work function layer 160 has a predetermined work function, that is, the second work function layer 160 can be an N-type work function metal layer having an N-type conductivity type, and the work function value is preferably between 3.9 eV and 4.2 eV. . In addition, the second work function layer 160 may be a single layer structure or a composite layer structure. In the preferred embodiment, the second work function layer 160 can be a metal layer, preferably a titanium aluminum layer formed by a CVD process or a PVD process.

Please refer to Figure 9. In the first gate trench 150 and the second gate trench 152 A top barrier layer 162 and a metal layer 170 are selectively formed on the second work function layer 160. The composition of the top barrier layer 162 may include TiN or TaN, but is not limited thereto, and may be used to improve adhesion and/or interstitial ability of the main conductive layer in the trench, or to prevent elements in the main conductive layer. Produces electrical diffusion or thermal diffusion. The metal layer 170 is used to fill the first gate trench 150 and the second gate trench 152, respectively, and may select a metal or metal oxide having excellent filling ability and lower resistance, such as aluminum (Al). Titanium aluminide (TiAl), titanium aluminum oxide (TiAlO), tungsten (tungsten, W) or copper (copper, Cu), but not limited herein.

Finally, referring to Figure 9 and Figure 10, a flattening system is performed. For example, a chemical mechanical polishing process for removing the metal layer 170 on the top surface of the interlayer dielectric layer 142, the top barrier layer 162, the second work function layer 160, the first work function layer 112, and the etch stop The layer 108 forms a gate metal layer 172 in the first gate trench 150 and the second gate trench 152, respectively. Thus, the fabrication of a first metal gate structure 180 and a second metal gate structure 182 is completed in the first region 10 and the second region 12, respectively. Among them, only the first metal gate structure 180 has a germanium-containing function layer. In addition, in this embodiment, the interlayer dielectric layer 142 and the contact hole etch stop layer 140 can be selectively removed, and then the contact hole etch stop and the interlayer dielectric layer are sequentially formed to effectively improve the electrical performance of the semiconductor device. Since the above CMP process and the like are known to those of ordinary skill in the art, they are not described herein.

In summary, according to the method of fabricating a metal gate provided by the present invention, a germanium-containing function layer for use in a P-type semiconductor device is provided. In contrast to the case where the value of the P-type work function layer work function is generally adjusted using nitrogen or oxygen, the ruthenium-containing work function layer of the present invention can be boosted without increasing the gate leakage current (J _g ). The electrical behavior of the crystal structure, such as increasing the flat band voltage (V _fb ) and reducing the equivalent oxidation thickness. In addition to ensuring that the metal gates of the P-type semiconductor elements have a satisfactory work function, the electrical performance of the P-type semiconductor elements having the metal gates is further ensured.

10‧‧‧First area

12‧‧‧Second area

100‧‧‧Base

102‧‧‧Shallow trench isolation structure

104‧‧‧ dielectric layer

106‧‧‧gate dielectric layer

108‧‧‧Barrier layer

110‧‧‧etch stop layer

112‧‧‧First work function layer

120‧‧‧First lightly doped bungee

122‧‧‧Second lightly doped bungee

124‧‧‧ Sidewall

130‧‧‧First source/bungee

132‧‧‧Second source/bungee

134‧‧‧metal telluride

140‧‧‧Contact hole etch stop layer

142‧‧‧Interlayer dielectric layer

150‧‧‧First Gate Ditch

152‧‧‧Second gate ditches

Claims (20)

A metal gate structure includes: a gate dielectric layer; a conductive metal layer disposed on the gate dielectric layer; and a germanium function layer disposed on the gate dielectric layer and the conductive Between metal layers. The metal gate structure of claim 1, further comprising a barrier layer disposed between the gate dielectric layer and the germanium-containing function layer, wherein the barrier layer comprises titanium nitride . The metal gate structure of claim 2, further comprising an etch stop layer disposed between the barrier layer and the germanium-containing work function layer, wherein the composition of the etch stop layer comprises tantalum nitride. The metal gate structure of claim 1, wherein the work function value of the work function layer is greater than 4.9 electron volts (eV). The metal gate structure of claim 1, wherein the atomic ratio of titanium to germanium in the work function layer is between 1.5 and 4. The metal gate structure of claim 1, wherein the germanium atomic function layer has a germanium atomic percentage of between 10% and 30%. The metal gate structure of claim 1, wherein the composition of the work function layer further comprises oxygen. The metal gate structure according to claim 7, wherein the ratio of the number of atoms between titanium, germanium, nitrogen and oxygen in the work function layer is 28.9:13.2:46.8:10. The metal gate structure of claim 8, wherein the work function layer comprises a vertical portion and a horizontal portion. A method for fabricating a metal gate structure includes: providing a substrate covered with an interlayer dielectric layer; forming a gate trench in the interlayer dielectric layer; and having a gate dielectric layer in the gate trench Forming a work function layer on the gate dielectric layer in the gate trench; and filling a conductive metal layer in the gate trench. The method for fabricating a metal gate structure according to claim 10, wherein the method of forming the germanium-containing work function layer comprises an atomic layer deposition (ALD) process. The method of fabricating a metal gate structure according to claim 11, wherein the atomic layer deposition process comprises alternately providing a titanium precursor and a hafnium precursor onto the substrate. The method for fabricating a metal gate structure according to claim 10, wherein the work function value of the work function layer containing the work function is greater than 4.9 eV. The method for fabricating a metal gate structure according to claim 10, wherein the atomic ratio of titanium to germanium in the work function layer is between 1.5 and 4. The method for fabricating a metal gate structure according to claim 10, wherein the percentage of germanium atoms in the work function layer is between 10% and 30%. The method for fabricating a metal gate structure according to claim 10, wherein the composition of the work function layer further comprises oxygen. The method of fabricating a metal gate structure according to claim 10, wherein the germanium-containing function layer comprises a vertical portion and a horizontal portion. The method for fabricating a metal gate structure according to claim 10, further comprising forming a barrier layer disposed between the gate dielectric layer and the germanium-containing function layer, and the top barrier layer The composition includes titanium nitride. The method for fabricating a metal gate structure according to claim 18, further comprising an etch stop layer disposed between the barrier layer and the germanium-containing function layer, wherein the composition of the etch stop layer comprises nitriding Hey. The method for fabricating a metal gate structure according to claim 10, wherein after forming the germanium-containing work function layer, further comprising forming a top barrier layer disposed on the germanium-containing work function layer and the conductive metal Between the layers, and the composition of the top barrier layer includes titanium nitride.