TW201440173A - Buried word line dram and manufacturing method thereof - Google Patents

Abstract

A buried word line DRAM and manufacturing method thereof are provided. The buried word line DRAM includes a substrate, at least one buried word line structure, a first doped region, and a second doped region. The buried word line structure is disposed within the substrate. The first doped region is disposed within the substrate neighboring with the buried word line structure. The second doped region is disposed within the substrate above the first doped region, wherein the doping concentration of the first doped region is lower than the doping concentration of the second doped region.

Description

Buried word line dynamic random access memory and manufacturing method thereof

The present invention relates to a dynamic random access memory and a method of fabricating the same, and more particularly to a buried word line dynamic random access memory and a method of fabricating the same.

Dynamic random access memory is a kind of volatile memory, which is composed of a plurality of memory cells. Each memory cell is mainly composed of a transistor and a capacitor controlled by a transistor, and each of the memory cells is electrically connected to each other by a word line and a bit line.

In order to improve the accumulative degree of dynamic random access memory to speed up the operation speed of components and meet the needs of consumers for miniaturized electronic devices, buried word line dynamic random access memory (buried word) has been developed in recent years. Line DRAM) to meet the above needs.

However, conventional embedded word line dynamic random access memory uses a single ion concentration ion implantation process to form the source/drain, which is buried A higher electric field is generated below the gate of the input word line, thereby causing a higher gate to cause a drain current (GIDL current) and a buried word in the overlap region between the source/drain and the gate. The retention time of the dynamic random access memory of the meta-line.

The invention provides a buried word line dynamic random access memory and a manufacturing method thereof, which can improve the problem of high gate induced drain leakage current and short memory time.

The present invention provides a buried word line dynamic random access memory, comprising a substrate, at least one buried word line structure, a first doped region, and a second doped region. The buried word line structure is disposed in the substrate. The first doped region is disposed adjacent to the buried word line structure in the substrate. The second doped region is disposed in the substrate above the first doped region, wherein the doping concentration of the first doped region is lower than the doping concentration of the second doped region.

According to an embodiment of the present invention, in the embedded word line dynamic random access memory, the doping amount of the first doping region is 1.5×10 ¹² atoms/cm ² to 1.5×10 ^{13 .} Atom/cm ² .

According to an embodiment of the present invention, in the embedded word line dynamic random access memory, the doping amount of the second doping region is 1.5×10 ¹³ atoms/cm ² to 1.5×10 ^{14 .} Atom/cm ² .

According to an embodiment of the invention, the embedded character line is moved In the random access memory, the buried word line structure includes a buried word line and a gate dielectric layer. The embedded word line is disposed in the trench of the substrate. The gate dielectric layer is disposed on the bottom and the sidewall of the trench, wherein the buried word line is separated from the substrate by the gate dielectric layer.

According to an embodiment of the present invention, in the embedded word line dynamic random access memory, the buried word line structure further includes a lining layer, and the lining layer is disposed on the buried word line and Between the gate dielectric layers.

According to an embodiment of the present invention, in the buried word line dynamic random access memory, the interface between the first doped region and the second doped region has a depth in the substrate as a buried word. The depth of the top surface of the wire in the substrate.

The invention provides a method for manufacturing a buried word line dynamic random access memory, which comprises the following steps. A substrate is provided, and at least one buried word line structure is formed in the substrate. A first doped region adjacent to the buried word line structure is formed in the substrate. A second doped region is formed in the substrate, wherein the second doped region is formed over the first doped region, and a doping concentration of the first doped region is lower than a doping concentration of the second doped region.

According to an embodiment of the present invention, in the method for fabricating a buried word line dynamic random access memory, the doping amount of the first doping region is 1.5×10 ¹² atoms/cm ² to 1.5. ×10 ¹³ atoms/cm ² , and the doping amount of the second doping region is 1.5 × 10 ¹³ atoms / cm ² ~ 1.5 × 10 ¹⁴ atoms / cm ² .

According to an embodiment of the present invention, in the method for fabricating a buried word line dynamic random access memory, the doping energy provided when the first doped region is formed is greater than the second doped region. The doping energy provided at the time.

According to an embodiment of the present invention, in the method of fabricating a buried word line dynamic random access memory, the step of forming a buried word line structure includes the following steps. A trench is formed in the substrate. A gate dielectric layer is formed on the surface of the trench. A buried word line is formed on the gate dielectric layer.

According to an embodiment of the present invention, in the method for fabricating a buried word line dynamic random access memory, before forming the buried word line, a liner may be formed on the surface of the gate dielectric layer. .

Based on the above, in the embedded word line dynamic random access memory of the present invention, the first doped region and the second doped region having different doping concentrations are disposed in the substrate adjacent to the buried word line structure. a doped region, wherein the doping concentration of the first doped region is less than the doping concentration of the second doped region, and thus, without degrading source/drain conductivity and cell current of the memory , can effectively reduce the electric field below the corner of the gate edge of the buried word line, and thereby improve the higher gate induced buckling leakage current of the old embedded word line dynamic random access memory and Short memory time issues.

The above described features and advantages of the invention will be apparent from the following description.

10, 20‧‧‧ Buried word line dynamic random access memory

100, 200‧‧‧ substrate

102, 202‧‧‧ Buried word line structure

104, 204‧‧‧First doped area

106, 206‧‧‧Second doped area

108, 208‧‧‧ Buried word line

110, 210‧‧‧ gate dielectric layer

112, 212‧‧‧ lining

114, 214‧‧‧ Well Area

200a‧‧‧ Ditch

Doping concentration curve of 304, 306, 314‧‧

1 is a cross-sectional view showing a buried word line dynamic random access memory in accordance with an embodiment of the present invention.

2A to 2C are flowcharts showing a method of manufacturing a buried word line dynamic random access memory in an embodiment of the present invention.

3 is a graph showing a doping concentration profile of a doped region of a buried word line dynamic random access memory in an embodiment of the present invention.

1 is a cross-sectional view showing a buried word line dynamic random access memory in accordance with an embodiment of the present invention.

Referring to FIG. 1 , the buried word line dynamic random access memory 10 includes a substrate 100 , at least one buried word line structure 102 , a first doped region 104 , and a second doped region 106 . The material of the substrate 100 is, for example, single crystal germanium, polycrystalline germanium, amorphous germanium or other suitable material. In the present embodiment, the substrate 100 may further include a well region 114, which is generally disposed on the substrate 100. The well region 114 is, for example, a region doped with a P-type dopant or an N-type dopant, and the formation method of the well region 114 includes an ion implantation method.

The buried word line structure 102 is disposed in the substrate 100. In the present embodiment, the buried word line structure 102 includes a buried word line 108, a gate dielectric layer 110, and a liner layer 112. The buried word line 108 is disposed in the trench of the substrate 100. The material of the buried word line 108 is, for example, a transition metal conductor such as tungsten, tungsten telluride, or titanium nitride. The forming method is, for example, physical vapor deposition. Chemical vapor deposition or atomic layer vapor deposition. The gate dielectric layer 110 is disposed on the bottom and sidewalls of the trench in the substrate 100, wherein the buried word line 108 is separated from the substrate 100 by the gate dielectric layer 110. The material of the gate dielectric layer 110 is, for example, hafnium oxide, and the method for forming the same includes forming in the furnace tube. A process such as a thermal oxidation process. The liner 112 is disposed between the buried word line 108 and the gate dielectric layer 110. The material of the lining layer 112 includes transition metal nitrides such as titanium nitride, nitrided group, etc., and the forming method thereof is, for example, physical vapor deposition, chemical vapor deposition or atomic layer vapor deposition. The role of the liner 112 is to increase the adhesion between the buried word line 108 and the gate dielectric layer 110, thereby increasing the reliability of the embedded word line dynamic random access memory 10.

The first doped region 104 is disposed adjacent to the buried word line structure 102 and disposed in the substrate 100. The method of forming the first doping region 104 is, for example, ion implantation. The dopant of the first doping region 104 is, for example, an N-type dopant (such as phosphorus or arsenic, but not limited thereto) or a P-type dopant (such as boron). However, the doping is opposite to the P-type or N-type dopant of the well region 114, and the doping amount of the first doping region 104 is, for example, 1.5×10 ¹² atoms/cm ² to 1.5×10 ¹³ atoms. /cm ² .

The second doping region 106 is disposed in the substrate 100 on the first doping region 104. The method of forming the second doping region 106 is, for example, an ion implantation method, wherein the dopant of the second doping region 106 is, for example, an N-type dopant or a P-type dopant, and the dopant is the same as that of the first doping region 104. And the doping amount of the second doping region 106 is, for example, 1.5×10 ¹³ atoms/cm ² to 1.5×10 ¹⁴ atoms/cm ² . In the present embodiment, the depth of the interface between the first doping region 104 and the second doping region 106 in the substrate 100 is approximately the depth of the top surface of the buried word line 108 in the substrate 100, thereby reducing the The overlapping depth of the doped region 106 and the buried word line 108 can reduce the area of the high electric field region near the gate of the buried word line 108, and further reduce the drain leakage current caused by the gate. In addition, the decrease in the doping concentration of the first doping region 104 also reduces the electric field strength of the overlapping region of the first doping region 104 and the buried word line 108, thereby reducing the gate-induced drain leakage current. More specifically, compared to the conventional single doping concentration of the buried word line dynamic random access memory, since in the present embodiment, the second doping region 106 hardly has a good depth. The conductive buried word lines 108 overlap, and the dopant concentration of the overlapping regions of the first doped region 104 and the buried word line 108 is lowered, thereby reducing the gate caused by the buried word line 108. Extremely induced blander leakage current.

It is worth mentioning that since the doping concentration of the first doping region 104 is lower than the doping concentration of the second doping region 106, and the second doping region 106 is hardly in the depth with the buried word line 108 The overlap, so that the gate-induced drain leakage current of the buried word line dynamic random access memory 10 can be reduced without degrading the single cell current of the embedded word line dynamic random access memory 10. And thereby increasing the memory time of the embedded word line dynamic random access memory 10. In addition, compared to a conventional buried word line dynamic random access memory having only a single doped region, since the buried word line 108 is hardly in depth with the second doped region 106 overlaps, so in the case where the gate-to-source/drain capacitance can be reduced, the buried word line dynamic random access memory 10 of the present embodiment can provide the source/ The interlayer control of gate to source/drain further reduces the gate-to-source/drain coupling capacitance and further improves the coupling disturbance.

Based on the above embodiment, the doping concentration of the second doping region 106 is larger than that of the first doping region 104 and is hardly heavy with the buried word line 108. Stacking, so that the gate-induced drain leakage current of the buried word line dynamic random access memory 10 can be reduced without degrading the single cell current of the embedded word line dynamic random access memory 10. Therefore, the memory time of the embedded word line dynamic random access memory 10 is improved.

It should be noted that, in the present embodiment, for the sake of convenience of explanation, the embedded word line dynamic random access memory 10 has a buried word line structure 102 as an example, but the present invention does not. This is limited to this. In other embodiments, the embedded word line dynamic random access memory 10 can also have a plurality of buried word line structures 102, that is, as long as it has at least one buried word line structure 102. The scope of protection of the present invention. In addition, in the present embodiment, although the above-described buried word line structure 102 is used, the present invention is not limited thereto, and in other embodiments, other types of buried characters may be used. Line structure.

2A to 2C are flowcharts showing a method of manufacturing a buried word line dynamic random access memory in an embodiment of the present invention.

First, referring to FIG. 2A, a substrate 200 is provided. At least one buried word line structure 202 and a well region 214 are formed in the substrate 200. In the present embodiment, forming the buried word line structure 202 includes the following steps. A trench 200a is formed in the substrate 200. The trench 200a is formed by a dry etching or other anisotropic etching method. Then, a gate dielectric layer 210 is formed on the surface of the trench 200a of the substrate 200. The formation method of the layer 210 is, for example, a thermal oxidation process in a furnace tube; then, a liner layer 212 is selectively formed on the gate dielectric layer 210, and the formation method of the liner layer 212 is, for example, physical vapor deposition, chemistry. Vapor deposition or original Sublayer vapor deposition. Next, a buried word line 208 is formed on the surface of the liner 212. The method of forming the buried word line 208 is, for example, a physical vapor deposition method, a chemical vapor deposition method, or an atomic layer vapor deposition method. In the present embodiment, the liner 212 is formed between the buried word line 208 and the gate dielectric layer 210. However, the present invention is not limited thereto. In other embodiments, the buried word line 208 may be formed directly on the bottom and sidewalls of the trench 200a of the substrate 200 without forming the liner 212. The structure and formation method of the well region 214 is similar to the well region 114 of the above embodiment, and therefore will not be described herein.

Next, referring to FIG. 2B, a first doped region 204 adjacent to the buried word line structure 202 is formed in the substrate 200. The dopant of the first doping region 204 may be an N-type dopant, such as phosphorus or arsenic, but is not limited thereto; or the dopant of the first doping region 204 may be a P-type dopant, such as boron, but is not limited thereto. this. The doping of the first doping region 204 is generally opposite to the P-type or N-type dopant of the well region 114, and the first doping region 204 is formed by, for example, ion implantation, and the doping amount is about 1.5×10. ¹² atoms/cm ² ~ 1.5 × 10 ¹³ atoms/cm ² .

Then, referring to FIG. 2C, a second doping region 206 is formed in the substrate 200, wherein the second doping region 206 is formed on the first doping region 204, and the doping concentration of the first doping region 204 is lower than Doping concentration of the second doping region 206. The dopant of the second doping region 206 is the same as the dopant of the first doping region 204. In the present embodiment, the method of forming the second doping region 206 is, for example, performing ion implantation on the substrate 200 with a small doping energy, as compared with the method of forming the first doping region 204. A second doping region 206 having a doping amount of about 1.5 × 10 ¹³ atoms / cm ² to 1.5 × 10 ¹⁴ atoms / cm ² is formed on the first doping region 204. Further, since the second doping region 206 is directly formed on the first doping region 204, the second doping region 206 can be performed without additionally providing an additional photomask when forming the second doping region 206. The ion implantation process reduces the cost of the mask and is fully compatible with today's DRAM process technology. In addition, in the present embodiment, since the doping energy provided by the first doping region 204 is greater than the doping energy provided, the doping depth of the first doping region 204 in the substrate 200 can be ensured. Greater than the doping depth of the second doped region 206 in the substrate 200. In addition, the above doping energy can be appropriately adjusted to adjust the depth of the second doping region 206, thereby avoiding excessive overlap of the second doping region 206 and the buried word line 208, thereby causing gate buckling. Leakage current problem.

Then, the embedded word line dynamic random access memory 20 is completed by the process of the embedded word line dynamic random access memory which is well known to those skilled in the art, and will not be described herein. .

Based on the above embodiment, since the doping concentration of the second doping region 206 is formed in the substrate 200 above the first doping region 204, the first doping region 204 and the second doping may be performed by using the same photomask. The ion implantation process of the impurity region 206, so the process method can save the use cost of the photomask.

Instance

The process parameters of the original doping energy of 20KeV and the doping amount of 2.8×10 ¹³ atoms/cm ² were changed to the doping energy of the first doping region of 35KeV, and the doping amount was 1×10 ¹³ atoms/cm. ² ; the doping energy of the second doping region is 10 KeV, and the doping amount is 2.4×10 ¹³ atoms/cm ² . As a result, the memory time of the two doped regions having different doping concentrations can be improved by more than 40 milliseconds compared to the original doped region.

3 is a graph showing a doping concentration profile of a doped region of a buried word line dynamic random access memory in an embodiment of the present invention. The vertical axis of Fig. 3 indicates the depth of the embedded random word line dynamic random access memory, and the horizontal axis of Fig. 3 indicates the doping concentration corresponding to the above depth.

Referring to FIG. 3, curve 314 is the doping concentration curve of well region 114 in the embodiment of FIG. 1, curve 304 is the doping concentration curve of first doping region 104 in the embodiment of FIG. 1, and curve 306 is shown. The doping concentration curve of the second doping region 106 in the embodiment of FIG. 1 is shown. In practice, the doping concentration of FIG. 3 can be achieved by the following doping amount: the doping depth of the first doping region 106 is about 200 nm to 300 nm, and the corresponding doping amount is about 1.5×10 ¹² atoms/ Cm ² ~ 1.5 × 10 ¹³ atoms / cm ² ; the doping depth of the second doping region 106 is about 100 nm ~ 200 nm, and the corresponding doping amount is about 1.5 × 10 ¹³ atoms / cm ² ~ 1.5 × 10 ¹⁴ Atom/cm ² .

In summary, the above embodiment has at least the following features. The embedded word line dynamic random access memory proposed in the above embodiment can effectively reduce the buried character without degrading the unit current of the embedded word line dynamic random access memory. The gate of the line dynamic random access memory causes a drain leakage current, and further improves the memory time of the embedded word line dynamic random access memory. In addition, according to the manufacturing method of the present invention, two ion implantation processes with different doping energies can be performed by using the same mask to save the cost of the mask.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of protection of the present invention It is subject to the definition of the scope of the patent application attached.

10‧‧‧ Buried word line dynamic random access memory

100‧‧‧Substrate

102‧‧‧ Buried word line structure

104‧‧‧First doped area

106‧‧‧Second doped area

108‧‧‧Blinded word line

110‧‧‧gate dielectric layer

112‧‧‧ lining

114‧‧‧ Well Area

Claims (11)

A buried word line dynamic random access memory, comprising: a substrate; at least one buried word line structure disposed in the substrate; a first doped region adjacent to the buried word line a structure disposed in the substrate; and a second doped region disposed in the substrate above the first doped region, wherein a doping concentration of the first doped region is lower than the second doping Doping concentration of the impurity region. The embedded word line dynamic random access memory according to claim 1, wherein the doping amount of the first doping region is 1.5×10 ¹² atoms/cm ² to 1.5×10 ¹³ atoms. /cm ² . The embedded word line dynamic random access memory according to claim 1, wherein the doping amount of the second doping region is 1.5×10 ¹³ atoms/cm ² to 1.5×10 ¹⁴ atoms. /cm ² . The embedded word line dynamic random access memory according to claim 1, wherein the buried word line structure comprises: a buried word line disposed in a trench of the substrate And a gate dielectric layer disposed on a bottom and a sidewall of the trench, wherein the buried word line is separated from the substrate by the gate dielectric layer. The embedded word line dynamic random access memory according to claim 4, wherein the buried word line structure further comprises a lining layer, and the lining layer is disposed in the buried word Between the element line and the gate dielectric layer. The embedded word line dynamic random access memory according to claim 1, wherein the interface between the first doped region and the second doped region has a depth in the substrate The depth of the top surface of the buried word line in the substrate. A method for fabricating a buried word line dynamic random access memory, comprising: providing a substrate, wherein at least one buried word line structure is formed in the substrate; and forming the adjacent embedded type in the substrate a first doped region of the word line structure; and forming a second doped region in the substrate, wherein the second doped region is formed over the first doped region, and the first doping The doping concentration of the region is lower than the doping concentration of the second doping region. The method for manufacturing a buried word line dynamic random access memory according to claim 7, wherein the doping amount of the first doping region is 1.5×10 ¹² atoms/cm ² to 1.5×. 10 ¹³ atoms/cm ² , and the doping amount of the second doping region is 1.5×10 ¹³ atoms/cm ² to 1.5×10 ¹⁴ atoms/cm ² . The method for fabricating a buried word line dynamic random access memory according to claim 7, wherein the doping energy provided when forming the first doped region is greater than forming the second doping Doping energy provided by the zone. The method for manufacturing a buried word line dynamic random access memory according to claim 7, wherein the step of forming the buried word line structure comprises: Forming a trench in the substrate; forming a gate dielectric layer on a surface of the trench; and forming a buried word line on the gate dielectric layer. The method for manufacturing a buried word line dynamic random access memory according to claim 10, wherein before the forming the buried word line, forming a surface of the gate dielectric layer is further formed. lining.