JP2015207692A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the characteristics of a cell transistor sharing a bit line.SOLUTION: A semiconductor device comprises: an active region AR composed of a semiconductor substrate 10 partitioned by an element isolation region STI; impurity diffusion layers 11 to 13 provided in the active region AR; a gate electrode 22 provided between the impurity diffusion layers 11 and 12 via a gate insulating film 21; and a gate electrode 32 provided between the impurity diffusion layers 11 and 13 via a gate insulating film 31. The impurity diffusion layers 12 and 13 are composed of a part of the semiconductor substrate 10. At least a part of the impurity diffusion layer 11 is composed of polysilicon. According to the present invention, the impurity diffusion layer 11 is composed of polysilicon, so impurity diffusion to the impurity diffusion layers 12 and 13 can be suppressed even when the impurity concentration is increased.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a cell transistor and a manufacturing method thereof.

  In a cell transistor provided in a semiconductor device such as a DRAM (Dynamic Random Access Memory), one of source / drain regions is connected to a memory element, and the other of the source / drain regions is connected to a bit line. For example, in the semiconductor device described in Patent Document 1, three impurity diffusion layers are provided in one active region, and two impurity diffusion layers located at both ends are respectively connected to the cell capacitor, and 1 located at the center. Two impurity diffusion layers are connected to the bit line. A gate trench is provided between adjacent impurity diffusion layers, and a gate electrode is embedded therein.

  In recent years, further miniaturization of semiconductor devices has progressed, and accordingly, the interval between two gate trenches has become narrower. When the interval between the gate trenches is narrowed, a phenomenon occurs in which the characteristics of the other cell transistor change depending on the potential of the gate electrode constituting the one cell transistor. This is because the potential of the gate electrode affects the impurity diffusion layer located in the center, thereby changing the surface potential of the transistor.

  FIG. 16 is a graph showing the relationship between the gate electrode interval and the threshold value of the cell transistor. In FIG. 16, what is plotted with a square is the threshold when a voltage of 2.6 V (on voltage) is applied to the gate electrode of an adjacent cell transistor, and plotted with a cross This shows the threshold value when a voltage of 0 V (off voltage) is applied to the gate electrode of the adjacent cell transistor. The same applies to FIG.

  As shown in FIG. 16, when the gap between the gate electrodes is narrowed to 25 nm or less, the threshold value when a voltage (ON voltage) of 2.6 V is applied to the gate electrode of the adjacent cell transistor, and the adjacent cell It can be seen that the threshold values differ greatly when a voltage of 0 V (off voltage) is applied to the gate electrode of the transistor. This means that when one cell transistor is turned on, the threshold value of the other cell transistor adjacent to the cell transistor is lowered, and the information retention characteristic is lowered due to an increase in off-leakage current. In order to suppress the off-leakage current, the gate voltage at the time of off may be lowered, but in this case, the electric field between the gate and the drain becomes strong and the refresh characteristic is deteriorated.

  FIG. 17 is a graph showing the relationship between the gate electrode spacing and the subthreshold coefficient.

  As shown in FIG. 17, when the gap between the gate electrodes is narrowed to 25 nm or less, the subthreshold coefficient in the case where a voltage (ON voltage) of 2.6 V is applied to the gate electrode of the adjacent cell transistor, and the adjacent cell It can be seen that the subthreshold coefficients differ greatly when a voltage of 0 V (off voltage) is applied to the gate electrode of the transistor. This is because when the cell transistor is changed from OFF to ON, the depleted central impurity diffusion layer (impurity diffusion layer connected to the bit line) needs to be inverted by the gate voltage, whereas the adjacent cell This is because the impurity diffusion layer is easily inverted when the transistor is already turned on.

  In order to suppress the depletion of the impurity diffusion layer due to the reduction in the distance between the gate electrodes, it is effective to increase the impurity concentration of the central impurity diffusion layer connected to the bit line.

JP 2012-234964 A

  However, when the impurity concentration of the impurity diffusion layer connected to the bit line is increased, the dopant implanted by ion implantation diffuses into the impurity diffusion layers on both ends. As a result, the junction electric field of the impurity diffusion layer connected to the cell capacitor becomes strong, and the refresh characteristics may be deteriorated.

  The semiconductor device according to the present invention includes an active region made of a semiconductor substrate partitioned by an element isolation region, first, second, and third impurity diffusion layers provided in the active region, and the first and second A first gate electrode provided between the impurity diffusion layers via a first gate insulating film; and a second gate provided between the first and third impurity diffusion layers via a second gate insulating film. An electrode, wherein the second and third impurity diffusion layers are constituted by a part of the semiconductor substrate, and at least a part of the first impurity diffusion layer is constituted by polysilicon. .

  A method of manufacturing a semiconductor device according to the present invention includes a step of forming a first trench in a semiconductor substrate, and a step of forming a first impurity diffusion layer by filling at least part of the first trench with polysilicon. Forming a second and a third impurity diffusion layer on the semiconductor substrate, forming a first gate electrode between the first and second impurity diffusion layers via a first gate insulating film, Forming a second gate electrode between the first and third impurity diffusion layers with a second gate insulating film interposed therebetween.

  According to the present invention, since one impurity diffusion layer is made of polysilicon, diffusion of impurities into the other impurity diffusion layer can be suppressed even when the impurity concentration is increased. .

1 is a cross-sectional view for explaining the structure of a semiconductor device 100 according to a first embodiment of the present invention. 3 is a graph showing a relationship between a gate electrode interval and a cell transistor threshold in the semiconductor device 100. 4 is a graph showing a relationship between a gate electrode interval and a subthreshold coefficient in a semiconductor device 100. 4A and 4B are process diagrams for explaining a manufacturing method of the semiconductor device 100, where FIG. 5A is a cross-sectional view, and FIG. 4A and 4B are process diagrams for explaining a manufacturing method of the semiconductor device 100, where FIG. 5A is a cross-sectional view, and FIG. 4A and 4B are process diagrams for explaining a manufacturing method of the semiconductor device 100, where FIG. 5A is a cross-sectional view, and FIG. It is sectional drawing for demonstrating the structure of the semiconductor device 200 by the 2nd Embodiment of this invention. It is sectional drawing for demonstrating the structure of the semiconductor device 300 by the 3rd Embodiment of this invention. FIG. 11 is a process diagram for describing the method for manufacturing the semiconductor device 300. FIG. 11 is a process diagram for describing the method for manufacturing the semiconductor device 300. It is process drawing for demonstrating the manufacturing method of the semiconductor device by the 4th Embodiment of this invention. It is process drawing for demonstrating the manufacturing method of the semiconductor device by the 4th Embodiment of this invention. It is process drawing for demonstrating the manufacturing method of the semiconductor device by the 5th Embodiment of this invention. It is process drawing for demonstrating the manufacturing method of the semiconductor device by the 5th Embodiment of this invention. It is process drawing for demonstrating the manufacturing method of the semiconductor device by the 5th Embodiment of this invention. It is a graph which shows the relationship between the space | interval of the gate electrode in a general semiconductor device, and the threshold value of a cell transistor. It is a graph which shows the relationship between the space | interval of the gate electrode in a general semiconductor device, and a subthreshold coefficient.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that the drawings used in the following description are for explaining the configuration of the embodiment of the present invention, and the size, thickness, dimensions, and the like of each part shown in the drawings are different from the dimensional relationship of an actual semiconductor device. There is.

  FIG. 1 is a cross-sectional view for explaining the structure of a semiconductor device 100 according to the first embodiment of the present invention.

  The semiconductor device 100 according to the present embodiment is a DRAM, and FIG. 1 shows a portion corresponding to one active region AR formed in the memory cell array region. The active region AR is a part of the p-type semiconductor substrate 10 partitioned by the element isolation region STI. In the active region AR, three n-type impurity diffusion layers 11 to 13 are provided. Among these, the impurity diffusion layer 11 is located at the center in the longitudinal direction of the active region AR, and the impurity diffusion layers 12 and 13 are located at both ends in the longitudinal direction of the active region AR.

  The semiconductor substrate 10 located between the impurity diffusion layer 11 and the impurity diffusion layer 12 is provided with a gate trench TR2. A gate electrode 22 is embedded in the gate trench TR2 via a gate insulating film 21. A gate cap insulating film 23 is disposed on the gate electrode 22. With this configuration, the impurity diffusion layers 11 and 12 and the gate electrode 22 form a MOS type cell transistor having the semiconductor substrate 10 located at the bottom of the gate trench TR2 as a channel. The gate electrode 22 is used as a word line.

  Similarly, the semiconductor substrate 10 located between the impurity diffusion layer 11 and the impurity diffusion layer 13 is provided with a gate trench TR3. A gate electrode 32 is embedded in the gate trench TR3 via a gate insulating film 31. A gate cap insulating film 33 is disposed on the gate electrode 32. With this configuration, the impurity diffusion layers 11 and 13 and the gate electrode 32 constitute a MOS cell transistor having the semiconductor substrate 10 located at the bottom of the gate trench TR3 as a channel. The gate electrode 22 is used as a word line.

  The impurity diffusion layer 11 is not formed of a part of the semiconductor substrate 10 but is formed of polysilicon buried in the trench TR1 formed in the semiconductor substrate 10. The polysilicon constituting the impurity diffusion layer 11 is doped with n-type impurities. The impurity diffusion layer 11 is connected to the bit line BL. The upper surface and side surfaces of the bit line BL are covered with an insulating film 41.

  On the other hand, the impurity diffusion layers 12 and 13 are formed of a part of the semiconductor substrate 10. The impurity diffusion layers 12 and 13 are connected to contact plugs 51 and 61, respectively. Side surfaces of the contact plugs 51 and 61 are covered with an insulating film 41.

  The bit line BL and the contact plugs 51 and 61 are embedded in the interlayer insulating film 42. On the surface of the interlayer insulating film 42, contact pads 52 and 62 connected to contact plugs 51 and 61, respectively, are provided. The contact pads 52 and 62 are connected to the lower electrodes 53 and 63 of the cell capacitor. The surfaces of the lower electrodes 53 and 63 are covered with the upper electrode 72 of the cell capacitor via the capacitive insulating film 71.

  With this configuration, the lower electrode 53, the capacitive insulating film 71, and the upper electrode 72 constitute one cell capacitor C1, and the lower electrode 63, the capacitive insulating film 71, and the upper electrode 72 constitute the other cell capacitor C2. The bit line BL is commonly assigned to the cell capacitors C1 and C2.

  As described above, in the semiconductor device 100 according to the present embodiment, the impurity diffusion layers 12 and 13 connected to the contact plugs 51 and 61 are made of single crystal silicon which is a part of the semiconductor substrate 10, whereas the bit line The impurity diffusion layer 11 connected to BL is made of polysilicon buried in the trench TR1. The impurity concentration of the impurity diffusion layer 11 is set to be higher than the impurity concentration of the impurity diffusion layers 12 and 13, thereby depleting the impurity diffusion layer 11 even when the distance between the gate trenches TR 2 and TR 3 is narrow. Can be suppressed.

In this embodiment, since the impurity diffusion layer 11 is made of polysilicon, it is not necessary to perform ion implantation into the impurity diffusion layer 11. For this reason, the impurity concentration of the impurity diffusion layers 12 and 13 is not affected. In addition, since the diffusion coefficient of the dopant such as arsenic (As) is larger in the polysilicon than in the single crystal silicon, the diffusion of the dopant from the impurity diffusion layer 11 is also suppressed.
Because.

  FIG. 2 is a graph showing the relationship between the gate electrode spacing and the cell transistor threshold in the semiconductor device 100. In FIG. 2, what is plotted with a circle indicates a threshold value when a 2.6 V voltage (ON voltage) is applied to the gate electrode of an adjacent cell transistor, and is plotted with a + mark. This shows the threshold value when a voltage of 0 V (off voltage) is applied to the gate electrode of the adjacent cell transistor. The same applies to FIG.

  As shown in FIG. 2, in the semiconductor device 100 according to the present embodiment, the threshold value when a voltage (ON voltage) of 2.6 V is applied to the gate electrode of the adjacent cell transistor, and the gate of the adjacent transistor. It can be seen that the threshold values when the voltage of 0 V (off voltage) is applied to the electrodes substantially match. For this reason, even if one cell transistor is turned on, the threshold value of the other cell transistor adjacent to the one cell transistor does not change, thereby preventing a decrease in information retention characteristics due to an increase in off-leakage current.

  FIG. 3 is a graph showing the relationship between the gate electrode spacing and the subthreshold coefficient in the semiconductor device 100.

  As shown in FIG. 3, in the semiconductor device 100 according to the present embodiment, the sub-threshold coefficient in the case where a voltage (ON voltage) of 2.6 V is applied to the gate electrode of the adjacent cell transistor, and the adjacent cell transistor It can be seen that the subthreshold coefficients when the voltage of 0 V (off voltage) is applied to the gate electrode substantially match.

  As described above, since the semiconductor device 100 according to the present embodiment can increase the impurity concentration of the impurity diffusion layer 11 without substantially affecting the impurity diffusion layers 12 and 13, good transistor characteristics can be obtained. It becomes possible.

  Next, the method for fabricating the semiconductor device 100 according to the present embodiment will be explained with reference to FIGS. 4-6, (a) is sectional drawing along the AA line shown to (b).

  First, as shown in FIG. 4, the semiconductor substrate 10 made of single crystal silicon is thermally oxidized to form a silicon oxide film 14 having a thickness of 10 nm on the surface 10A of the semiconductor substrate 10. Next, after patterning the silicon oxide film 14 in a line shape by photolithography, the semiconductor substrate 10 is etched using the patterned silicon oxide film 14 as a mask. As a result, a trench TR1 having a depth of about 180 nm is formed in the semiconductor substrate 10 in a line shape.

Next, polysilicon doped with arsenic (As) is deposited by CVD to fill the trench TR1 with the impurity diffusion layer 11 made of polysilicon. The concentration of arsenic (As) is, for example, 1 × 10 ²⁰ atm / cm ³ . Then, by using the CMP method or the like, unnecessary polysilicon formed on the upper surface of the silicon oxide film 14 is removed, so that polysilicon remains only in the trench TR1.

  Next, as shown in FIG. 5, a trench is formed in a portion where the element isolation region STI is to be formed, and this trench is filled with silicon oxide, thereby forming the element isolation region STI. Thereby, a portion of the semiconductor substrate 10 surrounded by the element isolation region STI in plan view becomes the active region AR. In the central portion in the longitudinal direction of the active region AR, there is an impurity diffusion layer 11 embedded in the trench TR1.

  Next, as shown in FIG. 6, two gate trenches TR <b> 2 and TR <b> 3 that cross the active region AR are formed in the semiconductor substrate 10. The depth of the gate trenches TR2 and TR3 is, for example, 200 nm. The gate trenches TR2 and TR3 are formed along both ends of the impurity diffusion layer 11. Thereby, the semiconductor substrate 10 and the impurity diffusion layer 11 are separated in the lateral direction via the gate trenches TR2 and TR3.

  Next, impurity diffusion layers 12 and 13 are formed on the surface of the semiconductor substrate 10 by ion implantation of n-type impurities such as arsenic (As). Then, as shown in FIG. 1, after forming the gate insulating films 21 and 31 on the inner walls of the gate trenches TR2 and TR3, the gate electrodes 22 and 32 are embedded, and further the gate cap insulating films 23 and 33 are embedded. Thereafter, the bit line BL, the contact plugs 51 and 61, the contact pads 52 and 62, the cell capacitors C1 and C2, and the like are formed using a known process, whereby the semiconductor device 100 according to the present embodiment is completed.

  As described above, the semiconductor device 100 according to the present embodiment can be manufactured by forming the trench TR1 in the semiconductor substrate 10 before forming the element isolation region STI and adding the step of filling the trench TR1 with polysilicon. It is.

  FIG. 7 is a cross-sectional view for explaining the structure of a semiconductor device 200 according to the second embodiment of the present invention.

  The semiconductor device 200 according to the present embodiment is different from the semiconductor device 100 according to the first embodiment shown in FIG. 1 in that an impurity diffusion layer 11A is provided in the semiconductor substrate 10 located at the bottom of the gate trenches TR2 and TR3. It is different. Since other configurations are the same as those of the semiconductor device 100 according to the first embodiment, the same elements are denoted by the same reference numerals, and redundant description is omitted.

  The impurity diffusion layer 11 </ b> A is a region formed by diffusing n-type impurities such as arsenic (As) in the semiconductor substrate 10. The impurity diffusion layer 11 </ b> A is in contact with the impurity diffusion layer 11 made of polysilicon, and thus can be regarded as a part of the impurity diffusion layer 11. With this configuration, only the portions along the side walls of the gate trenches TR2 and TR3 can function as the channel of the cell transistor.

  In the semiconductor device 200 according to the present embodiment, after forming the gate trenches TR2 and TR3 in the semiconductor substrate 10 and before forming the gate electrodes 22 and 32, a step of performing ion implantation inside the gate trenches TR2 and TR3 is added. Can be produced.

  FIG. 8 is a cross-sectional view for explaining the structure of a semiconductor device 300 according to the third embodiment of the present invention.

  The semiconductor device 300 according to the present embodiment is in accordance with the first embodiment shown in FIG. 1 in that the impurity diffusion layer 11 is constituted by a portion 11B made of polysilicon and a portion 11C made of a part of the semiconductor substrate 10. This is different from the semiconductor device 100. Since other configurations are the same as those of the semiconductor device 100 according to the first embodiment, the same elements are denoted by the same reference numerals, and redundant description is omitted.

  The impurity diffusion layer 11B made of polysilicon is made of polysilicon buried in the trench TR1, like the impurity diffusion layer 11 in the first embodiment. On the other hand, the impurity diffusion layer 11C formed of a part of the semiconductor substrate 10 is a portion formed by diffusing n-type impurities such as arsenic (As) into the semiconductor substrate 10 located at the bottom of the trench TR1. The impurity diffusion layer 11B made of polysilicon and the impurity diffusion layer 11C made of a part of the semiconductor substrate 10 are in contact with each other, whereby one impurity diffusion layer 11 is configured.

  A method for manufacturing the semiconductor device 300 according to the present embodiment is as follows.

  First, as described with reference to FIG. 4, the trench TR <b> 1 is formed in the semiconductor substrate 10 by etching the semiconductor substrate 10 using the patterned silicon oxide film 14 as a mask. At this time, the depth of the trench TR1 is set shallower than that in the first embodiment.

  Then, after forming the element isolation region STI, as shown in FIG. 9, an n-type impurity 91 such as arsenic (As) is ion-implanted into the bottom of the trench TR1. Thereby, an impurity diffusion layer 11C is formed in the semiconductor substrate 10 located at the bottom of the trench TR1. Thereafter, as shown in FIG. 10, if the impurity diffusion layer 11B is formed by burying the trench TR1 with polysilicon doped with impurities, the impurity diffusion layer 11 is completed.

  Thus, in the semiconductor device 300 according to the present embodiment, since the depth of the trench TR1 can be set shallow, it is easy to bury polysilicon. For this reason, even if there is a problem in the embedding property of the polysilicon in the trench TR1, it can be easily manufactured. Further, the impurity implanted into the impurity diffusion layer 11C formed of a part of the semiconductor substrate 10 is diffused also in the lateral direction of the semiconductor substrate 10, but the diffused region is removed in the process of forming the gate trenches TR2 and TR3. Therefore, the impurity diffusion layers 12 and 13 are hardly affected.

  11 and 12 are cross-sectional views for explaining a manufacturing process of a semiconductor device according to the fourth embodiment of the present invention.

  In the manufacturing process of the semiconductor device according to the present embodiment, first, the trench TR1 is formed in the semiconductor substrate 10 by etching the semiconductor substrate 10 using the patterned silicon oxide film 14 as a mask, as shown in FIG. An insulating film 80 is formed on the sidewall. The insulating film 80 can be left only on the side wall portion of the trench TR1 by, for example, depositing silicon oxide on the entire surface including the inner wall of the trench TR1 by a CVD method and then performing etch back. Alternatively, the insulating film 80 may be formed by thermally oxidizing the semiconductor substrate 10.

  Next, as shown in FIG. 12, the impurity diffusion layer 11 is formed by embedding the trench TR1 with polysilicon doped with n-type impurities. Thereafter, when the steps described with reference to FIGS. 5 and 6 are performed, the semiconductor device according to the present embodiment is completed. Here, since the insulating film 80 provided on the sidewall of the trench TR1 is completely removed when forming the gate trenches TR2 and TR3, the configuration of the completed semiconductor device is the same as that of the first embodiment.

  According to the present embodiment, since the sidewall of the trench TR1 is covered with the insulating film 80 until an intermediate step, it is possible to prevent the diffusion of impurities from the impurity diffusion layer 11 made of polysilicon into the semiconductor substrate 10. .

  13 to 15 are cross-sectional views for explaining a manufacturing process of a semiconductor device according to the fifth embodiment of the present invention.

  In the manufacturing process of the semiconductor device according to the present embodiment, as shown in FIG. 13, the trench TR1 is formed in the semiconductor substrate 10 by etching the semiconductor substrate 10 using the patterned silicon oxide film 14 as a mask, and then non-doped. By depositing polysilicon, the inside of trench TR1 is filled with non-doped polysilicon 11D.

  Next, after performing the steps described with reference to FIGS. 5 and 6, as shown in FIG. 14, the semiconductor substrate 10 is covered with a mask 90 exposing the polysilicon 11 </ b> D, and arsenic (As) or the like is used. An n-type impurity 91 is ion-implanted. As the mask 90, a mask used for forming the bit line BL can be used as it is. The energy at the time of ion implantation is preferably low enough to be implanted above the polysilicon 11D so that the impurity diffusion layers 12 and 13 are not affected.

  Thereafter, if heat treatment such as RTA treatment is performed, the implanted n-type impurity 91 is diffused into the polysilicon 11D, and as shown in FIG. 15, an impurity diffusion layer 11 made of polysilicon can be obtained. Here, since polysilicon has a larger diffusion coefficient of a dopant such as arsenic (As) than single crystal silicon, diffusion of n-type impurity 91 implanted into polysilicon 11D into semiconductor substrate 10 is sufficiently suppressed. . For this reason, the impurity contained in the polysilicon 11D hardly reaches the impurity diffusion layers 12 and 13. Further, since the depth of the impurity diffusion layer 11 is substantially defined by the depth of the trench TR1, the impurity diffusion layer 11 can be formed to a depth as designed.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

  For example, the transistor described in each of the above embodiments has a structure in which the gate electrode is embedded in the gate trench, but the present invention is not limited thereto, and the transistor has a fin-type structure channel. It does not matter.

DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 10A Semiconductor substrate surface 11-13, 11A-11C Impurity diffusion layer 11D Non-doped polysilicon 14 Silicon oxide film 21, 31 Gate insulating film 22, 32 Gate electrode 23, 33 Gate cap insulating film 41 Insulating film 42 Interlayer Insulating film 51, 61 Contact plug 52, 62 Contact pad 53, 63 Lower electrode 71 Capacitor insulating film 72 Upper electrode 80 Insulating film 90 Mask 91 N-type impurity 100, 200, 300 Semiconductor device AR Active region BL Bit lines C1, C2 Cell Capacitor STI Element isolation region TR1 Trench TR2, TR3 Gate trench

Claims (15)

An active region made of a semiconductor substrate partitioned by an element isolation region;
First, second and third impurity diffusion layers provided in the active region;
A first gate electrode provided between the first and second impurity diffusion layers via a first gate insulating film;
A second gate electrode provided between the first and third impurity diffusion layers via a second gate insulating film,
The second and third impurity diffusion layers are constituted by a part of the semiconductor substrate;
A semiconductor substrate, wherein at least a part of the first impurity diffusion layer is made of polysilicon.   2. The semiconductor device according to claim 1, wherein at least a part of the first impurity diffusion layer is embedded in a first trench formed in the active region.   3. The first impurity diffusion layer according to claim 2, wherein a lower portion of the first impurity diffusion layer is formed of a part of the semiconductor substrate and an upper portion of the first impurity diffusion layer is formed of the polysilicon buried in the first trench. Semiconductor device. The active region has second and third trenches;
The first gate insulating film and the first gate electrode are provided inside the second trench,
4. The semiconductor device according to claim 1, wherein the second gate insulating film and the second gate electrode are provided inside the third trench. 5.   5. The semiconductor device according to claim 4, wherein the first impurity diffusion layer has a portion made of a part of the semiconductor substrate located at a bottom portion of the second and third trenches.   6. The semiconductor device according to claim 1, wherein an impurity concentration of the first impurity diffusion layer is higher than an impurity concentration of the second and third impurity diffusion layers. A bit line connected to the first impurity diffusion layer;
A first cell capacitor connected to the second impurity diffusion layer;
The semiconductor device according to claim 6, further comprising a second cell capacitor connected to the third impurity diffusion layer. Forming a first trench in a semiconductor substrate;
Forming a first impurity diffusion layer by filling at least a portion of the first trench with polysilicon;
Forming second and third impurity diffusion layers in the semiconductor substrate;
A first gate electrode is formed between the first and second impurity diffusion layers via a first gate insulating film, and a first gate electrode is formed between the first and third impurity diffusion layers via a second gate insulating film. And a step of forming a second gate electrode. Forming a second trench and a third trench in the semiconductor substrate;
The first gate insulating film and the first gate electrode are provided inside the second trench,
9. The method of manufacturing a semiconductor device according to claim 8, wherein the second gate insulating film and the second gate electrode are provided in the third trench.   After forming the second and third trenches and before forming the first and second gate electrodes, a step of implanting ions into the semiconductor substrate located at the bottom of the second and third trenches. The method for manufacturing a semiconductor device according to claim 9, further comprising:   11. The semiconductor substrate according to claim 8, wherein the step of forming the first impurity diffusion layer is performed by embedding polysilicon containing a dopant in the first trench. Production method.   The step of forming the first impurity diffusion layer is performed by implanting polysilicon containing a dopant into the first trench after ion implantation into the semiconductor substrate located at the bottom of the first trench. The method for manufacturing a semiconductor substrate according to claim 8, wherein the method is a semiconductor substrate manufacturing method.   11. The step of forming the first impurity diffusion layer is performed by implanting non-doped polysilicon into the first trench and then implanting ions into the polysilicon. A method for manufacturing a semiconductor substrate according to claim 1.   14. The method according to claim 8, further comprising a step of covering a sidewall of the first trench with an insulating film after forming the first trench and before filling the first trench with polysilicon. A manufacturing method of a semiconductor device given in any 1 paragraph. Forming a bit line connected to the first impurity diffusion layer;
The method further includes: forming first and second cell capacitors connected to the second and third impurity diffusion layers, respectively. A method for manufacturing a semiconductor device.

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