TW201436472A - Apparatus and method for parallel type SAR ADC - Google Patents

Abstract

An apparatus for parallel type SAR (Successive Approximation Register) ADC (Analog to Digital Converter) is disclosed. The apparatus for parallel type SAR ADC includes two switches, two capacitor arrays, a compare module, a fast buffer, a slow buffer, a delay buffer, and a control logic module. The switches, the capacitor arrays, and the compare module are electrically connected. The compare module is to produce a compare signal. The slow buffer is to accept the compare signal and to produce a ValidSlow signal. The fast buffer is to accept the compare signal and to produce a ValidFast signal. The delay buffer is to accept the compare signal and to produce a ValidLoop signal to reset the compare module. The control logic module is to accept the ValidFast signal and the ValidSlow signal to control the voltage of the capacitors of the capacitor arrays.

Description

Parallel signal type progressive analog digital converter and method

The present invention relates to a progressive analog digital converter and method, and more particularly to a parallel signal type progressive analog digital converter and method.

With the advancement of technology, electronic technology and equipment play an increasingly important role in modern life. The processing of various types of data: sound, temperature, light, pressure, and signal can be seen in applications processed by electronic devices. Electronic devices usually only process electronic digital signals, so analog to digital converters (ADCs) have emerged.

The main function of the analog-to-digital converter is to convert the natural analog signal into a digital signal that can be processed by electronic devices. Among them, the Progressive Approximation Register (SAR) analog digital converter (ADC) is recognized as having low power consumption, but Since the architecture of the SAR ADC itself requires multiple comparison cycles, which limits its conversion speed, traditional SAR ADCs have been limited to low power and low speed. use.

In recent years, with the improvement of architecture and process, SAR ADC has also begun to develop high-speed applications, especially the timing-interleaved architecture is more often used in high-speed analog digital converters. The basic working principle of SAR ADC is to use binary method to find the resolution of each bit. Therefore, it needs a bit cycling clock higher than the sampling frequency to achieve 10 bits. For example, in the case of a bit cycle clock that is more than 10 times the sampling frequency, in order to avoid the high-speed clock passing through the entire wafer, an asynchronous bit cycling clock is born.

However, even though the conventional SAR ADC has overcome many problems and speeds up compared with the initial development period, it is still limited by the fact that its architecture needs to be compared multiple times, and in order to operate normally in each comparison, every next comparison is made. It is necessary to delay enough time to ensure that the input signal can pass through the SAR ADC circuit. This delay time also limits the speed of the SAR ADC. The delay time becomes a higher speed bottleneck for the development of SAR ADC.

Accordingly, it is an object of the present invention to provide a parallel signal type progressive analog digital converter and method for high speed progressive analog digital conversion.

According to an embodiment of the present invention, a parallel signal type progressive analog digital converter is provided, which comprises a two switch, a two capacitor array, and a a comparison module, a fast buffer, a slow buffer, a delay buffer, and a control logic module, wherein each capacitor array is electrically connected to each switch, and each capacitor array has a plurality of capacitors, and the comparison module has two inputs. a terminal, an output terminal and a comparison clock terminal, each input terminal is electrically connected to each capacitor array, the comparison module is used to generate a comparison signal; the fast buffer is electrically connected to the output end of the comparison module, and the fast buffer device There is a fast buffer time, the fast buffer is used to receive the comparison signal and generate an effective fast signal, the effective fast signal is used to switch the capacitance of the two capacitor array; the slow buffer is electrically connected to the output of the comparison module, and the slow buffer has a slow Buffer time, and the slow buffer time is longer than the fast buffer time. The slow buffer is used to receive the comparison signal and generate a valid slow signal. The effective slow signal is used to trigger the switching of the capacitors of the two capacitor array. The delay buffer is electrically connected to the comparison module. The output buffer and the comparison clock terminal have a delay buffer time and delay The buffering time is shorter than the slow buffering time and longer than the fast buffering time. The delay buffer receives the comparison signal from the output terminal and generates an effective loop signal, and the comparison clock terminal of the comparison module is configured to receive the effective loop signal to reset the comparison. The control logic module is electrically connected to the fast buffer, the slow buffer and the two capacitor array, and the control logic module receives the effective fast signal and the effective slow signal to generate the complex switching signals, and the switching signals are used to control the two capacitor arrays. The voltage value of those capacitors.

According to the above parallel signal type progressive analog digital converter, wherein the switch can be a bootstrap switch, the comparison module can include a comparator and a comparator reverse gate, wherein the comparator has two comparison outputs and two inputs. And comparing the clock terminals, the comparator is used to generate two comparison output signals, each comparison The output signals are respectively outputted to the comparison outputs, and the comparators are connected to the comparators and the comparison outputs are generated.

According to the above parallel signal type progressive analog digital converter, wherein the control logic module can include a cyclic clock generator, a logic unit, a complex driver and a complex switch, wherein the cyclic clock generator is configured to receive a slow buffer generation The effective slow signal and a preset sampling clock signal, and generate an ordered complex cyclic clock signal, those cyclic clock signals are used to trigger those capacitors that switch the two capacitor array, the logic unit and the fast buffer, the cyclic clock The comparator and the comparator are electrically connected to the comparison output, and the logic unit is configured to receive the comparison output signals, the cyclic clock signals, the preset sampling clock signals, and the effective fast signals generated by the flash buffer, and generate the logic units. The plurality of bit signals are electrically connected to the logic unit for receiving the bit signals and generating the plurality of driving signals. The switches are electrically connected to the drivers, and the switches are used to receive the driving signals and generate the switching signals. . The cyclic clock generator can be a D-type flip-flop array.

According to the above-mentioned parallel signal type progressive analog digital converter, a comparison clock module can be further included, which is electrically connected to the delay buffer, the cyclic clock generator and the comparison clock of the comparison module, and compares the clock. The module includes a comparison clock inverse gate and a comparison clock reverse gate, and the comparison clock reverse gate is used to receive the preset sampling clock signal, the effective loop signal generated by the delay buffer, and the cyclic clock generator. The last one of the cyclic clock signals is generated, and a comparison clock reverse signal or signal is generated, and the clock reverse gate is electrically connected to the clock reverse gate or the gate to receive the comparison clock signal or signal. A comparison clock signal is used to compare the clock signal to the comparison clock terminal of the comparison module to reset the comparison module.

According to another embodiment of the present invention, a parallel signal type progressive analog digital converter includes a two switch, a two capacitor array, a comparison module, a fast buffer, a slow buffer, a delay buffer, and a a cyclic clock generator, a logic unit, a complex driver, a complex switch, and a comparison clock module, wherein each capacitor array is electrically connected to each switch, and each capacitor array has a plurality of capacitors, and the comparison module has two inputs. And an output terminal and a comparison clock end, each input end is electrically connected to each capacitor array, and the comparison module is configured to generate two comparison output signals and perform a comparison signal by inversely calculating the two comparison output signals; The buffer is electrically connected to the output end of the comparison module, the fast buffer has a fast buffer time, and the fast buffer is used to receive the comparison signal and generate an effective fast signal; the slow buffer is electrically connected to the output end of the comparison module, and is slowly buffered. Has a slow buffer time, and the slow buffer time is longer than the fast buffer time, and the slow buffer is used to receive the comparison. And generate a valid slow signal; the delay buffer is electrically connected to the output of the comparison module and the comparison clock end, the delay buffer has a delay buffer time, and the delay buffer time is shorter than the slow buffer time and longer than the fast buffer time, the delay The buffer receives the comparison signal from the output end and generates an effective loop signal, and the comparison clock terminal of the comparison module is configured to receive the effective loop signal to reset the comparison module; the loop clock generator is configured to receive the slow buffer generation The effective slow signal and a preset sampling clock signal, and generate an ordered complex cyclic clock signal, those cyclic clock signals are used to trigger those capacitors that switch the two capacitor array; logic unit and fast The buffer, the comparison module and the cyclic clock generator are electrically connected, and the logic unit is configured to receive the comparison output signals, the cyclic clock signals, the preset sampling clock signals, and the effective fast signals generated by the fast buffer, and generate The plurality of bit signals; the drivers are electrically connected to the logic unit, the drivers are used to receive the bit signals and generate the plurality of driving signals; the switches are electrically connected to the drivers, and the switches are used to receive the driving signals and generate the complex signals. Switching signals, those switching signals are used to control the voltage values of those capacitors of the two-capacitor array; comparing the time-pulse modules of the clock-connecting module electrically connecting the delay buffer, the cyclic clock generator and the comparison module to compare the clock modes The group is configured to receive a preset sampling clock signal, an effective loop signal generated by the delay buffer, and a last one of the cyclic clock signals generated by the cyclic clock generator, and generate a comparison clock signal for input to the comparison. The module compares the clock end to reset the comparison module.

According to the above parallel signal type progressive analog digital converter, wherein the switch can be a bootstrap switch, and the cyclic clock generator can be a D-type flip-flop array.

According to still another embodiment of the present invention, a parallel signal type progressive analog digital conversion method is provided, comprising the steps of: performing a comparison step of converting a two input signal into a comparison signal through a comparison module, delaying the comparison signal A fast buffering time generates an effective fast signal, and a preparation capacitor step is performed. The preparation capacitor step delays the comparison signal by a slow buffering time to generate a valid slow signal, wherein the slow buffering time is longer than the fast buffering time, by effectively slowing the signal Triggering switching the complex capacitance of the two capacitor arrays, performing a progressive conversion step, progressive conversion The step of generating a complex switching signal by using the effective fast signal and the effective slow signal, and performing a comparator step by preparing the comparator to control the voltage value of the capacitors of the two capacitor array, preparing the comparator step to delay the comparison signal by a delay buffer The time generates an effective loop signal, wherein the delay buffer time is shorter than the slow buffer time and longer than the fast buffer time, and the comparison module is reset by the effective loop signal.

According to the above parallel signal type progressive analog digital conversion method, the comparing step may further include converting the two input signals into a second comparison output signal through a comparator, and performing a reverse and logical operation on each of the comparison output signals to generate a comparison. Signal.

According to the above parallel signal type progressive analog digital conversion method, the step of preparing the capacitance may further comprise generating an ordered complex cyclic clock signal by combining the effective slow signal with a preset sampling clock signal, and by using the cyclic clock. The signal triggers switching those capacitors of the two capacitor array.

According to the above parallel signal type progressive analog digital conversion method, the progressive conversion step may further include converting each comparison output signal into one of an effective fast signal, a preset sampling clock signal, and one of those cyclic clock signals. The bit signal converts the bit signal into a driving signal, and converts the driving signal into one of those switching signals. The switching signal switches one of those capacitors of the two capacitor array to control the voltage values of those capacitors of the two capacitor array. The voltage value of the two capacitor array is used as a two-input signal.

According to the above parallel signal type progressive analog digital conversion method, the step of preparing the comparator may further comprise generating an effective loop signal with a preset sampling clock signal and a last one of the cyclic clock signals. Comparing the clock signals, the clock signals are compared to the comparison module to reset the comparison module.

It can be seen from the above that the parallel signal type progressive analog digital converter and the parallel signal type analog analog digital conversion method of the present invention use a two-way parallel asynchronous clock to complete the conversion process of the progressive analog digital converter, so that each time The trigger signal required for the conversion is ready in the last comparison cycle, so that the time for waiting for the trigger signal for each conversion can be saved, thereby increasing the sampling frequency of the analog digital conversion to achieve high-speed performance.

110, 120‧‧‧ switch

111, 112‧‧‧ contacts

210‧‧‧First Capacitor Array

211, 212‧‧‧ contacts

220‧‧‧Second capacitor array

300‧‧‧Comparative Module

301‧‧‧output

310‧‧‧ Comparator

311‧‧‧ first input

312‧‧‧ second input

313‧‧‧First comparison output

314‧‧‧Second comparison output

315‧‧‧Compared with the clock

320‧‧‧ Comparator reverse gate

400‧‧‧Quick buffer

401, 402‧‧‧Contacts

500‧‧‧ Slow buffer

600‧‧‧Delay buffer

700‧‧‧Control logic module

710‧‧‧Cycle clock generator

711‧‧‧D type flip-flop

720‧‧‧Logical unit

721‧‧‧Logical unit and gate

722‧‧‧Logical unit D type flip-flop

730‧‧‧ drive

731, 732‧‧‧ contacts

740‧‧‧Switcher

741, 742‧‧‧ contacts

800‧‧‧Compared Clock Module

810‧‧‧Compare clock reverse or gate

820‧‧‧Compare clock reverse gate

S101~S107‧‧‧Steps

S910‧‧‧Compare steps

S920‧‧‧ Generate effective fast signal steps

S930‧‧‧Preparation of capacitance steps

S940‧‧‧Preparation of comparator steps

S950‧‧‧ Progressive conversion steps

S960‧‧‧Next cycle steps

Biti‧‧ bits

Clk(i+1)‧‧‧cycle clock signal

The last of the Clk12‧‧‧ cycle signals

Clki‧‧‧One of the loop signals

Clkc‧‧·Compare clock signal

Clkcb‧‧‧Compare clock or signal

Clks‧‧‧Preset sampling clock signal

Outp‧‧‧First comparison output signal

Outn‧‧‧Second comparison output signal

Spi, Sni‧‧‧ bit signal

Vip, Vin‧‧‧ input signal

ValidPre‧‧‧ comparison signal

ValidFast‧‧‧ effective fast signal

ValidSlow‧‧‧ effective slow signal

ValidLoop‧‧‧effective loop signal

FIG. 1 is a schematic diagram showing the architecture of a parallel signal type progressive analog digital converter according to an embodiment of the present invention.

FIG. 2 is a schematic diagram showing the conversion process of the parallel signal type progressive analog digital converter according to FIG. 1.

Fig. 3 is a circuit diagram showing the switch of Fig. 1.

4 is a circuit layout diagram of the first capacitor array of FIG. 1.

Fig. 5 is a circuit diagram showing the comparator of Fig. 1.

Fig. 6 is a circuit diagram showing the fast buffer of Fig. 1.

Fig. 7 is a circuit diagram showing the cyclic clock generator of Fig. 1 and the comparison clock reverse gate.

Figure 8 is a circuit diagram showing the logic unit of Figure 1.

Figure 9 is a timing chart showing the signals in Figures 7 and 8.

Fig. 10 is a circuit diagram showing the driver of Fig. 1.

Fig. 11 is a circuit diagram showing the switch of Fig. 1.

FIG. 12 is a flow chart showing a parallel signal type progressive analog digital conversion method according to still another embodiment of the present invention.

Referring to FIG. 1 , a schematic diagram of a parallel signal type progressive analog digital converter according to an embodiment of the present invention is shown. The present embodiment uses a 10-bit parallel signal progressive analog digital converter as an example, but The number of bits of the actual application can be varied by the person having ordinary knowledge in the art as needed.

The parallel signal type analog analog digital converter shown in FIG. 1 includes two switches 110 and 120, a first capacitor array 210, a second capacitor array 220, a comparison module 300, a fast buffer 400, and a a slow buffer 500, a delay buffer 600, a control logic module 700, and a comparison clock module 800, wherein the first capacitor array 210 is electrically connected to the switch 110, and the second capacitor array 220 is electrically connected to the switch 120, A capacitor array 210 and a second capacitor array 220 each have a plurality of capacitors. The first capacitor array 210 provides an input signal Vip from the voltage value of the capacitor to the comparison module 300, and the second capacitor array 220 has a voltage value of the capacitor. An input signal Vin is provided to the comparison module 300.

The comparison module 300 has a second input end, an output end 301 and a comparison clock end 315. The two input ends are respectively a first input end 311 and a second input end 312, and the first input end 311 is electrically connected. A capacitor array 210 is used to receive the input signal Vip, and the second input terminal 312 is electrically connected. The second capacitor array 220 is connected to receive the input signal Vin. The comparison module 300 is configured to generate a comparison signal ValidPre at the output terminal 301. In more detail, the comparison module 300 includes a comparator 310 and a comparator inverse gate 320. The comparator 310 has two comparison outputs, two input terminals and a comparison clock terminal 315, wherein the two input terminals are respectively the foregoing The first input terminal 311 and the second input terminal 312, the second comparison output terminals are a first comparison output terminal 313 and a second comparison output terminal 314, respectively, and the comparator 310 is configured to generate a first comparison output signal Outp at the first Comparing the output terminal 313 and the second comparison output signal Outn to the second comparison output terminal 314, the comparator and the gate 320 are electrically connected to the first comparison output terminal 313 and the second comparison output terminal 314 of the comparator 310, so that the first The comparison output signal Outp and the second comparison output signal Outn pass through the comparator reverse gate 320 and generate a comparison signal ValidPre at the output terminal 301.

The fast buffer 400 is electrically connected to the output terminal 301 of the comparison module 300, and the fast buffer 400 has a fast buffer time. The fast buffer 400 is configured to receive the comparison signal ValidPre and generate a valid fast signal ValidFast. The effective fast signal ValidFast is used to switch the capacitance of the first capacitor array 210 or the second capacitor array 220, the mechanism of which will be detailed later with the control logic module 700.

The slow buffer 500 is electrically connected to the output terminal 301 of the comparison module 300. The slow buffer 500 has a slow buffer time, and the slow buffer time is longer than the fast buffer time. The slow buffer 500 is used to receive the comparison signal ValidPre and generate a slow response. Signal ValidSlow. The effective slow signal ValidSlow is used to trigger the switching of the first capacitor array 210 or the second capacitor The capacitance of the array 220, the mechanism of which will be described in detail later in the control logic module 700.

The delay buffer 600 is electrically connected to the output terminal 301 of the comparison module 300. The delay buffer 600 has a delay buffer time, and the delay buffer time is shorter than the slow buffer time and longer than the fast buffer time. The delay buffer 600 receives from the output terminal 301. Compare the signal ValidPre and generate a valid loop signal ValidLoop. The loop signal ValidLoop is used to input to the comparison clock module 800 to reset the comparison module 300. The mechanism will be detailed later with the comparison clock module 800.

The control logic module 700 is electrically connected to the fast buffer 400, the slow buffer 500, the first capacitor array 210 and the second capacitor array 220. The control logic module 700 receives the valid fast signal ValidFast and the valid slow signal ValidSlow to generate a complex switching signal. These switching signals are used to control the voltage values of those capacitors of the first capacitor array 210 and the second capacitor array 220 for progressive analog digital conversion.

In more detail, the control logic module 700 includes a cyclic clock generator 710, a logic unit 720, a complex driver 730, and a complex switch 740. The loop clock generator 710 is configured to receive a preset sampling clock signal Clks. And the effective slow signal ValidSlow generated by the slow buffer 500, and generates an ordered complex cyclic clock signal Clk(i+1), and the cyclic clock signals Clk(i+1) are used to trigger the switching of the first capacitor array 210. And the capacitors of the second capacitor array 220; the logic unit 720 is electrically connected to the comparison buffers 313 and 314 of the fast buffer 400, the cyclic clock generator 710, and the comparator 310, and the logic unit 720 is configured to receive each ratio The output signal Outp or Outn, the cyclic clock signal Clk(i+1), the preset sampling clock signal Clks, and the valid fast signal ValidFast generated by the fast buffer 400, and generate a complex bit signal; each driver 730 respectively The switch 740 is electrically connected to each of the drivers 730, and the switch 740 is configured to receive the drive signals and generate the foregoing, and the driver 730 is electrically connected to the logic unit 720. Those switching signals are used to control the voltage values of those capacitors of the first capacitor array 210 and the second capacitor array 220.

The comparison clock module 800 is electrically connected to the comparison clock terminal 315 of the delay buffer 600, the cyclic clock generator 710, and the comparison module 300, and the comparison clock module 800 receives the effective loop signal from the delay buffer 600. The ValidLoop generates a comparison clock signal Clkc output to the comparison clock terminal 315 of the comparison module 300 for resetting the comparison module 300. In more detail, the comparison clock module 800 includes a comparison clock inverse gate 810 and a comparison clock reverse gate 820. The comparison clock inverse gate 810 is configured to receive a preset sampling clock signal Clks and a delay buffer. The effective loop signal generated by 600, ValidLoop, and the last one of the cyclic clock signals Clk(i+1) generated by the cyclic clock generator 710, Clk12, and a comparison clock reverse signal or signal Clkcb, compare clock reverse The gate 820 is electrically connected to the clock reverse gate 810 for receiving the comparison clock inverse signal Clkcb, and generates the comparison clock signal Clkc to be input to the comparison clock terminal 315 of the comparison module 300 to reset the comparison. Module 300.

Referring to FIG. 2, it is a schematic diagram showing a conversion flow of a parallel signal type progressive analog digital converter according to FIG. After the start, step S101 is performed, and the comparison module 300 compares and determines whether the input signal Vip input by the first capacitor array 210 is greater than the input signal Vin input by the second capacitor array 220, and is not used in the first comparison period. You need to switch any capacitors to start the comparison. If the result of the determination in step S101 is YES, that is, if the input signal Vip is greater than the input signal Vin, proceeding to step S102, the bit Biti compared with the comparison period is set to 1, and step S103 is performed to switch the first capacitor array. The capacitance of 210 changes the capacitance value, so that the input signal Vip in the switched first capacitor array 210 becomes the original input signal Vip-Vref/2 ⁱ , where Vref is the voltage value range of the parallel signal type progressive analog digital converter, and The input signal Vin in the second capacitor array 220 remains unchanged, and then proceeds to step S106; if the result of the determination in step S101 is no, that is, if the input signal Vip is not greater than the input signal Vin, then proceeding to step S104, the comparison is performed. The bit Biti of the cycle is set to 0, and step S105 is performed to switch the capacitance of the second capacitor array 220 to change the capacitance value, so that the input signal Vin in the switched second capacitor array 220 becomes the original input signal Vin-Vref/ 2 ⁱ , wherein Vref is a voltage value range of the parallel signal type progressive analog digital converter, and the input signal Vip in the first capacitor array 210 remains unchanged, and then proceeds to step S106. Step S106 determines that i=N, where N represents a parallel signal type progressive analog digital converter sharing N bits, so step S106 is used to determine whether the currently compared i-th bit is the last bit, for example, as shown in FIG. The implementation is 10 bits, then N = 10, which means that a total of 10 comparisons will be made. If the result of step S106 is no, that is, if the comparison is not completed, then step S107 is performed, setting i to i+1 to continue the comparison of the next bit, and returning to step S101 to continue; if the result of step S106 is YES, That is to say, after completing the comparison of all the bits, it stops and completes the parallel signal type progressive analog digital conversion.

Referring to FIG. 3, a circuit diagram of the switch 110 of FIG. 1 is shown. Both the switch 110 and the switch 120 can use the bootstrap switch as shown in FIG. 3. Here, only the switch 110 is taken as an example. The contact 111 of the switch 110 receives a preset preset sampling clock signal Clks as a signal for triggering the switch 110, and the contact 112 outputs a switching signal to the first capacitor array 210. In addition, the switch 120 can use the same or similar structure as the switch 110, wherein the other switching signal of the open 120 output is transmitted to the second capacitor array 220, which is not shown here. The switch 110 and the switch 120 may alternatively be MOS switches or other switches, and are not limited to the boot band switches of the present embodiment.

Referring to FIG. 4, which is a circuit layout diagram of the first capacitor array 210 of FIG. 1, the second capacitor array 220 and the first capacitor array 210 can use the circuit layout as shown in FIG. This is only illustrated by taking the first capacitor array 210 as an example. The contact 211 of the first capacitor array 210 is electrically connected to the contact 112 of the switch 110 in FIG. 3, and the contact 211 is used for receiving the switching signal from the contact 112, and is electrically connected to the comparison module by the contact 212. The first input terminal 311 of the second capacitor array 220 can use the same or similar circuit layout as the first capacitor array 210, and the second capacitor array receives the switching signal from the switch 120 and is electrically connected to the comparison module 300. Second input 312.

Referring to FIG. 5, a circuit diagram of the comparator 310 of the comparison module 300 in FIG. 1 is shown, wherein the signal from the first capacitor array 210 is input from the first input terminal 311 to the comparator 310 from the second capacitor. Array The signal of the column 220 is input from the second input terminal 312 to the comparator 310, and the comparison clock terminal 315 is configured to receive the comparison clock signal Clkc to reset the comparator 310. The first comparison output signal Outp is from the first comparison output terminal 313. The second comparison output signal Outn is electrically connected to the comparator opposite gate 320 from the second comparison output terminal 314, and the comparison signal ValidPre is outputted to the output terminal 301 via the comparator reverse gate 320. .

Referring to FIG. 6 , it is a circuit diagram of the fast buffer 400 of FIG. 1 , wherein the fast buffer 400 , the slow buffer 500 , and the delay buffer 600 can adopt a circuit diagram similar to that shown in FIG. 6 . This is exemplified by the fast buffer 400. The contact 401 of the fast buffer 400 is electrically connected to the output terminal 301 of the comparison module 300 and receives the comparison signal ValidPre, and delays a fast buffer time by the circuit shown in FIG. 6, generating an effective fast signal ValidFast to the contact 402, which is fast. The contact 402 of the buffer 400 is electrically connected to the logic unit 720 of the control logic module 700; the slow buffer 500 is electrically connected to the output terminal 301 of the comparison module 300, accepts the comparison signal ValidPre and delays a slow buffer time, and generates The effective slow signal ValidSlow is electrically connected to the cyclic clock generator 710 of the logic module 700; the delay buffer 600 is electrically connected to the output terminal 301 of the comparison module 300, receives the comparison signal ValidPre and delays a delay buffer time, and generates The valid loop signal ValidLoop is electrically coupled to the compare clock inverse gate 810 of the comparison clock module 800.

Referring to FIG. 7, a circuit diagram of the cyclic clock generator 710 and the comparison clock inverse gate 810 of FIG. 1 is illustrated, wherein the cyclic clock generator 710 can be composed of a D-type flip-flop 711. D-type flip-flop The array, the cyclic clock generator 710 receives the preset sampling clock signal Clks and the valid slow signal ValidSlow, and sequentially generates the cyclic clock signal Clk(i+1), where i represents the bit currently being compared, and Clki uses In order to trigger the switching of the capacitance of the first capacitor array 210 or the second capacitor array 220, the cyclic clock signal Clk(i+1) is used to trigger the switching of the first capacitor array 210 or the second capacitor array 220 in the next comparison period. Capacitance, so the capacitor trigger signal in the next comparison cycle can be prepared in the previous comparison cycle, so the parallel signal type analog analog converter of this example can save the delay time of the waiting capacitor trigger signal, thereby improving A parallel signal analog progressive analog converter with a sampling frequency for high speed applications. In the embodiment, the 10-bit is taken as an example, so that the high potentials of the cyclic clock signals Clk1, Clk2, Clk3, ..., Clk12 are sequentially generated, wherein the Clk12 is electrically connected to the comparison clock of the comparison clock module 800. Or gate 810 is used to generate a comparison clock signal Clkc.

Please refer to FIG. 1 , FIG. 2 and FIG. 8 together. FIG. 8 is a circuit diagram of the logic unit 720 of FIG. 1 . The logic unit 720 can include a logic unit and a gate 721 and a logic unit D-type flip-flop 722. The logic unit and the gate 721 receive the cyclic clock signal Clki from the cyclic clock generator 710 and the effective fast from the fast buffer 400. The signal ValidFast is electrically connected to the logic unit D-type flip-flop 722. The input and output of the logic unit D-type flip-flop 722 are related to the determination result of step S101 in FIG. 2, first, taking the result of the determination in step S101 as an example, and representing that the input signal Vip is greater than the input signal Vin, the logic unit The D-type flip-flop 722 accepts the output of the logic unit and the gate 721, and the first comparison loses The first comparison output signal Outp of the output 313, the preset sampling clock signal Clks, and the bit signal Spi and the bit Biti are generated, wherein Biti is 1; if the judgment result of step S101 in FIG. 2 is no, the representative The input signal Vip is not greater than the input signal Vin, and the logic unit D-type flip-flop 722 receives the output of the logic unit and the gate 721, the second comparison output signal Outn of the second comparison output 314, and the preset sampling clock signal Clks, and A bit signal Sni and a bit Biti are generated, where Biti is 0.

Please refer to FIG. 1 , FIG. 7 , FIG. 8 and FIG. 9 together. FIG. 9 is a timing diagram of signals in FIG. 7 and FIG. 8 , including preset sampling clock signal Clks and comparison time. Pulse signal Clkc, effective fast signal ValidFast, effective slow signal ValidSlow, cyclic clock signal Clk1, cyclic clock signal Clk1 and valid fast signal ValidFast through the logic unit and gate 721 after the signal Clk1 & ValidFast, cyclic clock signal Clk2, cycle time The pulse signal Clk2 and the fast signal ValidFast jointly pass the signal Clk2 & ValidFast after the logic unit and the gate 721, the cyclic clock signal Clk9, the cyclic clock signal Clk10, the cyclic clock signal Clk11 and the last one of the cyclic clock signals Clk12. It can be seen that the preset sampling clock signal Clks makes the contact Qb of the first D-type flip-flop 711 as shown in FIG. 7 set to "1", that is, the cyclic clock signal Clk1 is generated, and other D-type positive and negative The device is reset to "0"; with the switching of the valid slow signal ValidSlow, the signal of 1 is sequentially transmitted, that is, the cyclic pulse signal Clk2 to the cyclic pulse signal Clk11 sequentially generate a high potential, that is, the cyclic pulse signal Clk2 The cycle clock signal Clk11 is set to "1" in sequence; when the signal of "1" is transmitted to Clk11, the last one of the cyclic clock signals generated by the last D-type flip-flop Clk12 is set to "1", and the value of the modified clock signal Clkc is corrected to be high, and one cycle is completed; when the high potential of the pulse signal Clks is generated for the next preset sampling, all D-type flip-flops are generated. Go back to the initial value and start the next cycle.

Continuing to refer to FIG. 10, which is a circuit diagram of the driver 730 of FIG. 1, wherein the contact 731 is electrically connected to the logic unit 720 and receives the bit signal Spi or Sni in FIG. 8, and the contact 732 is electrically connected. The switch 740 is connected. Each driver 730 is electrically connected to each switch 740 for triggering the switch 740 to trigger the switching capacitor.

Referring to FIG. 1 , FIG. 4 and FIG. 11 together, FIG. 11 is a circuit diagram of the switch 740 of FIG. 1 , wherein the contact 741 is electrically connected to the driver 730 , and the contact 742 is electrically connected to the first capacitor. A contact 211 of one of the capacitors of the array 210 or the second capacitor array 220, wherein each capacitor of the first capacitor array 210 and the second capacitor array 220 is electrically connected to a switch 740, and the switch 740 is used to switch capacitors. To change the voltage value of the capacitor, thereby changing the voltage value of the input signal Vip of the first capacitor array 210 where the capacitor is located, or changing the voltage value of the input signal Vin of the second capacitor array 220 where the variable capacitance is located, and at each bit In the comparison period, only one switch 740 switches a capacitor.

As can be seen from the above embodiments of the present invention, the delay buffer time of the delay buffer 600 needs to be longer than the fast buffer time of the fast buffer 400, but the delay buffer time can be approximately equal to the fast buffer time and only slightly longer to maintain the signal. Stable, while achieving a fairly short delay; again through the effective loop signal generated by the delay buffer 600 ValidLoop The comparison module 300 is set, so the reset of the comparison module 300 of the next cycle can be completed in the previous cycle, so that no additional time is required to wait for the reset of the comparator, so that the parallel signal type analog analog digital converter is realized. The required delay time can be reduced to a relatively fast speed; the effective slow signal ValidSlow generated by the slow buffer 500 can trigger the switching of the capacitance of the next bit comparison period, saving the delay time of waiting for the capacitor trigger preparation.

According to the above embodiment, the comparison module 300 can take 150 ps (picoseconds), the fast buffer 400 can have a fast buffer time of 70 ps, the logic unit 720 can take 110 ps, and the driver 730 can take At 80 ps, the time taken by the switch 740 can be 50 ps, so the total delay time taken to convert one bit per comparison can be 310 ps, which is greatly reduced compared to the prior art, and thus the sampling frequency according to one embodiment of the present invention. Up to 167 MS/s (million times per second), the following table shows a specification sheet based on an example of the present invention compared to the prior art specification sheet:

It can be seen from the above table that an embodiment according to the present invention performs better than the prior art, and in particular, the sampling frequency is greatly improved compared to the prior art.

Referring to FIG. 12 and the above description together, FIG. 12 is a flow chart showing a parallel signal type progressive analog digital conversion method according to still another embodiment of the present invention. After the start, a comparison step S910 is performed to convert the two input signals into two comparison output signals through a comparator, and each of the comparison output signals is subjected to a reverse logic operation to generate a comparison signal.

Then, an effective fast signal generating step S920, a preparation capacitor step S930, and a preparation comparator step S940 are generated, and an effective fast signal is generated. Step S920 is to delay the comparison signal by a fast buffering time to generate an effective fast signal ValidFast; the preparing capacitor step S930 is to be performed. Comparative signal delay Slowly buffering time to generate a valid slow signal, wherein the slow buffering time is longer than the fast buffering time, and the effective slow signal is matched with a preset sampling clock signal to generate an ordered complex cyclic clock signal Clk(i+1), The capacitors of the two capacitor arrays are triggered by the cyclic pulse signals Clk(i+1); the comparator step S940 is configured to delay the comparison signal by a delay buffer time to generate an effective loop signal, wherein the delay buffer time is shorter than The slow buffer time is longer than the fast buffer time. The effective loop signal is matched with the preset sampling clock signal and the last one of the cyclic clock signals Clk(i+1) to generate a comparison clock signal Clkc, which will compare the clock. The signal Clkc is input to the comparison module to reset the comparison module.

The progressive conversion step S950 performs the analog-to-digital conversion of the one-bit element by using the effective fast signal ValidFast generated by the effective fast signal step S920 and the cyclic clock signal Clk(i+1) generated by the preparatory capacitance step S930, including each Comparing the output signal with the valid fast signal ValidFast, the preset sampling clock signal and one of the cyclic clock signals Clk(i+1), Clki, into a one-dimensional signal and one bit Biti, converting the bit signal into Driving the signal, converting the driving signal into a switching signal, switching the signal to switch one of the capacitors of the two capacitor array to control the voltage values of the capacitors of the two capacitor array, and using the voltage value of the two capacitor array as the two input signals of the comparator .

The next cycle step S960 is performed to determine whether the comparison conversion of all the bits has been completed. If the comparison conversion of all the bits is not completed, the process returns to the comparison step S910 to continue, and if the comparison conversion of all the bits has been completed, the process ends.

In summary, the parallel signal type progressive analogy of the present invention is applied. The digital converter and the parallel signal type progressive analog digital conversion method prepare the signal required for the next one-dimensional comparison period in advance, thereby shortening the necessary delay time, thereby greatly increasing the sampling frequency, achieving high speed, and maintaining the progressive analog digital converter. The advantage of low power, while achieving the advantages of low power and high speed.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and modified without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.

110, 120‧‧‧ switch

210‧‧‧First Capacitor Array

220‧‧‧Second capacitor array

300‧‧‧Comparative Module

301‧‧‧output

310‧‧‧ Comparator

311‧‧‧ first input

312‧‧‧ second input

313‧‧‧First comparison output

314‧‧‧Second comparison output

315‧‧‧Compared with the clock

320‧‧‧ Comparator reverse gate

400‧‧‧Quick buffer

500‧‧‧ Slow buffer

600‧‧‧Delay buffer

700‧‧‧Control logic module

710‧‧‧Cycle clock generator

720‧‧‧Logical unit

730‧‧‧ drive

740‧‧‧Switcher

800‧‧‧Compared Clock Module

810‧‧‧Compare clock reverse or gate

820‧‧‧Compare clock reverse gate

Claims (14)

A parallel signal type progressive analog digital converter comprising: two switches; two capacitor arrays, each of which is electrically connected to each of the switches, and each of the capacitor arrays has a plurality of capacitors; and a comparison module has two An input terminal, an output terminal and a comparison clock terminal, each of the input terminals being electrically connected to each of the capacitor arrays, wherein the comparison module is configured to generate a comparison signal; and a fast buffer electrically connected to the comparison module The fast buffer has a fast buffer time for receiving the comparison signal and generating an effective fast signal, the effective fast signal is used to switch the capacitors of the two capacitor array; a slow buffer The slow buffer has a slow buffering time, and the slow buffering time is longer than the fast buffering time. The slow buffer is configured to receive the comparison signal and generate a valid slow signal. The effective slow signal is used to trigger the switching of the capacitors of the two capacitor arrays; a delay buffer electrically connected to the comparison And the output buffer and the comparison clock end, the delay buffer has a delay buffer time, and the delay buffer time is shorter than the slow buffer time and longer than the fast buffer time, the delay buffer receives the comparison from the output end The signal generates an effective loop signal, and the comparison clock terminal is configured to receive the effective loop signal to reset the comparison module; and a control logic module electrically connected to the fast buffer, the slow The buffer and the two capacitor arrays, the control logic module receives the valid fast signal and the effective slow signal to generate a plurality of switching signals, and the switching signals are used to control voltage values of the capacitors of the two capacitor arrays. A parallel-signal progressive analog digital converter according to claim 1, wherein the switch is a bootstrap switch. The parallel signal type analog analog digital converter of claim 1, wherein the comparison module comprises: a comparator having two comparison outputs, the two input terminals and the comparison clock terminal, wherein the comparator is configured to generate two Comparing the output signals, each of the comparison output signals is respectively outputted to each of the comparison output terminals; and a comparator is connected to the gate, and is electrically connected to the two comparison output terminals to generate the comparison signal. The parallel signal type analog analog digital converter of claim 3, wherein the control logic module comprises: a cyclic clock generator for receiving the valid slow signal generated by the slow buffer and a predetermined sampling clock And generating an ordered plurality of cyclic clock signals, wherein the cyclic clock signals are used to trigger switching of the capacitors of the two capacitor arrays; a logic unit, the fast buffer, the loop clock generator, and the The two comparison output terminals of the comparator are electrically connected, and the logic unit is configured to receive each of the comparison output signals, the cyclic clock signals, and the preset sampling time. a pulse signal and the valid fast signal generated by the fast buffer, and generating a complex bit signal; a plurality of drivers electrically connected to the logic unit for receiving the bit signals and generating a complex driving signal; and a plurality of switchers Each of the switches is electrically connected to each of the drivers, and the switches are configured to receive the driving signals and generate the switching signals. The parallel signal type progressive analog digital converter of claim 4, wherein the cyclic clock generator is a D-type flip-flop array. The parallel-signal progressive analog-to-digital converter of claim 4, further comprising: a comparison clock module electrically connected to the delay buffer, the cyclic clock generator, and the comparison module The pulse clock module includes: a comparison clock reverse gate or a gate for receiving the preset sampling clock signal, the effective loop signal generated by the delay buffer, and the loop clock generator generating The last one of the cyclic clock signals, and a comparison clock reverse signal or signal; and a comparison clock reverse gate, which is electrically connected to the comparison clock reverse gate or the gate to receive the comparison clock reverse Or the signal generates a comparison clock signal, and the comparison clock signal is input to the comparison clock end of the comparison module to reset the comparison module. A parallel signal type progressive analog digital converter comprising: two switches; two capacitor arrays, each of which is electrically connected to each of the switches, and each of the capacitor arrays has a plurality of capacitors; and a comparison module has two An input end, an output end, and a comparison clock end, each of the input ends is electrically connected to each of the capacitor arrays, wherein the comparison module is configured to generate two comparison output signals and inversely calculate the two comparison output signals. Generating a comparison signal; a fast buffer electrically connected to the output end of the comparison module, the fast buffer having a fast buffer time, the fast buffer for receiving the comparison signal and generating an effective fast signal; a buffer electrically connected to the output end of the comparison module, the slow buffer has a slow buffer time, and the slow buffer time is longer than the fast buffer time, the slow buffer is configured to receive the comparison signal and generate an effective slow a delay buffer electrically connected to the output of the comparison module and the comparison clock end, the delay buffer a delay buffering time, and the delay buffering time is shorter than the slow buffering time and longer than the fast buffering time, the delay buffer receives the comparison signal from the output end and generates an effective loop signal, and the comparison clock end uses Receiving the effective loop signal to reset the comparison module; a loop clock generator for receiving the valid slow signal generated by the slow buffer and a preset sampling clock signal, and generating an ordered complex number Looping clock signals, the cyclic clock signals are used to trigger switching of the two capacitors The logic unit is electrically connected to the fast buffer, the comparison module, and the cyclic clock generator, and the logic unit is configured to receive each of the comparison output signals, the cyclic clock signals, The preset sampling clock signal and the valid fast signal generated by the fast buffer, and generating a complex bit signal; the plurality of drivers are electrically connected to the logic unit for receiving the bit signals and generating a complex driving signal The plurality of switches are electrically connected to the respective drivers, and the switches are configured to receive the driving signals and generate a plurality of switching signals, wherein the switching signals are used to control voltages of the capacitors of the two capacitor arrays And a comparison clock module electrically connected to the delay buffer, the loop clock generator and the comparison clock end of the comparison module, wherein the comparison clock module is configured to receive the preset sampling a clock signal, the active loop signal generated by the delay buffer, and the last one of the cyclic clock signals generated by the loop clock generator, and generating a comparison clock signal When input to the clock terminal of the comparator, thereby resetting the comparison module. A parallel-signal progressive analog digital converter according to claim 7, wherein the switch is a bootstrap switch. The parallel signal type progressive analog digital converter of claim 7, wherein the cyclic clock generator is a D-type flip-flop array. A parallel signal type analog analog digital conversion method includes: performing a comparison step of: converting a two input signal into a comparison signal through a comparison module; delaying the comparison signal by a fast buffer time to generate an effective fast signal; Performing a step of preparing a capacitor: delaying the comparison signal by a slow buffering time to generate a valid slow signal, wherein the slow buffering time is longer than the fast buffering time, and the effective slow signal is used to trigger the switching of the complex capacitance of the two capacitor array; a progressive conversion step: generating a complex switching signal by using the effective fast signal and the effective slow signal, wherein the switching signals are used to control voltage values of the capacitors of the two capacitor arrays; and performing a preparation comparator step: The comparison signal delays a delay buffer time to generate an effective loop signal, wherein the delay buffer time is shorter than the slow buffer time and longer than the fast buffer time, and the valid loop signal is used to reset the comparison module. The parallel signal type progressive analog digital conversion method of claim 10, wherein the comparing step further comprises: converting the two input signals into a second comparison output signal through a comparator; and respectively performing each of the comparison output signals The comparison operation is generated by a logical operation. The parallel signal analog digital conversion method of claim 11, wherein the step of preparing the capacitance further comprises: generating the ordered complex cyclic clock signal by using the effective slow signal with a preset sampling clock signal; The cyclic clock signals trigger switching of the capacitors of the two capacitor arrays. The parallel signal type progressive analog digital conversion method of claim 12, wherein the progressive conversion step further comprises: matching each of the comparison output signals with the valid fast signal, the preset sampling clock signal, and the cyclic pulse signals Converting to a one-bit signal; converting the bit signal into a driving signal; converting the driving signal into one of the switching signals; the switching signal switching one of the capacitors of the two capacitor array The voltage values of the capacitors of the two capacitor arrays are controlled; and the voltage values of the two capacitor arrays are used as the two input signals. The parallel signal type analog analog digital conversion method of claim 12, wherein the preparing the comparator step comprises: generating the valid loop signal with the preset sampling clock signal and the last one of the cyclic clock signals Comparing the clock signal; and inputting the comparison clock signal to the comparison module to reset the comparison module.