44 t 19 2 5806twt'.d〇c/006 A7 五、發明說明（f)44 t 19 2 5806twt'.d〇c / 006 A7 V. Description of the invention (f)
本發明是有關於一種類比數位轉換積體電路的測試方 法及電路，且特別是有關於一種連續漸進型類比數位轉換 積體電路的測試方法及電路D 請參照第1A圖及第1B圖，其中，第1A圖顯示的是 習知所使用的類比數位轉換積體電路（Analog Digital Converter Integration Circuit，以下稱爲 ADC 1C)的電路圖 D 而第IB圖則顯示了在ADC IC中，將類比訊號轉換爲數位 訊號的時序圖。由於這種ADC 1C因爲類比數位之間的轉 換方法必須在藉由層層的比較之後，才能得到數位轉換 値，因此又被稱爲連續漸進型（Successive Approximation)類 比數位轉換積體電路。 在第1A圖中，連續漸進型ADC 1C 100包括了一個比 較器105以及一個數位類比轉換器（Digital Analog Converter，DAC) IC 110。習知所使用的連續漸進型ADC IC 100有數個數位輸出端，由這些輸出端就能輸出由類比訊 號轉換而得的數位訊號。在轉換過程中，就如第1B圖所示 的’連續漸進型ADC 1C 100首先會將最具意義位元 (Maximal Significant Bit，MSB)設定爲1，在與輸入的類比 訊號電壓値比較後，由於類比訊號電壓値比較小，所以將 數位輸出的MSB設定爲0。而後，對後續的位元也進行同 樣的動作’直到所有的數位輸出位元都被設定完畢爲止。 此時所得到的數位輸出位元組（如第1B圖中的數位輸出 ◦ 1101011)所代表的就是輸入之類比訊號的數位轉換値。 在得到這樣一組數位輸出位元組之後，就可以開始規 本紙張尺度適用中國國家標準（CNS)A4規格<210 X 297公爱） <請先閱讀背面之注咅？事項再填寫本頁) 裝--------訂----1----線 經濟部智慧財產局員Η消費合作社印製 卜 441 1 9 2 . 5 8 0 61 w d 〇 c/0 0 6 A/ B7 五、發明說明（α) 格測試的程序。請參照第1 c圖，其顯示的是習知中檢驗連 續漸進型類比數位轉換器所使用的方法流程圖。首先，在 步驟S100之中，必須先提供用來與上述之數位轉換値相比 較的一個數位預設値，並且設定一個測試値與此數位預設 値相當，以方便後續的動作。此外，也設定一個誤差倍數 爲0。接下來，在步驟S105之中，就先測試測試値與數位 轉換値是否相同。如果相同，則此類比數位轉換器就符合 規格；而若不相同，就必須進行下一步的測試流程，也就 是步驟S110。在步驟S110之中，會將誤差倍數加1 d這個 誤差倍數的用途在於與最低意義位元（Least Significant Bit，LSB)相乘而得到一個誤差値。之後，在步驟S115的 時候，會判斷誤差倍數是否大於一個預設的固定値，也就 .是要確保誤差値仍在容許的範圍內。而當誤差倍數大於此 預設的固定値的時候，此連續漸進型類比數位轉換器就不 符合規格，否則則需進行下一步的測試。 在步驟S120中，就先將數位預設値加上誤差値之後所 得到的値設定爲測試値。之後，在步驟S125之中再對測試 値與數位轉換値加以比較。若兩者相同，則此連續漸進型 類比數位轉換器就合於規格；而當兩者不同的時候，就必 須進行步驟S130。步驟S130將數位預設値減去誤差値之後 所得到的値設定爲測試値，之後回到步驟S105繼續執行測 試的動作，直到判斷出此連續漸進型類比數位轉換器是否 符合規格爲止。 假設可以容忍的誤差値在3個最低意義位元之內，則 (請先閱讀背面之注意事項再填寫本頁) 裝------— I 訂· I-------. 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中囤國家標準（CNS)A4規格X 297公釐） A7 B7 441192 5 806twf.doc/006 五、發明說明（3 ) 總共最多必須做7次的測試，才能判定出此連續漸進型類 比數位轉換器是否符合規格。而旦隨著可容忍的誤差與最 低意義位元値之間的比値增加，必須測試的次數就會更 多。 綜上所述，習知在測試連續漸進型類比數位轉換器是 否符合規格的時候，必須進行多次的測試才能完成。而且 測試的次數會隨著可容忍之誤差値與最低意義位元値之間 的比値增加而增加。 有鑒於此，本發明提出一種連續漸進型類比數位轉換 積體電路的測試方法，其適用於可容忍一個誤差電壓値的 連續漸進型類比數位轉換積體電路上。此測試方法首先提 供一個類比測試電壓，以及代表此類比測試電壓的一個數 .位測試値。之後，輸入將數位測試値加上誤差電壓値，並 經由數位類比轉換而得的電壓上限値，以及輸入將數位測 試値減去誤差電壓値，並經由數位類比轉換而得的電壓下 限値。最後’將類比測試電壓分別與電壓上限値及電壓下 限値相比較。而當類比測試電壓較電壓上限値大時，此一 連續漸進型類比數位轉換積體電路就不符合規格；當此類 比測試電壓較電壓下限値小時，此連續漸進型類比數位轉 換積體電路也同樣不合規格。 本發明另外提出一種連續漸進型類比數位轉換積體電 路的測試方法，其適用於可容忍一個誤差電壓値的連續漸 進型類比數位轉換積體電路上。首先，本方法提供一個類 比測試電壓及代表此類比測試電壓的一個數位測試値。之 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------------ 裝-------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 -441192 5 8 0 61 w f. d 〇 c / 0 0 6 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（十） 後’藉由提供比此數位測試値大一個誤差電壓値的電麼上 限値’以及比此數位測試値小一個誤差電壓値的電壓下限 値，來測試此連續漸進型類比數位轉換積體電路是否合於 規格。 其中，當類比測試電壓小於電壓下限値，或是類比測 試電壓大於電壓上限値時 '，此連續漸進型類比數位轉換積 體電路就不合於規格。 本發明還提出一種類比數位轉換積體電路的測試電 路’適用於可容忍一段誤差電壓値的連續漸進型類比數位 轉換積體電路’在以一個類比測試電壓進行測試時使用。 此類比測試電壓可由連續漸進型類比數位轉換積體電路轉 換爲一個數位測試値。此測試電路包括一個數位類比轉換 .器以及一個比較器。其中，數位類比轉換器可將輸入其中 的一個數位電壓値轉換爲一個類比電壓値。數位電壓値則 可以是由數位測試値加上誤差値所得的値，或是由數位測 試値減去誤差値所得的値。此外，比較器用以比較類比測 試電壓與類比電壓値，並輸出一個比較結果。其中，當類 比測試電壓大於類比電壓値時，比較結果爲1 ;而當類比測 試電壓小於類比電壓値時，比較結果則爲〇。 綜上所述，本發明藉由輸入於類比測試電壓上下各一 個誤差電壓値的數位電壓，經過數位類比轉換之後，直接 測得連續漸進型類比數位轉換積體電路是否合乎規格。如 此就可省去許多測試的步驟及時間0 爲讓本發明之上述和其他目的、特徵、和優點能更明 表紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐〉 (請先閱讀背面之注意事項再填寫本頁) 裝 • I n n ----訂---------線The present invention relates to a test method and circuit for an analog digital conversion integrated circuit, and in particular, to a test method and circuit D for a continuous progressive analog digital conversion integrated circuit. Please refer to FIG. 1A and FIG. 1B. Among them, Figure 1A shows the circuit diagram D of the analog digital converter integration circuit (hereinafter referred to as ADC 1C) used in the conventional art, and Figure IB shows the analog signal in the ADC IC. Timing diagram of conversion to digital signal. Because this ADC 1C conversion method between analog digits can only obtain digital conversion 层 after a layer-by-layer comparison, it is also called a Continuous Approximation analog digital conversion integrated circuit. In Fig. 1A, the continuous progressive ADC 1C 100 includes a comparator 105 and a digital analog converter (DAC) IC 110. The continuous progressive ADC IC 100 used in the prior art has a plurality of digital output terminals, and these output terminals can output digital signals obtained by analog signal conversion. During the conversion process, as shown in Figure 1B, the 'continuously progressive ADC 1C 100 first sets the most significant bit (MSB) to 1 and compares it with the input analog signal voltage 値. Since the analog signal voltage 値 is relatively small, the MSB of the digital output is set to 0. Then, the same operation is performed on subsequent bits' until all the digital output bits are set. The digital output byte obtained at this time (such as the digital output in Figure 1B ◦ 1101011) represents the digital conversion of the input analog signal 値. After getting such a set of digital output bytes, you can start to standardize the paper size to the Chinese National Standard (CNS) A4 specifications < 210 X 297 public love " < Please read the note on the back first? Please fill in this page for matters) Install -------- Order ---- 1 ---- Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 441 1 9 2. 5 8 0 61 wd 〇c / 0 0 6 A / B7 V. Description of the invention (α) Procedure for grid test. Please refer to Figure 1c, which shows a flow chart of the method used to test a continuous progressive analog-to-digital converter in the prior art. First, in step S100, a digital preset 値 for comparison with the above-mentioned digital conversion 値 must be provided first, and a test 値 is set to be equivalent to this digital preset ， to facilitate subsequent actions. Also, set an error multiple to zero. Next, in step S105, it is first tested whether the test value and the digital conversion value are the same. If they are the same, the digital-to-digital converter meets the specifications; if they are not the same, the next test process must be performed, which is step S110. In step S110, the error multiple is increased by 1 d. The purpose of the error multiple is to multiply it with the Least Significant Bit (LSB) to obtain an error 値. Then, at step S115, it is judged whether the error multiple is greater than a preset fixed value, that is, to ensure that the error value is still within the allowable range. When the error multiple is greater than the preset fixed threshold, the continuous progressive analog-to-digital converter does not meet the specifications; otherwise, the next test is required. In step S120, the digital preset 値 plus the error 先 is first set as the test 値. After that, the test 値 is compared with the digital conversion 値 in step S125. If the two are the same, the continuous progressive analog-to-digital converter meets the specifications; when the two are different, step S130 must be performed. Step S130 sets the digital preset 値 minus the error 値 as the test 値, and then returns to step S105 to continue the test operation until it is determined whether the continuous progressive analog digital converter meets the specifications. Assuming that the error that can be tolerated is within the 3 least significant bits, then (please read the precautions on the back before filling this page). ------------ I Order · I -------. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives, the paper size is applicable to the national standard (CNS) A4 size X 297 mm) A7 B7 441192 5 806twf.doc / 006 5. Description of the invention (3) Must be done up to 7 times in total Testing to determine whether this continuous-to-analog analog-to-digital converter meets specifications. As the ratio between the tolerable error and the least significant bit 値 increases, more tests must be performed. In summary, it is known that when testing whether a continuous progressive analog-to-digital converter meets the specifications, it must be tested multiple times to complete. And the number of tests will increase as the ratio between the tolerable error 値 and the least significant bit 値 increases. In view of this, the present invention proposes a continuous progressive analog digital conversion integrated circuit test method, which is applicable to a continuous progressive analog digital conversion integrated circuit that can tolerate an error voltage 値. This test method first provides an analog test voltage and a digital test bit representing the analog test voltage. After that, input the upper limit voltage 値 of the digital test 误差 plus the error voltage 値 and the digital analog conversion, and the lower limit voltage 値 of the digital test 値 minus the error voltage 値 and the digital analog conversion. Finally, compare the analog test voltage with the upper voltage limit 値 and lower voltage limit 値, respectively. When the analog test voltage is larger than the upper voltage limit, this continuous progressive analog digital conversion integrated circuit does not meet the specifications; when the analog test voltage is less than the lower voltage limit, the continuous progressive analog digital conversion integrated circuit also Also out of specification. The invention also proposes a continuous progressive analog digital conversion integrated circuit test method, which is applicable to a continuous progressive analog digital conversion integrated circuit that can tolerate an error voltage 値. First, the method provides an analog test voltage and a digital test 代表 that represents the analog test voltage. The paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) ------------ installed ------------------------- (Please read the notes on the back before filling out this page) Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs-441192 5 8 0 61 w f. D 〇c / 0 0 6 A7 B7 Employees’ Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. After printing 5. Description of the invention (ten), 'continue this test by providing an upper limit of the electrical voltage which is larger than the digital test 误差 by an error voltage 値 and a lower voltage limit of the error 値 which is smaller than the digital test 値. Whether the progressive analog-to-digital conversion integrated circuit meets specifications. Among them, when the analog test voltage is lower than the lower voltage limit 値, or when the analog test voltage is higher than the upper voltage limit ', the continuous progressive analog digital conversion integrated circuit is out of specification. The invention also proposes a test circuit of an analog digital conversion integrated circuit, which is suitable for a continuous progressive analog digital conversion integrated circuit that can tolerate a period of error voltage, and is used when testing with an analog test voltage. The analog test voltage can be converted from a continuous progressive analog digital conversion integrated circuit to a digital test 値. This test circuit includes a digital analog converter and a comparator. Among them, a digital analog converter can convert a digital voltage 输入 inputted into an analog voltage 値. The digital voltage can be the value obtained by adding the error to the digital test or the error obtained by subtracting the error from the digital test. In addition, the comparator is used to compare the analog test voltage with the analog voltage 値 and output a comparison result. Among them, when the analog test voltage is greater than the analog voltage 値, the comparison result is 1; and when the analog test voltage is less than the analog voltage 値, the comparison result is 0. In summary, the present invention directly measures whether a continuous progressive analog-to-digital conversion integrated circuit conforms to the specifications after the digital-to-analog conversion of the digital voltage input to the error voltage 値 above and below the analog test voltage. This saves many testing steps and time. In order to make the above and other objects, features, and advantages of the present invention clearer, the paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please (Please read the precautions on the back before filling in this page) Equipment • I nn ---- Order --------- line
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A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（f) 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下： 圖式之簡單說明： 第1A圖繪示的是習知所使用的類比數位轉換積體電 路的電路圖； 第1B圖繪示的是在連續漸進型類比數位轉換積體電 路中，將類比訊號轉換爲數位訊號的時序圖； 第1C圖繪示的是習知中檢驗連續漸進型類比數位轉 換器所使用的方法流程圖； 第2圖繪示的是根據本發明之一較佳實施例的實施方 法流程圖； 第3圖繪示的是根據本發明之另一較佳實施例的電路 .結構圖；以及 第4A-4C圖繪示的是本發明之結果輸出的可能狀況。 重要元件標號 100，200 :連續漸進型類比數位轉換積體電路 105，210 :比較器 110，205 :數位類比轉換器 較佳實施例 請參照第2圖，其繪示的是依照本發明一較佳實施例 的一種方法流程圖。本實施例適用於可容忍一段誤差電壓 値的一個連續漸進型類比數位轉換積體電路上。首先，在 步驟S200中，系統提供用以測試的一個類比測試電壓 Vat，以及經由規格書所定義，將類比測試電壓Vat經過類 比數位轉換後所得到，代表此類比測試電壓Vat的一個數 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------------ 裝---- - - - 訂---------線· (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧射產局員工湞費合作社印*'1^ if - 44 1 ; ir 2 — 5 806twt'.doc/006 ^ __B7 _ 五、發明說明（g) 位測試値Dat。之後，在步驟S205之中，數位測試値Dat 加上可容許的誤差値Err ’ I經由數位類比轉換而得到-個 電壓上限値Vup ;此外，由數位測試値Dat減去可容許的 誤差値Err，再經過數位類比轉換，得到一個電壓下限値 Vdn。接下來，於步驟S210時，就將類比測試電壓Vat分 別與電壓上限値Vup以及電壓下限値Vdn相比較。僅有在 當類比測試電壓Vat介於電壓上限値Vup及電壓下限値 Vdn之間的時候，連續漸進型類比數位轉換積體電路才算 是符合規格。若是類比測試電壓Vat比電壓上限値Vup大， 或是比電壓下限値Vdn小，則此連續漸進型類比數位轉換 積體電路就不符合規格。 其中，要比較電壓上限値Vup與類比測試電壓Vat大 .小的時候，可以先將數位測試値Dat加上容許誤差値，經 由數位類比轉換而成爲電壓上限値Vup，之後再以此電壓 上限値Vup與類比測試電壓Vat相比較。同樣的，要比較 電壓下限値Vdn與類比測試電壓Vat大小的時候，可以先 將數位測試値Dat減去容許誤差値，經由數位類比轉換而 成爲電壓下限値Vdn，之後再以此電壓下限値Vdn與類比 測試電壓Vat相比較^ 接下來請參照第3圖，其顯示了根據本發明之一較佳 實施例的電路結構圖。其適於在可容忍一段誤差電壓値的 連續漸進型類比數位轉換積體電路中，以一個類比測試電 壓進行測試時使用。此外，類比測試電壓可由規格所定的 預定値而轉換爲一個數位測試値。 ----------- 裝--------訂·! •線 · (請先閱讀背面之注音？事項再填寫本頁) 本紙張尺度適用令國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產居員工消費合作社印製 441192 5S06twf.doc/006 A7 _____B7 __ 五、發明說明（9) 在本實施例中，連續漸進型類比數位轉換積體電路200 包括一個比較器210以及一個數位類比轉換器205。其中， 數位類比轉換器205可以經由數位輸出輸入端Dl/Ο將一個 數位電壓値輸入於其中，並可將此數位電壓値轉換爲一個 類比電壓値。而用來測試此連續漸進型類比數位轉換積體 電路200的類比測試電壓，則會經由類比輸入端IN輸入於 比較器210之中。比較器210會將此類比測試電壓與上述 的類比電壓値加以比較，並將比較後所得的一個比較結果 經過輸出端Ro加以輸出。 其中，上述的數位電壓値，可以是由數位測試値加上 誤差値後所得的一個數位上限値，或是由數位測試値減去 誤差値後所得的一個數位下限値。此外，由輸出端Ro所輸 出的比較結果會有幾種的狀況。請參照第4A-4C圖，其分 別顯示了幾種可能的比較結果輸出狀況。在第4A圖中，時 間T0到T1之間，由於數位輸入電壓(即上述的數位電壓値） 比類比輸入電壓（即上述的類比測試電壓）還小，所以經由 比較器210所輸出的電壓爲低電壓(或一般在二進位中通稱 爲0)。而在時間T1到T2之間，由於數位輸入電壓比類比 輸入電壓還大，所以經由比較器210所輸出的電壓爲高電 壓(或一般在二進位中通稱爲1)。在有這種測試輸出結果的 狀況下，就代表此連續漸進型類比數位轉換積體電路合於 規格。 必須注意的是，在第4A圖中是先以數位上限値與類比 測試電壓相比較，再以數位下限値與類比測試電壓相比 ------------^*-------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） A7 B7 441192 5 8 06 t\v f. doc/006 五、發明說明（分） 較，所以所得的比較器輸出結果是01。但是若先以數位下 限値與類比測試電壓相比，再以數位上限値與類比測試電 壓相比較，則若連續漸進型類比數位轉換積體電路合於規 格，輸出結果就應該是10。 至於第4B及第4C圖，則是連續漸進型類比數位轉換 積體電路不合規格時所可能出現的輸出結果13在第4B圖 中，由於數位輸入電壓（包括數位上限値與數位下限値）一 直都小於類比輸入電壓，所以輸出結果都是高電壓（以1表 示）。而相反的，在第4C圖中，由於數位輸入電壓（包括數 位上限値與數位下限値)一直都大於類比輸入電壓，所以輸 出結果都是低電壓(以0表示）。由此也可以看出.，藉由輸 出結果的不同，還可以判斷出此連續漸進型類比數位轉換 .積體電路不合規格的原因。 綜上所述，現將本發明的優點略述如下。本發明不但 可省去許多測試的步驟及時間，而且當測試後發現不合規 格的時候，還可以進一步得知不合規格的原因。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之沒意事項再填寫本頁) 裝·-----— —訂--------線 經濟部智慧財產局員工消費合作社印製Sr 58 (M \ ^ dlc / 3〇 (9 2. A7 B7 Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (f) is easy to understand. The following exemplifies the preferred embodiments and cooperates with the attached drawings) The detailed description is as follows: Brief description of the diagram: Figure 1A shows a circuit diagram of an analog-to-digital conversion integrated circuit used in the conventional art; Figure 1B shows a continuous-to-digital analog-to-digital conversion integrated product In the circuit, a timing diagram for converting an analog signal into a digital signal; FIG. 1C shows a flowchart of a conventional method for testing a continuous progressive analog-to-digital converter; FIG. 2 shows a method according to the present invention. A flowchart of a method for implementing a preferred embodiment; FIG. 3 illustrates a circuit and a structural diagram according to another preferred embodiment of the present invention; and FIGS. 4A-4C illustrate the output of the results of the present invention. Possible conditions: Important component numbers 100, 200: continuous progressive analog digital conversion integrated circuits 105, 210: comparators 110, 205: digital analog converters. For a preferred embodiment, please refer to FIG. 2, which is shown in accordance with this A preferred embodiment of the invention The method is applicable to a continuous progressive analog digital conversion integrated circuit that can tolerate a period of error voltage. First, in step S200, the system provides an analog test voltage Vat for testing, and passes the specification As defined in the book, the analog test voltage Vat is obtained after analog digital conversion. A number of paper sizes representing the analog test voltage Vat are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ----- ------- Install -------Order --------- Line · (Please read the precautions on the back before filling out this page) Staff of the Ministry of Economic Affairs, Smart Injection Bureau印 * '1 ^ if-44 1; ir 2 — 5 806twt'.doc / 006 ^ __B7 _ V. Description of the invention (g) Bit test 値 Dat. After that, in step S205, the digital test 値 Dat plus may be The allowable error 値 Err'I is obtained through digital analog conversion to obtain a voltage upper limit 値 Vup; in addition, the digital test 値 Dat is subtracted from the allowable error 値 Err, and then subjected to digital analog conversion to obtain a voltage lower limit 値 Vdn. Next, at step S210, the analog test voltage Vat is set. Compared with the upper voltage limit 値 Vup and lower voltage limit 値 Vdn respectively. Only when the analog test voltage Vat is between the upper voltage limit 値 Vup and the lower voltage limit 値 Vdn, the continuous progressive analog digital conversion integrated circuit is considered to comply. Specifications. If the analog test voltage Vat is greater than the upper voltage limit 値 Vup or lower than the lower voltage limit 値 Vdn, then this continuous progressive analog digital conversion integrated circuit does not meet the specifications. Among them, the upper voltage limit 値 Vup must be compared with the analog test When the voltage Vat is large or small, the digital test 値 Dat plus the allowable error 先 can be converted to a voltage upper limit 値 Vup through digital analog conversion, and then this voltage upper limit 値 Vup can be compared with the analog test voltage Vat. Similarly, when comparing the voltage lower limit 値 Vdn with the analog test voltage Vat, you can first subtract the digital test 値 Dat minus the allowable error 値, and then convert it to digital lower limit 値 Vdn through digital analog conversion. Comparison with the analog test voltage Vat ^ Please refer to FIG. 3, which shows a circuit structure diagram according to a preferred embodiment of the present invention. It is suitable for testing with an analog test voltage in a continuous progressive analog digital conversion integrated circuit that can tolerate a period of error voltage 値. In addition, the analog test voltage can be converted into a digital test voltage from a predetermined voltage specified by the specification. ----------- Install -------- Order ·! • Line · (Please read the phonetic on the back? Matters before filling out this page) This paper size applies the national standard of the country (CNS ) A4 specification (210 X 297 mm) Printed by the Consumers ’Cooperative of Intellectual Property of the Ministry of Economic Affairs 441192 5S06twf.doc / 006 A7 _____B7 __ V. Description of the invention (9) In this embodiment, a continuous progressive analog digital conversion product The circuit 200 includes a comparator 210 and a digital analog converter 205. The digital analog converter 205 can input a digital voltage through the digital output input terminal D1 / 0, and convert the digital voltage 为 into an analog voltage 値. The analog test voltage used to test the continuous progressive analog digital conversion integrated circuit 200 is input into the comparator 210 through the analog input terminal IN. The comparator 210 compares the analog test voltage with the analog voltage 値 described above, and outputs a comparison result obtained through the comparison through the output terminal Ro. The above-mentioned digital voltage 値 can be a digital upper limit 所得 obtained by adding a digital test 値 and an error 値, or a digital lower limit 値 obtained by subtracting an error 由 from the digital test 値. In addition, the comparison result output from the output terminal Ro may have several conditions. Please refer to Figures 4A-4C, which respectively show several possible comparison result output conditions. In Figure 4A, between time T0 and T1, since the digital input voltage (ie, the above-mentioned digital voltage 値) is smaller than the analog input voltage (ie, the above-mentioned analog test voltage), the voltage output by the comparator 210 is Low voltage (or commonly referred to as 0 in binary). Between the time T1 and T2, since the digital input voltage is larger than the analog input voltage, the voltage output through the comparator 210 is a high voltage (or generally referred to as 1 in binary). In the case of such test output results, it means that the continuous progressive analog digital conversion integrated circuit is in compliance with the specifications. It must be noted that in Figure 4A, the digital upper limit is first compared with the analog test voltage, and then the digital lower limit is compared with the analog test voltage ------------ ^ *- ----- Order --------- Line (Please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) A7 B7 441192 5 8 06 t \ v f. Doc / 006 V. Description of the invention (points) Comparison, so the comparator output is 01. However, if the digital lower limit is first compared with the analog test voltage, and then the digital upper limit is compared with the analog test voltage, if the continuous progressive analog digital conversion integrated circuit meets the specifications, the output result should be 10. Figures 4B and 4C are the output results that may occur when the continuous progressive analog digital conversion integrated circuit is out of specification. 13 In Figure 4B, the digital input voltage (including the upper digital limit and lower digital limit) has been Both are smaller than the analog input voltage, so the output results are all high voltage (represented by 1). In contrast, in Figure 4C, because the digital input voltage (including the digital upper limit 値 and digital lower limit 値) is always greater than the analog input voltage, the output results are all low voltage (represented by 0). It can also be seen that, based on the difference in the output results, it is also possible to determine the reason for this continuous progressive analog-to-digital conversion. The integrated circuit is out of specification. In summary, the advantages of the present invention are briefly described below. The invention not only can save many steps and time for testing, but also can find out the reason for non-compliance when it finds non-compliance after the test. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (please read the unintentional matter on the back before filling this page). -Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs