TW201431231A - Over temperature protection circuit - Google Patents

Abstract

The present invention provides an over temperature protection circuit. The over temperature protection circuit includes a reference circuit and a hysteretic comparator. The reference circuit is used for generating a reference voltage and a changeable voltage. The changeable voltage is varied by temperature. The hysteretic comparator compares the reference voltage with the changeable voltage to output a power down signal.

Description

Over temperature protection circuit

The present invention relates to an over temperature protection circuit, and more particularly to an over temperature protection circuit having a hysteresis comparator.

An experienced circuit designer will know that when designing a power supply, the calculation of current and the control of current must be considered to improve the efficiency of the circuit. An over-temperature protection circuit is often added to a power supply to current limit or overload protection of the power supply.

Conventional over temperature protection circuits include an overload computing component and a temperature computing component. However, one of the main drawbacks of such a circuit architecture is that when performing circuit overload and over temperature protection, the overload calculation and over temperature calculation must be performed separately by different components, overload calculation components and temperature calculation components. That is to say, the conventional over-temperature protection circuit design must use a plurality of comparison circuit units to confirm whether an overload or over-temperature condition occurs, so that the volume of the conventional over-temperature protection circuit cannot be reduced.

The invention provides an over temperature protection circuit. The over temperature protection circuit has a reference circuit and a hysteresis comparator. The reference circuit is used to generate a reference voltage and a variable voltage. This variable voltage can vary with temperature. The hysteresis comparator is used to compare the variable voltage with the reference voltage to output a power down signal.

According to an embodiment of the invention, the hysteresis comparator further includes a bias current unit, a switching unit, a current extraction unit, and a signal output unit. The bias current unit is used to generate a fixed current. The switching unit is configured to couple the bias current unit. The switching unit includes a first current path and a second current path. The switching unit can receive the reference voltage and the variable voltage, thereby arranging the fixed current in the first current path and the second current path. The current extraction unit is coupled to the switching unit. The current extraction unit draws current into the first current path and the second current path. The signal output unit is coupled to the current extraction unit to output the power down signal.

According to another embodiment of the present invention, the switching unit further includes a first transistor and a second transistor. The first transistor receives this variable voltage to control the current flowing through the first current path. The second transistor receives this reference voltage to control the current flowing through the second current path.

According to another embodiment of the present invention, the current extraction unit further includes a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The third transistor and the fourth transistor form a current mirror architecture. The third transistor is coupled to the first current path. The fourth transistor is coupled to the second current path. The fifth transistor and the sixth transistor form a current mirror architecture. The fifth transistor is coupled to the first current path. The sixth transistor is coupled to the second current path. Wherein the length/width ratio of the fourth transistor is greater than the length/width ratio of the third transistor. The length/width ratio of the sixth transistor is greater than the length/width ratio of the fifth transistor.

According to another embodiment of the present invention, the signal output unit further includes a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor. The eighth transistor and the seventh transistor form a current mirror architecture. The drain of the ninth transistor is coupled to the seventh transistor, and the gate of the ninth transistor is coupled to the second Current path. The drain of the tenth transistor is coupled to the eighth transistor, and the gate of the tenth transistor is coupled to the first current path.

According to still another embodiment of the present invention, the current drawing unit further includes a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The gate of the third transistor is coupled to the drain of the third transistor and the first current path. The gate of the fourth transistor and the drain of the fourth transistor are coupled to the second current path. The gate of the fifth transistor is coupled to the gate of the fourth transistor and the signal output unit. The sixth transistor is connected between the gate of the fourth transistor and the drain of the fifth transistor, and the gate of the sixth transistor is coupled to the signal output unit.

According to still another embodiment of the present invention, the signal output unit further includes a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor. The eighth transistor and the seventh transistor form a current mirror architecture. The drain of the ninth transistor is coupled to the seventh transistor and the sixth transistor gate. The gate of the ninth transistor is coupled to the gate of the fifth transistor and the gate of the fourth transistor. The drain of the tenth transistor is coupled to the eighth transistor. The gate of the tenth transistor is coupled to the gate of the third transistor.

According to still another embodiment of the present invention, the reference circuit is a band gap reference circuit. The operation circuit includes an operational amplifier, a first transistor, a second transistor, a third transistor, a resistor, a voltage divider, a first diode, a second diode, and a first Triode. The gate of the first transistor is coupled to the output of the operational amplifier, the source of the first transistor is coupled to a power supply, and the drain of the first transistor is coupled to the positive input of the operational amplifier. a gate of the second transistor is coupled to an output end of the operational amplifier, and a source of the second transistor is coupled to the power supply, The drain of the two transistors is coupled to the negative input of the operational amplifier. The gate of the third transistor is coupled to the output of the operational amplifier, and the source of the third transistor is coupled to the power supply. The first end of the resistor is coupled to the positive input of the operational amplifier. The first end of the voltage divider is coupled to the drain of the third transistor for generating a reference voltage. The first end of the first diode is coupled to the second end of the resistor, and the second end of the first diode is grounded. The first end of the second diode is coupled to the negative input terminal of the operational amplifier for generating a variable voltage, and the second end of the second diode is grounded. The first end of the third diode is coupled to the drain of the third transistor, and the second end of the third diode is grounded. Wherein, the first transistor, the second transistor and the third transistor are P-type MOS transistors. The first diode, the second diode, and the third diode are both PNP-type bipolar junction transistors, and the collector terminals are coupled to the base terminal.

The following description of the preferred embodiments of the invention is in the

Fig. 1 is a schematic view showing an over temperature protection circuit according to an embodiment of the present invention. The over temperature protection circuit 100 has a reference circuit 101 and a hysteresis comparator 102. The reference circuit 101 is configured to generate a reference voltage VBG and a variable voltage VN. This variable voltage VN can vary with temperature. The variable voltage VN and the reference voltage VBG are transmitted to the hysteresis comparator 102, and the hysteresis comparator 102 compares the variable voltage VN with the reference voltage VBG to output a power down signal to limit the output current of a power supply. In order to prevent over temperature conditions from occurring.

According to an embodiment of the invention, the reference circuit 101 is a band gap reference circuit. 2 is a schematic illustration of a reference circuit 101 in accordance with an embodiment of the present invention. The operation circuit 101 includes an operational amplifier 1011, a first transistor 1012, a second transistor 1013, a third transistor 1014, a resistor 1015, a voltage divider 1016, a first diode 1017, and a first diode. The second diode 1018 and a third diode 1019.

The gate of the first transistor 1012 is coupled to the output terminal of the operational amplifier 1011, the source of the first transistor 1012 is coupled to a power supply VDD, and the drain of the first transistor 1012 is coupled to the positive input terminal of the operational amplifier 1011. (+). The gate of the second transistor 1013 is coupled to the output terminal of the operational amplifier 1011, the source of the second transistor 1013 is coupled to the power supply VDD, and the drain of the second transistor 1013 is coupled to the negative input terminal of the operational amplifier 1011. (-). The gate of the third transistor 1014 is coupled to the output terminal of the operational amplifier 1011, the source of the third transistor 1014 is coupled to the power supply VDD, and the drain of the third transistor 1014 is coupled to the voltage divider 1016 for A reference voltage VBG is generated. The first end of the resistor 1015 is coupled to the positive input terminal (+) of the operational amplifier 1011, the second end of the resistor 1015 is coupled to the first end of the first diode 1017, and the second terminal of the first diode 1017 is grounded to GND. . The first terminal of the second diode 1018 is coupled to the negative input terminal (-) of the operational amplifier 1011 for generating a variable voltage VN, and the second terminal of the second diode 1018 is grounded to GND. The first end of the third diode 1019 is coupled to the drain of the third transistor 1014, and the second end of the third diode 1019 is connected to the ground GND. The first transistor 1012, the second transistor 1013, and the third transistor 1014 are P-type MOS transistors. First diode 1017, second diode 1018, and third diode 1019 is a PNP type bipolar junction transistor, and the set terminal is coupled to the base terminal. The reference circuit 101 of the present invention utilizes a voltage divider 1016 to reduce the output variable voltage VBG.

Figure 3 is a diagrammatic representation of a hysteresis comparator 102 in accordance with an embodiment of the present invention. The hysteresis comparator 102 includes a bias current unit 201, a switching unit 202, a current extraction unit 203, and a signal output unit 204.

The bias current unit 201 is coupled to the switching unit 202 for maintaining a fixed current I. The switching unit 202 includes a first current path 2023 and a second current path 2024 controlled by a first transistor 2021 and a second transistor 2022, respectively. The gate of the first transistor 2021 acts as the first input (INN) of the hysteresis comparator 102 for receiving the variable voltage VN. The gate of the second transistor 2022 serves as a second input (INP) of the hysteresis comparator 102 for receiving the reference voltage VBG. The drain of the first transistor 2021 and the drain of the second transistor 2022 are connected to each other and coupled to the bias current unit 201. The first transistor 2021 and the second transistor 2022 are arranged to fix the fixed current I in the first current path 2023 and the second current path 2024 in accordance with the reference voltage VBG and the variable voltage VN.

The current capturing unit 203 is coupled to the switching unit 202. The current extraction unit 203 is configured to draw current into the first current path 2023 and the second current path 2024. According to another embodiment of the present invention, the current extraction unit 203 is composed of a third transistor 2031, a fourth transistor 2032, a fifth transistor 2033, and a sixth transistor 2034. The third transistor 2031 and the fourth transistor 2032 form a current mirror architecture. The drain of the third transistor 2031 is coupled to the first current path 2023. The fourth transistor 2032 The pole is coupled to the second current path 2024. The gate of the third transistor 2031 is connected to its drain and is connected to the gate of the fourth transistor 2032, and together with the fourth transistor 2032 forms a current mirror architecture. The length/width ratio of the fourth transistor 2032 is greater than the length/width ratio of the third transistor 2031. The fifth transistor 2033 and the sixth transistor 2034 also form a current mirror architecture. The drain of the fifth transistor 2033 is coupled to the first current path 2023. The drain of the sixth transistor 2034 is coupled to the second current path 2024. The gate of the sixth transistor 2034 is connected to the drain and is connected to the gate of the fifth transistor 2033, and together with the fifth transistor 2033 forms a current mirror architecture. The length/width ratio of the sixth transistor 2034 is greater than the length/width ratio of the fifth transistor 2033.

The signal output unit 204 is coupled to the current extraction unit 203 to output the power down signal. The signal output unit 204 is composed of a seventh transistor 2041, an eighth transistor 2042, a ninth transistor 2043, and a tenth transistor 2044. The gate of the eighth transistor 2042 is connected to the drain and is connected to the gate of the seventh transistor 2041 to form a current mirror structure together with the seventh transistor. The drain of the ninth transistor 2043 is coupled to the drain of the seventh transistor 2041, and the gate of the ninth transistor 2043 is coupled to the second current path 2024. The drain of the tenth transistor 2044 is coupled to the drain of the eighth transistor 2042, and the gate of the tenth transistor 2044 is coupled to the first current path 2023. In an embodiment, the first transistor 2021, the second transistor 2022, the seventh transistor 2041, and the eighth transistor 2042 are P-type MOS transistors. The third transistor 2031, the fourth transistor 2032, the fifth transistor 2033, the sixth transistor 2034, the ninth transistor 2043, and the tenth transistor 2044 are N-type MOS transistors.

When a voltage comparator having the structure as described above is performing a reference voltage The comparison between VBG and variable voltage VN is to output a low-order signal or a high-order signal, and the operation flow is as follows.

First, if the variable voltage VN input to the first input (INN) of the hysteresis comparator 102 is less than the reference voltage VBG input to the second input (INP) of the hysteresis comparator 102, the current flowing through the first current path 2023 It will be greater than the current flowing through the second current path 2024. Most of the constant current I generated by the bias current unit 201 will flow into the ground via the first transistor 2021, the first current path 2023, the third transistor 2031, and the fifth transistor 2033. It is worth noting that because of the current mirror architecture, the current flowing through the fifth transistor 2033 is almost equal to the current flowing through the sixth transistor 2034. Almost no current flows into the ground via the second transistor 2022, the second current path 2024, the fourth transistor 2032, and the sixth transistor 2034. It is worth noting that since the current mirror structure is formed with the third transistor 2031, most of the current flowing through the second transistor 2022 flows into the fourth transistor 2032. At this time, the gate voltage of the current mirror structure formed by the fifth transistor 2033 and the sixth transistor 2034 is a low level, and accordingly, the output point 2045 will output a high level signal.

On the other hand, if the variable voltage VN input to the first input (INN) of the hysteresis comparator 102 is greater than the reference voltage VBG input to the second input (INP) of the hysteresis comparator 102, the second transistor 2022 flows. The current flowing into the ground of the second current path 2024, the fourth transistor 2032, and the sixth transistor 2034 gradually increases, and when the current flowing through the fourth transistor 2032 corresponds to the current flowing through the sixth transistor 2034, The comparator switches. Thus, the current flowing through the sixth transistor 2034 is greater than the current flowing through the fourth transistor 2032. In order to initiate this switching operation, the previous low level The gate capacitances of the fifth transistor 2033 and the sixth transistor 2034 are charged to a high level state for a certain period of time Dt. This ninth transistor 2043 is then turned on to output a low level signal at output point 2045.

Figure 4 is a schematic illustration of a hysteresis comparator in accordance with another embodiment of the present invention. The hysteresis comparator 102 includes a bias current unit 301, a switching unit 302, a current extraction unit 303, and a signal output unit 304.

The bias current unit 301 is coupled to the switching unit 302 for maintaining a fixed current I. The switching unit 302 includes a first current path 3023 and a second current path 3024 controlled by a first transistor 3021 and a second transistor 3022, respectively. The gate of the first transistor 3021 acts as the first input (INN) of the hysteresis comparator 102 for receiving the variable voltage VN. The gate of the second transistor 3022 serves as a second input (INP) of the hysteresis comparator 102 for receiving the reference voltage VBG. The drain of the first transistor 3021 and the drain of the second transistor 3022 are connected to each other and coupled to the bias current unit 301. The first transistor 3021 and the second transistor 3022 are arranged to fix the fixed current I in the first current path 3023 and the second current path 3024 in accordance with the reference voltage VBG and the variable voltage VN.

The current extraction unit 303 is coupled to the switching unit 302. The current extraction unit 303 is configured to draw current into the first current path 3023 and the second current path 3024. According to another embodiment of the present invention, the current extraction unit 303 is composed of a third transistor 3031, a fourth transistor 3032, a fifth transistor 3033, and a sixth transistor 3034. The drain of the third transistor 3031 is coupled to the first current path 3023. The fourth transistor 3032 The pole is coupled to the second current path 3024. The gate of the third transistor 3031 is connected to the drain thereof and is connected to the signal output unit 304. The gate of the fourth transistor 3032 is connected to its drain. The gate of the fifth transistor 3033 is connected to the gate of the fourth transistor 3032 and the signal output unit 304. The sixth transistor 3034 is connected between the gate of the fourth transistor 3032 and the drain of the fifth transistor 2033. The gate of the sixth transistor 3034 is connected to the signal output unit 304.

The signal output unit 304 is coupled to the current extraction unit 303 to output the power down signal. The signal output unit 304 is composed of a seventh transistor 3041, an eighth transistor 3042, a ninth transistor 3043, and a tenth transistor 3044. The gate of the eighth transistor 3042 is connected to the drain and is connected to the gate of the seventh transistor 3041 to form a current mirror structure together with the seventh transistor 3041. The drain of the ninth transistor 3043 is coupled to the drain of the seventh transistor 3041 and the gate of the sixth transistor 3034. The gate of the ninth transistor 3043 is coupled to the gate of the fifth transistor 3033 and the fourth The gate of crystal 3032. The drain of the tenth transistor 3044 is coupled to the drain of the eighth transistor 3042, and the gate of the tenth transistor 3044 is coupled to the gate of the third transistor 3031. In an embodiment, the first transistor 3021, the second transistor 3022, the seventh transistor 3041, and the eighth transistor 3042 are P-type MOS transistors. The third transistor 3031, the fourth transistor 3032, the fifth transistor 3033, the sixth transistor 3034, the ninth transistor 3043, and the tenth transistor 3044 are N-type MOS transistors.

First, if the variable voltage VN input to the first input (INN) of the hysteresis comparator 102 is less than the reference voltage VBG input to the second input (INP) of the hysteresis comparator 102, the current flowing through the first current path 3023 It will be greater than the current flowing through the second current path 3024. Most of the bias current unit The constant current I generated by 301 will flow into the ground via the first transistor 3021, the first current path 3023, and the third transistor 3031. The current flowing through the second transistor 3022, the second current path 3024, and the fourth transistor 3032 into the ground is only a small portion or almost no current. At this time, the gate voltage of the ninth transistor 3043 is at a low level, and accordingly, the output point 3045 will output a high level signal.

On the other hand, if the variable voltage VN input to the first input (INN) of the hysteresis comparator 102 is greater than the reference voltage VBG input to the second input (INP) of the hysteresis comparator 102, the second transistor 3022 flows. The current flowing into the ground by the second current path 3024 and the fourth transistor 3032 gradually increases, and the current flowing through the second transistor 3022 and the fourth transistor 3032 flows through the second transistor 3022 and the fifth transistor 2033 correspondingly. When the current is current, the comparator is switched. In order to initiate this switching operation, the gate capacitances of the fifth transistor 3033 and the fourth transistor 3032, which were previously in the low level state, are charged to a high level state for a certain period of time Dt. This ninth transistor 3043 is then turned on to output a low level signal at output point 3045.

In summary, the over temperature protection circuit of the present invention is composed of a reference circuit and a hysteresis comparator, so that the overall volume and manufacturing cost of the over temperature protection circuit can be greatly reduced.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and modified without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.

100‧‧‧Over temperature protection circuit

101‧‧‧ reference circuit

102‧‧‧hysteresis comparator

VBG‧‧‧ reference voltage

VN‧‧‧Variable voltage

1011‧‧‧Operational Amplifier

1015‧‧‧resistance

1016‧‧ ‧ Voltage divider

1017‧‧‧First Diode

1018‧‧‧second diode

1019‧‧‧ Third Dipole

301 and 201‧‧‧ bias current unit

302 and 202‧‧‧Switching unit

303 and 203‧‧‧ current extraction unit

304 and 204‧‧‧ signal output units

3023 and 2023‧‧‧First current path

3024 and 2024‧‧‧second current path

1012, 3021 and 2021‧‧‧ first transistor

1013, 3022 and 2022‧‧‧second transistor

1014, 3031 and 2031‧‧‧ third transistor

3032 and 2032‧‧‧ fourth transistor

3033 and 2033‧‧‧ fifth transistor

3034 and 2034‧‧‧ sixth transistor

3041 and 2041‧‧‧ seventh transistor

3042 and 2042‧‧‧ eighth transistor

3043 and 2043‧‧‧ ninth transistor

3044 and 2044‧‧‧10th transistor

3045 and 2045‧‧‧ output points

The above and other objects, features, advantages and embodiments of the present invention will become more <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; .

Figure 2 is a schematic illustration of a reference circuit in accordance with an embodiment of the present invention.

Figure 3 is a schematic illustration of a hysteresis comparator in accordance with an embodiment of the present invention.

Figure 4 is a schematic illustration of a hysteresis comparator in accordance with another embodiment of the present invention.

100‧‧‧Over temperature protection circuit

101‧‧‧ reference circuit

102‧‧‧hysteresis comparator

VBG‧‧‧ reference voltage

VN‧‧‧Variable voltage

Claims (27)

An over temperature protection circuit includes at least: a reference circuit for generating a reference voltage and a variable voltage, wherein the variable voltage is changeable with temperature; and a hysteresis comparator for comparing the variable voltage and the The reference voltage is output to a power supply down signal, wherein the hysteresis comparator further comprises: a bias current unit for generating a fixed current; a switching unit coupled to the bias current unit, wherein the switching unit includes a first current a path and a second current path, and the switching unit can arrange the fixed current in the first current path and the second current path according to the reference voltage and the variable voltage; a current capturing unit is coupled to the switching a unit, wherein the current extraction unit draws current into the first current path and the second current path; and a signal output unit, wherein the signal output unit is coupled to the current extraction unit to output the power down signal. The over temperature protection circuit of claim 1, wherein the switching unit further comprises: a first transistor for receiving the variable voltage to control a current flowing through the first current path; and a second transistor Receiving the reference voltage to control flow through the first The current of the two current paths. The over temperature protection circuit of claim 2, wherein the current extraction unit further comprises: a third transistor and a fourth transistor forming a current mirror architecture, wherein the third transistor is coupled to the first current path The fourth transistor is coupled to the second current path; and a fifth transistor and a sixth transistor form a current mirror structure, wherein the fifth transistor is coupled to the first current path, The sixth transistor is coupled to the second current path. The over temperature protection circuit of claim 3, wherein a length/width ratio of the fourth transistor is greater than a length/width ratio of the third transistor, and a length/width ratio of the sixth transistor is greater than the fifth The length/width ratio of the crystal. The over temperature protection circuit of claim 3, wherein the signal output unit further comprises: a seventh transistor; an eighth transistor, wherein the eighth transistor and the seventh transistor form a current mirror architecture; a ninth transistor, wherein a drain of the ninth transistor is coupled to the seventh transistor, a gate of the ninth transistor is coupled to the second current path; and a tenth transistor, wherein the tenth The gate of the crystal is coupled to the eighth transistor, and the gate of the tenth transistor is coupled to the first current path. The over temperature protection circuit of claim 3, wherein the first transistor, the second transistor, the seventh transistor, and the eighth transistor are P-type MOS transistors, and the third device The crystal, the fourth transistor, the fifth transistor, the sixth transistor, the ninth transistor, and the tenth transistor are N-type gold oxide semi-transistors. The over temperature protection circuit of claim 2, wherein the current extraction unit further comprises: a third transistor, wherein the gate of the third transistor is coupled to the drain of the third transistor and the first current a fourth transistor, wherein a gate of the fourth transistor is coupled to a drain of the fourth transistor and the second current path; a fifth transistor, wherein the gate of the fifth transistor is coupled Connected to the gate of the fourth transistor and the signal output unit; and a sixth transistor, wherein the sixth transistor is connected between the gate of the fourth transistor and the drain of the fifth transistor, and The gate of the sixth transistor is coupled to the signal output unit. The over temperature protection circuit of claim 7, wherein the signal output unit further comprises: a seventh transistor; an eighth transistor, wherein the eighth transistor and the seventh transistor form a current mirror architecture; a ninth transistor, wherein a gate of the ninth transistor is coupled to the seventh transistor and the sixth transistor gate, and a gate of the ninth transistor is coupled to a gate of the fifth transistor and a gate of the fourth transistor; and a tenth transistor, wherein a drain of the tenth transistor is coupled to the eighth transistor, and a gate of the tenth transistor is coupled to a gate of the third transistor . The over temperature protection circuit of claim 8, wherein the first transistor, the second transistor, the seventh transistor, and the eighth transistor are P-type MOS transistors, and the third device The crystal, the fourth transistor, the fifth transistor, the sixth transistor, the ninth transistor, and the tenth transistor are N-type gold oxide semi-transistors. The over temperature protection circuit of claim 1, wherein the reference circuit is a band gap reference circuit. The over temperature protection circuit of claim 10, wherein the operation circuit further comprises: an operational amplifier; a first transistor, wherein the gate of the first transistor is coupled to the output of the operational amplifier, the A source of the transistor is coupled to a power supply, and a drain of the first transistor is coupled to a positive input terminal of the operational amplifier. a second transistor, wherein a gate of the second transistor is coupled to an output end of the operational amplifier, a source of the second transistor is coupled to the power supply, and a drain of the second transistor is coupled a negative input terminal of the operational amplifier; a third transistor, wherein the gate of the third transistor is coupled to the operation An output of the amplifier, the source of the third transistor is coupled to the power supply; a resistor, wherein the first end of the resistor is coupled to the positive input terminal of the operational amplifier; a voltage divider, wherein the voltage divider The first end is coupled to the drain of the third transistor for generating the reference voltage; the first diode, wherein the first end of the first diode is coupled to the second end of the resistor, The second end of the first diode is grounded; a second diode, wherein the first end of the second diode is coupled to the negative input of the operational amplifier for generating a variable voltage, the second The second end of the second diode is grounded; and the third end of the third diode is coupled to the drain of the third transistor, and the second end of the third diode is grounded. The over temperature protection circuit of claim 11, wherein the first transistor, the second transistor, and the third transistor are P-type MOS transistors. The over temperature protection circuit of claim 11, wherein the first diode, the second diode, and the third diode are PNP type bipolar junction transistors, and the PNP type is double The collector terminal of the polar junction transistor is coupled to the base terminal. The display is coupled to a computer host; and when the computer host executes an application and displays the application screen on the display, superimposing one of the patterns on the application screen. The display method of claim 1, wherein one of the patterns is a shooting quasi-heart pattern. The display method of claim 3, further comprising: setting the shot alignment pattern to a center of the display screen as a pattern center. The display method of claim 1, wherein one of the patterns is a timer pattern. The display method of claim 5, further comprising: displaying at least one location pattern on the display, wherein the location pattern indicates a location of the timer pattern on the display. The display method of claim 6, further comprising: setting the timer pattern on the display according to the location of the location pattern indication. The display method of claim 5, further comprising: adjusting the number of counts in the timer pattern according to an input signal. The display method of claim 5, further comprising driving the timer pattern according to a clock signal of the display for counting. The display method of claim 1, wherein the OSD option is a hierarchical structure, including at least a first layer OSD option and a second layer OSD option, wherein the first layer OSD option displays at least two category patterns, the first The Layer 2 OSD option displays a plurality of patterns based on the first layer of OSD option categories. The display method of claim 10, wherein the input signal comprises at least a first input signal and a second input signal, wherein displaying the one of the patterns on the display according to an input signal further comprises: Displaying the two types of patterns of the first layer of OSD options on the display; displaying, according to the first input signal, a plurality of patterns of the second layer OSD option of one of the two categories; and according to the second input A signal that displays one of the patterns on the display. The display method of claim 11, wherein the at least two category patterns of the first layer OSD option comprise: a quasi-heart category pattern and a timer category pattern. The display method of claim 12, wherein the plurality of patterns of the second layer OSD option further comprises: a plurality of alignment patterns or a plurality of timings Pattern. The display method of claim 13, wherein the plurality of alignment patterns have different appearance shapes and colors. The display method of claim 13, wherein the timer patterns have different appearance shapes, colors, and timing hours. The display method of claim 1, wherein the screen display control system further comprises an OSD control module and a control circuit coupled to the OSD control module and the display.