TW201430900A - Method of fabricating capacitor structure - Google Patents

Abstract

A method of fabricating a capacitor structure includes the following steps. Firstly, a substrate is provided. A first conductive layer, a first insulation layer, a second conductive layer and a second insulation layer are sequentially formed over the substrate. A hard mask material layer is formed on the second insulation layer. Then, the hard mask material layer is defined with a photo resist pattern, so that a hard mask is formed. After the photo resist pattern is removed, the second conductive layer is defined with the hard mask, so that a first electrode of the capacitor structure is formed.

Description

Capacitor structure manufacturing method

The present invention relates to a method of fabricating a semiconductor structure, and more particularly to a method of fabricating a capacitor structure.

For today's miniature integrated circuit, when the integration density of various circuit components is higher, the integrated circuit can obtain more or higher performance, among which metal-insulation-metal (hereinafter referred to as MIM) Capacitors are combined with various circuit components to be a widely used design. However, in the manufacturing process of miniature MIM capacitor structures, many sources of pollution can cause the performance of MIM capacitors to decrease or even fail. Therefore, how to avoid the above various pollution problems and manufacture a high-performance MIM capacitor is to develop the object of the present invention.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of fabricating a capacitor structure, the method comprising the following steps. First, a substrate is provided, and a first conductive layer, a first insulating layer, a second conductive layer and a second insulating layer are sequentially formed on the substrate. Next, a hard mask layer is formed over the second insulating layer. Thereafter, the hard mask layer is defined by a photoresist pattern to form a hard mask. And, after the photoresist pattern is removed, the second conductive layer is defined by a hard mask to form a first electrode of the capacitor structure.

The invention forms a hard mask by using a photoresist pattern to define a hard mask layer, and removes the photoresist After the pattern, the first electrode of the capacitor structure is formed by a hard mask, thereby avoiding the problem of contamination and manufacturing a high-performance MIM capacitor.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

100‧‧‧Base

111‧‧‧First conductive layer

112‧‧‧First insulation

113‧‧‧Second conductive layer

114, 1141‧‧‧Second insulation

115, 1151‧‧‧ hard mask layer

120‧‧‧hard mask

130‧‧‧resist pattern

140‧‧‧Inline structure

141‧‧‧Wiring insulation

142‧‧‧ Third conductive layer

150‧‧‧Insulation structure

151‧‧‧ Third insulation layer

152‧‧‧fourth insulation layer

160‧‧‧ fifth insulation

1101, 1102‧‧‧MIM capacitor structure

1131‧‧‧first electrode

1121‧‧‧ dielectric structure

1111‧‧‧second electrode

1131a, 1111a and 142a‧‧‧Contact plugins

1A to 1C are schematic cross-sectional views showing a part of steps according to an embodiment of the present invention.

Referring to FIG. 1A , first, a first conductive layer 111 , a first insulating layer 112 , a second conductive layer 113 , and a second insulating layer 114 are sequentially formed on the substrate 100 . Next, a hard mask layer 115 is formed over the second insulating layer 114. Then, the photoresist pattern 130 is formed on the hard mask layer 115 by using a lithography technique, and the hard mask layer 115 is defined by the photoresist pattern 130 to form a hard mask, or a second conductive layer as in this embodiment. The layer 113 is a stop layer, and the hard mask layer 115 and the second insulating layer 114 (the portion shown by a broken line in the figure) outside the photoresist pattern 130 are sequentially removed, and the remaining second insulating layer 1141 and the remaining hard mask are removed. The cover layer 1151 together constitutes the hard mask 120. In the technical solution of the present invention, the material or the doping type of the substrate; the material for forming the first conductive layer 111, the first insulating layer 112, the second conductive layer 113, and the second insulating layer 114 are not particularly limited, and wherein Different materials may be used to form the hard mask layer 115 and the second insulating layer 114 such that the hard mask layer 115 and the second insulating layer 114 have etch selectivity for the same etch recipe.

In this embodiment, the MIM capacitor structure uses titanium nitride (TiN) as a material for forming the second conductive layer 113 and/or the first conductive layer 111; and silicon nitride is used as the first insulating layer 112. And a material of the second insulating layer 114; and a silicon oxide as a material forming the hard mask layer 115. In addition, before the first insulating layer is formed over the substrate 100, the interconnect structure 140 may be selectively formed between the substrate 100 and the first conductive layer 111, and Insulation structure 150. In detail, various functional circuits (not shown) may be previously completed in the substrate 100, and thereafter, wirings as various functional circuits are formed on the surface of the substrate, including the wiring insulating layer 141 and the third conductive layer formed by the damascene process. Layer 142. Then, a third insulating layer 151 and a fourth insulating layer 152 are sequentially formed on the interconnect structure 140 to form an insulating structure 150, wherein a material similar to the first insulating layer 112 may be selected, for example, germanium nitride ( Silicon nitride is formed to form a third insulating layer 151; and a material similar to the hard mask layer 115, such as silicon oxide, to form a fourth insulating layer 152.

It is worth noting that the organic material as a photoresist is mostly a long-chain organic molecule containing many reactive functional groups. During the etching process using the patterned photoresist as a mask, some of the long-chain organic molecules in the photoresist pattern are still decomposed by the etching process. After inventors carefully analyzed the causes of many functional circuits that have electrical defects, it was found that long-chain organic molecules decomposed by the etching process are easily combined with various materials to form a source of pollution, especially in combination with metal atoms. The resulting organometallic complex, the organometallic complex, has high stability in addition to the molecular structure to be difficult to remove, and is more conductive because it contains a metal atom, on an insulating layer in a functional circuit, for example: MIM When the surface of the sidewall of the dielectric structure of the capacitor is left with residual organic metal, it may cause a short circuit of the functional circuit to fail. Based on the above analysis results, the inventor of the present invention proposed a technical solution for defining a conductive layer with a hard mask to prevent contamination problems caused by residual photoresist materials.

Referring to FIG. 1B, after the photoresist pattern is removed, the second conductive layer 113 is defined by the hard mask 120, and the first insulating layer 112 is used as a stop layer to form the first electrode 1131 of the MIM capacitor structure. Since the photoresist pattern has been removed, the step of reducing the transfer process equipment can be selected, and the hard mask layer 115 and the second insulating layer 114 are in-situ removed using the same etching chamber. The photoresist 130 is removed to form the hard mask 120. The first electrode 1131, the first insulating layer 112, and the first conductive layer 111 may constitute the MIM capacitor structure 1101.

Referring to FIG. 1C , and referring to FIG. 1A and FIG. 1B , the MIM capacitor structure 1101 in FIG. 1B is disposed on the interconnect structure 140 and the insulating structure 150 for integrating the MIM. After the capacitor and the functional circuit are connected, a mask (not shown) may be further formed on the MIM capacitor structure 1101, and a portion of the first insulating layer 112, a portion of the first conductive layer 111, and a portion thereof are sequentially removed. The fourth insulating layer 152 forms a dielectric structure 1121 and a second electrode 1111. The first electrode 1131, the dielectric structure 1121, and the second electrode 1111 may constitute the MIM capacitor structure 1102. Next, on the MIM capacitor structure 1102 and the interconnect structure 140, a material similar to the hard mask layer 115, such as silicon oxide, may be selected to form the fifth insulating layer 160. Thereafter, contact plugs 1131a, 1111a, and 142a are formed on the first electrode 1131, the second electrode 1111, and the third conductive layer 142, respectively, to integrate the MIM capacitor 1102 and the internal wiring of the functional circuit.

It is to be noted that the process of forming the contact plugs 1131a, 1111a, and 142a shown in FIG. 1C includes openings (not shown) formed above the first electrode 1131, the second electrode 1111, and the third conductive layer 142, respectively. Referring to the descriptions of 1A and 1C, the step of forming the opening needs to remove a portion of the hard mask layer 1151 and a portion of the fifth insulating layer 160, and then remove portions of the second insulating layer 1141, part of the dielectric structure 1121, and portions thereof. The third insulating layer 151. In the present embodiment, the hard mask layer 115 and the fifth insulating layer 160 are formed of the same silicon oxide, so that a portion of the fifth insulating layer 160 and a portion of the hard mask layer 1151 can be simultaneously removed. The material of the first insulating layer 112, the second insulating layer 114, and the third insulating layer 151 is silicon nitride, and the hard mask layer 115 and the second insulating layer 114 have different etching rates for removing. During a portion of the fifth insulating layer 160 and a portion of the hard mask layer 1151, the second insulating layer 1141, the dielectric structure 1121, and the third insulating layer 151 can serve as a stop layer without causing excessive etching of the MIM capacitor 1102. Dielectric structure 1121. Then, a portion of the second insulating layer 1141, a portion of the dielectric structure 1121, and a portion of the third insulating layer 151 can be simultaneously removed to form an opening. Thereafter, the contact plugs 1131a, 1111a, and 142a are completed by filling the openings with a conductive material.

In summary, in the manufacturing method of the capacitor structure of the present invention, a hard mask is formed by using a photoresist pattern to form a hard mask, and after removing the photoresist pattern, the first electrode of the capacitor structure is formed by a hard mask, thereby being effective Prevent contamination problems caused by residual photoresist materials. In addition, this issue It is also possible to select a material having an etch selectivity to form a dielectric structure of a hard mask layer and a MIM capacitor, respectively, in addition to avoiding excessive removal of the dielectric structure of the MIM capacitor, thereby achieving the effects of reducing the etching process step and improving the capacitance performance.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection shall be subject to the definition of the patent application scope in this case.

1141‧‧‧Second insulation

1151‧‧‧hard mask layer

120‧‧‧hard mask

140‧‧‧Inline structure

141‧‧‧Wiring insulation

142‧‧‧ Third conductive layer

150‧‧‧Insulation structure

151‧‧‧ Third insulation layer

152‧‧‧fourth insulation layer

160‧‧‧ fifth insulation

1102‧‧‧MIM capacitor structure

1131‧‧‧first electrode

1121‧‧‧ dielectric structure

1111‧‧‧second electrode

1131a, 1111a and 142a‧‧‧Contact plugins

Claims (10)

A method for manufacturing a capacitor structure, the method comprising the steps of: providing a substrate, a first conductive layer, a first insulating layer, a second conductive layer and a second insulating layer are sequentially formed on the substrate; Forming a hard mask layer over the second insulating layer; defining the hard mask layer in a photoresist pattern to form a hard mask; removing the photoresist pattern; and defining the second conductive layer with the hard mask to form One of the capacitor structures is a first electrode. The method of manufacturing a capacitor structure according to claim 1, wherein the first insulating layer and the second insulating layer are formed of the same material. The method of fabricating a capacitor structure according to claim 1, wherein the second insulating layer and the material of the hard mask layer are formed to have different etching rates. The method for manufacturing a capacitor structure according to claim 1, wherein the step of forming the hard mask comprises using the second conductive layer as a stop layer, and sequentially removing the hard mask layer exposed outside the photoresist pattern And the second insulating layer and the photoresist mask are removed in situ. The method for manufacturing a capacitor structure according to claim 1, wherein the step of defining the second conductive layer is such that the first insulating layer is a stop layer, and the second conductive layer exposing the hard mask is removed. The method of fabricating a capacitor structure according to claim 1, wherein an in-line structure and an insulating structure are formed on the substrate before the first conductive layer is formed. The method for manufacturing a capacitor structure according to claim 6, wherein the method for forming the interconnect structure comprises the steps of: forming a wiring insulating layer on the substrate; and forming a third conductive layer in the wiring insulating layer Floor. The method of manufacturing a capacitor structure according to claim 7, wherein the method of forming the insulating structure comprises the steps of: forming a third insulating layer on the interconnect structure; and forming a third insulating layer The fourth insulating layer constitutes the insulating structure. The method of manufacturing a capacitor structure according to claim 8, wherein the third insulating layer is formed of the same material as the first insulating layer. The method for manufacturing a capacitor structure according to claim 1, further comprising sequentially removing the portion of the first insulating layer and the first conductive layer to form a dielectric structure and a second electrode.