CN112018240B - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN112018240B CN112018240B CN201910469713.5A CN201910469713A CN112018240B CN 112018240 B CN112018240 B CN 112018240B CN 201910469713 A CN201910469713 A CN 201910469713A CN 112018240 B CN112018240 B CN 112018240B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
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Abstract
The invention relates to a semiconductor device and a preparation method thereof, when a first contact plug and a second contact plug are formed, steps are formed between the first contact plug and a first dielectric layer and between the second contact plug and the first dielectric layer, and further when a first metal layer is formed subsequently, the steps are also formed on the first metal layer; then directly depositing a second dielectric layer and a second metal layer, then photoetching once, etching the second metal layer and the second dielectric layer, staying at the step of the first metal layer, and exposing the residual second dielectric layer by the first metal layer on the second contact plug; and then forming an etching protective layer on the exposed first metal layer on the second contact plug, and etching the residual second dielectric layer and the first metal layer outside the position of the first contact plug. Compared with the traditional two-time photoetching, the photoetching method has the advantages that only one-time photoetching is performed, so that the one-time photoetching process is reduced, and a layer of mask is saved, so that the production cost is reduced.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a semiconductor device and a preparation method thereof.
Background
Passive components such as capacitors and resistors are commonly included in semiconductor devices, wherein the capacitors include polysilicon-dielectric-polysilicon (PIP) capacitors and Metal-Insulator-Metal (MIM) capacitors. MIM capacitors are widely used in high frequency devices due to their relatively low resistivity. The MIM capacitor is generally formed simultaneously when forming the metal interconnection layer, but when forming the upper and lower electrode plates of the MIM capacitor structure, photolithography and etching are often performed once, which results in higher production cost.
Disclosure of Invention
In view of this, it is necessary to provide a semiconductor device and a method for manufacturing the same, which address the problem of high production cost of MIM capacitors.
A method of making a semiconductor device, comprising:
forming a first dielectric layer on a semiconductor substrate and a first layer of contact plugs which penetrate through the first dielectric layer and are arranged at intervals, wherein the first layer of contact plugs at least comprise first contact plugs and second contact plugs;
grinding or etching the first dielectric layer to form steps between the first contact plug and the first dielectric layer and between the second contact plug and the first dielectric layer;
depositing a first metal layer, wherein steps are reserved between the first metal layer on the first contact plug and the first metal layer on the first dielectric layer and between the first metal layer on the second contact plug and the first metal layer on the first dielectric layer;
depositing a second dielectric layer and a second metal layer in sequence;
etching the second metal layer and the second dielectric layer, wherein the second metal layer and the second dielectric layer on the first contact plug are reserved, the first metal layer on the second contact plug is used as an etching stop layer, when etching is stopped, the second dielectric layer is reserved on the first metal layer except the position of the first contact plug, and the first metal layer on the second contact plug is exposed out of the second dielectric layer;
forming an etching protection layer on the first metal layer on the second contact plug;
etching the residual second dielectric layer and the first metal layer outside the position of the first layer contact plug;
and depositing a third dielectric layer and manufacturing a second layer contact plug.
In one embodiment, the step of forming a first dielectric layer on a semiconductor substrate and a first layer of contact plugs penetrating through the first dielectric layer and arranged at intervals comprises:
providing a semiconductor substrate, and forming a first dielectric layer on the semiconductor substrate;
etching the first dielectric layer until the surface of the semiconductor substrate is exposed so as to form a first through hole and a second through hole;
depositing a conductive material in the first and second vias to form the first and second contact plugs, respectively.
In one embodiment, the step of grinding or etching the first dielectric layer to form steps between the first contact plug and the first dielectric layer and between the second contact plug and the first dielectric layer includes:
grinding the residual conductive material on the surface of the first medium layer in a first chamber until the surface of the first medium layer is exposed;
and grinding the first medium layer in the second chamber to form steps between the first contact plug and the first medium layer and between the second contact plug and the first medium layer.
In one embodiment, the step of grinding or etching the first dielectric layer to form steps between the first contact plug and the first dielectric layer and between the second contact plug and the first dielectric layer includes:
etching the residual conductive material on the surface of the first dielectric layer by using a first etching gas so as to expose the surface of the first dielectric layer;
introducing reaction gas into the reaction chamber so that the reaction gas reacts with the first contact plug and the second contact plug to form a protective layer;
etching the first dielectric layer by using a second etching gas so as to form steps between the first contact plug and the first dielectric layer and between the second contact plug and the first dielectric layer;
and removing the protective layer.
In one embodiment, the step height is
In one embodiment, the step of etching the second metal layer and the second dielectric layer, and the step of retaining the second metal layer and the second dielectric layer on the first contact plug includes:
forming a photoresist layer on the surface of the second metal layer;
and exposing and developing the photoresist layer, reserving the corresponding photoresist layer on the first contact plug, and etching the second metal layer and the second dielectric layer by using the corresponding photoresist layer on the first contact plug as a mask.
In one embodiment, the step of forming an etching protection layer on the first metal layer on the second contact plug includes:
and introducing reaction gas into the reaction chamber, wherein the reaction gas reacts with the first metal layer on the surface of the second contact plug to form the etching protection layer on the surface of the first metal layer on the surface of the second contact plug.
In one embodiment, the reactive gas comprises oxygen and the etch protection layer comprises titanium oxide or titanium oxynitride.
In one embodiment, the step of etching the remaining second dielectric layer and the first metal layer outside the position of the first layer contact plug includes:
etching the second dielectric layer and the first metal layer outside the position of the first layer of contact plug by using the photoresist layer corresponding to the second metal layer on the first contact plug and the etching protective layer as masks;
the method also comprises the following steps after the residual second dielectric layer and the first metal layer outside the position of the first layer contact plug are etched:
and removing the etching protective layer by adopting sulfur hexafluoride, and removing the photoresist layer.
A semiconductor device is prepared by the method.
According to the semiconductor device and the preparation method thereof, when the first contact plug and the second contact plug are formed, the first contact plug and the second contact plug and the first medium layer form steps, and then when the first metal layer is formed subsequently, the steps are formed on the first metal layer; then directly depositing a second dielectric layer and a second metal layer, then photoetching once, and etching the second metal layer and the second dielectric layer, wherein the etching can stay at the step of the first metal layer due to the existence of the step on the first metal layer, the second metal layer and the second dielectric layer on the first contact plug are reserved and respectively used as an upper pole plate and a middle dielectric layer of the capacitor, and the first metal layer on the second contact plug exposes out of the residual second dielectric layer; and then forming an etching protective layer on the exposed first metal layer on the second contact plug, and etching the residual second dielectric layer and the first metal layer outside the position of the first layer of contact plug, wherein the first metal layer on the first contact plug is reserved as a lower electrode plate of the capacitor, and the first metal layer on the second contact plug is reserved as a contact pad between the upper contact plug and the lower contact plug. Compared with the traditional two-time photoetching, the photoetching method has the advantages that only one-time photoetching is performed, so that the one-time photoetching process is reduced, and a layer of mask is saved, so that the production cost is reduced. Moreover, due to the formation of the upper step of the first metal layer, the upper surface area of the contact pad or the upper and lower electrode plates of the capacitor is larger than that of the contact plug, and the position of the upper and lower electrode plates of the capacitor does not deviate obviously but stably falls on the top of the contact plug and is located at the position of the contact plug, so that the process window for forming the second layer contact plug can be improved. Meanwhile, due to the formation of the steps on the first metal layer, self-positioning can be carried out in the etching process.
Drawings
Fig. 1 is a flow chart of a method for fabricating a semiconductor device according to an embodiment of the present application;
fig. 2A to 2J are schematic cross-sectional structures of semiconductor devices fabricated according to the method of fig. 1.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.
It will be understood that when an element is referred to as being "disposed on" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only and do not represent the only embodiments.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
Referring to fig. 1, an embodiment of the present application provides a method for manufacturing a semiconductor device, including the following steps:
s100: the method comprises the steps of forming a first dielectric layer on a semiconductor substrate, and forming a first layer of contact plugs which penetrate through the first dielectric layer and are arranged at intervals, wherein the first layer of contact plugs at least comprise a first contact plug and a second contact plug.
In this embodiment, the Semiconductor substrate may include devices and circuits that have already been fabricated, such as a circuit composed of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). After the circuit structure is formed, the capacitor, the resistor and the metal interconnection layer are required to be prepared on the semiconductor substrate to realize the specific logic function.
Specifically, referring to fig. 2A, a first dielectric layer 110 is first deposited on a semiconductor substrate 100. The first dielectric layer 110 may be an insulating dielectric such as silicon oxide, silicon nitride, or silicon oxynitride, and may be prepared by chemical vapor deposition or physical vapor deposition. The first dielectric layer 110 may serve as an insulating dielectric for the front-level interconnect layer to isolate the connection lines in the front-level dielectric layer.
Photoresist is coated on the first dielectric layer 110, the photoresist is exposed and developed, and then the first dielectric layer 110 may be etched by using a dry etching technique until the surface of the semiconductor substrate 100 is exposed, so as to form a first through hole and a second through hole penetrating through the first dielectric layer 110. It is understood that there may be a plurality of through holes, and the embodiment is described by taking two through holes as an example.
Conductive materials are deposited within the first and second vias, respectively, to form first and second contact plugs 120 and 130. The conductive medium may be tungsten, or may be any of copper, aluminum, silver, and alloys thereof.
Since a portion of the conductive material is deposited on the surface of the first dielectric layer 110 when the conductive material is deposited in the via hole, the surface of the first dielectric layer 110 needs to be processed after the deposition is completed to remove the residual conductive material on the surface of the first dielectric layer 110.
S200: and grinding or etching the first dielectric layer to form steps between the first contact plug and the first dielectric layer and between the second contact plug and the first dielectric layer.
In this embodiment, a step may be formed when the residual conductive material on the surface of the first dielectric layer 110 is removed.
Specifically, referring to fig. 2B, in one embodiment, the removal can be performed by grinding. First, the conductive material on the surface of the first dielectric layer 110 is polished in a chamber to remove the residual conductive material on the surface. And detecting whether the surface of the first medium layer 110 is ground or not by using an end point detection mechanism, and stopping grinding when the surface of the first medium layer 110 is reached.
Then, the semiconductor device is moved to a second chamber, and the first dielectric layer 110 is polished in the second chamber, so that steps are formed between the first contact plug 120 and the first dielectric layer 110 and between the second contact plug 130 and the first dielectric layer 110. When grinding in first cavity and second cavity, the lapping liquid that adopts is different, and the effect object of lapping liquid is also different, and then can make and grind different layers in different cavities. In this embodiment, the step height can be controlled by controlling the grinding time, wherein the step height can be
The increase of the step height contributes to improvementAnd forming a process window for the upper connecting wire. Since the first contact plug 120 and the second contact plug 130 are stepped from the first dielectric layer 110, a subsequently deposited first electrode layer may have a stepped surface. In addition, since the first dielectric layer 110 is thick, a through hole formed by etching the first dielectric layer 110 is deep, and when the first contact plug 120 and the second contact plug 130 are deposited in the through hole, a gap may be generated between sidewalls of the first contact plug 120 and the second contact plug 130 and the first dielectric layer 110. By grinding the first dielectric layer 110, steps are generated between the first contact plug 120 and the second contact plug 130 and the first dielectric layer 110, and then the gap can be exposed, so that the subsequently formed first metal layer 140 can cover the steps and fill the gap between the first contact plug 120, the second contact plug 130 and the first dielectric layer 110.
In another embodiment, first contact plug 120 and second contact plug 130 may be stepped with first dielectric layer 110 in other ways. For example, after the first dielectric layer 110, the first contact plug 120, and the second contact plug 130 are formed on the surface of the semiconductor substrate, steps are formed by etching using a dry etching process. In this embodiment, the first etching gas may be used to etch the residual conductive material on the surface of the first dielectric layer 110 to expose the surface of the first dielectric layer 110. Wherein the first etching gas may be sulfur hexafluoride. Then, a reaction gas is introduced into the reaction chamber, so that the reaction gas reacts with the first contact plug 120 and the second contact plug 130 to form a protective layer, and the first contact plug 120 and the second contact plug 130 are prevented from being etched in a subsequent process. In this embodiment, the reaction gas may be oxygen, and the oxygen reacts with the first contact plug 120 and the second contact plug 130 to generate metal oxide, which has high etching resistance, so that the first contact plug 120 and the second contact plug 130 can be protected during the etching process.
And then introducing a second etching gas into the reaction chamber to etch the first dielectric layer 110, so that the first contact plug 120 and the second contact plug 130 form steps with the first dielectric layer 110 respectively. In this embodiment, the second etching gas may be carbon tetrafluoride, trifluoromethane, or the like. Can be controlled by controlling the etching time, etching rate and the like for etching the first dielectric layer 110Making the step height so that the step height reaches
After the etching is completed, the protective layer may be removed by using sulfur hexafluoride gas etching, so as to form a first metal layer on the surfaces of the first contact plug 120 and the second contact plug 130 in the following process.
S300: and depositing a first metal layer, wherein steps are reserved between the first metal layer on the first contact plug and the first metal layer on the first dielectric layer and between the first metal layer on the second contact plug and the first metal layer on the first dielectric layer.
Referring to fig. 2C, a first metal layer 140 may be deposited on the front structure surface by using a chemical vapor deposition, a physical vapor deposition, or an atomic layer deposition method, and the material of the first metal layer 140 may be titanium or titanium nitride. Since the deposition rates at the positions are the same during deposition, the thicknesses of the formed first metal layer 140 are uniform, so that steps can be remained between the first metal layer 140 on the first contact plug 120 and the first metal layer 140 on the first dielectric layer 110, and steps are also remained between the first metal layer 140 on the second contact plug 130 and the first metal layer 140 on the first dielectric layer 110.
S400: and depositing a second dielectric layer and a second metal layer in sequence.
Specifically, referring to fig. 2D, a second dielectric layer 150 and a second metal layer 160 may be sequentially deposited on the surface of the first metal layer 140 by using a chemical vapor deposition or a physical vapor deposition method. The material of the second dielectric layer 150 may be silicon oxide, silicon nitride or other high dielectric constant material. The material and formation method of the second metal layer 160 may be the same as those of the first metal layer 140.
S500: and etching the second metal layer and the second dielectric layer, reserving the second metal layer and the second dielectric layer on the first contact plug, taking the first metal layer on the second contact plug as an etching stop layer, and when the etching stops, leaving the second dielectric layer on the first metal layer outside the position of the first contact plug.
Referring to fig. 2E, in this step, the second metal layer 160 and the second dielectric layer 150 need to be patterned. Specifically, the photoresist layer 170 is coated on the second metal layer 160, and after the photoresist layer 170 is patterned, etching gas is introduced into the reaction chamber to etch the second metal layer 160 and the second dielectric layer 150, and the second metal layer 160 and the second dielectric layer 150 on the first contact plug 120 are remained. The remaining second metal layer 160 may serve as an upper plate of a capacitor and the remaining second dielectric layer 150 may serve as a dielectric layer of the capacitor. The first metal layer 140 on the second contact plug 130 is used as an etching stop layer, and an optical critical dimension measurement technology is used to detect whether the etching reaches the first metal layer 140 on the second contact plug 130, and the etching stops when the etching reaches the first metal layer 140 on the second contact plug 130. The first metal layer 140 on the second contact plug 130 may expose the remaining second dielectric layer 150.
S600: and forming an etching protection layer on the surface of the first metal layer on the second contact plug.
Referring to fig. 2F, before etching the first metal layer 140, an etching protection layer is formed on the surface of the first metal layer 140 on the second contact plug 130. Specifically, the reaction gas is introduced into the reaction chamber, and the reaction gas reacts only with the first metal layer 140 on the second contact plug 130 but does not react with the second dielectric layer 150, so that the reaction can occur on the surface of the first metal layer 140 on the second contact plug 130 to form the etching protection layer 141. In this embodiment, the reaction gas may be oxygen, and titanium oxide or titanium oxynitride generated by the reaction of oxygen and titanium or titanium nitride has a high etching resistance, so that the first metal layer 140 on the second contact plug 130 is protected from being etched in the subsequent etching step.
S700: and etching the residual second dielectric layer and the first metal layer outside the position of the first layer contact plug.
Referring to fig. 2G, in this step, a self-aligned etching is performed by using the photoresist layer 170 remaining on the second metal layer 160 and the etching protection layer 141, and an etching gas is introduced into the reaction chamber to etch the remaining second dielectric layer 150 and the first metal layer 140 outside the position of the first contact plug, so as to form a capacitor structure on the first contact plug 120 and a contact pad on the second contact plug 130, where the first metal layer 140 remaining on the first contact plug 120 is a lower plate of the capacitor structure. Since steps are formed between the first contact plug 120 and the first dielectric layer 110 and between the second contact plug 130 and the first dielectric layer 110, the first contact plug 120 and the second contact plug 130 both protrude from the surface of the first dielectric layer 110. As shown in fig. 2G, the first metal layer 140 (i.e., the lower plate of the capacitor and the contact pad) remaining after etching covers the surfaces and the side surfaces of the protruding first contact plug 120 and the protruding second contact plug 130, so that the upper surface area of the first metal layer 140 is larger than the upper surface areas of the first contact plug 120 and the second contact plug 130, thereby providing a larger process window for the second contact plug formed on the capacitor and the contact pad later. In addition, compared with the conventional process in which the first metal layer 140 is etched by using the mask, the self-aligned etching is performed by using the reserved photoresist layer 170 and the etching protection layer 141 generated by the reaction, so that a photolithography process is reduced, a layer of mask is saved, and the production cost can be reduced.
After this step, the etching protection layer 141 and the photoresist layer 170 are also removed. Specifically, the etching protection layer 141 may be removed by etching using sulfur hexafluoride gas, and the photoresist layer 170 may be removed by using a plasma dry etching method.
S800: and depositing a third dielectric layer and manufacturing a second layer contact plug.
Specifically, referring to fig. 2H, the third dielectric layer 180 may be formed by chemical vapor deposition or physical vapor deposition, and the material of the third dielectric layer 180 may be the same as the material of the first dielectric layer 110, and is silicon oxide, silicon nitride or silicon oxynitride.
Referring to fig. 2I, after the third dielectric layer 180 is formed, the third dielectric layer 180 is patterned. Specifically, a photoresist may be coated on the third dielectric layer 180, exposed and developed, and then the third dielectric layer 180 is etched to form the third through hole 181 and the fourth through hole 182. The etching of the third via 181 to the surface of the second metal layer 160 is stopped, and the etching of the fourth via 182 to the surface of the first metal layer 140 (i.e., the contact pad) is stopped. When the third through hole 181 and the fourth through hole 182 are formed, since the surface area of the first metal layer 140 is larger than the surface areas of the first contact plug 120 and the second contact plug 130, a process window is large, and the process difficulty in forming the third through hole 181 and the fourth through hole 182 is reduced.
Referring to fig. 2J, a conductive medium is deposited in the third through hole 181 and the fourth through hole 182 to form a third connection line 191 and a fourth connection line 192, respectively. The third and fourth connection lines 191 and 192 may be formed by the same method and material as those of the first and second contact plugs 120 and 130.
Another embodiment of the present application provides a semiconductor device fabricated by the foregoing fabrication method.
In the semiconductor device and the manufacturing method provided by the foregoing embodiment, when the first contact plug and the second contact plug are formed, the first contact plug and the second contact plug are both stepped with the first dielectric layer, and further when the first metal layer is formed subsequently, the first metal layer is also stepped; then directly depositing a second dielectric layer and a second metal layer, then photoetching once, and etching the second metal layer and the second dielectric layer, wherein the etching can stay at the step of the first metal layer due to the existence of the step on the first metal layer, the second metal layer and the second dielectric layer on the first contact plug are reserved and respectively used as an upper pole plate and a middle dielectric layer of the capacitor, and the first metal layer on the second contact plug exposes out of the residual second dielectric layer; and then forming an etching protective layer on the exposed first metal layer on the second contact plug, and etching the residual second dielectric layer and the first metal layer outside the position of the first layer of contact plug, wherein the first metal layer on the first contact plug is reserved as a lower electrode plate of the capacitor, and the first metal layer on the second contact plug is reserved as a contact pad between the upper contact plug and the lower contact plug. Compared with the traditional two-time photoetching, the photoetching method has the advantages that only one-time photoetching is performed, so that the one-time photoetching process is reduced, and a layer of mask is saved, so that the production cost is reduced. Moreover, due to the formation of the upper step of the first metal layer, the upper surface area of the contact pad or the upper and lower electrode plates of the capacitor is larger than that of the contact plug, and the position of the upper and lower electrode plates of the capacitor does not deviate obviously but stably falls on the top of the contact plug and is located at the position of the contact plug, so that the process window for forming the second layer contact plug can be improved. Meanwhile, due to the formation of the steps on the first metal layer, self-positioning can be carried out in the etching process.
All possible combinations of the technical features of the above embodiments may not be described for the sake of brevity, but should be considered as within the scope of the present disclosure as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (8)
1. A method of manufacturing a semiconductor device, comprising:
forming a first dielectric layer on a semiconductor substrate and a first layer of contact plugs which penetrate through the first dielectric layer and are arranged at intervals, wherein the first layer of contact plugs at least comprise first contact plugs and second contact plugs;
grinding or etching the first dielectric layer to form steps between the first contact plug and the first dielectric layer and between the second contact plug and the first dielectric layer;
depositing a first metal layer, wherein steps are reserved between the first metal layer on the first contact plug and the first metal layer on the first dielectric layer and between the first metal layer on the second contact plug and the first metal layer on the first dielectric layer;
depositing a second dielectric layer and a second metal layer in sequence;
forming a photoresist layer on the surface of the second metal layer, exposing and developing the photoresist layer, reserving the corresponding photoresist layer on the first contact plug, etching the second metal layer and the second dielectric layer by using the corresponding photoresist layer on the first contact plug as a mask, reserving the second metal layer and the second dielectric layer on the first contact plug, using the first metal layer on the second contact plug as an etching stop layer, and when the etching is stopped, leaving the second dielectric layer on the first metal layer except the position of the first contact plug, and exposing the second dielectric layer on the first metal layer on the second contact plug;
forming an etching protection layer on the first metal layer on the second contact plug, wherein the step of introducing reaction gas into the reaction chamber is included, and the reaction gas reacts with the first metal layer on the second contact plug to form the etching protection layer on the surface of the first metal layer on the second contact plug;
etching the residual second dielectric layer and the first metal layer outside the position of the first layer contact plug;
and depositing a third dielectric layer and manufacturing a second layer contact plug.
2. The method of claim 1, wherein forming a first dielectric layer on the semiconductor substrate and a first layer of contact plugs spaced through the first dielectric layer comprises:
providing a semiconductor substrate, and forming a first dielectric layer on the semiconductor substrate;
etching the first dielectric layer until the surface of the semiconductor substrate is exposed so as to form a first through hole and a second through hole;
depositing a conductive material in the first and second vias to form the first and second contact plugs, respectively.
3. The method of claim 2, wherein the step of grinding or etching the first dielectric layer to form steps between the first contact plug and the first dielectric layer and between the second contact plug and the first dielectric layer comprises:
grinding the residual conductive material on the surface of the first medium layer in a first chamber until the surface of the first medium layer is exposed;
and grinding the first medium layer in the second chamber to form steps between the first contact plug and the first medium layer and between the second contact plug and the first medium layer.
4. The method of claim 2, wherein the step of grinding or etching the first dielectric layer to form steps between the first contact plug and the first dielectric layer and between the second contact plug and the first dielectric layer comprises:
etching the residual conductive material on the surface of the first dielectric layer by using a first etching gas so as to expose the surface of the first dielectric layer;
introducing reaction gas into the reaction chamber so that the reaction gas reacts with the first contact plug and the second contact plug to form a protective layer;
etching the first dielectric layer by using a second etching gas so as to form steps between the first contact plug and the first dielectric layer and between the second contact plug and the first dielectric layer;
and removing the protective layer.
5. A method according to claim 3 or 4, wherein the step height is
6. The method of claim 5, wherein the reactive gas comprises oxygen and the etch protection layer comprises titanium oxide or titanium oxynitride.
7. The method of claim 6, wherein etching the remaining second dielectric layer and the first metal layer outside the location of the first layer contact plug comprises:
etching the second dielectric layer and the first metal layer outside the position of the first layer of contact plug by using the photoresist layer corresponding to the second metal layer on the first contact plug and the etching protective layer as masks;
the method also comprises the following steps after the residual second dielectric layer and the first metal layer outside the position of the first layer contact plug are etched:
and removing the etching protective layer by adopting sulfur hexafluoride, and removing the photoresist layer.
8. A semiconductor device prepared by the method of any one of claims 1 to 7.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6258691B1 (en) * | 1998-07-16 | 2001-07-10 | Samsung Electronics Co., Ltd. | Cylindrical capacitor and method for fabricating same |
| US20030104638A1 (en) * | 2001-12-01 | 2003-06-05 | Wan-Don Kim | Method of fabricating capacitor of semiconductor device |
| CN103383933A (en) * | 2012-05-02 | 2013-11-06 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of fabricating |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6258691B1 (en) * | 1998-07-16 | 2001-07-10 | Samsung Electronics Co., Ltd. | Cylindrical capacitor and method for fabricating same |
| US20030104638A1 (en) * | 2001-12-01 | 2003-06-05 | Wan-Don Kim | Method of fabricating capacitor of semiconductor device |
| CN103383933A (en) * | 2012-05-02 | 2013-11-06 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of fabricating |
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