TW201430095A - Dicing tape integrated adhesive sheet, method of manufacturing semiconductor device using dicing tape integrated adhesive sheet, and semiconductor device - Google Patents

Dicing tape integrated adhesive sheet, method of manufacturing semiconductor device using dicing tape integrated adhesive sheet, and semiconductor device Download PDF

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TW201430095A
TW201430095A TW102145448A TW102145448A TW201430095A TW 201430095 A TW201430095 A TW 201430095A TW 102145448 A TW102145448 A TW 102145448A TW 102145448 A TW102145448 A TW 102145448A TW 201430095 A TW201430095 A TW 201430095A
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film
dicing tape
back surface
sheet
substrate
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TW102145448A
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TWI615453B (en
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Goji Shiga
Koji Mizuno
Naohide Takamoto
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Nitto Denko Corp
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Priority claimed from JP2013088565A external-priority patent/JP2014135468A/en
Priority claimed from JP2013088568A external-priority patent/JP2014135469A/en
Priority claimed from JP2013088566A external-priority patent/JP6129629B2/en
Priority claimed from JP2013088567A external-priority patent/JP6297786B2/en
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Abstract

A dicing tape integrated adhesive sheet including a substrate, a dicing tape in which a pressure-sensitive adhesive layer is laminated on the substrate, and an adhesive sheet formed on the pressure-sensitive adhesive layer, wherein a peeling force between the pressure-sensitive adhesive layer and the adhesive sheet is 0.02 to 0.5 N/20 mm obtained with a peeling test at a peeling rate of 10 m/minute and a peeling angle of 150 DEG , and an absolute value of a peeling electrification voltage is 0.5 kV or less when the pressure-sensitive adhesive layer and the adhesive sheet are peeled off under conditions of the peeling test.

Description

切晶帶一體型接著片材、使用切晶帶一體型接著片材之半導體裝置之製造方法、及半導體裝置 Cutting strip integrated type bonding sheet, manufacturing method of semiconductor device using dicing tape integrated type bonding sheet, and semiconductor device

本發明係關於一種切晶帶一體型接著片材、使用切晶帶一體型接著片材之半導體裝置之製造方法、及半導體裝置。 The present invention relates to a dicing tape-integrated sheet, a method of manufacturing a semiconductor device using the dicing tape-integrated sheet, and a semiconductor device.

近年來,進一步要求半導體裝置及其封裝體之薄型化、小型化。因此,作為半導體裝置及其封裝體,廣泛利用將半導體晶片等半導體元件藉由倒裝晶片接合安裝(倒裝晶片連接)於基板上而得之倒裝晶片型之半導體裝置。該倒裝晶片連接係以半導體晶片之電路面與基板之電極形成面相對之方式進行固定者。於此種半導體裝置等中,存在利用保護膜保護半導體晶片之背面而防止半導體晶片之損傷等之情形。 In recent years, the semiconductor device and its package have been required to be thinner and smaller. Therefore, as a semiconductor device and a package thereof, a flip-chip type semiconductor device obtained by flip-chip bonding (flip-chip bonding) of a semiconductor element such as a semiconductor wafer is widely used. The flip chip connection is performed such that the circuit surface of the semiconductor wafer faces the electrode forming surface of the substrate. In such a semiconductor device or the like, there is a case where the back surface of the semiconductor wafer is protected by a protective film to prevent damage of the semiconductor wafer or the like.

先前,作為上述保護膜,存在於切晶帶上積層有作為保護膜之倒裝晶片型半導體背面用膜之切晶帶一體型半導體背面用膜(例如參照專利文獻1)。於使用該切晶帶一體型半導體背面用膜之半導體裝置之製造步驟中,首先,將半導體晶圓貼附固定於切晶帶一體型半導體背面用膜之倒裝晶片型半導體背面用膜上,於該狀態下進行切割。藉此,半導體晶圓被單片化成特定之尺寸,成為半導體晶片。繼而,進行半導體晶片之拾取,以將固定於切晶帶一體型半導體背面用膜之半導體晶片與倒裝晶片型半導體背面用膜一起自切割膜剝離。 In the above-mentioned protective film, a film for a diced tape-integrated semiconductor back surface in which a film for flip chip type semiconductor back surface is used as a protective film is laminated on a dicing tape (see, for example, Patent Document 1). In the manufacturing process of the semiconductor device using the film for the dicing tape-integrated semiconductor back surface, first, the semiconductor wafer is attached and fixed to the film for flip chip type semiconductor back surface of the film for dicing tape-integrated semiconductor back surface, Cutting is performed in this state. Thereby, the semiconductor wafer is singulated into a specific size to become a semiconductor wafer. Then, the semiconductor wafer is picked up, and the semiconductor wafer fixed to the film for dicing tape-integrated semiconductor back surface is peeled off from the dicing film together with the film for flip-chip type semiconductor back surface.

又,於半導體裝置之製造中,除了使用倒裝晶片型半導體背面用膜以外,亦存在例如使用於切晶帶上積層黏晶膜(die-bond film)或底 部填充片材(underfill sheet)等而成之切晶帶一體型接著片材之情形。黏晶膜係用於將半導體晶片向被黏著體進行黏晶之膜,底部填充片材係用於將倒裝晶片型半導體裝置中之半導體晶片之電路面與基板之電極形成面之間進行密封之片材。 Further, in the manufacture of a semiconductor device, in addition to the film for flip chip type semiconductor back surface, there is also a die-bond film or a bottom layer which is used for, for example, a dicing tape. A case where a diced tape-integrated type of sheet is formed by filling an underfill sheet or the like. The die-bonding film is a film for bonding a semiconductor wafer to an adherend, and the underfill sheet is used for sealing between a circuit surface of a semiconductor wafer in a flip-chip type semiconductor device and an electrode forming surface of the substrate. The sheet.

[先前技術文獻] [Previous Technical Literature] [專利文獻] [Patent Literature]

[專利文獻1]日本專利特開2011-228496號公報 [Patent Document 1] Japanese Patent Laid-Open Publication No. 2011-228496

然而,於使用上述切晶帶一體型接著片材製造半導體裝置之情形時,先前存在形成於半導體元件(例如半導體晶片)上之電路被破壞之情況。 However, in the case of manufacturing a semiconductor device using the above-described dicing tape-integrated bonding sheet, there has previously been a case where a circuit formed on a semiconductor element (for example, a semiconductor wafer) is broken.

本發明者等人對半導體元件上之電路被破壞之原因進行了研究。結果查明,於拾取步驟中,將附著有接著片材(例如,倒裝晶片型半導體背面用膜、黏晶膜、底部填充片材)之半導體元件自切晶帶剝離時,存在以下情形:於接著片材與切晶帶之間產生剝離靜電,因該產生之靜電導致半導體元件上之電路被破壞。 The inventors of the present invention have studied the cause of the destruction of the circuit on the semiconductor element. As a result, it was found that in the pick-up step, when the semiconductor element to which the adhesive sheet (for example, the film for flip chip type semiconductor back surface, the adhesive film, and the underfill sheet) is attached is peeled off from the dicing tape, there are the following cases: Stripping static electricity is generated between the sheet and the dicing tape, and the generated static electricity causes the circuit on the semiconductor element to be broken.

本發明者等人為了解決上述先前之問題而進行了研究,結果發現:將切晶帶之黏著劑層與接著片材之剝離力設於一定之範圍內,並且將剝離時之剝離靜電壓之絕對值設於一定之範圍內,藉此可抑制半導體元件上之電路被破壞,從而完成第1本發明。 The present inventors have conducted research to solve the above-mentioned problems, and as a result, found that the peeling force of the adhesive layer of the dicing tape and the subsequent sheet is set within a certain range, and the peeling static voltage is peeled off. The absolute value is set within a certain range, whereby the circuit on the semiconductor element is suppressed from being destroyed, thereby completing the first invention.

即,第1本發明之特徵在於,其係包含於基材上積層有黏著劑層之切晶帶、及形成於上述黏著劑層上之接著片材之切晶帶一體型接著片材,且 於剝離速度10m/min、剝離角度150°之剝離試驗中,上述黏著劑 層與上述接著片材之剝離力為0.02~0.5N/20mm,根據上述剝離試驗之條件,將上述黏著劑層與上述接著片材剝離時之剝離靜電壓之絕對值為0.5kV以下。 That is, the first aspect of the invention is characterized in that it comprises a dicing tape in which an adhesive layer is laminated on a substrate, and a dicing tape-integrated lining sheet of a subsequent sheet formed on the adhesive layer, and In the peeling test at a peeling speed of 10 m/min and a peeling angle of 150°, the above adhesive The peeling force of the layer and the above-mentioned succeeding sheet was 0.02 to 0.5 N/20 mm, and the absolute value of the peeling static voltage when the adhesive layer was peeled off from the adhesive sheet was 0.5 kV or less according to the conditions of the peeling test.

根據上述構成,於剝離速度10m/min、剝離角度150°之剝離試驗中,上述黏著劑層與上述接著片材之剝離力為0.02~0.5N/20mm。由於上述剝離力為0.02N/20mm以上,因此於切割時,能夠固定半導體晶圓。又,由於上述剝離力為0.5N/20mm以下,因此於拾取時,能夠容易地將附接著片材之半導體元件自黏著劑層剝離。又,由於根據上述剝離試驗之條件,將上述黏著劑層與上述接著片材剝離時之剝離靜電壓之絕對值為0.5kV以下,因此能夠發揮抗靜電效果。其結果,可防止由於拾取時之剝離靜電導致半導體元件被破壞,提高作為器件之可靠性。 According to the above configuration, in the peeling test at a peeling speed of 10 m/min and a peeling angle of 150°, the peeling force of the adhesive layer and the adhesive sheet was 0.02 to 0.5 N/20 mm. Since the peeling force is 0.02 N/20 mm or more, the semiconductor wafer can be fixed at the time of dicing. Moreover, since the peeling force is 0.5 N/20 mm or less, the semiconductor element attached to the sheet can be easily peeled off from the adhesive layer at the time of picking up. Moreover, since the absolute value of the peeling static voltage when the adhesive layer and the adhesive sheet are peeled off is 0.5 kV or less according to the conditions of the peeling test, an antistatic effect can be exhibited. As a result, it is possible to prevent the semiconductor element from being broken due to the peeling of static electricity at the time of picking up, and the reliability as a device is improved.

於上述構成中,較佳為上述接著片材為用於在倒裝晶片連接於被黏著體上之半導體元件之背面形成之倒裝晶片型半導體背面用膜。於上述接著片材為倒裝晶片型半導體背面用膜之情形時,倒裝晶片型半導體背面用膜形成於半導體元件之背面,半導體元件之電路面裸露。然而,根據上述剝離試驗之條件,將上述黏著劑層與上述接著片材剝離時之剝離靜電壓之絕對值為0.5kV以下。其結果,能夠防止裸露之半導體元件之電路面由於剝離靜電而被破壞。 In the above configuration, it is preferable that the adhesive sheet is a film for flip chip type semiconductor back surface formed on the back surface of a semiconductor element in which a flip chip is connected to an adherend. In the case where the subsequent sheet is a film for flip chip type semiconductor back surface, the film for flip chip type semiconductor back surface is formed on the back surface of the semiconductor element, and the circuit surface of the semiconductor element is exposed. However, according to the conditions of the peeling test, the absolute value of the peeling static voltage when the adhesive layer was peeled off from the adhesive sheet was 0.5 kV or less. As a result, it is possible to prevent the circuit surface of the bare semiconductor element from being broken by peeling off static electricity.

於上述構成中,較佳為於上述基材中含有抗靜電劑。切割後,自固定切晶帶之吸附台取下切晶帶時,存在於切晶帶與吸附台之間產生剝離靜電之情形。因此,若於基材中含有抗靜電劑,則能夠抑制該基材與吸附台之間之剝離靜電。 In the above configuration, it is preferred that the substrate contains an antistatic agent. After the dicing, when the dicing tape is removed from the adsorption stage of the fixed dicing tape, there is a case where the static electricity is peeled off between the dicing tape and the adsorption stage. Therefore, when an antistatic agent is contained in a base material, it can suppress the discharge static electricity between this base material and a adsorption|suction stage.

於上述構成中,較佳為:上述基材具有多層結構,於上述多層結構之基材之至少一個最外層中含有抗靜電劑。若於上述多層結構之基材之黏著劑層側之最外層中含有抗靜電劑,則能夠抑制基材與黏著劑 層兩者之靜電。又,若於上述多層結構之基材之與黏著劑層相反側之最外層中含有抗靜電劑,則能夠更有效地抑制基材與吸附台之間之剝離靜電。 In the above configuration, preferably, the substrate has a multilayer structure, and an antistatic agent is contained in at least one outermost layer of the substrate of the multilayer structure. If an antistatic agent is contained in the outermost layer on the side of the adhesive layer of the substrate of the multilayer structure, the substrate and the adhesive can be suppressed. The static electricity of both layers. Further, when the antistatic agent is contained in the outermost layer on the side opposite to the adhesive layer of the substrate of the multilayer structure, the peeling static electricity between the substrate and the adsorption stage can be more effectively suppressed.

於上述構成中,較佳為於上述基材之至少一個面上形成有含有抗靜電劑之抗靜電劑層。若於上述基材之黏著劑層側之面上形成有抗靜電劑層,則能夠抑制基材與黏著劑層兩者之靜電。又,若於上述基材之與黏著劑層相反側之面上形成有抗靜電劑層,則能夠更有效地抑制基材與吸附台之間之剝離靜電。 In the above configuration, it is preferable that an antistatic agent layer containing an antistatic agent is formed on at least one surface of the substrate. When an antistatic agent layer is formed on the surface of the adhesive layer side of the substrate, static electricity can be suppressed between the substrate and the adhesive layer. Further, when the antistatic agent layer is formed on the surface of the substrate opposite to the adhesive layer, the peeling static electricity between the substrate and the adsorption stage can be more effectively suppressed.

於上述構成中,較佳為於上述黏著劑層中含有抗靜電劑。若於黏著劑層中含有抗靜電劑,則能夠更有效地抑制將黏著劑層與接著片材剝離時之剝離靜電。 In the above configuration, it is preferred that the adhesive layer contains an antistatic agent. When the antistatic agent is contained in the adhesive layer, it is possible to more effectively suppress the peeling of static electricity when the adhesive layer and the adhesive sheet are peeled off.

於上述構成中,較佳為於上述接著片材中含有抗靜電劑。若於接著片材中含有抗靜電劑,則於自切晶帶剝離後亦具有抗靜電效果。其結果,於自切晶帶剝離後,亦能夠抑制由靜電導致之半導體元件之破壞。 In the above configuration, it is preferred that the adhesive sheet contains an antistatic agent. If the antistatic agent is contained in the subsequent sheet, it also has an antistatic effect after being peeled off from the dicing tape. As a result, it is possible to suppress the destruction of the semiconductor element due to static electricity after peeling from the dicing tape.

又,第1本發明之特徵在於,其係使用上述記載之切晶帶一體型接著片材之半導體裝置之製造方法,且包括如下步驟:於上述切晶帶一體型接著片材中之接著片材上貼著半導體晶圓之步驟;切割上述半導體晶圓而形成半導體元件之步驟;以及將上述半導體元件與上述接著片材一起自切晶帶之黏著劑層拾取之步驟。 Further, according to a first aspect of the invention, there is provided a method of manufacturing a semiconductor device using the dicing tape-integrated bonding sheet described above, comprising the step of: forming a bonding sheet in the dicing tape-integrated bonding sheet; a step of attaching a semiconductor wafer to the material; a step of cutting the semiconductor wafer to form a semiconductor element; and a step of picking the semiconductor element together with the adhesive sheet from the adhesive layer of the dicing tape.

根據上述構成,使用上述記載之切晶帶一體型接著片材。因此,上述黏著劑層與上述接著片材之剝離力為0.02~0.5N/20mm。由於上述剝離力為0.02N/20mm以上,因此於切割時,能夠固定半導體晶圓。又,由於上述剝離力為0.5N/20mm以下,因此於拾取時,能夠 容易地將附接著片材之半導體元件自黏著劑層剝離。又,由於藉由上述剝離試驗剝離時之剝離靜電壓之絕對值為0.5kV以下,因此能夠發揮抗靜電效果。其結果,可防止由於拾取時之剝離靜電導致半導體元件被破壞,提高作為器件之可靠性。 According to the above configuration, the above-described diced tape-integrated bonding sheet is used. Therefore, the peeling force of the above adhesive layer and the above-mentioned succeeding sheet is 0.02 to 0.5 N/20 mm. Since the peeling force is 0.02 N/20 mm or more, the semiconductor wafer can be fixed at the time of dicing. Moreover, since the peeling force is 0.5 N/20 mm or less, it is possible to pick up The semiconductor element attached to the sheet is easily peeled off from the adhesive layer. Further, since the absolute value of the peeling static voltage at the time of peeling by the peeling test is 0.5 kV or less, an antistatic effect can be exhibited. As a result, it is possible to prevent the semiconductor element from being broken due to the peeling of static electricity at the time of picking up, and the reliability as a device is improved.

又,為了解決上述問題,第1本發明之半導體裝置之特徵在於,其係使用上述記載之切晶帶一體型接著片材而製造。 Moreover, in order to solve the above problem, the semiconductor device according to the first aspect of the invention is characterized in that it is produced by using the above-described diced tape-integrated bonding sheet.

又,本發明者等人為了解決上述先前之問題而進行了研究,結果發現:藉由將切晶帶之基材、以及黏著劑層中之至少一個表面之表面電阻率值設於一定之範圍內,能夠抑制半導體元件上之電路被破壞,從而完成第2本發明。 Further, the inventors of the present invention conducted research to solve the above-mentioned problems, and as a result, found that the surface resistivity value of at least one of the base material of the dicing tape and the adhesive layer is set to a certain range. The second invention can be completed by suppressing destruction of the circuit on the semiconductor element.

即,第2本發明之特徵在於,其係包含於基材上積層有黏著劑層之切晶帶、及形成於上述黏著劑層上之接著片材之切晶帶一體型接著片材,且上述基材、以及上述黏著劑層中之至少一個表面之表面電阻率值為1.0×1011Ω以下。 In other words, the second aspect of the invention is characterized in that it comprises a dicing tape in which an adhesive layer is laminated on a substrate, and a dicing tape-integrated lining sheet of a subsequent sheet formed on the adhesive layer, and The surface resistivity of at least one of the substrate and the pressure-sensitive adhesive layer has a surface resistivity of 1.0 × 10 11 Ω or less.

根據上述構成,由於上述基材、以及上述黏著劑層中之至少一個表面之表面電阻率值為1.0×1011Ω以下,因此不易帶電。因此,能夠發揮抗靜電效果。其結果,可防止由於拾取時之剝離靜電導致半導體元件被破壞,提高作為器件之可靠性。 According to the above configuration, since at least one of the surface of the base material and the pressure-sensitive adhesive layer has a surface resistivity of 1.0 × 10 11 Ω or less, charging is less likely. Therefore, an antistatic effect can be exerted. As a result, it is possible to prevent the semiconductor element from being broken due to the peeling of static electricity at the time of picking up, and the reliability as a device is improved.

於上述構成中,較佳為上述接著片材為用於在倒裝晶片連接於被黏著體上之半導體元件之背面形成之倒裝晶片型半導體背面用膜。於上述接著片材為倒裝晶片型半導體背面用膜之情形時,倒裝晶片型半導體背面用膜形成於半導體元件之背面,半導體元件之電路面裸露。然而,上述基材、以及上述黏著劑層中之至少一個表面之表面電阻率值為1.0×1011Ω以下。其結果,能夠防止裸露之半導體元件之電路面由於剝離靜電而被破壞。 In the above configuration, it is preferable that the adhesive sheet is a film for flip chip type semiconductor back surface formed on the back surface of a semiconductor element in which a flip chip is connected to an adherend. In the case where the subsequent sheet is a film for flip chip type semiconductor back surface, the film for flip chip type semiconductor back surface is formed on the back surface of the semiconductor element, and the circuit surface of the semiconductor element is exposed. However, at least one of the surface of the substrate and the adhesive layer has a surface resistivity of 1.0 × 10 11 Ω or less. As a result, it is possible to prevent the circuit surface of the bare semiconductor element from being broken by peeling off static electricity.

於上述構成中,較佳為於上述基材中含有抗靜電劑。切割後,自固定切晶帶之吸附台取下切晶帶時,存在於切晶帶與吸附台之間產生剝離靜電之情形。因此,若於基材中含有抗靜電劑,則能夠抑制該基材與吸附台之間之剝離靜電。 In the above configuration, it is preferred that the substrate contains an antistatic agent. After the dicing, when the dicing tape is removed from the adsorption stage of the fixed dicing tape, there is a case where the static electricity is peeled off between the dicing tape and the adsorption stage. Therefore, when an antistatic agent is contained in a base material, it can suppress the discharge static electricity between this base material and a adsorption|suction stage.

於上述構成中,較佳為:上述基材具有多層結構,於上述多層結構之基材之至少一個最外層中含有抗靜電劑。若於上述多層結構之基材之黏著劑層側之最外層中含有抗靜電劑,則能夠抑制基材與黏著劑層兩者之靜電。又,若於上述多層結構之基材之與黏著劑層相反側之最外層中含有抗靜電劑,則能夠更有效地抑制基材與吸附台之間之剝離靜電。 In the above configuration, preferably, the substrate has a multilayer structure, and an antistatic agent is contained in at least one outermost layer of the substrate of the multilayer structure. When an antistatic agent is contained in the outermost layer on the side of the adhesive layer of the substrate of the multilayer structure, static electricity between the substrate and the adhesive layer can be suppressed. Further, when the antistatic agent is contained in the outermost layer on the side opposite to the adhesive layer of the substrate of the multilayer structure, the peeling static electricity between the substrate and the adsorption stage can be more effectively suppressed.

於上述構成中,較佳為於上述基材之至少一個面上形成有含有抗靜電劑之抗靜電劑層。若於上述基材之黏著劑層側之面上形成有抗靜電劑層,則能夠抑制基材與黏著劑層兩者之靜電。又,若於上述基材之與黏著劑層相反側之面上形成有抗靜電劑層,則能夠更有效地抑制基材與吸附台之間之剝離靜電。 In the above configuration, it is preferable that an antistatic agent layer containing an antistatic agent is formed on at least one surface of the substrate. When an antistatic agent layer is formed on the surface of the adhesive layer side of the substrate, static electricity can be suppressed between the substrate and the adhesive layer. Further, when the antistatic agent layer is formed on the surface of the substrate opposite to the adhesive layer, the peeling static electricity between the substrate and the adsorption stage can be more effectively suppressed.

於上述構成中,較佳為於上述黏著劑層中含有抗靜電劑。若於黏著劑層中含有抗靜電劑,則能夠更有效地抑制將黏著劑層與接著片材剝離時之剝離靜電。 In the above configuration, it is preferred that the adhesive layer contains an antistatic agent. When the antistatic agent is contained in the adhesive layer, it is possible to more effectively suppress the peeling of static electricity when the adhesive layer and the adhesive sheet are peeled off.

於上述構成中,較佳為上述抗靜電劑為高分子型抗靜電劑。若上述抗靜電劑為高分子型抗靜電劑,則不易自基材或黏著劑層滲出。其結果,能夠抑制經時導致之抗靜電功能之降低。 In the above configuration, it is preferred that the antistatic agent is a polymer type antistatic agent. When the antistatic agent is a polymer type antistatic agent, it is less likely to bleed out from the substrate or the adhesive layer. As a result, it is possible to suppress a decrease in the antistatic function caused by the passage of time.

又,第2本發明之特徵在於,其係使用上述記載之切晶帶一體型接著片材之半導體裝置之製造方法,且包括如下步驟:於上述切晶帶一體型接著片材中之接著片材上貼著半導體晶圓之步驟;切割上述半導體晶圓而形成半導體元件之步驟;以及 將上述半導體元件與上述接著片材一起自切晶帶之黏著劑層拾取之步驟。 Further, according to a second aspect of the invention, there is provided a method of manufacturing a semiconductor device using the dicing tape-integrated bonding sheet described above, comprising the step of: forming a bonding sheet in the dicing tape-integrated bonding sheet; a step of attaching a semiconductor wafer to the material; and cutting the semiconductor wafer to form a semiconductor element; The step of picking up the above-mentioned semiconductor element together with the above-mentioned succeeding sheet from the adhesive layer of the dicing tape.

根據上述構成,使用上述記載之切晶帶一體型接著片材。因此,上述基材、以及上述黏著劑層中之至少一個表面之表面電阻率值為1.0×1011Ω以下。由於上述表面電阻率值為1.0×1011Ω以下,因此能夠發揮抗靜電效果。其結果,可防止由於拾取時之剝離靜電導致半導體元件被破壞,提高作為器件之可靠性。 According to the above configuration, the above-described diced tape-integrated bonding sheet is used. Therefore, at least one surface of the substrate and the pressure-sensitive adhesive layer has a surface resistivity value of 1.0 × 10 11 Ω or less. Since the surface resistivity value is 1.0 × 10 11 Ω or less, an antistatic effect can be exhibited. As a result, it is possible to prevent the semiconductor element from being broken due to the peeling of static electricity at the time of picking up, and the reliability as a device is improved.

又,本發明者等人為了解決上述先前之問題而進行了研究,結果發現:藉由在切晶帶之基材、以及黏著劑層中之至少一者中含有高分子型抗靜電劑,能夠抑制半導體元件上之電路被破壞,從而完成第3本發明。 In addition, the inventors of the present invention have studied in order to solve the above-mentioned problems, and have found that a polymer type antistatic agent can be contained in at least one of a base material of a dicing tape and an adhesive layer. The third invention is completed by suppressing destruction of the circuit on the semiconductor element.

即,第3本發明之特徵在於,其係包含於基材上積層有黏著劑層之切晶帶、及形成於上述黏著劑層上之接著片材之切晶帶一體型接著片材,且於上述基材、以及上述黏著劑層中之至少一者中含有高分子型抗靜電劑。 In other words, the third aspect of the invention is characterized in that it comprises a dicing tape in which an adhesive layer is laminated on a substrate, and a dicing tape-integrated lining sheet of a subsequent sheet formed on the adhesive layer, and A polymer type antistatic agent is contained in at least one of the substrate and the adhesive layer.

根據上述構成,由於在上述基材、以及上述黏著劑層中之至少一者中含有高分子型抗靜電劑,因此不易帶電。因此,能夠發揮抗靜電效果。又,由於使用高分子型抗靜電劑作為抗靜電劑,因此不易自基材或黏著劑層滲出。其結果,能夠抑制經時導致之抗靜電功能之降低。 According to the above configuration, since at least one of the base material and the pressure-sensitive adhesive layer contains a polymer type antistatic agent, charging is less likely. Therefore, an antistatic effect can be exerted. Further, since a polymer type antistatic agent is used as an antistatic agent, it is less likely to bleed out from the substrate or the adhesive layer. As a result, it is possible to suppress a decrease in the antistatic function caused by the passage of time.

於上述構成中,較佳為上述接著片材為用於在倒裝晶片連接於被黏著體上之半導體元件之背面形成之倒裝晶片型半導體背面用膜。於上述接著片材為倒裝晶片型半導體背面用膜之情形時,倒裝晶片型半導體背面用膜形成於半導體元件之背面,半導體元件之電路面裸露。然而,於上述基材、以及上述黏著劑層中之至少一者中含有高分子型 抗靜電劑。其結果,能夠防止裸露之半導體元件之電路面由於剝離靜電而被破壞。 In the above configuration, it is preferable that the adhesive sheet is a film for flip chip type semiconductor back surface formed on the back surface of a semiconductor element in which a flip chip is connected to an adherend. In the case where the subsequent sheet is a film for flip chip type semiconductor back surface, the film for flip chip type semiconductor back surface is formed on the back surface of the semiconductor element, and the circuit surface of the semiconductor element is exposed. However, at least one of the above substrate and the above adhesive layer contains a polymer type Antistatic agent. As a result, it is possible to prevent the circuit surface of the bare semiconductor element from being broken by peeling off static electricity.

於上述構成中,較佳為:上述基材具有多層結構,於上述多層結構之基材之至少一個最外層中含有抗靜電劑。若於上述多層結構之基材之黏著劑層側之最外層中含有抗靜電劑,則能夠抑制基材與黏著劑層兩者之靜電。又,若於上述多層結構之基材之與黏著劑層相反側之最外層中含有抗靜電劑,則能夠更有效地抑制基材與吸附台之間之剝離靜電。 In the above configuration, preferably, the substrate has a multilayer structure, and an antistatic agent is contained in at least one outermost layer of the substrate of the multilayer structure. When an antistatic agent is contained in the outermost layer on the side of the adhesive layer of the substrate of the multilayer structure, static electricity between the substrate and the adhesive layer can be suppressed. Further, when the antistatic agent is contained in the outermost layer on the side opposite to the adhesive layer of the substrate of the multilayer structure, the peeling static electricity between the substrate and the adsorption stage can be more effectively suppressed.

於上述構成中,較佳為於上述基材之至少一個面上形成有含有抗靜電劑之抗靜電劑層。若於上述基材之黏著劑層側之面上形成有抗靜電劑層,則能夠抑制基材與黏著劑層兩者之靜電。又,若於上述基材之與黏著劑層相反側之面上形成有抗靜電劑層,則能夠更有效地抑制基材與吸附台之間之剝離靜電。 In the above configuration, it is preferable that an antistatic agent layer containing an antistatic agent is formed on at least one surface of the substrate. When an antistatic agent layer is formed on the surface of the adhesive layer side of the substrate, static electricity can be suppressed between the substrate and the adhesive layer. Further, when the antistatic agent layer is formed on the surface of the substrate opposite to the adhesive layer, the peeling static electricity between the substrate and the adsorption stage can be more effectively suppressed.

又,第3本發明之特徵在於,其係使用上述記載之切晶帶一體型接著片材之半導體裝置之製造方法,且包括如下步驟:於上述切晶帶一體型接著片材中之接著片材上貼著半導體晶圓之步驟;切割上述半導體晶圓而形成半導體元件之步驟;以及將上述半導體元件與上述接著片材一起自切晶帶之黏著劑層拾取之步驟。 According to a third aspect of the invention, there is provided a method of manufacturing a semiconductor device using the dicing tape-integrated bonding sheet described above, comprising the step of: forming a bonding sheet in the dicing tape-integrated bonding sheet; a step of attaching a semiconductor wafer to the material; a step of cutting the semiconductor wafer to form a semiconductor element; and a step of picking the semiconductor element together with the adhesive sheet from the adhesive layer of the dicing tape.

根據上述構成,使用上述記載之切晶帶一體型接著片材。因此,於上述基材、以及上述黏著劑層中之至少一者中含有高分子型抗靜電劑。由於在上述基材、以及上述黏著劑層中之至少一者中含有高分子型抗靜電劑,因此能夠發揮抗靜電效果。其結果,可防止由於拾取時之剝離靜電導致半導體元件被破壞,提高作為器件之可靠性。又,由於使用高分子型抗靜電劑作為抗靜電劑,因此不易自基材或黏著劑層 滲出。其結果,能夠抑制經時導致之抗靜電功能之降低。 According to the above configuration, the above-described diced tape-integrated bonding sheet is used. Therefore, a polymer type antistatic agent is contained in at least one of the base material and the pressure-sensitive adhesive layer. Since at least one of the base material and the pressure-sensitive adhesive layer contains a polymer-type antistatic agent, an antistatic effect can be exhibited. As a result, it is possible to prevent the semiconductor element from being broken due to the peeling of static electricity at the time of picking up, and the reliability as a device is improved. Moreover, since a polymer type antistatic agent is used as an antistatic agent, it is not easily formed from a substrate or an adhesive layer. Exudation. As a result, it is possible to suppress a decrease in the antistatic function caused by the passage of time.

又,本發明者等人為了解決上述先前之問題而進行了研究,結果發現:藉由將用於製造半導體裝置之接著片材之任一表面之表面電阻率值設於一定之範圍內,能夠抑制半導體元件上之電路被破壞,從而完成第4本發明。 Moreover, the inventors of the present invention have conducted research to solve the above-mentioned problems, and as a result, it has been found that by setting the surface resistivity value of any surface of the succeeding sheet for manufacturing a semiconductor device within a certain range, The fourth invention is completed by suppressing destruction of the circuit on the semiconductor element.

即,第4本發明之接著片材之特徵在於,其係用於製造半導體裝置之接著片材,且其任一表面之表面電阻率值為1.0×1011Ω以下。 That is, the succeeding sheet of the fourth aspect of the invention is characterized in that it is used for producing a succeeding sheet of a semiconductor device, and the surface resistivity value of any of the surfaces thereof is 1.0 × 10 11 Ω or less.

根據上述構成,由於接著片材之任一表面之表面電阻率值為1.0×1011Ω以下,因此不易帶電。因此,能夠發揮抗靜電效果。其結果,於貼附於切晶帶而作為切晶帶一體型接著片材使用時,可防止由於拾取時之剝離靜電導致半導體元件被破壞,提高作為器件之可靠性。 According to the above configuration, since the surface resistivity value of any of the subsequent sheets is 1.0 × 10 11 Ω or less, charging is not easy. Therefore, an antistatic effect can be exerted. As a result, when it is attached to a dicing tape and used as a dicing tape-integrated sheet, it is possible to prevent the semiconductor element from being broken due to peeling off static electricity during pick-up, and to improve reliability as a device.

於上述構成中,較佳為上述接著片材為用於在倒裝晶片連接於被黏著體上之半導體元件之背面形成之倒裝晶片型半導體背面用膜。於上述接著片材為倒裝晶片型半導體背面用膜之情形時,倒裝晶片型半導體背面用膜形成於半導體元件之背面,半導體元件之電路面裸露。然而,倒裝晶片型半導體背面用膜之任一表面之表面電阻率值為1.0×1011Ω以下。其結果,能夠防止裸露之半導體元件之電路面由於剝離靜電而被破壞。 In the above configuration, it is preferable that the adhesive sheet is a film for flip chip type semiconductor back surface formed on the back surface of a semiconductor element in which a flip chip is connected to an adherend. In the case where the subsequent sheet is a film for flip chip type semiconductor back surface, the film for flip chip type semiconductor back surface is formed on the back surface of the semiconductor element, and the circuit surface of the semiconductor element is exposed. However, the surface resistivity value of any surface of the film for flip chip type semiconductor back surface is 1.0 × 10 11 Ω or less. As a result, it is possible to prevent the circuit surface of the bare semiconductor element from being broken by peeling off static electricity.

於上述構成中,較佳為於上述接著片材中含有抗靜電劑。若於接著片材中含有抗靜電劑,則自切晶帶剝離後亦具有抗靜電效果。其結果,自切晶帶剝離後,亦能夠抑制由靜電導致之半導體元件之破壞。 In the above configuration, it is preferred that the adhesive sheet contains an antistatic agent. If an antistatic agent is contained in the subsequent sheet, it also has an antistatic effect after peeling off from the dicing tape. As a result, the destruction of the semiconductor element due to static electricity can be suppressed even after the dicing tape is peeled off.

又,第4本發明之切晶帶一體型接著片材之特徵在於,其包含於基材上積層有黏著劑層之切晶帶、及上述記載之接著片材,且上述接著片材形成於上述黏著劑層上。 Further, the dicing tape-integrated sheet of the fourth aspect of the invention is characterized in that it comprises a dicing tape in which an adhesive layer is laminated on a substrate, and the above-described succeeding sheet, and the above-mentioned succeeding sheet is formed on On the above adhesive layer.

根據上述構成,由於接著片材之任一表面之表面電阻率值為 1.0×1011Ω以下,因此不易帶電。因此,能夠發揮抗靜電效果。其結果,可防止由於拾取時之剝離靜電導致半導體元件被破壞,提高作為器件之可靠性。 According to the above configuration, since the surface resistivity value of any of the subsequent sheets is 1.0 × 10 11 Ω or less, charging is not easy. Therefore, an antistatic effect can be exerted. As a result, it is possible to prevent the semiconductor element from being broken due to the peeling of static electricity at the time of picking up, and the reliability as a device is improved.

又,第4本發明之特徵在於,其係使用上述記載之接著片材之半導體裝置之製造方法,且包括如下步驟:準備於基材上積層有黏著劑層之切晶帶之步驟;於上述切晶帶之上述黏著劑層上貼附上述接著片材,獲得切晶帶一體型接著片材之步驟;於上述切晶帶一體型接著片材中之接著片材上貼著半導體晶圓之步驟;切割上述半導體晶圓而形成半導體元件之步驟;以及將上述半導體元件與上述接著片材一起自切晶帶之黏著劑層拾取之步驟。 According to a fourth aspect of the invention, there is provided a method of manufacturing a semiconductor device using the above-described succeeding sheet, comprising the steps of: preparing a dicing tape having an adhesive layer laminated on a substrate; a step of attaching the above-mentioned adhesive sheet to the adhesive layer of the dicing tape to obtain a dicing tape-integrated sheet; and a semiconductor wafer is attached to the subsequent sheet in the dicing ribbon-integrated sheet a step of cutting the semiconductor wafer to form a semiconductor element; and a step of picking up the semiconductor element together with the adhesive sheet from the adhesive layer of the dicing tape.

又,第4本發明之特徵在於,其係使用上述記載之切晶帶一體型接著片材之半導體裝置之製造方法,且包括如下步驟:於上述切晶帶一體型接著片材中之接著片材上貼著半導體晶圓之步驟;切割上述半導體晶圓而形成半導體元件之步驟;以及將上述半導體元件與上述接著片材一起自切晶帶之黏著劑層拾取之步驟。 Further, according to a fourth aspect of the invention, there is provided a method of manufacturing a semiconductor device using the dicing tape-integrated film of the above-described dicing tape-integrated sheet, and comprising the step of: forming a film in the dicing tape-integrated sheet. a step of attaching a semiconductor wafer to the material; a step of cutting the semiconductor wafer to form a semiconductor element; and a step of picking the semiconductor element together with the adhesive sheet from the adhesive layer of the dicing tape.

根據上述構成,使用上述記載之接著片材或切晶帶一體型接著片材。因此,接著片材之任一表面之表面電阻率值為1.0×1011Ω以下。由於上述表面電阻率值為1.0×1011Ω以下,因此能夠發揮抗靜電效果。其結果,可防止由於拾取時之剝離靜電導致半導體元件被破壞,提高作為器件之可靠性。 According to the above configuration, the above-described succeeding sheet or the diced tape-integrated sheet is used. Therefore, the surface resistivity value of any of the surfaces of the sheet is then 1.0 × 10 11 Ω or less. Since the surface resistivity value is 1.0 × 10 11 Ω or less, an antistatic effect can be exhibited. As a result, it is possible to prevent the semiconductor element from being broken due to the peeling of static electricity at the time of picking up, and the reliability as a device is improved.

又,為了解決上述問題,第4本發明之半導體裝置之特徵在於, 其係使用上述記載之接著片材而製造。 Moreover, in order to solve the above problems, the semiconductor device of the fourth aspect of the invention is characterized in that This was produced using the above-described succeeding sheet.

又,為了解決上述問題,第4本發明之半導體裝置之特徵在於,其係使用上述記載之切晶帶一體型接著片材而製造。 Moreover, in order to solve the above problems, the semiconductor device according to the fourth aspect of the invention is characterized in that it is produced by using the above-described diced tape-integrated bonding sheet.

又,本發明者等人為了解決上述先前之問題而進行了研究,結果發現:藉由在用於製造半導體裝置之接著片材中含有高分子型抗靜電劑,能夠抑制半導體元件上之電路被破壞,從而完成第5本發明。 In addition, the inventors of the present invention have studied in order to solve the above-mentioned problems, and have found that it is possible to suppress the circuit on the semiconductor element by including the polymer type antistatic agent in the subsequent sheet for manufacturing the semiconductor device. Destroy, thereby completing the fifth invention.

即,第5本發明之接著片材之特徵在於,其係用於製造半導體裝置之接著片材,且含有高分子型抗靜電劑。 That is, the succeeding sheet of the fifth aspect of the invention is characterized in that it is used for producing a back sheet of a semiconductor device and contains a polymer type antistatic agent.

根據上述構成,由於在接著片材中含有高分子型抗靜電劑,因此不易帶電。因此,能夠發揮抗靜電效果。又,由於使用高分子型抗靜電劑作為抗靜電劑,因此不易自接著片材滲出。其結果,能夠抑制經時導致之抗靜電功能之降低。又,由於在接著片材中含有高分子型抗靜電劑,因此於貼附於切晶帶而作為切晶帶一體型接著片材使用時,自切晶帶剝離後亦具有抗靜電效果。其結果,自切晶帶剝離後,亦能夠抑制由靜電導致之半導體元件之破壞。 According to the above configuration, since the polymer type antistatic agent is contained in the subsequent sheet, charging is less likely. Therefore, an antistatic effect can be exerted. Moreover, since a polymer type antistatic agent is used as an antistatic agent, it is difficult to bleed out from the subsequent sheet. As a result, it is possible to suppress a decrease in the antistatic function caused by the passage of time. Further, since the polymer sheet contains a polymer type antistatic agent, when it is attached to a dicing tape and used as a dicing tape-integrated sheet, it also has an antistatic effect after being peeled off from the dicing tape. As a result, the destruction of the semiconductor element due to static electricity can be suppressed even after the dicing tape is peeled off.

於上述構成中,較佳為上述接著片材為用於在倒裝晶片連接於被黏著體上之半導體元件之背面形成之倒裝晶片型半導體背面用膜。於上述接著片材為倒裝晶片型半導體背面用膜之情形時,倒裝晶片型半導體背面用膜形成於半導體元件之背面,半導體元件之電路面裸露。然而,於接著片材中含有高分子型抗靜電劑。其結果,能夠防止裸露之半導體元件之電路面由於剝離靜電而被破壞。 In the above configuration, it is preferable that the adhesive sheet is a film for flip chip type semiconductor back surface formed on the back surface of a semiconductor element in which a flip chip is connected to an adherend. In the case where the subsequent sheet is a film for flip chip type semiconductor back surface, the film for flip chip type semiconductor back surface is formed on the back surface of the semiconductor element, and the circuit surface of the semiconductor element is exposed. However, a polymer type antistatic agent is contained in the subsequent sheet. As a result, it is possible to prevent the circuit surface of the bare semiconductor element from being broken by peeling off static electricity.

又,第5本發明之切晶帶一體型接著片材之特徵在於,其包含於基材上積層有黏著劑層之切晶帶、及上述記載之接著片材,且上述接著片材形成於上述黏著劑層上。 Further, the dicing tape-integrated sheet of the fifth aspect of the invention is characterized in that the dicing tape comprising a layer of an adhesive layer laminated on a substrate and the above-mentioned succeeding sheet are formed, and the above-mentioned succeeding sheet is formed on On the above adhesive layer.

根據上述構成,由於在接著片材中含有高分子型抗靜電劑,因此不易帶電。因此,能夠發揮抗靜電效果。其結果,可防止由於拾取時 之剝離靜電導致半導體元件被破壞,提高作為器件之可靠性。又,由於使用高分子型抗靜電劑作為抗靜電劑,因此不易自接著片材滲出。其結果,能夠抑制經時導致之抗靜電功能之降低。又,由於在接著片材中含有高分子型抗靜電劑,因此自切晶帶剝離後亦具有抗靜電效果。其結果,自切晶帶剝離後,亦能夠抑制由靜電導致之半導體元件之破壞。 According to the above configuration, since the polymer type antistatic agent is contained in the subsequent sheet, charging is less likely. Therefore, an antistatic effect can be exerted. As a result, it can be prevented due to picking The peeling of the static electricity causes the semiconductor element to be broken, improving the reliability as a device. Moreover, since a polymer type antistatic agent is used as an antistatic agent, it is difficult to bleed out from the subsequent sheet. As a result, it is possible to suppress a decrease in the antistatic function caused by the passage of time. Moreover, since the polymer type antistatic agent is contained in the subsequent sheet, it has an antistatic effect even after peeling from the dicing tape. As a result, the destruction of the semiconductor element due to static electricity can be suppressed even after the dicing tape is peeled off.

又,第5本發明之特徵在於,其係使用上述記載之接著片材之半導體裝置之製造方法,且包括如下步驟:準備於基材上積層有黏著劑層之切晶帶之步驟;於上述切晶帶之上述黏著劑層上貼附上述接著片材,獲得切晶帶一體型接著片材之步驟;於上述切晶帶一體型接著片材中之接著片材上貼著半導體晶圓之步驟;切割上述半導體晶圓而形成半導體元件之步驟;以及將上述半導體元件與上述接著片材一起自切晶帶之黏著劑層拾取之步驟。 Further, a fifth aspect of the invention is directed to a method of manufacturing a semiconductor device using the above-described succeeding sheet, and comprising the steps of: preparing a dicing tape having an adhesive layer laminated on a substrate; a step of attaching the above-mentioned adhesive sheet to the adhesive layer of the dicing tape to obtain a dicing tape-integrated sheet; and a semiconductor wafer is attached to the subsequent sheet in the dicing ribbon-integrated sheet a step of cutting the semiconductor wafer to form a semiconductor element; and a step of picking up the semiconductor element together with the adhesive sheet from the adhesive layer of the dicing tape.

又,第5本發明之特徵在於,其係使用上述記載之切晶帶一體型接著片材之半導體裝置之製造方法,且包括如下步驟:於上述切晶帶一體型接著片材中之接著片材上貼著半導體晶圓之步驟;切割上述半導體晶圓而形成半導體元件之步驟;以及將上述半導體元件與上述接著片材一起自切晶帶之黏著劑層拾取之步驟。 According to a fifth aspect of the invention, there is provided a method of manufacturing a semiconductor device using the dicing tape-integrated film of the above-described dicing tape-integrated sheet, and comprising the step of: forming a sheet in the dicing tape-integrated sheet. a step of attaching a semiconductor wafer to the material; a step of cutting the semiconductor wafer to form a semiconductor element; and a step of picking the semiconductor element together with the adhesive sheet from the adhesive layer of the dicing tape.

根據上述構成,使用上述記載之接著片材或切晶帶一體型接著片材。因此,由於在接著片材中含有高分子型抗靜電劑,因此能夠發揮抗靜電效果。其結果,可防止由於拾取時之剝離靜電導致半導體元件 被破壞,提高作為器件之可靠性。又,由於使用高分子型抗靜電劑作為抗靜電劑,因此不易自接著片材滲出。其結果,能夠抑制經時導致之抗靜電功能之降低。又,由於在接著片材中含有高分子型抗靜電劑,因此自切晶帶剝離後亦具有抗靜電效果。其結果,自切晶帶剝離後,亦能夠抑制由靜電導致之半導體元件之破壞。 According to the above configuration, the above-described succeeding sheet or the diced tape-integrated sheet is used. Therefore, since the polymer type antistatic agent is contained in the subsequent sheet, an antistatic effect can be exhibited. As a result, it is possible to prevent the semiconductor element from being peeled off due to pick-up during pick-up. Damaged and improved as a device's reliability. Moreover, since a polymer type antistatic agent is used as an antistatic agent, it is difficult to bleed out from the subsequent sheet. As a result, it is possible to suppress a decrease in the antistatic function caused by the passage of time. Moreover, since the polymer type antistatic agent is contained in the subsequent sheet, it has an antistatic effect even after peeling from the dicing tape. As a result, the destruction of the semiconductor element due to static electricity can be suppressed even after the dicing tape is peeled off.

又,為了解決上述問題,第5本發明之半導體裝置之特徵在於,其係使用上述記載之接著片材而製造。 Moreover, in order to solve the above problems, the semiconductor device of the fifth aspect of the invention is characterized in that it is manufactured using the above-described succeeding sheet.

又,為了解決上述問題,第5本發明之半導體裝置之特徵在於,其係使用上述記載之切晶帶一體型接著片材而製造。 Moreover, in order to solve the above problem, the semiconductor device according to the fifth aspect of the invention is characterized in that it is produced by using the above-described diced tape-integrated bonding sheet.

1、10、20‧‧‧切晶帶一體型半導體背面用膜 1,10,20‧‧‧Cutting tape integrated semiconductor back film

2‧‧‧倒裝晶片型半導體背面用膜(半導體背面用膜) 2‧‧‧Flip-chip type semiconductor back surface film (film for semiconductor back surface)

3‧‧‧切晶帶 3‧‧‧Cutting Tape

31‧‧‧基材 31‧‧‧Substrate

32‧‧‧黏著劑層 32‧‧‧Adhesive layer

33‧‧‧與半導體晶圓之貼著部分對應之部分 33‧‧‧Parts corresponding to the adhesive portion of the semiconductor wafer

35、36‧‧‧抗靜電劑層 35, 36‧‧‧Antistatic agent layer

4‧‧‧半導體晶圓 4‧‧‧Semiconductor wafer

5‧‧‧半導體晶片 5‧‧‧Semiconductor wafer

51‧‧‧形成於半導體晶片5之電路面側之凸塊 51‧‧‧Bumps formed on the circuit side of the semiconductor wafer 5

6‧‧‧被黏著體 6‧‧‧Adhesive body

61‧‧‧被黏著於被黏著體6之連接焊墊之接合用之導電材料 61‧‧‧ Conductive material for bonding to the bonding pads of the adherend 6

100‧‧‧丙烯酸系板樣品 100‧‧‧Acrylic board samples

102‧‧‧樣品固定台 102‧‧‧sample fixed table

104‧‧‧電位測定機 104‧‧‧potentiometer

110‧‧‧吸附台 110‧‧‧Adsorption station

圖1係本實施形態之切晶帶一體型半導體背面用膜之剖面模式圖。 Fig. 1 is a schematic cross-sectional view showing a film for a dicing tape-integrated semiconductor back surface of the embodiment.

圖2係用於說明剝離靜電壓之測定方法之概略構成圖。 Fig. 2 is a schematic configuration diagram for explaining a method of measuring the peeling static voltage.

圖3係另一實施形態之切晶帶一體型半導體背面用膜之剖面模式圖。 Fig. 3 is a schematic cross-sectional view showing a film for a dicing tape-integrated semiconductor back surface according to another embodiment.

圖4係另一實施形態之切晶帶一體型半導體背面用膜之剖面模式圖。 Fig. 4 is a schematic cross-sectional view showing a film for a dicing tape-integrated semiconductor back surface according to another embodiment.

圖5(a)-(d)係表示使用本實施形態之切晶帶一體型半導體背面用膜的半導體裝置之製造方法之一例之剖面模式圖。 (a) to (d) of FIG. 5 are schematic cross-sectional views showing an example of a method of manufacturing a semiconductor device using the dicing tape-integrated semiconductor back surface film of the present embodiment.

<第1本發明> <First invention>

對於第1本發明之實施形態,一面參照圖式一面進行說明,但第1本發明不限定於該等例。以下,首先對第1本發明之切晶帶一體型接著片材為切晶帶一體型半導體背面用膜之情形進行說明。即,對第1本發明之接著片材為倒裝晶片型半導體背面用膜之情形進行說明。圖1為表示本實施形態之切晶帶一體型半導體背面用膜之一例之剖面模 式圖。再者,本說明書中,於圖中省略不需要說明之部分,又,存在為了易於說明而放大或縮小等進行圖示之部分。 The first embodiment of the present invention will be described with reference to the drawings, but the first invention is not limited to the examples. In the following, first, the case where the diced tape-integrated sheet of the first invention is a film for a diced tape-integrated semiconductor back surface will be described. In other words, the case where the subsequent sheet of the first invention is a film for flip chip type semiconductor back surface will be described. Fig. 1 is a cross-sectional view showing an example of a film for a dicing tape-integrated semiconductor back surface of the embodiment; Figure. In addition, in this specification, the part which does not need to be described is abbreviate|omitted, and the part which shows in FIG.

(切晶帶一體型半導體背面用膜) (Cutting tape integrated semiconductor back surface film)

如圖1所示,切晶帶一體型半導體背面用膜1為包含於基材31上設置有黏著劑層32之切晶帶3、及設置於黏著劑層32上之倒裝晶片型半導體背面用膜(以下,有時稱為「半導體背面用膜」)2之構成。再者,第1本發明之切晶帶一體型半導體背面用膜可為如圖1所示,於切晶帶3之黏著劑層32上,僅在與半導體晶圓之貼著部分對應之部分33形成有半導體背面用膜2之構成;亦可為於黏著劑層32之整面形成有半導體背面用膜之構成;又,可為於比與半導體晶圓之貼著部分對應之部分33大且比黏著劑層32之整面小之部分形成有半導體背面用膜之構成。再者,半導體背面用膜2之表面(貼著於晶圓之背面之側之表面)可於貼著至晶圓背面之前之期間藉由分隔件(separator)等加以保護。 As shown in FIG. 1, the dicing tape-integrated semiconductor back surface film 1 is a dicing tape 3 including an adhesive layer 32 on a substrate 31, and a flip chip type semiconductor back surface provided on the adhesive layer 32. A film (hereinafter sometimes referred to as "film for semiconductor back surface") 2 is used. Further, the film for the dicing tape-integrated semiconductor back surface of the first aspect of the present invention may be as shown in FIG. 1, on the adhesive layer 32 of the dicing tape 3, only in the portion corresponding to the affixed portion of the semiconductor wafer. 33. The semiconductor back surface film 2 is formed; the semiconductor back surface film may be formed on the entire surface of the adhesive layer 32; and the film may be larger than the portion 33 corresponding to the semiconductor wafer. Further, a portion smaller than the entire surface of the adhesive layer 32 is formed with a film for a semiconductor back surface. Further, the surface of the film 2 for semiconductor back surface (the surface on the side opposite to the back surface of the wafer) can be protected by a separator or the like before being attached to the back surface of the wafer.

切晶帶一體型半導體背面用膜1於剝離速度10m/min、剝離角度150°之剝離試驗中,黏著劑層32與接著片材2之剝離力為0.02~0.5N/20mm,較佳為0.02~0.3N/20mm,更佳為0.02~0.2N/20mm。由於上述剝離力為0.02N/20mm以上,因此於切割時,能夠固定半導體晶圓。又,由於上述剝離力為0.5N/20mm以下,因此於拾取時,能夠容易地將附接著片材2之半導體元件自黏著劑層32剝離。 In the peeling test of the film 1 for the dicing tape-integrated semiconductor back surface at a peeling speed of 10 m/min and a peeling angle of 150°, the peeling force of the adhesive layer 32 and the succeeding sheet 2 is 0.02 to 0.5 N/20 mm, preferably 0.02. ~0.3N/20mm, more preferably 0.02~0.2N/20mm. Since the peeling force is 0.02 N/20 mm or more, the semiconductor wafer can be fixed at the time of dicing. Moreover, since the peeling force is 0.5 N/20 mm or less, the semiconductor element attached to the sheet 2 can be easily peeled off from the adhesive layer 32 at the time of picking up.

又,於切晶帶一體型半導體背面用膜1中,根據上述剝離試驗之條件,將黏著劑層32與接著片材2剝離時之剝離靜電壓之絕對值為0.5kV以下(-0.5kV~+0.5kV),較佳為0.3kV以下(-0.3kV~+0.3kV),更佳為0.2kV以下(-0.2kV~+0.2kV)。由於根據上述剝離試驗之條件,將黏著劑層32與接著片材2剝離時之剝離靜電壓之絕對值為0.5kV以下,因此能夠發揮抗靜電效果。其結果,可防止由於拾取時之 剝離靜電導致半導體元件被破壞,提高作為器件之可靠性。 Further, in the film 1 for the dicing tape-integrated semiconductor back surface, the absolute value of the peeling static voltage when the adhesive layer 32 and the succeeding sheet 2 are peeled off according to the conditions of the peeling test is 0.5 kV or less (-0.5 kV~ +0.5 kV), preferably 0.3 kV or less (-0.3 kV to +0.3 kV), more preferably 0.2 kV or less (-0.2 kV to +0.2 kV). According to the conditions of the peeling test, the absolute value of the peeling static voltage when the adhesive layer 32 and the succeeding sheet 2 are peeled off is 0.5 kV or less, so that an antistatic effect can be exhibited. As a result, it can be prevented due to picking The peeling of the static electricity causes the semiconductor element to be broken, improving the reliability as a device.

此處,對剝離靜電壓之測定方法進行說明。 Here, a method of measuring the peeling static voltage will be described.

圖2為用於說明剝離靜電壓之測定方法之概略構成圖。首先,將切晶帶一體型半導體背面用膜1貼合於經預先除電之丙烯酸系板100(厚度:1mm,寬度:70mm,長度:100mm)。於貼合時,使用手壓輥,以使丙烯酸系板100與切晶帶3介隔雙面膠帶相對之方式進行。於該狀態下,在23℃、50%RH之環境下放置一天。繼而,將貼合有切晶帶一體型半導體背面用膜1之丙烯酸系板100固定於樣品固定台102。繼而,將半導體背面用膜2之端部固定於自動捲取機,以剝離角度成為150°、剝離速度成為10m/min之方式進行剝離。藉由固定於距切晶帶之表面100mm之位置之電位測定機104(春日電機公司製造,KSD-0103),測定此時產生之切晶帶3側之面(黏著劑層32之面)之電位。測定係於23℃、50%RH之環境下進行。 Fig. 2 is a schematic configuration diagram for explaining a method of measuring a peeling static voltage. First, the film 1 for dicing tape-integrated semiconductor back surface was bonded to a previously removed acrylic plate 100 (thickness: 1 mm, width: 70 mm, length: 100 mm). At the time of bonding, a hand roller is used so that the acrylic plate 100 and the dicing tape 3 are opposed to each other via a double-sided tape. In this state, it was left to stand in an environment of 23 ° C and 50% RH. Then, the acrylic plate 100 to which the film 1 for dicing tape-integrated semiconductor back surface is bonded is fixed to the sample fixing table 102. Then, the end portion of the film 2 for semiconductor back surface was fixed to an automatic winder, and peeling was performed so that the peeling angle was 150 degrees and the peeling speed was 10 m/min. The surface of the dicing tape 3 side (the surface of the adhesive layer 32) which was produced at this time was measured by a potential measuring machine 104 (KSD-0103, manufactured by Kasuga Electric Co., Ltd.) fixed at a position of 100 mm from the surface of the dicing tape. Potential. The measurement was carried out in an environment of 23 ° C and 50% RH.

於切晶帶一體型半導體背面用膜1中,基材31、黏著劑層32、或半導體背面用膜2之至少任一表面之表面電阻率值較佳為1.0×1011Ω以下,更佳為1.0×1010Ω以下,進而較佳為1.0×109Ω以下。又,上述表面電阻率值越小越佳,但可列舉例如為1.0×105Ω以上、1.0×106Ω以上、1.0×107Ω以上。若上述表面電阻率值為1.0×1011Ω以下,則不易帶電。因此,能進一步發揮抗靜電效果。再者,於第1本發明中,所謂基材、黏著劑層、或半導體背面用膜之至少任一表面之表面電阻率值,係指基材之黏著劑層側之表面、基材之與黏著劑層相反側之表面、黏著劑層之基材側之表面、黏著劑層之與基材相反側之表面、半導體背面用膜之黏著劑層側之表面、半導體背面用膜之與黏著劑層相反側之表面中之至少任一表面之表面電阻率值。上述表面電阻率值係指藉由實施例中記載之方法測定之值。 In the film 1 for the dicing tape-integrated semiconductor back surface, at least one surface of the substrate 31, the adhesive layer 32, or the film for semiconductor back surface 2 preferably has a surface resistivity value of 1.0 × 10 11 Ω or less, more preferably It is 1.0 × 10 10 Ω or less, and more preferably 1.0 × 10 9 Ω or less. Further, the surface resistivity value is preferably as small as possible, and is, for example, 1.0 × 10 5 Ω or more, 1.0 × 10 6 Ω or more, and 1.0 × 10 7 Ω or more. When the surface resistivity value is 1.0 × 10 11 Ω or less, charging is not easy. Therefore, the antistatic effect can be further exerted. In the first aspect of the invention, the surface resistivity value of at least one surface of the substrate, the adhesive layer, or the film for semiconductor back surface refers to the surface of the adhesive layer side of the substrate and the substrate. The surface on the opposite side of the adhesive layer, the surface on the substrate side of the adhesive layer, the surface on the opposite side of the adhesive layer from the substrate, the surface on the adhesive layer side of the film for semiconductor back surface, and the film on the semiconductor back surface and the adhesive The surface resistivity value of at least any of the surfaces on the opposite side of the layer. The surface resistivity value is a value measured by the method described in the examples.

於切晶帶一體型半導體背面用膜1中,較佳為於基材31、黏著劑 層32、半導體背面用膜2中之至少一者中含有抗靜電劑。 In the film 1 for dicing tape-integrated semiconductor back surface, preferably on the substrate 31, the adhesive At least one of the layer 32 and the film 2 for semiconductor back surface contains an antistatic agent.

若於基材31中含有抗靜電劑,則能夠抑制自固定切晶帶3之吸附台取下時之基材31與吸附台之間之剝離靜電。尤其是若基材31具有多層結構,且於多層結構之基材31之黏著劑層32側之最外層中含有抗靜電劑,則能夠抑制基材31與黏著劑層32兩者之靜電。又,若於多層結構之基材31之與黏著劑層32相反側之最外層中含有抗靜電劑,則能夠更有效地抑制基材31與吸附台之間之剝離靜電。 When the antistatic agent is contained in the base material 31, it is possible to suppress the peeling static electricity between the substrate 31 and the adsorption stage when the adsorption stage of the fixed dicing tape 3 is removed. In particular, when the base material 31 has a multilayer structure and the antistatic agent is contained in the outermost layer on the side of the adhesive layer 32 of the base material 31 of the multilayer structure, static electricity can be suppressed between the base material 31 and the adhesive layer 32. Further, when the antistatic agent is contained in the outermost layer on the side opposite to the adhesive layer 32 of the substrate 31 of the multilayer structure, the peeling static electricity between the substrate 31 and the adsorption stage can be more effectively suppressed.

又,若於黏著劑層32中含有抗靜電劑,則能夠更有效地抑制將黏著劑層32與半導體背面用膜2剝離時之剝離靜電。 In addition, when the antistatic agent is contained in the adhesive layer 32, it is possible to more effectively suppress the peeling of static electricity when the adhesive layer 32 and the film for semiconductor back surface 2 are peeled off.

又,若於半導體背面用膜2中含有抗靜電劑,則自切晶帶3剝離後亦具有抗靜電效果。其結果,自切晶帶3剝離後,亦能夠抑制由靜電導致之半導體元件之破壞。尤其是若半導體背面用膜2具有多層結構,且於多層結構之半導體背面用膜2之切晶帶3側之最外層中含有抗靜電劑,則能夠進一步有效地抑制將黏著劑層32與半導體背面用膜2剝離時之剝離靜電。 Moreover, when the antistatic agent is contained in the film 2 for semiconductor back surface, it has an antistatic effect after peeling from the dicing tape 3. As a result, after the dicing tape 3 is peeled off, the destruction of the semiconductor element due to static electricity can also be suppressed. In particular, if the film 2 for semiconductor back surface has a multilayer structure and contains an antistatic agent in the outermost layer on the side of the dicing tape 3 of the film 2 for semiconductor back surface of the multilayer structure, the adhesive layer 32 and the semiconductor can be further effectively suppressed. When the film 2 for back surface peeling is peeled off, static electricity is peeled off.

作為上述抗靜電劑,可列舉:四級銨鹽、吡啶鎓鹽、具有第一、第二、第三胺基等陽離子性官能基之陽離子型抗靜電劑、磺酸鹽或硫酸酯鹽、膦酸鹽、磷酸酯鹽等具有陰離子性官能基之陰離子型抗靜電劑、烷基甜菜鹼及其衍生物、咪唑啉及其衍生物、丙胺酸及其衍生物等兩性型抗靜電劑、胺基醇及其衍生物、甘油及其衍生物、聚乙二醇及其衍生物等非離子型抗靜電劑,進而可列舉使上述陽離子型、陰離子型、兩性離子型之具有離子導電性基之單體聚合或者共聚合而得之離子導電性聚合物(高分子型抗靜電劑)。該等化合物可單獨使用,又,亦可混合兩種以上使用。其中,較佳為高分子型抗靜電劑。若使用高分子型抗靜電劑,則不易自基材31、黏著劑層32、以及半導體背面用膜2滲出。其結果,能夠抑制經時導致之抗靜電功能之降低。 Examples of the antistatic agent include a quaternary ammonium salt, a pyridinium salt, a cationic antistatic agent having a cationic functional group such as a first, second, or a third amino group, a sulfonate or sulfate salt, and a phosphine. Anionic antistatic agent having an anionic functional group such as an acid salt or a phosphate ester salt, an alkylbetaine and a derivative thereof, an imidazoline and a derivative thereof, an amphoteric antistatic agent such as alanine and a derivative thereof, and an amine group Examples of the nonionic antistatic agent such as an alcohol, a derivative thereof, glycerin and a derivative thereof, and a polyethylene glycol or a derivative thereof, and the above-mentioned cationic, anionic or zwitterionic type having an ion conductive group An ion conductive polymer (polymer type antistatic agent) obtained by bulk polymerization or copolymerization. These compounds may be used singly or in combination of two or more. Among them, a polymer type antistatic agent is preferred. When a polymer type antistatic agent is used, it is less likely to bleed out from the substrate 31, the adhesive layer 32, and the film 2 for semiconductor back surface. As a result, it is possible to suppress a decrease in the antistatic function caused by the passage of time.

具體而言,作為陽離子型抗靜電劑,例如可列舉:烷基三甲基銨鹽、醯基醯胺丙基三甲基銨甲基硫酸鹽(acyloyl amide propyl trimethyl ammonium methosulfate)、烷基苄基甲基銨鹽、醯基氯化膽鹼、聚甲基丙烯酸二甲基胺基乙酯等具有四級銨基之(甲基)丙烯酸酯共聚物、聚乙烯基苄基三甲基銨氯化物等具有四級銨基之苯乙烯共聚物、聚二烯丙基二甲基銨氯化物等具有四級銨基之二烯丙基胺共聚物等。該等化合物可單獨使用,又,亦可混合兩種以上使用。 Specific examples of the cationic antistatic agent include an alkyltrimethylammonium salt, a acyloyl amide propyl trimethyl ammonium methosulfate, and an alkylbenzyl group. a (meth) acrylate copolymer having a quaternary ammonium group such as methylammonium salt, mercapto choline chloride or polydimethylaminoethyl methacrylate, polyvinylbenzyltrimethylammonium chloride A diallylamine copolymer having a quaternary ammonium group such as a styrene copolymer having a quaternary ammonium group or a polydiallyldimethylammonium chloride or the like. These compounds may be used singly or in combination of two or more.

作為陰離子型抗靜電劑,例如可列舉:烷基磺酸鹽、烷基苯磺酸鹽、烷基硫酸酯鹽、烷基乙氧基硫酸酯鹽、烷基磷酸酯鹽、含磺酸基之苯乙烯共聚物。該等化合物可單獨使用,又,亦可混合兩種以上使用。 Examples of the anionic antistatic agent include an alkylsulfonate, an alkylbenzenesulfonate, an alkylsulfate, an alkylethoxysulfate, an alkyl phosphate, and a sulfonic acid group. Styrene copolymer. These compounds may be used singly or in combination of two or more.

作為兩性離子型抗靜電劑,例如可列舉:烷基甜菜鹼、烷基咪唑鎓甜菜鹼、羧酸甜菜鹼(carbobetaine)接枝共聚物。該等化合物可單獨使用,又,亦可混合兩種以上使用。 Examples of the zwitterionic antistatic agent include alkylbetaine, alkylimidazolium betaine, and carbobetaine graft copolymer. These compounds may be used singly or in combination of two or more.

作為非離子型抗靜電劑,例如可列舉:脂肪酸烷醇醯胺(alkylol amide)、二(2-羥基乙基)烷基胺、聚氧乙烯烷基胺、脂肪酸甘油酯、聚氧乙二醇脂肪酸酯、山梨糖醇酐脂肪酸酯、聚氧山梨糖醇酐脂肪酸酯、聚氧乙烯烷基苯醚、聚氧乙烯烷基醚、聚乙二醇、聚氧乙烯二胺、包含聚醚、聚酯及聚醯胺之共聚物、甲氧基聚乙二醇(甲基)丙烯酸酯等。該等化合物可單獨使用,又,亦可混合兩種以上使用。 Examples of the nonionic antistatic agent include fatty acid alkylol amide, bis(2-hydroxyethyl)alkylamine, polyoxyethylene alkylamine, fatty acid glyceride, and polyoxyethylene glycol. Fatty acid ester, sorbitan fatty acid ester, polyoxysorbitol fatty acid ester, polyoxyethylene alkyl phenyl ether, polyoxyethylene alkyl ether, polyethylene glycol, polyoxyethylene diamine, containing poly Ether, a copolymer of polyester and polyamine, methoxypolyethylene glycol (meth) acrylate, and the like. These compounds may be used singly or in combination of two or more.

作為高分子型抗靜電劑之其他例,例如可列舉聚苯胺、聚吡咯、聚噻吩等。 Other examples of the polymer type antistatic agent include polyaniline, polypyrrole, and polythiophene.

又,作為上述抗靜電劑,可列舉導電性物質。作為導電性物質,例如可列舉:氧化錫、氧化銻、氧化銦、氧化鎘、氧化鈦、氧化鋅、銦、錫、銻、金、銀、銅、鋁、鎳、鉻、鈦、鐵、鈷、碘化銅、以及該等之合金或混合物。 Further, examples of the antistatic agent include conductive materials. Examples of the conductive material include tin oxide, antimony oxide, indium oxide, cadmium oxide, titanium oxide, zinc oxide, indium, tin, antimony, gold, silver, copper, aluminum, nickel, chromium, titanium, iron, and cobalt. , copper iodide, and alloys or mixtures thereof.

上述抗靜電劑之含量相對於添加之層之全部樹脂成分,較佳為50重量%以下,更佳為30重量%以下。又,上述抗靜電劑之含量相對於添加之層之全部樹脂成分,較佳為5重量%以上,更佳為10重量%以上。藉由在上述數值範圍內含有上述抗靜電劑,能夠附加抗靜電功能而不損害添加之層之功能。此處,「相對於添加之層之全部樹脂成分為50重量%以下」係指以下含義。 The content of the antistatic agent is preferably 50% by weight or less, and more preferably 30% by weight or less based on the total resin component of the layer to be added. Further, the content of the antistatic agent is preferably 5% by weight or more, and more preferably 10% by weight or more based on the total resin component of the layer to be added. By including the above antistatic agent within the above numerical range, it is possible to add an antistatic function without impairing the function of the layer to be added. Here, "50% by weight or less based on the total resin component of the layer to be added" means the following meaning.

(a)於添加之層為基材31之情形時 (a) When the added layer is the substrate 31

於基材31包含1層之情形時,係指相對於構成基材31之全部樹脂成分為50重量%以下。 When the base material 31 includes one layer, it means 50% by weight or less based on the total resin component of the constituent base material 31.

於基材31包含多層結構之情形時,係指相對於構成複數層中之1層之全部樹脂成分為50重量%以下。 In the case where the substrate 31 includes a multilayer structure, it means 50% by weight or less based on the total resin component of one of the plurality of layers.

(b)於添加之層為黏著劑層32之情形時 (b) When the added layer is the adhesive layer 32

係指相對於構成黏著劑層32之全部樹脂成分為50重量%以下。 It means 50% by weight or less with respect to all the resin components constituting the adhesive layer 32.

(c)於添加之層為半導體背面用膜2之情形時 (c) When the layer to be added is the film 2 for semiconductor back surface

於半導體背面用膜2包含1層之情形時,係指相對於構成半導體背面用膜2之全部樹脂成分為50重量%以下。 In the case where the film 2 for semiconductor back surface includes one layer, it means 50% by weight or less based on the total resin component of the film 2 for semiconductor back surface.

於半導體背面用膜2包含多層結構之情形時,係指相對於構成複數層中之1層之全部樹脂成分為50重量%以下。 In the case where the film 2 for semiconductor back surface includes a multilayer structure, it means 50% by weight or less based on the total resin component of one of the plurality of layers.

再者,關於「相對於添加之層之全部樹脂成分為30重量%以下」、「相對於添加之層之全部樹脂成分為5重量%以上」、「相對於添加之層之全部樹脂成分為10重量%以上」,亦與上述同樣地,於基材、黏著劑層、半導體背面用膜包含1層之情形時,係指相對於構成該基材、該黏著劑層、或該半導體背面用膜之全部樹脂成分之比率,於包含多層結構之情形時,係指相對於構成該基材、或該半導體背面用膜之複數層中之1層之全部樹脂成分之比率。 In addition, it is "30% by weight or less based on the total resin component of the layer to be added", "5% by weight or more based on the total resin component of the layer to be added", and "10% of the total resin component with respect to the layer to be added" In the case where the substrate, the adhesive layer, and the film for semiconductor back surface comprise one layer, the film, the adhesive layer, or the film for semiconductor back surface is formed in the same manner as described above. The ratio of all the resin components in the case of including a multilayer structure means the ratio of all the resin components of one of the plurality of layers constituting the substrate or the film for semiconductor back surface.

於切晶帶一體型半導體背面用膜中,亦可於基材之至少一個面上 形成含有抗靜電劑之抗靜電劑層。圖3及圖4為另一實施形態之切晶帶一體型半導體背面用膜之剖面模式圖。 In the film for the dicing tape-integrated semiconductor back surface, on at least one surface of the substrate An antistatic agent layer containing an antistatic agent is formed. 3 and 4 are schematic cross-sectional views showing a film for a dicing tape-integrated semiconductor back surface according to another embodiment.

如圖3所示,切晶帶一體型半導體背面用膜10形成有於基材31上設置有黏著劑層32之切晶帶3、設置於黏著劑層32上之半導體背面用膜2、以及形成於基材31之與黏著劑層32相反側之面上之抗靜電劑層35。於切晶帶一體型半導體背面用膜10中,由於在基材31之與黏著劑層32相反側之面上形成有抗靜電劑層35,因此能夠更有效地抑制基材31與吸附台之間之剝離靜電。 As shown in FIG. 3, the dicing tape-integrated semiconductor back surface film 10 is formed with a dicing tape 3 provided with an adhesive layer 32 on a substrate 31, a semiconductor back surface film 2 provided on the adhesive layer 32, and An antistatic agent layer 35 is formed on the surface of the substrate 31 opposite to the adhesive layer 32. In the film 10 for the dicing tape-integrated semiconductor back surface, since the antistatic agent layer 35 is formed on the surface of the substrate 31 opposite to the adhesive layer 32, the substrate 31 and the adsorption stage can be more effectively suppressed. Stripping static electricity between.

又,如圖4所示,切晶帶一體型半導體背面用膜20為下述構成,該構成包含:於基材31上設置有黏著劑層32之切晶帶3、設置於基材31與黏著劑層32之間之抗靜電劑層36、以及設置於黏著劑層32上之半導體背面用膜2。於切晶帶一體型半導體背面用膜20中,由於在基材31之黏著劑層32側之面上形成有抗靜電劑層36,因此能夠抑制基材31與黏著劑層32兩者之靜電。 Further, as shown in FIG. 4, the dicing tape-integrated semiconductor back surface film 20 has a structure including a dicing tape 3 provided with an adhesive layer 32 on a substrate 31, and a substrate 31 provided thereon. An antistatic agent layer 36 between the adhesive layers 32 and a film 2 for semiconductor back surface provided on the adhesive layer 32. In the film 20 for the dicing tape-integrated semiconductor back surface, since the antistatic agent layer 36 is formed on the surface of the substrate 31 on the side of the adhesive layer 32, it is possible to suppress static electricity between the substrate 31 and the adhesive layer 32. .

(抗靜電劑層) (antistatic agent layer)

抗靜電劑層35、36為至少含有抗靜電劑之層。作為抗靜電劑層35、36中含有之抗靜電劑,可使用與在基材31、黏著劑層32、半導體背面用膜2中含有之情形時之上述抗靜電劑同樣者。再者,於抗靜電劑層35、36中,除了抗靜電劑以外,亦可根據需要含有黏合劑成分、溶劑等。 The antistatic agent layers 35 and 36 are layers containing at least an antistatic agent. The antistatic agent contained in the antistatic agent layers 35 and 36 can be the same as the antistatic agent in the case where the substrate 31, the adhesive layer 32, and the semiconductor back surface film 2 are contained. Further, the antistatic agent layers 35 and 36 may contain a binder component, a solvent, or the like as needed in addition to the antistatic agent.

抗靜電劑層35、36之厚度較佳為0.01~5μm,更佳為0.03~1μm。藉由將抗靜電劑層35、抗靜電劑層36之厚度設為0.01μm以上,能夠易於表現出抗靜電功能。又,藉由將抗靜電劑層35、抗靜電劑層36之厚度設為5μm以下,能夠提高黏著劑與基材之密接性能。 The thickness of the antistatic agent layers 35, 36 is preferably from 0.01 to 5 μm, more preferably from 0.03 to 1 μm. By setting the thickness of the antistatic agent layer 35 and the antistatic agent layer 36 to 0.01 μm or more, the antistatic function can be easily exhibited. Moreover, by setting the thickness of the antistatic agent layer 35 and the antistatic agent layer 36 to 5 μm or less, the adhesion performance between the adhesive and the substrate can be improved.

抗靜電劑層35、36可藉由將抗靜電劑層形成用溶液塗佈於基材31並使其乾燥而形成。作為塗佈方法,可採用旋塗、噴塗、浸塗、絲網 印刷、線棒塗佈等各種塗佈方法。 The antistatic agent layers 35 and 36 can be formed by applying a solution for forming an antistatic agent layer to the substrate 31 and drying it. As a coating method, spin coating, spray coating, dip coating, and wire mesh can be used. Various coating methods such as printing and wire bar coating.

(倒裝晶片型半導體背面用膜) (film for flip chip type semiconductor back surface)

半導體背面用膜2具有膜狀之形態。關於半導體背面用膜2,通常,於作為製品之切晶帶一體型半導體背面用膜之形態下為未硬化狀態(包括半硬化狀態),在將切晶帶一體型半導體背面用膜貼著於半導體晶圓後進行熱硬化(關於詳細情況見後述)。 The film 2 for semiconductor back surface has a film form. The film 2 for semiconductor back surface is usually in an uncured state (including a semi-hardened state) in the form of a film for a dicing tape-integrated semiconductor back surface as a product, and is bonded to a film for a dicing tape-integrated semiconductor back surface. The semiconductor wafer is thermally hardened (see below for details).

上述半導體背面用膜可由樹脂組合物形成,可由含有熱塑性樹脂及熱硬化性樹脂之樹脂組合物構成。再者,半導體背面用膜可由未使用熱硬化性樹脂之熱塑性樹脂組合物構成,亦可由未使用熱塑性樹脂之熱硬化性樹脂組合物構成。 The film for semiconductor back surface may be formed of a resin composition, and may be composed of a resin composition containing a thermoplastic resin and a thermosetting resin. Further, the film for semiconductor back surface may be composed of a thermoplastic resin composition not using a thermosetting resin, or may be composed of a thermosetting resin composition not using a thermoplastic resin.

作為上述熱塑性樹脂,例如可列舉:天然橡膠、丁基橡膠、異戊二烯橡膠、氯丁二烯橡膠、乙烯-乙酸乙烯酯共聚物、乙烯-丙烯酸共聚物、乙烯-丙烯酸酯共聚物、聚丁二烯樹脂、聚碳酸酯樹脂、熱塑性聚醯亞胺樹脂、尼龍6、尼龍6,6等聚醯胺樹脂、苯氧基樹脂、丙烯酸系樹脂、PET(聚對苯二甲酸乙二酯)或PBT(聚對苯二甲酸丁二酯)等飽和聚酯樹脂、聚醯胺醯亞胺樹脂、或氟樹脂等。熱塑性樹脂可單獨使用或併用兩種以上。於該等熱塑性樹脂中,較佳為丙烯酸系樹脂或苯氧基樹脂,進而,尤佳為可將拉伸儲存彈性模數維持得較高並可膜化之苯氧基樹脂。 Examples of the thermoplastic resin include natural rubber, butyl rubber, isoprene rubber, chloroprene rubber, ethylene-vinyl acetate copolymer, ethylene-acrylic acid copolymer, ethylene-acrylate copolymer, and poly Butadiene resin, polycarbonate resin, thermoplastic polyimide resin, nylon 6, nylon 6,6 and other polyamide resin, phenoxy resin, acrylic resin, PET (polyethylene terephthalate) Or a saturated polyester resin such as PBT (polybutylene terephthalate), a polyamidoximine resin, or a fluororesin. The thermoplastic resin may be used singly or in combination of two or more. Among these thermoplastic resins, an acrylic resin or a phenoxy resin is preferable, and further, a phenoxy resin which can maintain a high tensile modulus of stretch and can be film-formed is particularly preferable.

作為上述苯氧基樹脂,並無特別限定,例如可列舉藉由表氯醇與二元酚系化合物反應而得之樹脂、藉由二元環氧系化合物與二元酚系化合物之反應而得之樹脂等在結構單元中組入有酚成分之環氧樹脂等。作為苯氧基樹脂,例如可例示具有選自雙酚骨架(雙酚A型骨架、雙酚F型骨架、雙酚A/F混合型骨架、雙酚S型骨架、雙酚M型骨架、雙酚P型骨架、雙酚A/P混合型骨架、雙酚Z型骨架等)、萘骨架、降烯骨架、茀骨架、聯苯骨架、蒽骨架、酚醛清漆骨架、芘骨架、 骨架、金剛烷骨架以及二環戊二烯骨架中之至少一種骨架之苯氧基樹脂等。此外,苯氧基樹脂亦可使用市售品。苯氧基樹脂可單獨使用或組合兩種以上使用。 The phenoxy resin is not particularly limited, and examples thereof include a resin obtained by reacting epichlorohydrin with a dihydric phenol compound, and a reaction between a binary epoxy compound and a dihydric phenol compound. An epoxy resin or the like having a phenol component is incorporated in the structural unit. The phenoxy resin may, for example, be exemplified to have a bisphenol skeleton (bisphenol A type skeleton, bisphenol F type skeleton, bisphenol A/F mixed type skeleton, bisphenol S type skeleton, bisphenol M type skeleton, double). Phenol P-type skeleton, bisphenol A/P mixed type skeleton, bisphenol Z type skeleton, etc.), naphthalene skeleton, drop Alkene skeleton, anthracene skeleton, biphenyl skeleton, anthracene skeleton, novolak skeleton, anthracene skeleton, a phenoxy resin or the like of at least one of a skeleton, an adamantane skeleton, and a dicyclopentadiene skeleton. Further, a commercially available product can also be used as the phenoxy resin. The phenoxy resins may be used singly or in combination of two or more.

作為上述丙烯酸系樹脂,並無特別限定,可列舉將具有碳數30以下(較佳為碳數4~18,進而較佳為碳數6~10,尤佳為碳數8或9)之直鏈或支鏈烷基之丙烯酸或甲基丙烯酸之酯中之一種或兩種以上作為單體成分之聚合物等。即,於第1本發明中,所謂丙烯酸系樹脂,係指亦包括甲基丙烯酸系樹脂之廣義之含義。作為上述烷基,例如可列舉:甲基、乙基、丙基、異丙基、正丁基、第三丁基、異丁基、戊基、異戊基、己基、庚基、2-乙基己基、辛基、異辛基、壬基、異壬基、癸基、異癸基、十一烷基、十二烷基(月桂基)、十三烷基、十四烷基、硬脂基、十八烷基等。 The acrylic resin is not particularly limited, and may have a carbon number of 30 or less (preferably, a carbon number of 4 to 18, more preferably a carbon number of 6 to 10, and particularly preferably a carbon number of 8 or 9). One or two or more of a chain or branched alkyl group of acrylic acid or methacrylic acid ester as a monomer component or the like. That is, in the first aspect of the invention, the term "acrylic resin" means the broad meaning of the methacrylic resin. Examples of the alkyl group include a methyl group, an ethyl group, a propyl group, an isopropyl group, a n-butyl group, a tert-butyl group, an isobutyl group, a pentyl group, an isopentyl group, a hexyl group, a heptyl group, and a 2-ethyl group. Hexyl, octyl, isooctyl, decyl, isodecyl, decyl, isodecyl, undecyl, dodecyl (lauryl), tridecyl, tetradecyl, stearic acid Base, octadecyl and the like.

又,作為用於形成上述丙烯酸系樹脂之其他單體(除了烷基之碳數為30以下之丙烯酸或甲基丙烯酸之烷基酯以外之單體),並無特別限定,例如可列舉:丙烯酸、甲基丙烯酸、丙烯酸羧基乙酯、丙烯酸羧基戊酯、伊康酸、順丁烯二酸、反丁烯二酸或者丁烯酸等之類之含羧基之單體;順丁烯二酸酐或伊康酸酐等之類之酸酐單體;(甲基)丙烯酸2-羥基乙酯、(甲基)丙烯酸2-羥基丙酯、(甲基)丙烯酸4-羥基丁酯、(甲基)丙烯酸6-羥基己酯、(甲基)丙烯酸8-羥基辛酯、(甲基)丙烯酸10-羥基癸酯、(甲基)丙烯酸12-羥基月桂酯或丙烯酸(4-羥基甲基環己基)-甲酯等之類之含羥基之單體;苯乙烯磺酸、烯丙基磺酸、2-(甲基)丙烯醯胺-2-甲基丙磺酸、(甲基)丙烯醯胺丙磺酸、(甲基)丙烯酸磺丙酯或(甲基)丙烯醯氧基萘磺酸等之類之含磺酸基之單體;或者2-羥基乙基丙烯醯基磷酸酯等之類之含磷酸基之單體等。再者,所謂(甲基)丙烯酸,係指丙烯酸及/或甲基丙烯酸,與第1本發明之(甲基)係完全相同之含義。 Further, the other monomer (the monomer other than the alkyl ester of acrylic acid or methacrylic acid having an alkyl group having 30 or less carbon atoms) for forming the acrylic resin is not particularly limited, and examples thereof include acrylic acid. a carboxyl group-containing monomer such as methacrylic acid, carboxyethyl acrylate, carboxy amyl acrylate, itaconic acid, maleic acid, fumaric acid or crotonic acid; maleic anhydride or Anhydride monomer such as itaconic acid anhydride; 2-hydroxyethyl (meth)acrylate, 2-hydroxypropyl (meth)acrylate, 4-hydroxybutyl (meth)acrylate, (meth)acrylic acid 6 -hydroxyhexyl ester, 8-hydroxyoctyl (meth)acrylate, 10-hydroxydecyl (meth)acrylate, 12-hydroxylauryl (meth)acrylate or (4-hydroxymethylcyclohexyl)-acrylic acid a hydroxyl group-containing monomer such as an ester; styrenesulfonic acid, allylsulfonic acid, 2-(methyl)acrylamido-2-methylpropanesulfonic acid, (meth)acrylamide aminesulfonic acid a sulfonic acid group-containing monomer such as sulfopropyl (meth) acrylate or (meth) propylene phthaloxy naphthalene sulfonic acid; or 2-hydroxyethyl acrylonitrile phosphate Of the phosphoric acid group-containing monomer. Further, the term "(meth)acrylic acid" means acrylic acid and/or methacrylic acid, and has the same meaning as the (meth) group of the first invention.

又,作為上述熱硬化性樹脂,除了環氧樹脂、酚樹脂之外,亦可列舉:胺基樹脂、不飽和聚酯樹脂、聚胺基甲酸酯樹脂、聚矽氧樹脂、熱硬化性聚醯亞胺樹脂等。熱硬化性樹脂可單獨使用或併用兩種以上。作為熱硬化性樹脂,尤其適宜為腐蝕半導體元件之離子性雜質等含有較少之環氧樹脂。又,作為環氧樹脂之硬化劑,可適宜地使用酚樹脂。 Further, examples of the thermosetting resin include an epoxy resin and a phenol resin, and an amine resin, an unsaturated polyester resin, a polyurethane resin, a polyoxyxylene resin, and a thermosetting polymer.醯 imine resin and the like. The thermosetting resin may be used singly or in combination of two or more. As the thermosetting resin, it is particularly preferable to contain a small amount of epoxy resin such as ionic impurities for etching a semiconductor element. Further, as the curing agent for the epoxy resin, a phenol resin can be suitably used.

作為環氧樹脂,並無特別限定,例如可使用:雙酚A型環氧樹脂、雙酚F型環氧樹脂、雙酚S型環氧樹脂、溴化雙酚A型環氧樹脂、氫化雙酚A型環氧樹脂、雙酚AF型環氧樹脂、聯苯型環氧樹脂、萘型環氧樹脂、茀型環氧樹脂、苯酚酚醛清漆型環氧樹脂、鄰甲酚酚醛清漆型環氧樹脂、三羥基苯基甲烷型環氧樹脂、四酚基乙烷型環氧樹脂等二官能環氧樹脂或多官能環氧樹脂、或者乙內醯脲型環氧樹脂、異氰脲酸三縮水甘油酯型環氧樹脂或縮水甘油胺型環氧樹脂等環氧樹脂。 The epoxy resin is not particularly limited, and for example, a bisphenol A epoxy resin, a bisphenol F epoxy resin, a bisphenol S epoxy resin, a brominated bisphenol A epoxy resin, or a hydrogenation double can be used. Phenolic A type epoxy resin, bisphenol AF type epoxy resin, biphenyl type epoxy resin, naphthalene type epoxy resin, bismuth type epoxy resin, phenol novolac type epoxy resin, o-cresol novolac type epoxy Difunctional epoxy resin or polyfunctional epoxy resin such as resin, trishydroxyphenylmethane type epoxy resin or tetraphenol ethane type epoxy resin, or ethyl uret urea type epoxy resin or isocyanuric acid tricondensate An epoxy resin such as a glyceride type epoxy resin or a glycidylamine type epoxy resin.

作為環氧樹脂,尤佳為上述例示中之酚醛清漆型環氧樹脂、聯苯型環氧樹脂、三羥基苯基甲烷型環氧樹脂、四酚基乙烷型環氧樹脂。其原因在於,該等環氧樹脂與作為硬化劑之酚樹脂之反應性充分,耐熱性等優異。 As the epoxy resin, a novolak type epoxy resin, a biphenyl type epoxy resin, a trishydroxyphenylmethane type epoxy resin, or a tetraphenol ethane type epoxy resin in the above examples is particularly preferable. This is because the epoxy resin and the phenol resin as the curing agent have sufficient reactivity and are excellent in heat resistance and the like.

進而,上述酚樹脂係作為上述環氧樹脂之硬化劑發揮作用者,例如可列舉:苯酚酚醛清漆樹脂、苯酚芳烷基樹脂、甲酚酚醛清漆樹脂、第三丁基苯酚酚醛清漆樹脂、壬基苯酚酚醛清漆樹脂等酚醛清漆型酚樹脂、可溶酚醛型酚樹脂、聚對羥基苯乙烯等聚羥基苯乙烯等。酚樹脂可單獨使用或併用兩種以上。該等酚樹脂中,尤佳為苯酚酚醛清漆樹脂、苯酚芳烷基樹脂。其原因在於,可提高半導體裝置之連接可靠性。 Further, the phenol resin functions as a curing agent for the epoxy resin, and examples thereof include a phenol novolak resin, a phenol aralkyl resin, a cresol novolak resin, a third butyl phenol novolak resin, and a mercapto group. A phenol novolak type phenol resin such as a phenol novolak resin, a novolac type phenol resin, or a polyhydroxy styrene such as polyparaxyl styrene. The phenol resin may be used singly or in combination of two or more. Among these phenol resins, a phenol novolac resin and a phenol aralkyl resin are particularly preferable. The reason for this is that the connection reliability of the semiconductor device can be improved.

關於環氧樹脂與酚樹脂之調配比率,例如適宜以相對於上述環氧 樹脂成分中之每1當量環氧基,酚樹脂中之羥基成為0.5當量~2.0當量之方式調配。更適宜為0.8當量~1.2當量。即,其原因在於,若兩者之調配比率偏離上述範圍,則無法進行充分之硬化反應,環氧樹脂硬化物之特性容易劣化。 Regarding the ratio of the epoxy resin to the phenol resin, for example, it is suitable to be relative to the above epoxy The epoxy group in the resin component is blended in an amount of from 0.5 equivalent to 2.0 equivalents per one equivalent of the epoxy group in the phenol resin. More preferably, it is 0.8 equivalent - 1.2 equivalent. In other words, when the blending ratio of the two is out of the above range, a sufficient curing reaction cannot be performed, and the properties of the cured epoxy resin are likely to deteriorate.

於第1本發明中,可使用環氧樹脂與酚樹脂之熱硬化促進觸媒。作為熱硬化促進觸媒,並無特別限定,可自公知之熱硬化促進觸媒之中適當地選擇使用。熱硬化促進觸媒可單獨使用或組合兩種以上使用。作為熱硬化促進觸媒,例如可使用胺系硬化促進劑、磷系硬化促進劑、咪唑系硬化促進劑、硼系硬化促進劑、磷-硼系硬化促進劑等。 In the first invention, a thermosetting-promoting catalyst for an epoxy resin and a phenol resin can be used. The thermosetting-promoting catalyst is not particularly limited, and can be appropriately selected from among the known thermosetting-promoting catalysts. The thermosetting-promoting catalyst may be used singly or in combination of two or more. As the thermosetting-promoting catalyst, for example, an amine-based curing accelerator, a phosphorus-based curing accelerator, an imidazole-based curing accelerator, a boron-based curing accelerator, a phosphorus-boron-based curing accelerator, or the like can be used.

作為上述胺系硬化促進劑,並無特別限定,例如可列舉單乙醇胺三氟硼酸鹽(STELLA CHEMIFA股份有限公司製造)、雙氰胺(NACALAI TESQUE股份有限公司製造)等。 The amine-based curing accelerator is not particularly limited, and examples thereof include monoethanolamine trifluoroborate (manufactured by STELLA CHEMIFA Co., Ltd.), dicyandiamide (manufactured by NACALAI TESQUE Co., Ltd.), and the like.

作為上述磷系硬化促進劑,並無特別限定,例如可列舉:三苯基膦、三丁基膦、三(對甲基苯基)膦、三(壬基苯基)膦、二苯基甲苯基膦等三有機膦、溴化四苯基鏻(商品名:TPP-PB)、甲基三苯基鏻(商品名:TPP-MB)、氯化甲基三苯基鏻(商品名:TPP-MC)、甲氧基甲基三苯基鏻(商品名:TPP-MOC)、氯化苄基三苯基鏻(商品名:TPP-ZC)等(均為北興化學股份有限公司製造)。又,作為上述三苯基膦系化合物,較佳為相對於環氧樹脂實質上顯示非溶解性者。若相對於環氧樹脂為非溶解性,則能夠抑制熱硬化過度進行。作為具有三苯基膦結構且相對於環氧樹脂實質上顯示非溶解性之熱硬化觸媒,例如可例示甲基三苯基鏻(商品名:TPP-MB)等。又,所謂上述「非溶解性」,係指包含三苯基膦系化合物之熱硬化觸媒相對於包含環氧樹脂之溶劑為不溶性,更詳細而言,係指於溫度10~40℃之範圍內有10重量%以上不溶解。 The phosphorus-based curing accelerator is not particularly limited, and examples thereof include triphenylphosphine, tributylphosphine, tris(p-methylphenyl)phosphine, tris(nonylphenyl)phosphine, and diphenyltoluene. Triorganophosphine such as phosphine, tetraphenylphosphonium bromide (trade name: TPP-PB), methyltriphenylphosphonium (trade name: TPP-MB), methyltriphenylphosphonium chloride (trade name: TPP) -MC), methoxymethyltriphenylphosphonium (trade name: TPP-MOC), benzyltriphenylphosphonium chloride (trade name: TPP-ZC), etc. (all manufactured by Beixing Chemical Co., Ltd.). Further, the triphenylphosphine-based compound is preferably one which exhibits substantially no solubility with respect to the epoxy resin. When it is insoluble with respect to an epoxy resin, it can suppress that the thermal hardening progresses excessively. As the thermosetting catalyst having a triphenylphosphine structure and exhibiting substantially insolubility with respect to the epoxy resin, for example, methyltriphenylphosphonium (trade name: TPP-MB) or the like can be exemplified. In addition, the term "non-solubility" means that the thermosetting catalyst containing a triphenylphosphine-based compound is insoluble with respect to a solvent containing an epoxy resin, and more specifically, it is in the range of 10 to 40 ° C in temperature. 10% by weight or more of the inside does not dissolve.

作為上述咪唑系硬化促進劑,可列舉:2-甲基咪唑(商品名:2MZ)、2-十一烷基咪唑(商品名:C11-Z)、2-十七烷基咪唑(商品名:C17Z)、1,2-二甲基咪唑(商品名:1.2DMZ)、2-乙基-4-甲基咪唑(商品名:2E4MZ)、2-苯基咪唑(商品名:2PZ)、2-苯基-4-甲基咪唑(商品名:2P4MZ)、1-苄基-2-甲基咪唑(商品名:1B2MZ)、1-苄基-2-苯基咪唑(商品名:1B2PZ)、1-氰基乙基-2-甲基咪唑(商品名:2MZ-CN)、1-氰基乙基-2-十一烷基咪唑(商品名:C11Z-CN)、1-氰基乙基-2-苯基咪唑鎓偏苯三甲酸鹽(商品名:2PZCNS-PW)、2,4-二胺基-6-[2'-甲基咪唑基-(1')]-乙基-均三(商品名:2MZ-A)、2,4-二胺基-6-[2'-十一烷基咪唑基-(1')]-乙基-均三(商品名:C11Z-A)、2,4-二胺基-6-[2'-乙基-4'-甲基咪唑基-(1')]-乙基-均三(商品名:2E4MZ-A)、2,4-二胺基-6-[2'-甲基咪唑基-(1')]-乙基-均三異氰脲酸加成物(商品名:2MA-OK)、2-苯基-4,5-二羥基甲基咪唑(商品名:2PHZ-PW)、2-苯基-4-甲基-5-羥基甲基咪唑(商品名:2P4MHZ-PW)等(均為四國化成工業股份有限公司製造)。 Examples of the imidazole-based hardening accelerator include 2-methylimidazole (trade name: 2MZ), 2-undecylimidazole (trade name: C11-Z), and 2-heptadecylimidazole (trade name: C17Z), 1,2-dimethylimidazole (trade name: 1.2DMZ), 2-ethyl-4-methylimidazole (trade name: 2E4MZ), 2-phenylimidazole (trade name: 2PZ), 2- Phenyl-4-methylimidazole (trade name: 2P4MZ), 1-benzyl-2-methylimidazole (trade name: 1B2MZ), 1-benzyl-2-phenylimidazole (trade name: 1B2PZ), 1 -Cyanoethyl-2-methylimidazole (trade name: 2MZ-CN), 1-cyanoethyl-2-undecylimidazole (trade name: C11Z-CN), 1-cyanoethyl- 2-Phenylimidazolium trimellitate (trade name: 2PZCNS-PW), 2,4-diamino-6-[2'-methylimidazolyl-(1')]-ethyl-all three (trade name: 2MZ-A), 2,4-diamino-6-[2'-undecylimidazolyl-(1')]-ethyl-all three (trade name: C11Z-A), 2,4-diamino-6-[2'-ethyl-4'-methylimidazolyl-(1')]-ethyl-all three (trade name: 2E4MZ-A), 2,4-diamino-6-[2'-methylimidazolyl-(1')]-ethyl-all three Isocyanuric acid adduct (trade name: 2MA-OK), 2-phenyl-4,5-dihydroxymethylimidazole (trade name: 2PHZ-PW), 2-phenyl-4-methyl-5 -Hydroxymethylimidazole (trade name: 2P4MHZ-PW), etc. (all manufactured by Shikoku Chemical Industry Co., Ltd.).

作為上述硼系硬化促進劑,並無特別限定,例如可列舉三氯硼烷等。 The boron-based hardening accelerator is not particularly limited, and examples thereof include trichloroborane and the like.

作為上述磷-硼系硬化促進劑,並無特別限定,例如可列舉:四苯基鏻四苯基硼酸鹽(商品名:TPP-K)、四苯基鏻四對三硼酸鹽(商品名:TPP-MK)、苄基三苯基鏻四苯基硼酸鹽(商品名:TPP-ZK)、三苯基膦三苯基硼烷(商品名:TPP-S)等(均為北興化學股份有限公司製造)。 The phosphorus-boron-based hardening accelerator is not particularly limited, and examples thereof include tetraphenylphosphonium tetraphenylborate (trade name: TPP-K) and tetraphenylphosphonium tetra-triborate (trade name: TPP-MK), benzyltriphenylphosphonium tetraphenylborate (trade name: TPP-ZK), triphenylphosphine triphenylborane (trade name: TPP-S), etc. (both Beixing Chemical Co., Ltd.) Made by the company).

上述熱硬化促進觸媒之比率相對於熱硬化性樹脂總量,較佳為0.01重量%以上且20重量%以下。若熱硬化促進觸媒之上述比率為0.01重量%以上,則即使倒裝晶片連接於被黏著體上之半導體元件為薄型(例如,即使厚度為300μm以下,進而為200μm以下),亦能夠有 效地抑制或防止其翹曲。又,藉由將熱硬化促進觸媒之上述比率設為20重量%以下,能夠使半導體背面用膜之收縮量不會變得過大,而控制成適度之大小。作為熱硬化促進觸媒之上述比率之下限值,較佳為0.03重量%以上(更佳為0.05重量%以上)。又,作為上限值,較佳為18重量%以下(更佳為15重量%以下)。 The ratio of the thermosetting-promoting catalyst is preferably 0.01% by weight or more and 20% by weight or less based on the total amount of the thermosetting resin. When the ratio of the thermosetting-promoting catalyst is 0.01% by weight or more, even if the semiconductor element to which the flip-chip is bonded to the adherend is thin (for example, even if the thickness is 300 μm or less and further 200 μm or less), Effectively inhibit or prevent warpage. In addition, when the ratio of the thermal curing-promoting catalyst is 20% by weight or less, the amount of shrinkage of the film for semiconductor back surface can be controlled to an appropriate size without being excessively large. The lower limit of the above ratio of the thermosetting-promoting catalyst is preferably 0.03% by weight or more (more preferably 0.05% by weight or more). Further, the upper limit is preferably 18% by weight or less (more preferably 15% by weight or less).

作為上述半導體背面用膜,較佳為由含有環氧樹脂及酚樹脂之樹脂組合物形成,尤其適宜為由含有環氧樹脂、酚樹脂及苯氧基樹脂之樹脂組合物形成。 The film for semiconductor back surface is preferably formed of a resin composition containing an epoxy resin and a phenol resin, and is particularly preferably formed of a resin composition containing an epoxy resin, a phenol resin, and a phenoxy resin.

重要的是半導體背面用膜2相對於半導體晶圓之背面(電路非形成面)具有接著性(密接性)。半導體背面用膜2例如可藉由含有作為熱硬化性樹脂之環氧樹脂之樹脂組合物形成。為了使半導體背面用膜2預先交聯至某程度,較佳為於製作時,預先添加與聚合物之分子鏈末端之官能基等反應之多官能性化合物作為交聯劑。藉此,能夠提高於高溫下之接著特性,實現耐熱性之改善。 It is important that the film 2 for semiconductor back surface has adhesiveness (adhesiveness) with respect to the back surface (circuit non-formed surface) of the semiconductor wafer. The film 2 for semiconductor back surface can be formed, for example, by a resin composition containing an epoxy resin as a thermosetting resin. In order to crosslink the film 2 for semiconductor back surface in advance to some extent, it is preferred to add a polyfunctional compound which reacts with a functional group at the end of the molecular chain of the polymer or the like as a crosslinking agent at the time of production. Thereby, it is possible to improve the adhesion characteristics at a high temperature and to improve the heat resistance.

半導體背面用膜相對於半導體晶圓之接著力(23℃,剝離角度180°,剝離速度300mm/min)較佳為1N/10mm寬以上(例如,1N/10mm寬~10N/10mm寬),進而較佳為2N/10mm寬以上(例如,2N/10mm寬~10N/10mm寬),尤佳為4N/10mm寬以上(例如,4N/10mm寬~10N/10mm寬)以上,藉此可以優異之密接性貼著於半導體晶圓或半導體元件,而能夠防止浮起等之產生。又,亦能夠防止於半導體晶圓之切割時產生晶片飛出。再者,半導體背面用膜相對於半導體晶圓之上述接著力為例如以如下方式測定之值。即,於半導體背面用膜之一個面貼著黏著帶(商品名「BT315」,日東電工股份有限公司製造)進行背面加強。然後,於經背面加強之長度150mm、寬度10mm之半導體背面用膜之表面,藉由在50℃下將2kg之輥往返一次之熱層壓法而貼合厚度0.6mm之半導體晶圓。然後,於熱板上(50℃)靜置2分鐘 後,在常溫(23℃左右)下靜置20分鐘。靜置後,使用剝離試驗機(商品名「Autograph AGS-J」,島津製作所公司製造),於溫度23℃下,在剝離角度:180°、拉伸速度:300mm/min之條件下,將經背面加強之半導體背面用膜撕拉剝離。上述接著力係此時之於半導體背面用膜與半導體晶圓之界面進行剝離而測定之值(N/10mm寬)。 The adhesion of the film for semiconductor back surface to the semiconductor wafer (23° C., peeling angle: 180°, peeling speed: 300 mm/min) is preferably 1 N/10 mm or more (for example, 1 N/10 mm width to 10 N/10 mm width). It is preferably 2 N/10 mm or more (for example, 2N/10 mm wide to 10 N/10 mm wide), and particularly preferably 4 N/10 mm or more (for example, 4 N/10 mm wide to 10 N/10 mm wide) or more, whereby it can be excellent. The adhesion is adhered to the semiconductor wafer or the semiconductor element, and the occurrence of floating or the like can be prevented. Moreover, it is also possible to prevent the wafer from flying out during the dicing of the semiconductor wafer. Further, the above-described adhesive force of the film for semiconductor back surface with respect to the semiconductor wafer is, for example, a value measured as follows. In other words, the back side is reinforced by an adhesive tape (trade name "BT315", manufactured by Nitto Denko Corporation) on one surface of the film for semiconductor back surface. Then, a semiconductor wafer having a thickness of 0.6 mm was bonded to the surface of the film for semiconductor back surface having a length of 150 mm and a width of 10 mm which was reinforced by the back surface by a thermal lamination method in which a 2 kg roller was reciprocated once at 50 °C. Then, let it stand on a hot plate (50 ° C) for 2 minutes. Thereafter, it was allowed to stand at room temperature (about 23 ° C) for 20 minutes. After standing, using a peeling tester (trade name "Autograph AGS-J", manufactured by Shimadzu Corporation), at a temperature of 23 ° C, at a peeling angle of 180 ° and a tensile speed of 300 mm / min, the warp was carried out. The back side of the semiconductor back surface is peeled off by a film. The adhesive force is a value (N/10 mm width) measured by peeling off the interface between the film for semiconductor back surface and the semiconductor wafer at this time.

作為上述交聯劑,並無特別限定,可使用公知之交聯劑。具體而言,例如除了異氰酸酯系交聯劑、環氧系交聯劑、三聚氰胺系交聯劑、過氧化物系交聯劑之外,亦可列舉:脲系交聯劑、金屬烷氧化物系交聯劑、金屬螯合物系交聯劑、金屬鹽系交聯劑、碳二醯亞胺系交聯劑、唑啉系交聯劑、氮丙啶系交聯劑、胺系交聯劑等。作為交聯劑,適宜為異氰酸酯系交聯劑或環氧系交聯劑。又,上述交聯劑可單獨使用或組合兩種以上使用。 The crosslinking agent is not particularly limited, and a known crosslinking agent can be used. Specifically, for example, in addition to the isocyanate crosslinking agent, the epoxy crosslinking agent, the melamine crosslinking agent, and the peroxide crosslinking agent, a urea crosslinking agent and a metal alkoxide system may be mentioned. a crosslinking agent, a metal chelate crosslinking agent, a metal salt crosslinking agent, a carbon diimide crosslinking agent, An oxazoline crosslinking agent, an aziridine crosslinking agent, an amine crosslinking agent, and the like. The crosslinking agent is preferably an isocyanate crosslinking agent or an epoxy crosslinking agent. Further, the above crosslinking agents may be used singly or in combination of two or more.

作為上述異氰酸酯系交聯劑,例如可列舉:1,2-伸乙基二異氰酸酯、1,4-伸丁基二異氰酸酯、1,6-六亞甲基二異氰酸酯等低級脂肪族聚異氰酸酯類;伸環戊基二異氰酸酯、伸環己基二異氰酸酯、異佛爾酮二異氰酸酯、氫化甲苯二異氰酸酯、氫化二甲苯二異氰酸酯等脂環族聚異氰酸酯類;2,4-甲苯二異氰酸酯、2,6-甲苯二異氰酸酯、4,4'-二苯基甲烷二異氰酸酯、苯二甲基二異氰酸酯等芳香族聚異氰酸酯類等,此外,亦可使用三羥甲基丙烷/甲苯二異氰酸酯三聚物加成物(Nippon Polyurethane Industry股份有限公司製造,商品名「CORONATE L」)、三羥甲基丙烷/六亞甲基二異氰酸酯三聚物加成物(Nippon Polyurethane Industry股份有限公司製造,商品名「CORONATE HL」)等。又,作為上述環氧系交聯劑,例如可列舉:N,N,N',N'-四縮水甘油基-間苯二甲胺、二縮水甘油基苯胺、1,3-雙(N,N-縮水甘油基胺基甲基)環己烷、1,6-己二醇二縮水甘油醚、新戊二醇二縮水甘油醚、乙二醇二縮水甘油醚、丙二醇二縮水甘油醚、聚 乙二醇二縮水甘油醚、聚丙二醇二縮水甘油醚、山梨糖醇聚縮水甘油醚、甘油聚縮水甘油醚、季戊四醇聚縮水甘油醚、聚甘油聚縮水甘油醚、山梨糖醇酐聚縮水甘油醚、三羥甲基丙烷聚縮水甘油醚、己二酸二縮水甘油酯、鄰苯二甲酸二縮水甘油酯、三(2-羥基乙基)異氰脲酸三縮水甘油酯、間苯二酚二縮水甘油醚、雙酚S-二縮水甘油醚,此外亦可列舉分子內具有2個以上環氧基之環氧系樹脂等。 Examples of the isocyanate crosslinking agent include lower aliphatic polyisocyanates such as 1,2-ethylidene diisocyanate, 1,4-butylene diisocyanate, and 1,6-hexamethylene diisocyanate; Cycloaliphatic diisocyanate, cyclohexyl diisocyanate, isophorone diisocyanate, hydrogenated toluene diisocyanate, hydrogenated xylene diisocyanate and other alicyclic polyisocyanates; 2,4-toluene diisocyanate, 2,6- An aromatic polyisocyanate such as toluene diisocyanate, 4,4'-diphenylmethane diisocyanate or benzodimethyl diisocyanate, or a trimethylolpropane/toluene diisocyanate trimer adduct may be used. (manufactured by Nippon Polyurethane Industry Co., Ltd., trade name "CORONATE L"), trimethylolpropane / hexamethylene diisocyanate terpolymer adduct (manufactured by Nippon Polyurethane Industry Co., Ltd., trade name "CORONATE HL" )Wait. Moreover, examples of the epoxy-based crosslinking agent include N, N, N', N'-tetraglycidyl-m-xylylenediamine, diglycidylaniline, and 1,3-bis(N, N-glycidylaminomethyl)cyclohexane, 1,6-hexanediol diglycidyl ether, neopentyl glycol diglycidyl ether, ethylene glycol diglycidyl ether, propylene glycol diglycidyl ether, poly Ethylene glycol diglycidyl ether, polypropylene glycol diglycidyl ether, sorbitol polyglycidyl ether, glycerol polyglycidyl ether, pentaerythritol polyglycidyl ether, polyglycerol polyglycidyl ether, sorbitan polyglycidyl ether , trimethylolpropane polyglycidyl ether, diglycidyl adipate, diglycidyl phthalate, tris(2-hydroxyethyl) isocyanuric acid triglycidyl ester, resorcinol Examples of the glycidyl ether and the bisphenol S-diglycidyl ether include an epoxy resin having two or more epoxy groups in the molecule.

再者,交聯劑之使用量並無特別限定,可根據交聯之程度適當地選擇。具體而言,作為交聯劑之使用量,較佳為例如相對於聚合物成分(尤其是具有分子鏈末端之官能基之聚合物),通常設為7重量份以下(例如,0.05重量份~7重量份)。若交聯劑之使用量相對於聚合物成分100重量份而多於7重量份,則接著力降低,故欠佳。再者,就提高凝聚力之觀點而言,較佳為交聯劑之使用量相對於聚合物成分100重量份為0.05重量份以上。 Further, the amount of the crosslinking agent used is not particularly limited, and may be appropriately selected depending on the degree of crosslinking. Specifically, the amount of the crosslinking agent to be used is preferably, for example, 7 parts by weight or less based on the polymer component (especially a polymer having a functional group at the end of the molecular chain) (for example, 0.05 part by weight or less). 7 parts by weight). When the amount of the crosslinking agent used is more than 7 parts by weight based on 100 parts by weight of the polymer component, the adhesion is lowered, which is not preferable. Further, from the viewpoint of improving the cohesive force, the amount of the crosslinking agent used is preferably 0.05 parts by weight or more based on 100 parts by weight of the polymer component.

再者,於第1本發明中,可代替使用交聯劑或者於使用交聯劑之同時藉由電子束或紫外線等之照射實施交聯處理。 Further, in the first aspect of the invention, the crosslinking treatment may be carried out by irradiation with an electron beam or ultraviolet rays instead of using a crosslinking agent or by using a crosslinking agent.

上述半導體背面用膜較佳為被著色。藉此,能夠發揮優異之標記性以及外觀性,可形成具有附加價值之外觀之半導體裝置。如此,由於經著色之半導體背面用膜具有優異之標記性,因此於半導體元件或使用有該半導體元件之半導體裝置之非電路面側之面,可經由半導體背面用膜,藉由利用印刷方法或鐳射標記方法等各種標記方法而施加標記,賦予文字資訊或圖形資訊等各種資訊。尤其是,藉由控制著色之顏色,可以優異之視認性對藉由標記所賦予之資訊(文字資訊、圖形資訊等)進行視認。又,由於半導體背面用膜被著色,因此能夠容易地區分切晶帶與半導體背面用膜,而可提高作業性等。進而,例如對於半導體裝置,亦可按製品類別進行顏色區分。於使半導體背面用膜為有色之情形時(並非為無色.透明之情形時),作為藉由著色呈現之 顏色,並無特別限定,例如較佳為黑色、藍色、紅色等濃色,尤其適宜為黑色。 The film for semiconductor back surface is preferably colored. Thereby, it is possible to exhibit excellent marking properties and appearance properties, and it is possible to form a semiconductor device having an appearance of added value. In this way, since the colored film for semiconductor back surface has excellent marking properties, the surface of the semiconductor element or the non-circuit surface side of the semiconductor device using the semiconductor element can be passed through the film for semiconductor back surface, by using a printing method or Various marking methods such as a laser marking method are applied to give various information such as text information or graphic information. In particular, by controlling the color of the coloring, the information (text information, graphic information, etc.) given by the mark can be visually recognized with excellent visibility. In addition, since the film for semiconductor back surface is colored, it is possible to easily distinguish between the dicing tape and the film for semiconductor back surface, and it is possible to improve workability and the like. Further, for example, in the case of a semiconductor device, color discrimination can be performed by product type. When the film for the back surface of the semiconductor is colored (not when it is colorless or transparent), it is rendered by coloring. The color is not particularly limited. For example, it is preferably a dark color such as black, blue or red, and particularly preferably black.

於本實施形態中,所謂濃色,基本上係指以L*a*b*表色系統規定之L*成為60以下(0~60)[較佳為50以下(0~50),進而較佳為40以下(0~40)]之較濃之顏色。 In the present embodiment, the term "dense color" basically means that the L* defined by the L*a*b* color system is 60 or less (0 to 60) (preferably 50 or less (0 to 50), and further Good is 40 or less (0~40)] thicker color.

又,所謂黑色,基本上係指以L*a*b*表色系統規定之L*成為35以下(0~35)[較佳為30以下(0~30),進而較佳為25以下(0~25)]之黑色系顏色。再者,於黑色中,以L*a*b*表色系統規定之a*或b*可分別根據L*之值適當地選擇。作為a*或b*,例如較佳為兩者均為-10~10,更佳為-5~5,尤其適宜為-3~3之範圍(特別是0或大致為0)。 In addition, the term "black" basically means that the L* defined by the L*a*b* color system is 35 or less (0 to 35) (preferably 30 or less (0 to 30), and more preferably 25 or less ( 0~25)] black color. Further, in black, a* or b* defined by the L*a*b* color system can be appropriately selected according to the value of L*. As a* or b*, for example, both of them are preferably -10 to 10, more preferably -5 to 5, and particularly preferably a range of -3 to 3 (particularly 0 or substantially 0).

再者,於本實施形態中,以L*a*b*表色系統規定之L*、a*、b*係藉由使用色彩色差計(商品名「CR-200」,MINOLTA公司製造之色彩色差計)進行測定而求出。再者,L*a*b*表色系統係國際照明委員會(CIE)於1976年推薦之顏色空間,指被稱為CIE1976(L*a*b*)表色系統之顏色空間。又,L*a*b*表色系統之日本工業規格規定於JIS Z 8729中。 Further, in the present embodiment, the L*, a*, and b* defined by the L*a*b* color system are color-color difference meters (trade name "CR-200", color manufactured by MINOLTA Co., Ltd.). The color difference meter was measured and determined. Furthermore, the L*a*b* color system is the color space recommended by the International Commission on Illumination (CIE) in 1976, referring to the color space known as the CIE1976 (L*a*b*) color system. Further, the Japanese industrial specifications of the L*a*b* color system are specified in JIS Z 8729.

於將半導體背面用膜著色時,根據作為目標之顏色,可使用色料(著色劑)。作為此種色料,可適宜地使用黑系色料、藍系色料、紅系色料等各種濃色系色料,尤其適宜為黑系色料。作為色料,顏料、染料等均可。色料可單獨使用或組合兩種以上使用。再者,作為染料,可使用酸性染料、反應染料、直接染料、分散染料、陽離子染料等任一形態之染料。又,顏料之形態亦無特別限定,可自公知之顏料中適當地選擇使用。 When the film for semiconductor back surface is colored, a coloring material (coloring agent) can be used depending on the intended color. As such a coloring material, various concentrated color materials such as a black coloring material, a blue coloring material, and a red coloring material can be suitably used, and a black coloring material is particularly preferable. As a coloring material, a pigment, a dye, or the like can be used. The colorants may be used singly or in combination of two or more. Further, as the dye, a dye of any form such as an acid dye, a reactive dye, a direct dye, a disperse dye, or a cationic dye can be used. Further, the form of the pigment is not particularly limited, and can be appropriately selected from known pigments.

尤其是,若使用染料作為色料,則由於在半導體背面用膜中,染料藉由溶解而成為均勻或大致均勻地分散之狀態,因此能夠容易地製造著色濃度均勻或大致均勻之半導體背面用膜(進而切晶帶一體型半 導體背面用膜)。因此,若使用染料作為色料,則能夠使切晶帶一體型半導體背面用膜中之半導體背面用膜之著色濃度均勻或大致均勻,而可提高標記性或外觀性。 In particular, when a dye is used as the coloring material, the dye is uniformly or substantially uniformly dispersed in the film for semiconductor back surface, so that the film for semiconductor back surface having uniform or substantially uniform coloring concentration can be easily produced. (There is a cleavage ribbon integrated half Film for the back of the conductor). Therefore, when a dye is used as the coloring material, the color density of the film for semiconductor back surface in the film for a dicing tape-integrated semiconductor back surface can be made uniform or substantially uniform, and the marking property or the appearance property can be improved.

作為黑系色料,並無特別限定,例如可自無機之黑系顏料、黑系染料中適當地選擇。又,作為黑系色料,可為將氰系色料(藍綠系色料)、品紅系色料(紫紅系色料)以及黃色系色料(黃系色料)混合而得之色料混合物。黑系色料可單獨使用或組合兩種以上使用。當然,黑系色料亦可與黑色以外之顏色之色料併用。 The black coloring material is not particularly limited, and can be appropriately selected, for example, from an inorganic black pigment or a black dye. Further, as the black coloring material, a color obtained by mixing a cyan coloring material (blue-green coloring material), a magenta coloring material (purple coloring coloring material), and a yellow coloring material (yellow coloring material) may be used. Mixture. The black coloring materials may be used singly or in combination of two or more. Of course, black pigments can also be used in combination with color materials other than black.

具體而言,作為黑系色料,例如可列舉:碳黑(爐黑、煙囪黑、乙炔黑、熱碳黑(thermal black)、燈黑等)、石墨(graphite)、氧化銅、二氧化錳、偶氮系顏料(甲亞胺偶氮黑(azomethineazoblack)等)、苯胺黑、苝黑、鈦黑、花青黑、活性碳、鐵氧體(非磁性鐵氧體、磁性鐵氧體等)、磁鐵礦(magnetite)、氧化鉻、氧化鐵、二硫化鉬、鉻錯合物、複合氧化物系黑色色素、蒽醌系有機黑色色素等。 Specifically, examples of the black coloring material include carbon black (furnace black, chimney black, acetylene black, thermal black, lamp black, etc.), graphite (graphite), copper oxide, and manganese dioxide. , azo-based pigments (azomethineazoblack, etc.), nigrosine, phthalocyanine, titanium black, cyanine black, activated carbon, ferrite (non-magnetic ferrite, magnetic ferrite, etc.) Magnetite, chromium oxide, iron oxide, molybdenum disulfide, chromium complex, composite oxide black pigment, lanthanide organic black pigment, and the like.

於第1本發明中,作為黑系色料,可列舉:C.I.溶劑黑3、C.I.溶劑黑7、C.I.溶劑黑22、C.I.溶劑黑27、C.I.溶劑黑29、C.I.溶劑黑34、C.I.溶劑黑43、C.I.溶劑黑70、C.I.直接黑17、C.I.直接黑19、C.I.直接黑22、C.I.直接黑32、C.I.直接黑38、C.I.直接黑51、C.I.直接黑71、C.I.酸性黑1、C.I.酸性黑2、C.I.酸性黑24、C.I.酸性黑26、C.I.酸性黑31、C.I.酸性黑48、C.I.酸性黑52、C.I.酸性黑107、C.I.酸性黑109、C.I.酸性黑110、C.I.酸性黑119、C.I.酸性黑154、C.I.分散黑1、C.I.分散黑3、C.I.分散黑10、C.I.分散黑24等黑系染料;C.I.顏料黑1、C.I.顏料黑7等黑系顏料等。 In the first invention, examples of the black coloring material include CI solvent black 3, CI solvent black 7, CI solvent black 22, CI solvent black 27, CI solvent black 29, CI solvent black 34, and CI solvent black 43. , CI Solvent Black 70, CI Direct Black 17, CI Direct Black 19, CI Direct Black 22, CI Direct Black 32, CI Direct Black 38, CI Direct Black 51, CI Direct Black 71, CI Acid Black 1, CI Acid Black 2 , CI Acid Black 24, CI Acid Black 26, CI Acid Black 31, CI Acid Black 48, CI Acid Black 52, CI Acid Black 107, CI Acid Black 109, CI Acid Black 110, CI Acid Black 119, CI Acid Black 154 Black dyes such as CI dispersion black 1, CI dispersion black 3, CI dispersion black 10, and CI dispersion black 24; black pigments such as CI pigment black 1, CI pigment black 7, and the like.

作為此種黑系色料,例如市售有商品名「Oil Black BY」、商品名「Oil Black BS」、商品名「Oil Black HBB」、商品名「Oil Black 803」、商品名「Oil Black 860」、商品名「Oil Black 5970」、商品名 「Oil Black 5906」、商品名「Oil Black 5905」(ORIENT CHEMICAL INDUSTRIES股份有限公司製造)等。 As such a black color material, for example, the product name "Oil Black BY", the trade name "Oil Black BS", the trade name "Oil Black HBB", the trade name "Oil Black 803", and the trade name "Oil Black 860" are commercially available. "Product name "Oil Black 5970", trade name "Oil Black 5906", trade name "Oil Black 5905" (manufactured by ORIENT CHEMICAL INDUSTRIES, Inc.), etc.

作為除黑系色料以外之色料,例如可列舉氰系色料、品紅系色料、黃色系色料等。作為氰系色料,例如可列舉:C.I.溶劑藍25、C.I.溶劑藍36、C.I.溶劑藍60、C.I.溶劑藍70、C.I.溶劑藍93、C.I.溶劑藍95;C.I.酸性藍6、C.I.酸性藍45等氰系染料;C.I.顏料藍1、C.I.顏料藍2、C.I.顏料藍3、C.I.顏料藍15、C.I.顏料藍15:1、C.I.顏料藍15:2、C.I.顏料藍15:3、C.I.顏料藍15:4、C.I.顏料藍15:5、C.I.顏料藍15:6、C.I.顏料藍16、C.I.顏料藍17、C.I.顏料藍17:1、C.I.顏料藍18、C.I.顏料藍22、C.I.顏料藍25、C.I.顏料藍56、C.I.顏料藍60、C.I.顏料藍63、C.I.顏料藍65、C.I.顏料藍66;C.I.還原藍4、C.I.還原藍60;C.I.顏料綠7等氰系顏料等。 Examples of the coloring material other than the black coloring material include a cyan coloring material, a magenta coloring material, and a yellow coloring material. Examples of the cyan-based coloring matter include CI solvent blue 25, CI solvent blue 36, CI solvent blue 60, CI solvent blue 70, CI solvent blue 93, CI solvent blue 95, CI acid blue 6, CI acid blue 45, and the like. Cyanide dye; CI Pigment Blue 1, CI Pigment Blue 2, CI Pigment Blue 3, CI Pigment Blue 15, CI Pigment Blue 15:1, CI Pigment Blue 15:2, CI Pigment Blue 15:3, CI Pigment Blue 15: 4, CI Pigment Blue 15:5, CI Pigment Blue 15:6, CI Pigment Blue 16, CI Pigment Blue 17, CI Pigment Blue 17:1, CI Pigment Blue 18, CI Pigment Blue 22, CI Pigment Blue 25, CI Pigment Blue 56, CI Pigment Blue 60, CI Pigment Blue 63, CI Pigment Blue 65, CI Pigment Blue 66; CI Reduction Blue 4, CI Reduction Blue 60; CI Pigment Green 7 and other cyanide pigments.

又,於品紅系色料中,作為品紅系染料,例如可列舉:C.I.溶劑紅1、C.I.溶劑紅3、C.I.溶劑紅8、C.I.溶劑紅23、C.I.溶劑紅24、C.I.溶劑紅25、C.I.溶劑紅27、C.I.溶劑紅30、C.I.溶劑紅49、C.I.溶劑紅52、C.I.溶劑紅58、C.I.溶劑紅63、C.I.溶劑紅81、C.I.溶劑紅82、C.I.溶劑紅83、C.I.溶劑紅84、C.I.溶劑紅100、C.I.溶劑紅109、C.I.溶劑紅111、C.I.溶劑紅121、C.I.溶劑紅122;C.I.分散紅9;C.I.溶劑紫8、C.I.溶劑紫13、C.I.溶劑紫14、C.I.溶劑紫21、C.I.溶劑紫27;C.I.分散紫1;C.I.鹼性紅1、C.I.鹼性紅2、C.I.鹼性紅9、C.I.鹼性紅12、C.I.鹼性紅13、C.I.鹼性紅14、C.I.鹼性紅15、C.I.鹼性紅17、C.I.鹼性紅18、C.I.鹼性紅22、C.I.鹼性紅23、C.I.鹼性紅24、C.I.鹼性紅27、C.I.鹼性紅29、C.I.鹼性紅32、C.I.鹼性紅34、C.I.鹼性紅35、C.I.鹼性紅36、C.I.鹼性紅37、C.I.鹼性紅38、C.I.鹼性紅39、C.I.鹼性紅40;C.I.鹼性紫1、C.I.鹼性紫3、C.I.鹼性紫7、C.I.鹼性紫10、C.I.鹼性紫14、C.I.鹼性紫15、C.I.鹼性紫21、C.I.鹼性紫25、C.I.鹼性紫26、C.I.鹼性 紫27、C.I.鹼性紫28等。 In the magenta dye, examples of the magenta dye include CI solvent red 1, CI solvent red 3, CI solvent red 8, CI solvent red 23, CI solvent red 24, and CI solvent red 25. CI solvent red 27, CI solvent red 30, CI solvent red 49, CI solvent red 52, CI solvent red 58, CI solvent red 63, CI solvent red 81, CI solvent red 82, CI solvent red 83, CI solvent red 84, CI solvent red 100, CI solvent red 109, CI solvent red 111, CI solvent red 121, CI solvent red 122; CI dispersion red 9; CI solvent violet 8, CI solvent violet 13, CI solvent violet 14, CI solvent violet 21, CI Solvent Violet 27; CI Disperse Violet 1; CI Alkaline Red 1, CI Alkali Red 2, CI Alkaline Red 9, CI Alkaline Red 12, CI Alkaline Red 13, CI Alkaline Red 14, CI Alkali Red 15, CI alkaline red 17, CI alkaline red 18, CI alkaline red 22, CI alkaline red 23, CI alkaline red 24, CI alkaline red 27, CI alkaline red 29, CI alkaline red 32, CI alkaline red 34, CI alkaline red 35, CI alkaline red 36, CI alkaline red 37, CI alkaline red 38, CI basic red 39, CI basic red 40; CI alkaline purple 1, CI alkali Sexual purple 3 C.I. Basic Violet 7, C.I. Basic Violet 10, C.I. Basic Violet 14, C.I. Basic Violet 15, C.I. Basic Violet 21, C.I. Basic Violet 25, C.I. Basic Violet 26, C.I. Basic Purple 27, C.I. Basic Violet 28 and the like.

於品紅系色料中,作為品紅系顏料,例如可列舉:C.I.顏料紅1、C.I.顏料紅2、C.I.顏料紅3、C.I.顏料紅4、C.I.顏料紅5、C.I.顏料紅6、C.I.顏料紅7、C.I.顏料紅8、C.I.顏料紅9、C.I.顏料紅10、C.I.顏料紅11、C.I.顏料紅12、C.I.顏料紅13、C.I.顏料紅14、C.I.顏料紅15、C.I.顏料紅16、C.I.顏料紅17、C.I.顏料紅18、C.I.顏料紅19、C.I.顏料紅21、C.I.顏料紅22、C.I.顏料紅23、C.I.顏料紅30、C.I.顏料紅31、C.I.顏料紅32、C.I.顏料紅37、C.I.顏料紅38、C.I.顏料紅39、C.I.顏料紅40、C.I.顏料紅41、C.I.顏料紅42、C.I.顏料紅48:1、C.I.顏料紅48:2、C.I.顏料紅48:3、C.I.顏料紅48:4、C.I.顏料紅49、C.I.顏料紅49:1、C.I.顏料紅50、C.I.顏料紅51、C.I.顏料紅52、C.I.顏料紅52:2、C.I.顏料紅53:1、C.I.顏料紅54、C.I.顏料紅55、C.I.顏料紅56、C.I.顏料紅57:1、C.I.顏料紅58、C.I.顏料紅60、C.I.顏料紅60:1、C.I.顏料紅63、C.I.顏料紅63:1、C.I.顏料紅63:2、C.I.顏料紅64、C.I.顏料紅64:1、C.I.顏料紅67、C.I.顏料紅68、C.I.顏料紅81、C.I.顏料紅83、C.I.顏料紅87、C.I.顏料紅88、C.I.顏料紅89、C.I.顏料紅90、C.I.顏料紅92、C.I.顏料紅101、C.I.顏料紅104、C.I.顏料紅105、C.I.顏料紅106、C.I.顏料紅108、C.I.顏料紅112、C.I.顏料紅114、C.I.顏料紅122、C.I.顏料紅123、C.I.顏料紅139、C.I.顏料紅144、C.I.顏料紅146、C.I.顏料紅147、C.I.顏料紅149、C.I.顏料紅150、C.I.顏料紅151、C.I.顏料紅163、C.I.顏料紅166、C.I.顏料紅168、C.I.顏料紅170、C.I.顏料紅171、C.I.顏料紅172、C.I.顏料紅175、C.I.顏料紅176、C.I.顏料紅177、C.I.顏料紅178、C.I.顏料紅179、C.I.顏料紅184、C.I.顏料紅185、C.I.顏料紅187、C.I.顏料紅190、C.I.顏料紅193、C.I.顏料紅202、C.I.顏料紅206、C.I.顏料紅207、C.I.顏料紅209、C.I.顏料紅219、C.I.顏料紅222、C.I.顏料紅 224、C.I.顏料紅238、C.I.顏料紅245;C.I.顏料紫3、C.I.顏料紫9、C.I.顏料紫19、C.I.顏料紫23、C.I.顏料紫31、C.I.顏料紫32、C.I.顏料紫33、C.I.顏料紫36、C.I.顏料紫38、C.I.顏料紫43、C.I.顏料紫50;C.I.還原紅1、C.I.還原紅2、C.I.還原紅10、C.I.還原紅13、C.I.還原紅15、C.I.還原紅23、C.I.還原紅29、C.I.還原紅35等。 In the magenta coloring material, examples of the magenta pigment include CI Pigment Red 1, CI Pigment Red 2, CI Pigment Red 3, CI Pigment Red 4, CI Pigment Red 5, CI Pigment Red 6, and CI Pigment. Red 7, CI Pigment Red 8, CI Pigment Red 9, CI Pigment Red 10, CI Pigment Red 11, CI Pigment Red 12, CI Pigment Red 13, CI Pigment Red 14, CI Pigment Red 15, CI Pigment Red 16, CI Pigment Red 17, CI Pigment Red 18, CI Pigment Red 19, CI Pigment Red 21, CI Pigment Red 22, CI Pigment Red 23, CI Pigment Red 30, CI Pigment Red 31, CI Pigment Red 32, CI Pigment Red 37, CI Pigment Red 38, CI Pigment Red 39, CI Pigment Red 40, CI Pigment Red 41, CI Pigment Red 42, CI Pigment Red 48:1, CI Pigment Red 48:2, CI Pigment Red 48:3, CI Pigment Red 48:4 , CI Pigment Red 49, CI Pigment Red 49:1, CI Pigment Red 50, CI Pigment Red 51, CI Pigment Red 52, CI Pigment Red 52:2, CI Pigment Red 53:1, CI Pigment Red 54, CI Pigment Red 55, CI Pigment Red 56, CI Pigment Red 57:1, CI Pigment Red 58, CI Pigment Red 60, CI Pigment Red 60:1, CI Pigment Red 63, CI Yan Red 63:1, CI Pigment Red 63:2, CI Pigment Red 64, CI Pigment Red 64:1, CI Pigment Red 67, CI Pigment Red 68, CI Pigment Red 81, CI Pigment Red 83, CI Pigment Red 87, CI Pigment Red 88, CI Pigment Red 89, CI Pigment Red 90, CI Pigment Red 92, CI Pigment Red 101, CI Pigment Red 104, CI Pigment Red 105, CI Pigment Red 106, CI Pigment Red 108, CI Pigment Red 112, CI Pigment Red 114, CI Pigment Red 122, CI Pigment Red 123, CI Pigment Red 139, CI Pigment Red 144, CI Pigment Red 146, CI Pigment Red 147, CI Pigment Red 149, CI Pigment Red 150, CI Pigment Red 151, CI Pigment Red 163, CI Pigment Red 166, CI Pigment Red 168, CI Pigment Red 170, CI Pigment Red 171, CI Pigment Red 172, CI Pigment Red 175, CI Pigment Red 176, CI Pigment Red 177, CI Pigment Red 178, CI Pigment Red 179, CI Pigment Red 184, CI Pigment Red 185, CI Pigment Red 187, CI Pigment Red 190, CI Pigment Red 193, CI Pigment Red 202, CI Pigment Red 206, CI Pigment Red 207, CI Pigment Red 209, CI Pigment Red 219, CI Pigment Red 222, CI Pigment Red 224, CI Pigment Red 238, CI Pigment Red 245; CI Pigment Violet 3, CI Pigment Violet 9, CI Pigment Violet 19, CI Pigment Violet 23, CI Pigment Violet 31, CI Pigment Violet 32, CI Pigment Violet 33, CI Pigment Violet 36, CI Pigment Violet 38, CI Pigment Violet 43, CI Pigment Violet 50; CI Reducing Red 1, CI Reducing Red 2, CI Reducing Red 10, CI Reducing Red 13, CI Reducing Red 15, CI Reducing Red 23, CI Reducing Red 29, CI restores red 35 and so on.

又,作為黃色系色料,例如可列舉:C.I.溶劑黃19、C.I.溶劑黃44、C.I.溶劑黃77、C.I.溶劑黃79、C.I.溶劑黃81、C.I.溶劑黃82、C.I.溶劑黃93、C.I.溶劑黃98、C.I.溶劑黃103、C.I.溶劑黃104、C.I.溶劑黃112、C.I.溶劑黃162等黃色系染料;C.I.顏料橙31、C.I.顏料橙43;C.I.顏料黃1、C.I.顏料黃2、C.I.顏料黃3、C.I.顏料黃4、C.I.顏料黃5、C.I.顏料黃6、C.I.顏料黃7、C.I.顏料黃10、C.I.顏料黃11、C.I.顏料黃12、C.I.顏料黃13、C.I.顏料黃14、C.I.顏料黃15、C.I.顏料黃16、C.I.顏料黃17、C.I.顏料黃23、C.I.顏料黃24、C.I.顏料黃34、C.I.顏料黃35、C.I.顏料黃37、C.I.顏料黃42、C.I.顏料黃53、C.I.顏料黃55、C.I.顏料黃65、C.I.顏料黃73、C.I.顏料黃74、C.I.顏料黃75、C.I.顏料黃81、C.I.顏料黃83、C.I.顏料黃93、C.I.顏料黃94、C.I.顏料黃95、C.I.顏料黃97、C.I.顏料黃98、C.I.顏料黃100、C.I.顏料黃101、C.I.顏料黃104、C.I.顏料黃108、C.I.顏料黃109、C.I.顏料黃110、C.I.顏料黃113、C.I.顏料黃114、C.I.顏料黃116、C.I.顏料黃117、C.I.顏料黃120、C.I.顏料黃128、C.I.顏料黃129、C.I.顏料黃133、C.I.顏料黃138、C.I.顏料黃139、C.I.顏料黃147、C.I.顏料黃150、C.I.顏料黃151、C.I.顏料黃153、C.I.顏料黃154、C.I.顏料黃155、C.I.顏料黃156、C.I.顏料黃167、C.I.顏料黃172、C.I.顏料黃173、C.I.顏料黃180、C.I.顏料黃185、C.I.顏料黃195;C.I.還原黃1、C.I.還原黃3、C.I.還原黃20等黃色系顏料等。 Further, examples of the yellow coloring material include CI Solvent Yellow 19, CI Solvent Yellow 44, CI Solvent Yellow 77, CI Solvent Yellow 79, CI Solvent Yellow 81, CI Solvent Yellow 82, CI Solvent Yellow 93, and CI Solvent Yellow. 98, CI Solvent Yellow 103, CI Solvent Yellow 104, CI Solvent Yellow 112, CI Solvent Yellow 162 and other yellow dyes; CI Pigment Orange 31, CI Pigment Orange 43; CI Pigment Yellow 1, CI Pigment Yellow 2, CI Pigment Yellow 3 , CI Pigment Yellow 4, CI Pigment Yellow 5, CI Pigment Yellow 6, CI Pigment Yellow 7, CI Pigment Yellow 10, CI Pigment Yellow 11, CI Pigment Yellow 12, CI Pigment Yellow 13, CI Pigment Yellow 14, CI Pigment Yellow 15 , CI Pigment Yellow 16, CI Pigment Yellow 17, CI Pigment Yellow 23, CI Pigment Yellow 24, CI Pigment Yellow 34, CI Pigment Yellow 35, CI Pigment Yellow 37, CI Pigment Yellow 42, CI Pigment Yellow 53, CI Pigment Yellow 55 , CI Pigment Yellow 65, CI Pigment Yellow 73, CI Pigment Yellow 74, CI Pigment Yellow 75, CI Pigment Yellow 81, CI Pigment Yellow 83, CI Pigment Yellow 93, CI Pigment Yellow 94, CI Pigment Yellow 95, CI Pigment Yellow 97 , CI Pigment Yellow 98, CI Pigment Yellow 100, CI Pigment Yellow 101, CI Pigment Yellow 104, CI Pigment Yellow 108 , CI Pigment Yellow 109, CI Pigment Yellow 110, CI Pigment Yellow 113, CI Pigment Yellow 114, CI Pigment Yellow 116, CI Pigment Yellow 117, CI Pigment Yellow 120, CI Pigment Yellow 128, CI Pigment Yellow 129, CI Pigment Yellow 133 , CI Pigment Yellow 138, CI Pigment Yellow 139, CI Pigment Yellow 147, CI Pigment Yellow 150, CI Pigment Yellow 151, CI Pigment Yellow 153, CI Pigment Yellow 154, CI Pigment Yellow 155, CI Pigment Yellow 156, CI Pigment Yellow 167 , CI Pigment Yellow 172, CI Pigment Yellow 173, CI Pigment Yellow 180, CI Pigment Yellow 185, CI Pigment Yellow 195; CI-reduced yellow 1, CI-reduced yellow 3, CI-reduced yellow 20 and other yellow pigments.

氰系色料、品紅系色料、黃色系色料等各種色料可分別單獨使用 或組合兩種以上使用。再者,於使用兩種以上氰系色料、品紅系色料、黃色系色料等各種色料之情形時,作為該等色料之混合比率(或調配比率),並無特別限定,可根據各色料之種類或作為目標之顏色等適當地選擇。 Various color materials such as cyanide coloring material, magenta coloring material, and yellow coloring material can be used separately Or use two or more combinations. In the case where two or more kinds of coloring materials such as a cyan coloring material, a magenta coloring material, and a yellow coloring material are used, the mixing ratio (or blending ratio) of the coloring materials is not particularly limited. It can be suitably selected according to the kind of each coloring material, the target color, etc.

於將半導體背面用膜2著色之情形時,其著色形態並無特別限定。例如,半導體背面用膜可為添加有著色劑之單層之膜狀物。又,亦可為至少積層有至少藉由熱硬化性樹脂形成之樹脂層、及著色劑層之積層膜。再者,於半導體背面用膜2為樹脂層與著色劑層之積層膜之情形時,作為積層形態之半導體背面用膜2,較佳為具有樹脂層/著色劑層/樹脂層之積層形態。於該情形時,著色劑層之兩側之2個樹脂層可為同一組成之樹脂層,亦可為不同組成之樹脂層。 When the film 2 for semiconductor back surface is colored, the color form is not particularly limited. For example, the film for semiconductor back surface may be a film of a single layer to which a colorant is added. Further, a laminated film in which at least a resin layer formed of a thermosetting resin and a coloring agent layer are laminated may be used. In the case where the film 2 for the semiconductor back surface is a laminated film of a resin layer and a coloring agent layer, the film 2 for semiconductor back surface which is a laminated form preferably has a laminated form of a resin layer/colorant layer/resin layer. In this case, the two resin layers on both sides of the colorant layer may be a resin layer of the same composition or a resin layer of a different composition.

於半導體背面用膜2中,可根據需要適當地調配其他添加劑。作為其他添加劑,例如除了填充劑(填料)、阻燃劑、矽烷偶合劑、離子捕捉劑之外,亦可列舉增量劑、防老化劑、抗氧化劑、界面活性劑等。 In the film 2 for semiconductor back surface, other additives can be appropriately formulated as needed. As other additives, for example, in addition to a filler (filler), a flame retardant, a decane coupling agent, and an ion scavenger, an extender, an anti-aging agent, an antioxidant, a surfactant, and the like may be mentioned.

作為上述填充劑,無機填充劑、有機填充劑均可,較佳為無機填充劑。藉由無機填充劑等填充劑之調配,能夠對半導體背面用膜實現導電性之賦予或導熱性之提高、及彈性模數之調節等。再者,作為半導體背面用膜2,可為導電性,亦可為非導電性。作為上述無機填充劑,例如可列舉:二氧化矽、黏土、石膏、碳酸鈣、硫酸鋇、氧化鋁、氧化鈹、碳化矽、氮化矽等陶瓷類、鋁、銅、銀、金、鎳、鉻、鉛、錫、鋅、鈀、焊錫等金屬或合金類、及其他包含碳等之各種無機粉末等。填充劑可單獨使用或併用兩種以上。作為填充劑,其中適宜為二氧化矽、尤其是熔融二氧化矽。再者,無機填充劑之平均粒徑較佳為0.1μm~80μm之範圍內。無機填充劑之平均粒徑例如可藉由鐳射繞射型粒度分佈測定裝置而測定。 As the filler, an inorganic filler or an organic filler may be used, and an inorganic filler is preferable. By the preparation of a filler such as an inorganic filler, it is possible to impart conductivity, thermal conductivity, and adjustment of the elastic modulus to the film for semiconductor back surface. Further, the film 2 for semiconductor back surface may be electrically conductive or non-conductive. Examples of the inorganic filler include ceramics such as cerium oxide, clay, gypsum, calcium carbonate, barium sulfate, aluminum oxide, cerium oxide, cerium carbide, and cerium nitride, aluminum, copper, silver, gold, and nickel. Metals or alloys such as chromium, lead, tin, zinc, palladium, and solder, and various inorganic powders including carbon. The filler may be used singly or in combination of two or more. As the filler, suitable is cerium oxide, especially molten cerium oxide. Further, the average particle diameter of the inorganic filler is preferably in the range of 0.1 μm to 80 μm. The average particle diameter of the inorganic filler can be measured, for example, by a laser diffraction type particle size distribution measuring apparatus.

上述填充劑(尤其是無機填充劑)之調配量相對於有機樹脂成分100重量份,較佳為80重量份以下(0重量份~80重量份),尤其適宜為0重量份~70重量份。 The amount of the filler (particularly, the inorganic filler) is preferably 80 parts by weight or less (0 parts by weight to 80 parts by weight) based on 100 parts by weight of the organic resin component, and particularly preferably 0 parts by weight to 70 parts by weight.

作為上述阻燃劑,例如可列舉:三氧化銻、五氧化銻、溴化環氧樹脂等。阻燃劑可單獨使用或併用兩種以上。作為上述矽烷偶合劑,例如可列舉:β-(3,4-環氧基環己基)乙基三甲氧基矽烷、γ-縮水甘油氧基丙基三甲氧基矽烷、γ-縮水甘油氧基丙基甲基二乙氧基矽烷等。矽烷偶合劑可單獨使用或併用兩種以上。作為上述離子捕捉劑,例如可列舉:水滑石類、氫氧化鉍等。離子捕捉劑可單獨使用或併用兩種以上。 Examples of the flame retardant include antimony trioxide, antimony pentoxide, and brominated epoxy resin. The flame retardant may be used singly or in combination of two or more. Examples of the above decane coupling agent include β-(3,4-epoxycyclohexyl)ethyltrimethoxydecane, γ-glycidoxypropyltrimethoxydecane, and γ-glycidoxypropyl c. Methyl diethoxy decane, and the like. The decane coupling agent may be used singly or in combination of two or more. Examples of the ion trapping agent include hydrotalcites and barium hydroxide. The ion scavenger may be used singly or in combination of two or more.

半導體背面用膜2例如可利用以下之慣用方法形成:將環氧樹脂等熱硬化性樹脂、根據需要而使用之苯氧基樹脂、丙烯酸系樹脂等熱塑性樹脂、以及根據需要而添加之溶劑或其他添加劑等混合而製備樹脂組合物,並使其形成為膜狀之層。具體而言,例如可藉由以下方法形成作為半導體背面用膜之膜狀之層(接著劑層):將上述樹脂組合物塗佈於切晶帶之黏著劑層32上之方法;及於適當之分隔件(剝離紙等)上塗佈上述樹脂組合物而形成樹脂層(或接著劑層),並將其轉印(轉移)至黏著劑層32上之方法等。再者,上述樹脂組合物可為溶液,亦可為分散液。 The film 2 for semiconductor back surface can be formed, for example, by a thermoplastic resin such as an epoxy resin or the like, a thermoplastic resin such as a phenoxy resin or an acrylic resin which is used as needed, and a solvent or the like which is added as needed. The resin composition is prepared by mixing additives and the like, and is formed into a film-like layer. Specifically, for example, a film-form layer (adhesive layer) as a film for semiconductor back surface can be formed by applying the above resin composition to the adhesive layer 32 of the dicing tape; A method of forming a resin layer (or an adhesive layer) by applying the above resin composition to a separator (peeling paper or the like), transferring it (transfer) to the adhesive layer 32, and the like. Further, the above resin composition may be a solution or a dispersion.

再者,於半導體背面用膜2由含有環氧樹脂等熱硬化性樹脂之樹脂組合物形成之情形時,半導體背面用膜在適用於半導體晶圓前之階段中,熱硬化性樹脂為未硬化或部分硬化之狀態。於該情形時,在適用於半導體晶圓後(具體而言,通常是於在倒裝晶片接合步驟中使密封材料固化時),使半導體背面用膜中之熱硬化性樹脂完全或大致完全地硬化。 In the case where the film 2 for semiconductor back surface is formed of a resin composition containing a thermosetting resin such as an epoxy resin, the film for semiconductor back surface is uncured before being applied to the semiconductor wafer, and the thermosetting resin is uncured. Or partially hardened state. In this case, after being applied to the semiconductor wafer (specifically, usually when the sealing material is cured in the flip chip bonding step), the thermosetting resin in the film for semiconductor back surface is completely or substantially completely hardening.

如此,半導體背面用膜即使含有熱硬化性樹脂,該熱硬化性樹脂 亦為未硬化或部分硬化之狀態,因此作為半導體背面用膜之凝膠分率,並無特別限定,例如可自50重量%以下(0重量%~50重量%)之範圍內適當地選擇,較佳為30重量%以下(0重量%~30重量%),尤其適宜為10重量%以下(0重量%~10重量%)。半導體背面用膜之凝膠分率之測定方法可藉由以下之測定方法測定。 As described above, the film for semiconductor back surface contains a thermosetting resin, and the thermosetting resin The gel fraction of the film for semiconductor back surface is not particularly limited, and may be appropriately selected from the range of 50% by weight or less (0% by weight to 50% by weight), for example, in a state in which it is not hardened or partially cured. It is preferably 30% by weight or less (0% by weight to 30% by weight), and particularly preferably 10% by weight or less (0% by weight to 10% by weight). The method for measuring the gel fraction of the film for semiconductor back surface can be measured by the following measurement method.

<凝膠分率之測定方法> <Method for measuring gel fraction>

自半導體背面用膜取樣約0.1g並精確稱量(試樣之重量),將該樣品用網狀片材包住後,於室溫下浸漬於約50ml之甲苯中1週。然後,將溶劑不溶成分(網狀片材之內容物)自甲苯中取出,於130℃下乾燥約2小時,秤量乾燥後之溶劑不溶成分(浸漬.乾燥後之重量),由下述式(a)算出凝膠分率(重量%)。 A film of about 0.1 g was sampled from the back surface of the semiconductor and accurately weighed (weight of the sample), and the sample was wrapped in a mesh sheet, and then immersed in about 50 ml of toluene at room temperature for one week. Then, the solvent-insoluble component (the content of the mesh sheet) was taken out from the toluene, and dried at 130 ° C for about 2 hours, and the solvent-insoluble matter (impregnated. the weight after drying) after drying was weighed, and the following formula was used ( a) Calculate the gel fraction (% by weight).

凝膠分率(重量%)=[(浸漬.乾燥後之重量)/(試樣之重量)]×100(a) Gel fraction (% by weight) = [(impregnation. weight after drying) / (weight of sample)] × 100 (a)

再者,對於半導體背面用膜之凝膠分率,除了樹脂成分之種類或其含量、交聯劑之種類或其含量之外,亦可藉由加熱溫度或加熱時間等進行控制。 Further, the gel fraction of the film for semiconductor back surface can be controlled by heating temperature, heating time, etc., in addition to the kind of the resin component or the content thereof, the kind of the crosslinking agent, or the content thereof.

於第1本發明中,在半導體背面用膜為由含有環氧樹脂等熱硬化性樹脂之樹脂組合物形成之膜狀物之情形時,能夠有效地發揮對半導體晶圓之密接性。 In the first aspect of the invention, when the film for semiconductor back surface is a film formed of a resin composition containing a thermosetting resin such as an epoxy resin, the adhesion to the semiconductor wafer can be effectively exhibited.

再者,由於在半導體晶圓之切割步驟中使用切削水,因此存在半導體背面用膜吸濕而具有常態以上之含水率之情形。若於此種高含水率之狀態下進行倒裝晶片接合,則存在水蒸汽於半導體背面用膜2與半導體晶圓或其加工體(半導體)之接著界面聚集,而產生浮起之情形。因此,作為半導體背面用膜,藉由設為於兩面設置有高透濕性之芯材料之構成,可使水蒸汽擴散而避開上述問題。就上述觀點而言,亦可使用於芯材料之單面或兩面形成有半導體背面用膜2之多層結構 作為半導體背面用膜。作為上述芯材料,可列舉膜(例如聚醯亞胺膜、聚酯膜、聚對苯二甲酸乙二酯膜、聚萘二甲酸乙二酯膜、聚碳酸酯膜等)、經玻璃纖維或塑膠製不織纖維強化之樹脂基板、矽基板或玻璃基板等。 Further, since the cutting water is used in the dicing step of the semiconductor wafer, there is a case where the film for semiconductor back surface absorbs moisture and has a water content of a normal state or higher. When flip chip bonding is performed in such a high water content state, water vapor is accumulated on the interface between the semiconductor back surface film 2 and the semiconductor wafer or the processed body (semiconductor) to cause floating. Therefore, as a film for semiconductor back surface, by providing a core material having high moisture permeability on both surfaces, water vapor can be diffused to avoid the above problem. From the above viewpoints, a multilayer structure in which the film 2 for semiconductor back surface is formed on one side or both sides of the core material can also be used. As a film for semiconductor back surface. Examples of the core material include a film (for example, a polyimide film, a polyester film, a polyethylene terephthalate film, a polyethylene naphthalate film, a polycarbonate film, etc.), a glass fiber or A resin-made non-woven fiber-reinforced resin substrate, a ruthenium substrate, or a glass substrate.

半導體背面用膜2之厚度(積層膜之情形時為總厚度)並無特別限定,例如可自2μm~200μm左右之範圍內適當地選擇。進而,上述厚度較佳為4μm~160μm左右,更佳為6μm~100μm左右,尤佳為10μm~80μm左右。 The thickness of the film 2 for semiconductor back surface (the total thickness in the case of a laminated film) is not particularly limited, and can be appropriately selected, for example, in the range of about 2 μm to 200 μm. Further, the thickness is preferably about 4 μm to 160 μm, more preferably about 6 μm to 100 μm, and still more preferably about 10 μm to 80 μm.

上述半導體背面用膜2於未硬化狀態下的23℃下之拉伸儲存彈性模數較佳為1GPa以上(例如,1GPa~50GPa),更佳為2GPa以上,尤其適宜為3GPa以上。若上述拉伸儲存彈性模數為1GPa以上,則於將半導體元件與半導體背面用膜2一起自切晶帶之黏著劑層32剝離後,將半導體背面用膜2載置於支持體上並進行輸送等時,能夠有效地抑制或防止半導體背面用膜貼著於支持體。上述支持體例如係指載帶中之頂帶、底帶等。再者,於半導體背面用膜2係由含有熱硬化性樹脂之樹脂組合物形成之情形時,如上所述,由於熱硬化性樹脂通常為未硬化或部分硬化之狀態,因此半導體背面用膜於23℃下之彈性模數通常為熱硬化性樹脂於未硬化狀態或部分硬化狀態下之23℃下之彈性模數。 The tensile storage elastic modulus at 23 ° C in the uncured state of the film 2 for semiconductor back surface is preferably 1 GPa or more (for example, 1 GPa to 50 GPa), more preferably 2 GPa or more, and particularly preferably 3 GPa or more. When the tensile storage elastic modulus is 1 GPa or more, the semiconductor element and the semiconductor back surface film 2 are peeled off from the adhesive layer 32 of the dicing tape, and then the semiconductor back surface film 2 is placed on the support and carried out. When transporting or the like, it is possible to effectively suppress or prevent the film for semiconductor back surface from sticking to the support. The above support means, for example, a top tape, a bottom tape or the like in the carrier tape. In the case where the film 2 for semiconductor back surface is formed of a resin composition containing a thermosetting resin, as described above, since the thermosetting resin is usually in an unhardened or partially cured state, the film for semiconductor back surface is The modulus of elasticity at 23 ° C is usually the modulus of elasticity of the thermosetting resin at 23 ° C in an uncured state or a partially hardened state.

此處,半導體背面用膜2可為單層,亦可為複數層積層而成之積層膜,於為積層膜之情形時,只要上述未硬化狀態下之23℃下之拉伸儲存彈性模數對積層膜整體而言為1GPa以上(例如1GPa~50GPa)之範圍即可。又,半導體背面用膜之未硬化狀態下之上述拉伸儲存彈性模數(23℃)可藉由樹脂成分(熱塑性樹脂、熱硬化性樹脂)之種類或其含量、二氧化矽填料等填充材料之種類或其含量等進行控制。再者,於半導體背面用膜2為複數層積層而成之積層膜之情形時(半導體背面 用膜具有積層之形態之情形時),作為其積層形態,例如可例示包含晶圓接著層及鐳射標記層之積層形態等。又,於此種晶圓接著層與鐳射標記層之間,可設置其他層(中間層、光線阻斷層、加強層、著色層、基材層、電磁波阻斷層、導熱層、黏著層等)。再者,晶圓接著層為對晶圓發揮優異之密接性(接著性)之層,且為與晶圓之背面接觸之層。另一方面,鐳射標記層係發揮優異之鐳射標記性之層,且為於半導體元件之背面進行鐳射標記時所利用之層。 Here, the film 2 for semiconductor back surface may be a single layer or a laminated film formed by laminating a plurality of layers, and in the case of a laminated film, the tensile storage elastic modulus at 23 ° C in the uncured state described above may be used. The entire laminated film may be in the range of 1 GPa or more (for example, 1 GPa to 50 GPa). Further, the tensile storage elastic modulus (23 ° C) in the uncured state of the film for semiconductor back surface can be filled with a resin component (thermoplastic resin, thermosetting resin), a content thereof, or a filler such as a cerium oxide filler. The type or its content is controlled. In the case where the film 2 for semiconductor back surface is a laminated film in which a plurality of layers are laminated (semiconductor back side) In the case where the film has a laminated form, the laminated form including the wafer subsequent layer and the laser mark layer may be exemplified as the laminated form. Further, another layer (intermediate layer, light blocking layer, reinforcing layer, colored layer, substrate layer, electromagnetic wave blocking layer, heat conducting layer, adhesive layer, etc.) may be disposed between the wafer underlayer and the laser marking layer. ). Further, the wafer underlayer is a layer that exhibits excellent adhesion (adhesion) to the wafer and is a layer that is in contact with the back surface of the wafer. On the other hand, the laser marking layer is a layer that exhibits excellent laser marking properties and is used for laser marking on the back surface of the semiconductor element.

再者,上述拉伸儲存彈性模數設為以下之值:不積層於切晶帶3地製作未硬化狀態之半導體背面用膜2,使用Rheometric公司製造之動態黏彈性測定裝置「Solid Analyzer RS A2」,於拉伸模式下,在樣品寬度:10mm、樣品長度:22.5mm、樣品厚度:0.2mm、頻率:1Hz、升溫速度:10℃/min、氮氣氛圍下、特定之溫度(23℃)下之條件下測定而得之拉伸儲存彈性模數之值。 In addition, the tensile storage elastic modulus is a value of the following: a film for semiconductor back surface 2 in which an uncured state is not laminated in the dicing tape 3, and a dynamic viscoelasticity measuring device "Solid Analyzer RS A2" manufactured by Rheometric Co., Ltd. In the tensile mode, the sample width: 10 mm, sample length: 22.5 mm, sample thickness: 0.2 mm, frequency: 1 Hz, temperature increase rate: 10 ° C / min, nitrogen atmosphere, specific temperature (23 ° C) The value of the tensile storage elastic modulus obtained under the conditions of the measurement.

上述半導體背面用膜2較佳為至少一個面由分隔件(剝離襯墊)所保護(未圖示)。例如,於切晶帶一體型半導體背面用膜1之情形時,可僅於半導體背面用膜之一個面設置分隔件,另一方面,於未與切晶帶一體化之半導體背面用膜之情形時,可於半導體背面用膜之單面或兩面設置分隔件。分隔件於供於實際使用之前具有作為保護半導體背面用膜之保護材料之功能。又,於切晶帶一體型半導體背面用膜1之情形時,分隔件進而亦可作為將半導體背面用膜2轉印至切晶帶之基材上之黏著劑層32時之支持基材使用。分隔件於將半導體晶圓貼著於半導體背面用膜上時被剝離。作為分隔件,亦可使用藉由聚乙烯、聚丙烯、或氟系剝離劑、長鏈烷基丙烯酸酯系剝離劑等剝離劑進行表面塗佈之塑膠膜(聚對苯二甲酸乙二酯等)或紙等。再者,分隔件可藉由先前公知之方法形成。又,分隔件之厚度等亦無特別限定。 It is preferable that the film 2 for semiconductor back surface is protected by at least one surface by a separator (release liner) (not shown). For example, in the case of the film 1 for the dicing tape-integrated semiconductor back surface, the spacer may be provided only on one surface of the film for semiconductor back surface, and on the other hand, the film for semiconductor back surface which is not integrated with the dicing tape. In this case, a separator may be provided on one or both sides of the film for semiconductor back surface. The separator has a function as a protective material for protecting the film for semiconductor back surface before being used for practical use. Further, in the case of the film 1 for the dicing tape-integrated semiconductor back surface, the separator may be used as a supporting substrate when the film 2 for semiconductor back surface is transferred to the adhesive layer 32 on the substrate of the dicing tape. . The separator is peeled off when the semiconductor wafer is attached to the film for semiconductor back surface. As the separator, a plastic film (polyethylene terephthalate or the like) which is surface-coated with a release agent such as polyethylene, polypropylene, or a fluorine-based release agent or a long-chain alkyl acrylate release agent may be used. ) or paper, etc. Further, the separator can be formed by a previously known method. Further, the thickness of the separator or the like is not particularly limited.

又,半導體背面用膜2之可見光(波長:400nm~800nm)之光線 透射率(可見光透射率)並無特別限定,例如較佳為20%以下(0%~20%)之範圍,更佳為10%以下(0%~10%),尤佳為5%以下(0%~5%)。若半導體背面用膜2之可見光透射率大於20%,則存在由於光線通過而對半導體元件產生不良影響之虞。又,上述可見光透射率(%)可藉由半導體背面用膜2之樹脂成分之種類或其含量、著色劑(顏料或染料等)之種類或其含量、無機填充材料之含量等進行控制。 Further, the visible light (wavelength: 400 nm to 800 nm) of the film 2 for semiconductor back surface The transmittance (visible light transmittance) is not particularly limited, and is, for example, preferably 20% or less (0% to 20%), more preferably 10% or less (0% to 10%), and particularly preferably 5% or less ( 0%~5%). When the visible light transmittance of the film 2 for semiconductor back surface is more than 20%, there is a possibility that the semiconductor element is adversely affected by the passage of light. In addition, the visible light transmittance (%) can be controlled by the kind and content of the resin component of the film 2 for semiconductor back surface, the kind of the coloring agent (pigment, dye, etc.), the content, the content of the inorganic filler, and the like.

半導體背面用膜2之可見光透射率(%)可以如下方式測定。即,製作厚度(平均厚度)20μm之半導體背面用膜2單獨體。繼而,以特定之強度對半導體背面用膜2照射波長:400nm~800nm之可見光線[裝置:島津製作所製造之可見光產生裝置(商品名「ABSORPTION SPECTRO PHOTOMETR」)],測定透過之可見光線之強度。進而,根據可見光線透過半導體背面用膜2前後之強度變化,可求出可見光透射率之值。再者,亦可根據厚度並非為20μm之半導體背面用膜2之可見光透射率(%;波長:400nm~800nm)之值導出厚度20μm之半導體背面用膜2之可見光透射率(%;波長:400nm~800nm)。又,於第1本發明中,求出厚度20μm之半導體背面用膜2之情形時之可見光透射率(%),但其並非旨在將第1本發明之半導體背面用膜限定為厚度20μm者。 The visible light transmittance (%) of the film 2 for semiconductor back surface can be measured as follows. That is, a film 2 for semiconductor back surface having a thickness (average thickness) of 20 μm was produced as a single body. Then, the film 2 for semiconductor back surface is irradiated with visible light having a wavelength of 400 nm to 800 nm at a specific intensity [Device: visible light generating device (product name "ABSORPTION SPECTRO PHOTOMETR") manufactured by Shimadzu Corporation), and the intensity of visible light transmitted through is measured. Further, the value of the visible light transmittance can be obtained from the change in intensity before and after the visible light is transmitted through the film 2 for semiconductor back surface. Further, the visible light transmittance (%; wavelength: 400 nm) of the film 2 for semiconductor back surface having a thickness of 20 μm can be derived from the value of visible light transmittance (%; wavelength: 400 nm to 800 nm) of the film 2 for semiconductor back surface having a thickness of not 20 μm. ~800nm). Further, in the first aspect of the invention, the visible light transmittance (%) in the case of the film 2 for semiconductor back surface having a thickness of 20 μm is obtained, but the film for semiconductor back surface of the first invention is not intended to be limited to a thickness of 20 μm. .

又,作為半導體背面用膜2,較佳為其吸濕率較低者。具體而言,上述吸濕率較佳為1重量%以下,更佳為0.8重量%以下。藉由將上述吸濕率設為1重量%以下,能夠提高鐳射標記性。又,例如於回流焊步驟中,亦能夠抑制或防止於半導體背面用膜2與半導體元件之間產生孔隙等。又,上述吸濕率為根據將半導體背面用膜2於溫度85℃、相對濕度85%RH之氛圍下放置168小時前後之重量變化算出之值。於半導體背面用膜2係由含有熱硬化性樹脂之樹脂組合物形成之情形時,上述吸濕率係指對於熱硬化後之半導體背面用膜,於溫度85 ℃、相對濕度85%RH之氛圍下放置168小時之時之值。又,上述吸濕率例如可藉由改變無機填料之添加量而調整。 Moreover, as the film 2 for semiconductor back surface, it is preferable that the moisture absorption rate is low. Specifically, the moisture absorption rate is preferably 1% by weight or less, more preferably 0.8% by weight or less. By setting the moisture absorption rate to 1% by weight or less, the laser marking property can be improved. Further, for example, in the reflow soldering step, it is also possible to suppress or prevent generation of voids or the like between the semiconductor back surface film 2 and the semiconductor element. In addition, the moisture absorption rate is a value calculated based on the change in weight of the film 2 for semiconductor back surface in an atmosphere of a temperature of 85 ° C and a relative humidity of 85% RH for 168 hours. In the case where the film 2 for semiconductor back surface is formed of a resin composition containing a thermosetting resin, the moisture absorption rate means a film for semiconductor back surface after heat curing at a temperature of 85 The value is 168 hours at a temperature of °C and a relative humidity of 85% RH. Further, the moisture absorption rate can be adjusted, for example, by changing the amount of addition of the inorganic filler.

又,作為半導體背面用膜2,較佳為揮發成分之比率較少。具體而言,加熱處理後之半導體背面用膜2之重量減少率(重量減少量之比率)較佳為1重量%以下,更佳為0.8重量%以下。加熱處理之條件例如為加熱溫度250℃、加熱時間1小時。藉由將上述重量減少率設為1重量%以下,能夠提高鐳射標記性。又,例如於回流焊步驟中,能夠抑制或防止於倒裝晶片型之半導體裝置產生龜裂。上述重量減少率例如可藉由添加能夠減少無鉛回流焊時之龜裂產生之無機物進行調整。再者,於半導體背面用膜2係由含有熱硬化性樹脂之樹脂組合物形成之情形時,上述重量減少率係指對於熱硬化後之半導體背面用膜,於加熱溫度250℃、加熱時間1小時之條件下加熱時之值。 Moreover, as the film 2 for semiconductor back surface, it is preferable that the ratio of a volatile component is small. Specifically, the weight reduction ratio (ratio of the weight loss amount) of the film 2 for semiconductor back surface after the heat treatment is preferably 1% by weight or less, more preferably 0.8% by weight or less. The conditions of the heat treatment are, for example, a heating temperature of 250 ° C and a heating time of 1 hour. By setting the weight reduction rate to 1% by weight or less, the laser marking property can be improved. Further, for example, in the reflow soldering step, it is possible to suppress or prevent cracking in the flip chip type semiconductor device. The weight reduction rate can be adjusted, for example, by adding an inorganic substance which can reduce cracks generated during lead-free reflow soldering. In the case where the film 2 for semiconductor back surface is formed of a resin composition containing a thermosetting resin, the weight reduction ratio means a film for semiconductor back surface after heat curing at a heating temperature of 250 ° C and a heating time of 1 The value when heating under hours.

(切晶帶) (Cutting tape)

上述切晶帶3係於基材31上形成黏著劑層32而構成。如此,切晶帶3只要具有基材31與黏著劑層32積層而成之構成即可。基材(支持基材)可用作黏著劑層等之支持母體。上述基材31較佳為具有放射線透射性。作為上述基材31,例如可使用:紙等紙系基材;布、不織布、毛氈、網等纖維系基材;金屬箔、金屬板等金屬系基材;塑膠之膜或片材等塑膠系基材;橡膠片材等橡膠系基材;發泡片材等發泡體、或該等之積層體(尤其是塑膠系基材與其他基材之積層體、或塑膠膜(或片材)彼此之積層體等)等適當之薄層體。於第1本發明中,作為基材,可適宜地使用塑膠之膜或片材等塑膠系基材。作為此種塑膠材料之素材,例如可列舉:聚乙烯(PE)、聚丙烯(PP)、乙烯-丙烯共聚物等烯烴系樹脂;乙烯-乙酸乙烯酯共聚物(EVA)、離子聚合物樹脂、乙烯-(甲基)丙烯酸共聚物、乙烯-(甲基)丙烯酸酯(無規、交替)共聚物等將乙烯作為單體成分之共聚物;聚對苯二甲酸乙二酯(PET)、聚萘二甲 酸乙二酯(PEN)、聚對苯二甲酸丁二酯(PBT)等聚酯;丙烯酸系樹脂;聚氯乙烯(PVC);聚胺基甲酸酯;聚碳酸酯;聚苯硫醚(PPS);聚醯胺(尼龍)、全芳香族聚醯胺(聚芳醯胺)等醯胺系樹脂;聚醚醚酮(PEEK);聚醯亞胺;聚醚醯亞胺;聚偏二氯乙烯;ABS(丙烯腈-丁二烯-苯乙烯共聚物);纖維素系樹脂;聚矽氧樹脂;氟樹脂等。 The dicing tape 3 is formed by forming an adhesive layer 32 on the substrate 31. As described above, the dicing tape 3 may have a structure in which the base material 31 and the adhesive layer 32 are laminated. The substrate (support substrate) can be used as a support matrix for an adhesive layer or the like. The base material 31 preferably has radioelasticity. As the substrate 31, for example, a paper-based substrate such as paper; a fiber-based substrate such as a cloth, a nonwoven fabric, a felt, or a net; a metal-based substrate such as a metal foil or a metal plate; and a plastic film such as a film or a sheet of plastic can be used. a base material; a rubber base material such as a rubber sheet; a foam such as a foamed sheet, or a laminate (especially a laminate of a plastic base material and another base material, or a plastic film (or sheet)) Appropriate thin layer bodies such as laminates of each other. In the first aspect of the invention, a plastic substrate such as a plastic film or a sheet can be suitably used as the substrate. Examples of the material of the plastic material include an olefin resin such as polyethylene (PE), polypropylene (PP), or an ethylene-propylene copolymer; an ethylene-vinyl acetate copolymer (EVA), an ionic polymer resin, and the like. Ethylene-(meth)acrylic acid copolymer, ethylene-(meth)acrylate (random, alternating) copolymer, etc. copolymer of ethylene as a monomer component; polyethylene terephthalate (PET), poly Naphthalene Polyesters such as acid diethyl ester (PEN), polybutylene terephthalate (PBT); acrylic resin; polyvinyl chloride (PVC); polyurethane; polycarbonate; polyphenylene sulfide ( PPS); decylamine resin such as polyamine (nylon), wholly aromatic polyamine (polyarylamine); polyetheretherketone (PEEK); polyimine; polyether quinone; Vinyl chloride; ABS (acrylonitrile-butadiene-styrene copolymer); cellulose resin; polyoxyl resin; fluororesin, and the like.

又,作為基材31之材料,可列舉上述樹脂之交聯體等聚合物。上述塑膠膜可使用未延伸者,亦可使用根據需要而實施有單軸或雙軸之延伸處理者。根據藉由延伸處理等而賦予有熱收縮性之樹脂片材,可藉由在切割後使該基材31熱收縮而降低黏著劑層32與半導體背面用膜2之接著面積,實現半導體元件之回收之容易化。 Moreover, as a material of the base material 31, a polymer such as a crosslinked body of the above resin may be mentioned. The plastic film may be used without stretching, or may be subjected to a uniaxial or biaxial stretching treatment as needed. According to the resin sheet which is heat-shrinkable by the stretching treatment or the like, the semiconductor element can be reduced by thermally shrinking the substrate 31 after dicing to reduce the adhesion area between the adhesive layer 32 and the film 2 for semiconductor back surface. The recycling is easy.

為了提高與鄰接層之密接性、保持性等,基材31之表面可實施慣用之表面處理,例如鉻酸處理、臭氧暴露、火焰暴露、高壓電擊暴露、離子化放射線處理等化學性或物理性處理、及利用底塗劑(例如後述之黏著物質)之塗佈處理。 In order to improve adhesion to the adjacent layer, retention, etc., the surface of the substrate 31 can be subjected to conventional surface treatment such as chromic acid treatment, ozone exposure, flame exposure, high voltage electric shock exposure, ionizing radiation treatment, etc. The treatment and the coating treatment using a primer (for example, an adhesive substance to be described later).

上述基材31可適當地選擇同種或不同種者使用,根據需要可使用摻雜有數種者。又,對於基材31,為了賦予抗靜電能力,可於上述基材31上設置包含金屬、合金、該等之氧化物等之厚度為30~500Å左右之導電性物質之蒸鍍層。基材31可為單層或兩種以上之複層。 The substrate 31 may be appropriately selected from the same species or different species, and may be doped with several kinds as needed. Further, in order to impart antistatic ability to the base material 31, a vapor deposition layer containing a conductive material having a thickness of about 30 to 500 Å, such as a metal, an alloy, or the like, may be provided on the base material 31. The substrate 31 may be a single layer or a composite layer of two or more.

基材31之厚度(積層體之情形時為總厚度)並無特別限定,可根據強度或柔軟性、使用目的等適當地選擇,例如通常為1000μm以下(例如,1μm~1000μm),較佳為10μm~500μm,進而較佳為20μm~300μm,尤佳為30μm~200μm左右,但不限定於此。 The thickness of the substrate 31 (the total thickness in the case of the laminate) is not particularly limited, and may be appropriately selected depending on the strength, flexibility, purpose of use, etc., and is usually, for example, 1000 μm or less (for example, 1 μm to 1000 μm), preferably 10 μm to 500 μm, more preferably 20 μm to 300 μm, and particularly preferably 30 μm to 200 μm, but is not limited thereto.

再者,於基材31中,可於不損及第1本發明之效果等之範圍內含有各種添加劑(著色劑、填充材料、塑化劑、防老化劑、抗氧化劑、界面活性劑、阻燃劑等)。 Further, in the substrate 31, various additives (colorant, filler, plasticizer, anti-aging agent, antioxidant, surfactant, and resistance) can be contained within a range that does not impair the effects of the first aspect of the invention. Fuel, etc.).

上述黏著劑層32係藉由黏著劑形成,具有黏著性。作為此種黏著 劑,並無特別限定,可自公知之黏著劑中適當地選擇。具體而言,作為黏著劑,例如可自丙烯酸系黏著劑、橡膠系黏著劑、乙烯基烷基醚系黏著劑、聚矽氧系黏著劑、聚酯系黏著劑、聚醯胺系黏著劑、胺基甲酸酯系黏著劑、氟系黏著劑、苯乙烯-二烯嵌段共聚物系黏著劑、及於該等黏著劑中調配熔點為約200℃以下之熱熔融性樹脂而成之蠕變特性改良型黏著劑等公知之黏著劑(例如參照日本專利特開昭56-61468號公報、日本專利特開昭61-174857號公報、日本專利特開昭63-17981號公報、日本專利特開昭56-13040號公報等)中,適當地選擇具有上述特性之黏著劑使用。又,作為黏著劑,亦可使用放射線硬化型黏著劑(或能量射線硬化型黏著劑)、或熱膨脹性黏著劑。黏著劑可單獨使用或組合兩種以上使用。 The adhesive layer 32 is formed of an adhesive and has adhesiveness. As such adhesion The agent is not particularly limited and may be appropriately selected from known adhesives. Specifically, the adhesive may be, for example, an acrylic adhesive, a rubber adhesive, a vinyl alkyl ether adhesive, a polyoxynoxy adhesive, a polyester adhesive, or a polyamide adhesive. A urethane-based adhesive, a fluorine-based adhesive, a styrene-diene block copolymer-based adhesive, and a thermal-melting resin having a melting point of about 200 ° C or less in these adhesives A known adhesive such as a modified property-adjusting adhesive (for example, Japanese Patent Laid-Open Publication No. SHO 56-61468, Japanese Patent Laid-Open No. Hei 61-174857, Japanese Patent Laid-Open No. SHO63-17981, and Japanese Patent No. In the publication of Kai-kai No. 56-13040, etc., an adhesive having the above characteristics is appropriately selected and used. Further, as the adhesive, a radiation curable adhesive (or an energy ray-curable adhesive) or a heat-expandable adhesive can also be used. The adhesives may be used singly or in combination of two or more.

作為上述黏著劑,可適宜地使用丙烯酸系黏著劑、橡膠系黏著劑,尤其適宜為丙烯酸系黏著劑。作為丙烯酸系黏著劑,可列舉將使用(甲基)丙烯酸烷基酯之一種或兩種以上作為單體成分之丙烯酸系聚合物(均聚物或共聚物)作為基底聚合物之丙烯酸系黏著劑。 As the above-mentioned adhesive, an acrylic pressure-sensitive adhesive or a rubber-based pressure-sensitive adhesive can be suitably used, and an acrylic pressure-sensitive adhesive is particularly preferable. Examples of the acrylic adhesive include an acrylic adhesive (such as a homopolymer or a copolymer) using one or two or more kinds of alkyl (meth)acrylates as a monomer component as a base polymer. .

作為上述丙烯酸系黏著劑中之(甲基)丙烯酸烷基酯,例如可列舉:(甲基)丙烯酸甲酯、(甲基)丙烯酸乙酯、(甲基)丙烯酸丙酯、(甲基)丙烯酸異丙酯、(甲基)丙烯酸丁酯、(甲基)丙烯酸異丁酯、(甲基)丙烯酸第二丁酯、(甲基)丙烯酸第三丁酯、(甲基)丙烯酸戊酯、(甲基)丙烯酸己酯、(甲基)丙烯酸庚酯、(甲基)丙烯酸辛酯、(甲基)丙烯酸2-乙基己酯、(甲基)丙烯酸異辛酯、(甲基)丙烯酸壬酯、(甲基)丙烯酸異壬酯、(甲基)丙烯酸癸酯、(甲基)丙烯酸異癸酯、(甲基)丙烯酸十一烷基酯、(甲基)丙烯酸十二烷基酯、(甲基)丙烯酸十三烷基酯、(甲基)丙烯酸十四烷基酯、(甲基)丙烯酸十五烷基酯、(甲基)丙烯酸十六烷基酯、(甲基)丙烯酸十七烷基酯、(甲基)丙烯酸十八烷基酯、(甲基)丙烯酸十九烷基酯、(甲基)丙烯酸二十烷基酯等(甲基)丙烯酸 烷基酯等。作為(甲基)丙烯酸烷基酯,適宜為烷基之碳數為4~18之(甲基)丙烯酸烷基酯。再者,(甲基)丙烯酸烷基酯之烷基為直鏈狀或支鏈狀均可。 Examples of the (meth)acrylic acid alkyl ester in the acrylic pressure-sensitive adhesive include methyl (meth)acrylate, ethyl (meth)acrylate, propyl (meth)acrylate, and (meth)acrylic acid. Isopropyl ester, butyl (meth)acrylate, isobutyl (meth)acrylate, second butyl (meth)acrylate, tert-butyl (meth)acrylate, amyl (meth)acrylate, Methyl)hexyl acrylate, heptyl (meth)acrylate, octyl (meth)acrylate, 2-ethylhexyl (meth)acrylate, isooctyl (meth)acrylate, bismuth (meth)acrylate Esters, isodecyl (meth)acrylate, decyl (meth)acrylate, isodecyl (meth)acrylate, undecyl (meth)acrylate, dodecyl (meth)acrylate, Tridecyl (meth)acrylate, tetradecyl (meth)acrylate, pentadecyl (meth)acrylate, cetyl (meth)acrylate, (meth)acrylic acid (meth)acrylic acid, such as heptayl ester, octadecyl (meth) acrylate, pentadecyl (meth) acrylate, eicosyl (meth) acrylate Alkyl esters and the like. The alkyl (meth)acrylate is preferably an alkyl (meth)acrylate having an alkyl group having 4 to 18 carbon atoms. Further, the alkyl group of the (meth)acrylic acid alkyl ester may be linear or branched.

再者,上述丙烯酸系聚合物亦可以凝聚力、耐熱性、交聯性等之改質為目的,而根據需要含有能與上述(甲基)丙烯酸烷基酯共聚合之其他單體成分(共聚性單體成分)所對應之單元。作為此種共聚性單體成分,例如可列舉:(甲基)丙烯酸(丙烯酸、甲基丙烯酸)、丙烯酸羧基乙酯、丙烯酸羧基戊酯、伊康酸、順丁烯二酸、反丁烯二酸、丁烯酸等含羧基之單體;順丁烯二酸酐、伊康酸酐等含酸酐基之單體;(甲基)丙烯酸羥基乙酯、(甲基)丙烯酸羥基丙酯、(甲基)丙烯酸羥基丁酯、(甲基)丙烯酸羥基己酯、(甲基)丙烯酸羥基辛酯、(甲基)丙烯酸羥基癸酯、(甲基)丙烯酸羥基月桂酯、甲基丙烯酸(4-羥基甲基環己基)甲酯等含羥基之單體;苯乙烯磺酸、烯丙基磺酸、2-(甲基)丙烯醯胺-2-甲基丙磺酸、(甲基)丙烯醯胺丙磺酸、(甲基)丙烯酸磺丙酯、(甲基)丙烯醯氧基萘磺酸等含磺酸基之單體;2-羥基乙基丙烯醯基磷酸酯等含磷酸基之單體;(甲基)丙烯醯胺、N,N-二甲基(甲基)丙烯醯胺、N-丁基(甲基)丙烯醯胺、N-羥甲基(甲基)丙烯醯胺、N-羥甲基丙烷(甲基)丙烯醯胺等(N-取代)醯胺系單體;(甲基)丙烯酸胺基乙酯、(甲基)丙烯酸N,N-二甲基胺基乙酯、(甲基)丙烯酸第三丁基胺基乙酯等(甲基)丙烯酸胺基烷基酯系單體;(甲基)丙烯酸甲氧基乙酯、(甲基)丙烯酸乙氧基乙酯等(甲基)丙烯酸烷氧基烷基酯系單體;丙烯腈、甲基丙烯腈等氰基丙烯酸酯單體;(甲基)丙烯酸縮水甘油酯等含環氧基之丙烯酸系單體;苯乙烯、α-甲基苯乙烯等苯乙烯系單體;乙酸乙烯酯、丙酸乙烯酯等乙烯酯系單體;異戊二烯、丁二烯、異丁烯等烯烴系單體;乙烯醚等乙烯醚系單體;N-乙烯基吡咯烷酮、甲基乙烯基吡咯烷酮、乙烯基吡啶、乙烯基哌啶酮、乙烯基嘧啶、乙烯基哌、 乙烯基吡、乙烯基吡咯、乙烯基咪唑、乙烯基唑、乙烯基啉、N-乙烯基羧醯胺類、N-乙烯基己內醯胺等含氮單體;N-環己基順丁烯二醯亞胺、N-異丙基順丁烯二醯亞胺、N-月桂基順丁烯二醯亞胺、N-苯基順丁烯二醯亞胺等順丁烯二醯亞胺系單體;N-甲基伊康醯亞胺、N-乙基伊康醯亞胺、N-丁基伊康醯亞胺、N-辛基伊康醯亞胺、N-2-乙基己基伊康醯亞胺、N-環己基伊康醯亞胺、N-月桂基伊康醯亞胺等伊康醯亞胺系單體;N-(甲基)丙烯醯氧基亞甲基琥珀醯亞胺、N-(甲基)丙烯醯基-6-氧基六亞甲基琥珀醯亞胺、N-(甲基)丙烯醯基-8-氧基八亞甲基琥珀醯亞胺等琥珀醯亞胺系單體;聚乙二醇(甲基)丙烯酸酯、聚丙二醇(甲基)丙烯酸酯、甲氧基乙二醇(甲基)丙烯酸酯、甲氧基聚丙二醇(甲基)丙烯酸酯等二醇系丙烯酸酯單體;(甲基)丙烯酸四氫糠酯、氟(甲基)丙烯酸酯、聚矽氧(甲基)丙烯酸酯等具有雜環、鹵素原子、矽原子等之丙烯酸酯系單體;己二醇二(甲基)丙烯酸酯、(聚)乙二醇二(甲基)丙烯酸酯、(聚)丙二醇二(甲基)丙烯酸酯、新戊二醇二(甲基)丙烯酸酯、季戊四醇二(甲基)丙烯酸酯、三羥甲基丙烷三(甲基)丙烯酸酯、季戊四醇三(甲基)丙烯酸酯、二季戊四醇六(甲基)丙烯酸酯、環氧丙烯酸酯、聚酯丙烯酸酯、丙烯酸胺基甲酸酯、二乙烯苯、丁基二(甲基)丙烯酸酯、己基二(甲基)丙烯酸酯等多官能單體等。該等共聚性單體成分可使用一種或兩種以上。 Further, the acrylic polymer may be modified for cohesive force, heat resistance, crosslinkability, etc., and may contain other monomer components copolymerizable with the above (meth)acrylic acid alkyl ester (copolymerization), if necessary. The unit corresponding to the monomer component). Examples of such a copolymerizable monomer component include (meth)acrylic acid (acrylic acid, methacrylic acid), carboxyethyl acrylate, carboxy amyl acrylate, itaconic acid, maleic acid, and antibutene. a carboxyl group-containing monomer such as acid or crotonic acid; an acid anhydride group-containing monomer such as maleic anhydride or itaconic anhydride; hydroxyethyl (meth)acrylate; hydroxypropyl (meth)acrylate; Hydroxybutyl acrylate, hydroxyhexyl (meth) acrylate, hydroxyoctyl (meth) acrylate, hydroxy decyl (meth) acrylate, hydroxylauryl (meth) acrylate, methacrylic acid (4-hydroxymethyl) Hydroxyl-containing monomer such as cyclohexyl)methyl ester; styrenesulfonic acid, allylsulfonic acid, 2-(methyl)acrylamido-2-methylpropanesulfonic acid, (meth)acrylamide a sulfonic acid group-containing monomer such as sulfonic acid, sulfopropyl (meth) acrylate, (meth) propylene phthaloxy naphthalene sulfonic acid or the like; a phosphate group-containing monomer such as 2-hydroxyethyl acryl decyl phosphate; (Meth) acrylamide, N,N-dimethyl(meth) acrylamide, N-butyl(meth) acrylamide, N-methylol (meth) acrylamide, N- Hydroxymethylpropane (methyl) (N-substituted) guanamine monomer such as ketamine; aminoethyl (meth) acrylate, N, N-dimethylaminoethyl (meth) acrylate, third butyl (meth) acrylate Aminoalkyl (meth) acrylate monomer such as arylaminoethyl ester; (meth)acrylic acid alkoxylate such as methoxyethyl (meth)acrylate or ethoxyethyl (meth)acrylate Alkyl ester monomer; cyanoacrylate monomer such as acrylonitrile or methacrylonitrile; epoxy group-containing acrylic monomer such as glycidyl (meth)acrylate; styrene, α-methylstyrene a styrene monomer; a vinyl ester monomer such as vinyl acetate or vinyl propionate; an olefin monomer such as isoprene, butadiene or isobutylene; a vinyl ether monomer such as vinyl ether; N-ethylene Pyrrolidone, methylvinylpyrrolidone, vinylpyridine, vinylpiperidone, vinylpyrimidine, vinylpiper Vinyl pyridyl , vinyl pyrrole, vinyl imidazole, vinyl Azole, vinyl Nitrogen-containing monomers such as porphyrin, N-vinyl carbamide, N-vinyl caprolactam, N-cyclohexyl maleimide, N-isopropyl maleimide, a maleimide-based monomer such as N-lauryl maleimide or N-phenyl maleimide; N-methyl Ikonide, N-ethyl Coconine, N-butyl Ikonide, N-octyl Icinoimine, N-2-ethylhexylkkonium imine, N-cyclohexylkkonium imine, N- Ikonideimine monomer such as lauryl ikonium imine; N-(methyl) propylene oxymethylene succinimide, N-(methyl) propylene fluorenyl-6-oxy-6 Amber quinone imine monomer such as methylene succinimide or N-(methyl) propylene decyl-8-oxy octamethylene succinimide; polyethylene glycol (meth) acrylate, a glycol-based acrylate monomer such as polypropylene glycol (meth) acrylate, methoxyethylene glycol (meth) acrylate or methoxy polypropylene glycol (meth) acrylate; tetrahydroanthracene (meth) acrylate Acrylates having a heterocyclic ring, a halogen atom, a ruthenium atom or the like, such as an ester, a fluorine (meth) acrylate or a polyfluorene (meth) acrylate Monomer; hexanediol di(meth)acrylate, (poly)ethylene glycol di(meth)acrylate, (poly)propylene glycol di(meth)acrylate, neopentyl glycol di(meth)acrylic acid Ester, pentaerythritol di(meth)acrylate, trimethylolpropane tri(meth)acrylate, pentaerythritol tri(meth)acrylate, dipentaerythritol hexa(meth)acrylate, epoxy acrylate, polyester A polyfunctional monomer such as acrylate, urethane acrylate, divinyl benzene, butyl di(meth) acrylate or hexyl di(meth) acrylate. These copolymerizable monomer components may be used alone or in combination of two or more.

於使用放射線硬化型黏著劑(或能量射線硬化型黏著劑)作為黏著劑之情形時,作為放射線硬化型黏著劑(組合物),例如可列舉將於聚合物側鏈或者主鏈中或主鏈末端具有自由基反應性碳-碳雙鍵之聚合物用作基底聚合物之內在型之放射線硬化型黏著劑、或於黏著劑中調配有紫外線硬化性之單體成分或低聚物成分之放射線硬化型黏著劑等。又,於使用熱膨脹性黏著劑作為黏著劑之情形時,作為熱膨脹性黏著劑,例如可列舉含有黏著劑及發泡劑(尤其是熱膨脹性微小球)之 熱膨脹性黏著劑等。 When a radiation curable adhesive (or energy ray hardening type adhesive) is used as the adhesive, the radiation curable adhesive (composition) may, for example, be in the side chain or main chain of the polymer or the main chain. A polymer having a radical-reactive carbon-carbon double bond at the end and used as an intrinsic type of radiation-curable adhesive for a base polymer or a radiation-curable monomer component or oligomer component in an adhesive Hardening type adhesives, etc. In the case of using a heat-expandable pressure-sensitive adhesive as an adhesive, examples of the heat-expandable pressure-sensitive adhesive include an adhesive and a foaming agent (especially, heat-expandable microspheres). Heat-expandable adhesive, etc.

於第1本發明中,在黏著劑層32中,可於無損第1本發明之效果之範圍內含有各種添加劑(例如,黏著賦予樹脂、著色劑、增稠劑、增量劑、填充材料、塑化劑、防老化劑、抗氧化劑、界面活性劑、交聯劑等)。 In the first aspect of the invention, various additives (for example, an adhesion-imparting resin, a coloring agent, a thickener, an extender, a filler, and the like) can be contained in the adhesive layer 32 within the range in which the effects of the first invention are not impaired. Plasticizers, anti-aging agents, antioxidants, surfactants, cross-linking agents, etc.).

作為上述交聯劑,並無特別限定,可使用公知之交聯劑。具體而言,作為交聯劑,除了異氰酸酯系交聯劑、環氧系交聯劑、三聚氰胺系交聯劑、過氧化物系交聯劑之外,可列舉脲系交聯劑、金屬烷氧化物系交聯劑、金屬螯合物系交聯劑、金屬鹽系交聯劑、碳二醯亞胺系交聯劑、唑啉系交聯劑、氮丙啶系交聯劑、胺系交聯劑等,適宜為異氰酸酯系交聯劑或環氧系交聯劑。交聯劑可單獨使用或組合兩種以上使用。再者,交聯劑之使用量並無特別限定。 The crosslinking agent is not particularly limited, and a known crosslinking agent can be used. Specifically, the crosslinking agent includes, in addition to the isocyanate crosslinking agent, the epoxy crosslinking agent, the melamine crosslinking agent, and the peroxide crosslinking agent, a urea crosslinking agent and a metal alkoxide. a substance crosslinking agent, a metal chelate crosslinking agent, a metal salt crosslinking agent, a carbon diimide crosslinking agent, The oxazoline crosslinking agent, the aziridine crosslinking agent, and the amine crosslinking agent are preferably an isocyanate crosslinking agent or an epoxy crosslinking agent. The crosslinking agent may be used singly or in combination of two or more. Further, the amount of the crosslinking agent used is not particularly limited.

作為上述異氰酸酯系交聯劑,例如可列舉:1,2-伸乙基二異氰酸酯、1,4-伸丁基二異氰酸酯、1,6-六亞甲基二異氰酸酯等低級脂肪族聚異氰酸酯類;伸環戊基二異氰酸酯、伸環己基二異氰酸酯、異佛爾酮二異氰酸酯、氫化甲苯二異氰酸酯、氫化二甲苯二異氰酸酯等脂環族聚異氰酸酯類;2,4-甲苯二異氰酸酯、2,6-甲苯二異氰酸酯、4,4'-二苯基甲烷二異氰酸酯、苯二甲基二異氰酸酯等芳香族聚異氰酸酯類等,此外亦可使用三羥甲基丙烷/甲苯二異氰酸酯三聚物加成物[Nippon Polyurethane Industry股份有限公司製造,商品名「CORONATE L」]、三羥甲基丙烷/六亞甲基二異氰酸酯三聚物加成物[Nippon Polyurethane Industry股份有限公司製造,商品名「CORONATE HL」]等。又,作為上述環氧系交聯劑,例如可列舉:N,N,N',N'-四縮水甘油基-間苯二甲胺、二縮水甘油基苯胺、1,3-雙(N,N-縮水甘油基胺基甲基)環己烷、1,6-己二醇二縮水甘油醚、新戊二醇二縮水甘油醚、乙二醇二縮水甘油醚、丙二醇二縮水甘油醚、聚 乙二醇二縮水甘油醚、聚丙二醇二縮水甘油醚、山梨糖醇聚縮水甘油醚、甘油聚縮水甘油醚、季戊四醇聚縮水甘油醚、聚甘油聚縮水甘油醚、山梨糖醇酐聚縮水甘油醚、三羥甲基丙烷聚縮水甘油醚、己二酸二縮水甘油酯、鄰苯二甲酸二縮水甘油酯、三(2-羥基乙基)異氰脲酸三縮水甘油酯、間苯二酚二縮水甘油醚、雙酚S-二縮水甘油醚,此外可列舉於分子內具有2個以上環氧基之環氧系樹脂等。 Examples of the isocyanate crosslinking agent include lower aliphatic polyisocyanates such as 1,2-ethylidene diisocyanate, 1,4-butylene diisocyanate, and 1,6-hexamethylene diisocyanate; Cycloaliphatic diisocyanate, cyclohexyl diisocyanate, isophorone diisocyanate, hydrogenated toluene diisocyanate, hydrogenated xylene diisocyanate and other alicyclic polyisocyanates; 2,4-toluene diisocyanate, 2,6- An aromatic polyisocyanate such as toluene diisocyanate, 4,4'-diphenylmethane diisocyanate or benzodimethyl diisocyanate, or a trimethylolpropane/toluene diisocyanate trimer adduct may be used. Nippon Polyurethane Industry Co., Ltd., trade name "CORONATE L"], trimethylolpropane / hexamethylene diisocyanate trimer adduct [manufactured by Nippon Polyurethane Industry Co., Ltd., trade name "CORONATE HL"] Wait. Moreover, examples of the epoxy-based crosslinking agent include N, N, N', N'-tetraglycidyl-m-xylylenediamine, diglycidylaniline, and 1,3-bis(N, N-glycidylaminomethyl)cyclohexane, 1,6-hexanediol diglycidyl ether, neopentyl glycol diglycidyl ether, ethylene glycol diglycidyl ether, propylene glycol diglycidyl ether, poly Ethylene glycol diglycidyl ether, polypropylene glycol diglycidyl ether, sorbitol polyglycidyl ether, glycerol polyglycidyl ether, pentaerythritol polyglycidyl ether, polyglycerol polyglycidyl ether, sorbitan polyglycidyl ether , trimethylolpropane polyglycidyl ether, diglycidyl adipate, diglycidyl phthalate, tris(2-hydroxyethyl) isocyanuric acid triglycidyl ester, resorcinol The glycidyl ether and the bisphenol S-diglycidyl ether are exemplified by an epoxy resin having two or more epoxy groups in the molecule.

再者,於第1本發明中,可代替使用交聯劑或者於使用交聯劑之同時藉由電子束或紫外線等之照射實施交聯處理。 Further, in the first aspect of the invention, the crosslinking treatment may be carried out by irradiation with an electron beam or ultraviolet rays instead of using a crosslinking agent or by using a crosslinking agent.

黏著劑層32例如可利用下述慣用之方法形成:將黏著劑(感壓接著劑)、及根據需要而添加之溶劑或其他添加劑等加以混合,並使其形成為片狀之層。具體而言,例如可藉由以下方法形成黏著劑層32:將含有黏著劑以及根據需要而添加之溶劑或其他添加劑之混合物塗佈於基材31上之方法;及於適當之分隔件(剝離紙等)上塗佈上述混合物而形成黏著劑層32,並將其轉印(轉移)至基材31上之方法等。 The adhesive layer 32 can be formed, for example, by a usual method of mixing an adhesive (pressure-sensitive adhesive), a solvent or other additives added as needed, and forming a sheet-like layer. Specifically, for example, the adhesive layer 32 can be formed by applying a mixture containing an adhesive and a solvent or other additive added as needed to the substrate 31; and a suitable separator (peeling) A method of forming the adhesive layer 32 by applying the above mixture to paper, etc., and transferring (transferring) the same to the substrate 31.

黏著劑層32之厚度並無特別限定,例如為5μm~300μm(較佳為5μm~200μm,進而較佳為5μm~100μm,尤佳為7μm~50μm)左右。若黏著劑層32之厚度為上述範圍內,則能夠發揮適度之黏著力。再者,黏著劑層32為單層、複層均可。 The thickness of the adhesive layer 32 is not particularly limited, and is, for example, about 5 μm to 300 μm (preferably 5 μm to 200 μm, more preferably 5 μm to 100 μm, and particularly preferably 7 μm to 50 μm). When the thickness of the adhesive layer 32 is within the above range, an appropriate adhesive force can be exhibited. Further, the adhesive layer 32 may be a single layer or a multiple layer.

上述切晶帶3之黏著劑層32相對於半導體背面用膜2之接著力(23℃,剝離角度180度,剝離速度300mm/min)較佳為0.02N/20mm~10N/20mm之範圍,更佳為0.05N/20mm~5N/20mm之範圍。藉由將上述接著力設為0.02N/20mm以上,能夠防止於切割半導體晶圓時半導體元件產生晶片飛出。另一方面,藉由將上述接著力設為10N/20mm以下,能夠防止於拾取半導體元件時該半導體元件之剝離變得困難或者產生糊劑殘餘。 The adhesion force of the adhesive layer 32 of the dicing tape 3 to the film 2 for semiconductor back surface is preferably in the range of 0.02 N/20 mm to 10 N/20 mm with respect to the adhesion force (23 ° C, peeling angle of 180 degrees, peeling speed of 300 mm/min) of the film 2 for semiconductor back surface. Good range of 0.05N/20mm~5N/20mm. By setting the above-described adhesion force to 0.02 N/20 mm or more, it is possible to prevent the wafer from flying out of the semiconductor element when the semiconductor wafer is diced. On the other hand, by setting the above-described adhesion force to 10 N/20 mm or less, it is possible to prevent peeling of the semiconductor element from being difficult or to cause paste residue when the semiconductor element is picked up.

又,半導體背面用膜2或切晶帶一體型半導體背面用膜1可以捲繞 成輥狀之形態形成,亦可以片材(膜)積層而成之形態形成。例如,於具有捲繞成輥狀之形態之情形時,可將半導體背面用膜2、或半導體背面用膜2與切晶帶3之積層體於根據需要藉由分隔件進行保護之狀態下捲繞成輥狀,而製作為捲繞成輥狀之狀態或形態之半導體背面用膜2或切晶帶一體型半導體背面用膜1。再者,作為捲繞成輥狀之狀態或形態之切晶帶一體型半導體背面用膜1,可由基材31、形成於上述基材31之一個面之黏著劑層32、形成於上述黏著劑層32上之半導體背面用膜、以及形成於上述基材31之另一個面之剝離處理層(背面處理層)構成。 Further, the film 2 for semiconductor back surface or the film 1 for dicing tape-integrated semiconductor back surface can be wound It is formed in the form of a roll, and may be formed in a form in which a sheet (film) is laminated. For example, in the case of having a form of being wound into a roll, the film for semiconductor back surface 2, or the laminate of the film 2 for semiconductor back surface and the diced tape 3 can be wound by a separator as needed. The film 2 for semiconductor back surface or the film 1 for dicing tape-integrated semiconductor back surface in a state or a form of being wound into a roll is formed in a roll shape. Further, the film-integrated semiconductor back surface film 1 in a state or a form of being wound into a roll may be formed of the substrate 31, an adhesive layer 32 formed on one surface of the substrate 31, and the adhesive. The film for semiconductor back surface on the layer 32 and the release treatment layer (back surface treatment layer) formed on the other surface of the base material 31 are comprised.

再者,作為切晶帶一體型半導體背面用膜1之厚度(半導體背面用膜之厚度與包含基材31及黏著劑層32之切晶帶之厚度之總厚度),例如可自8μm~1500μm之範圍內選擇,較佳為20μm~850μm(進而較佳為31μm~500μm,尤佳為47μm~330μm)。 In addition, the thickness of the film 1 for the dicing tape-integrated semiconductor back surface (the thickness of the film for the semiconductor back surface and the total thickness of the thickness of the dicing tape including the substrate 31 and the adhesive layer 32) may be, for example, from 8 μm to 1500 μm. The range is preferably from 20 μm to 850 μm (and more preferably from 31 μm to 500 μm, particularly preferably from 47 μm to 330 μm).

再者,於切晶帶一體型半導體背面用膜1中,藉由控制半導體背面用膜2之厚度與切晶帶3之黏著劑層32之厚度之比、或半導體背面用膜2之厚度與切晶帶3之厚度(基材31與黏著劑層32之總厚度)之比,能夠提高切割步驟時之切割性、拾取步驟時之拾取性等,而能夠於半導體晶圓之切割步驟~半導體元件(例如,半導體晶片)之倒裝晶片接合步驟中有效地利用切晶帶一體型半導體背面用膜1。 Further, in the film 1 for dicing tape-integrated semiconductor back surface, the ratio of the thickness of the film 2 for semiconductor back surface to the thickness of the adhesive layer 32 of the dicing tape 3 or the thickness of the film 2 for semiconductor back surface is controlled. The ratio of the thickness of the dicing tape 3 (the total thickness of the substrate 31 to the adhesive layer 32) can improve the cutting property in the cutting step, the pick-up property in the picking step, and the like, and can be performed in the semiconductor wafer cutting step to the semiconductor The dicing tape-integrated film 1 for semiconductor back surface is effectively utilized in the flip chip bonding step of an element (for example, a semiconductor wafer).

(切晶帶一體型半導體背面用膜之製造方法) (Manufacturing method of film for dicing tape integrated semiconductor back surface)

對於本實施形態之切晶帶一體型半導體背面用膜之製造方法,以圖1所示之切晶帶一體型半導體背面用膜1為例進行說明。首先,基材31可藉由先前公知之製膜方法而製膜。此時,於基材31中含有抗靜電劑之情形時,適當地於基材形成用材料中預先添加抗靜電劑。作為該製膜方法,例如可例示:壓延製膜法、於有機溶劑中之澆鑄法、於密閉體系中之吹脹擠出法、T模擠出法、共擠出法、乾式層壓法等。 In the method for producing a film for a dicing tape-integrated semiconductor back surface of the present embodiment, the film 1 for dicing tape-integrated semiconductor back surface shown in FIG. 1 will be described as an example. First, the substrate 31 can be formed into a film by a conventionally known film forming method. In this case, when the antistatic agent is contained in the substrate 31, an antistatic agent is appropriately added to the material for forming the substrate. Examples of the film forming method include a calender film forming method, a casting method in an organic solvent, an inflation extrusion method in a closed system, a T-die extrusion method, a co-extrusion method, a dry lamination method, and the like. .

繼而,於基材31上塗佈黏著劑組合物,使其乾燥(根據需要使其加熱交聯)而形成黏著劑層32。此時,於黏著劑層32中含有抗靜電劑之情形時,適當地於黏著劑組合物中預先添加抗靜電劑。作為塗佈方式,可列舉輥塗覆、絲網塗覆、凹版塗覆等。再者,可將黏著劑層組合物直接塗佈於基材31,而於基材31上形成黏著劑層32,又,亦可將黏著劑組合物塗佈於表面進行了剝離處理之剝離紙等而形成黏著劑層32,然後將該黏著劑層32轉印至基材31。藉此,製作於基材31上形成有黏著劑層32之切晶帶3。 Then, the adhesive composition is applied onto the substrate 31, dried (heated and crosslinked as needed) to form the adhesive layer 32. At this time, when the antistatic agent is contained in the adhesive layer 32, an antistatic agent is appropriately added to the adhesive composition in advance. As a coating method, roll coating, screen coating, gravure coating, etc. are mentioned. Further, the adhesive layer composition may be directly applied to the substrate 31 to form the adhesive layer 32 on the substrate 31, or the adhesive composition may be applied to the surface of the release paper which has been subjected to the release treatment. The adhesive layer 32 is formed, and then the adhesive layer 32 is transferred to the substrate 31. Thereby, the dicing tape 3 in which the adhesive layer 32 was formed on the base material 31 was produced.

另一方面,將用於形成半導體背面用膜2之形成材料以乾燥後之厚度成為特定厚度之方式塗佈於剝離紙上,進而於特定條件下進行乾燥(於必需熱硬化之情形等時,根據需要實施加熱處理並乾燥)而形成塗佈層。此時,於半導體背面用膜2中含有抗靜電劑之情形時,適當地於用於形成半導體背面用膜2之形成材料中預先添加抗靜電劑。藉由將該塗佈層轉印至上述黏著劑層32上,而於黏著劑層32上形成半導體背面用膜2。再者,亦可於上述黏著劑層32上直接塗佈用於形成半導體背面用膜2之形成材料,然後於特定條件下進行乾燥(於必需熱硬化之情形等時,根據需要實施加熱處理並乾燥),藉此於黏著劑層32上形成半導體背面用膜2。於將半導體背面用膜2設為多層結構且於任一個最外層中含有抗靜電劑之情形時,較佳為於含有抗靜電劑之最外層上形成黏著劑層32。藉由上述操作,可獲得第1本發明之切晶帶一體型半導體背面用膜1。再者,於形成半導體背面用膜2時進行熱硬化之情形時,在成為部分硬化之狀態之程度上進行熱硬化較為重要,但較佳為不進行熱硬化。 On the other hand, the material for forming the film for semiconductor back surface 2 is applied to the release paper so that the thickness after drying becomes a specific thickness, and further dried under specific conditions (in the case of necessity of heat hardening, etc., according to It is necessary to carry out heat treatment and drying to form a coating layer. In the case where the antistatic agent is contained in the film 2 for semiconductor back surface, an antistatic agent is appropriately added to the material for forming the film for semiconductor back surface 2 in advance. The film for semiconductor back surface 2 is formed on the adhesive layer 32 by transferring the coating layer onto the above-mentioned adhesive layer 32. Further, a material for forming the film for semiconductor back surface 2 may be directly applied onto the above-mentioned adhesive layer 32, and then dried under specific conditions (in the case where heat hardening is necessary, etc., heat treatment is performed as needed Drying), the film 2 for semiconductor back surface is formed on the adhesive layer 32. When the film 2 for semiconductor back surface is formed into a multilayer structure and an antistatic agent is contained in any of the outermost layers, it is preferred to form the adhesive layer 32 on the outermost layer containing the antistatic agent. According to the above operation, the film-forming integrated semiconductor back surface film 1 of the first aspect of the invention can be obtained. In the case where the film for semiconductor back surface 2 is thermally cured, it is important to perform thermal hardening to the extent that it is partially cured, but it is preferable not to perform thermal hardening.

第1本發明之切晶帶一體型半導體背面用膜1可於包含倒裝晶片接合步驟之半導體裝置之製造時適宜地使用。即,第1本發明之切晶帶一體型半導體背面用膜1於製造倒裝晶片安裝之半導體裝置時使用, 於半導體元件之背面貼著有切晶帶一體型半導體背面用膜1之半導體背面用膜2之狀態或形態下,製造倒裝晶片安裝之半導體裝置。因此,第1本發明之切晶帶一體型半導體背面用膜1可對倒裝晶片安裝之半導體裝置(半導體元件以倒裝晶片接合方式固定於基板等被黏著體之狀態或形態之半導體裝置)使用。 The film-integrated semiconductor back surface film 1 of the first aspect of the invention can be suitably used in the production of a semiconductor device including a flip chip bonding step. In other words, the film 1 for dicing tape-integrated semiconductor back surface of the first aspect of the present invention is used in the manufacture of a flip-chip mounted semiconductor device. A flip-chip mounted semiconductor device is manufactured in a state or a form in which the film for semiconductor back surface 2 of the film-integrated semiconductor back surface film 1 is bonded to the back surface of the semiconductor element. Therefore, the dicing tape-integrated semiconductor back surface film 1 of the present invention can be used for flip-chip mounted semiconductor devices (semiconductor devices in which the semiconductor elements are fixed by flip-chip bonding to a state or form of an adherend such as a substrate) use.

(半導體晶圓) (semiconductor wafer)

作為半導體晶圓,只要為公知或慣用之半導體晶圓,則並無特別限定,可自各種素材之半導體晶圓中適當地選擇使用。於第1本發明中,作為半導體晶圓,可適宜地使用矽晶圓。 The semiconductor wafer is not particularly limited as long as it is a known or conventional semiconductor wafer, and can be appropriately selected from semiconductor wafers of various materials. In the first aspect of the invention, a germanium wafer can be suitably used as the semiconductor wafer.

(半導體裝置之製造方法) (Method of Manufacturing Semiconductor Device)

第1本發明之半導體裝置之製造方法為至少包含以下步驟之半導體裝置之製造方法:於上述切晶帶一體型接著片材中之接著片材上貼著半導體晶圓之步驟;切割上述半導體晶圓而形成半導體元件之步驟;以及將上述半導體元件與上述接著片材一起自切晶帶之黏著劑層拾取之步驟。 A method of manufacturing a semiconductor device according to the first aspect of the present invention is the method of manufacturing a semiconductor device comprising at least the step of: attaching a semiconductor wafer to a subsequent sheet in the dicing tape-integrated sheet; and cutting the semiconductor crystal a step of forming a semiconductor element in a circle; and a step of picking up the semiconductor element from the adhesive layer of the dicing tape together with the above-mentioned succeeding sheet.

尤其是,於第1本發明之接著片材為半導體背面用膜之情形時,上述半導體裝置之製造方法至少包含以下步驟:於上述切晶帶一體型半導體背面用膜上貼著半導體晶圓之背面之步驟;切割上述半導體晶圓之步驟;拾取藉由切割所得之半導體元件之步驟;以及將上述半導體元件倒裝晶片連接於被黏著體上之步驟。 In particular, in the case where the adhesive sheet of the first aspect of the invention is a film for semiconductor back surface, the method for manufacturing the semiconductor device includes at least the step of: attaching a semiconductor wafer to the film for the dicing tape-integrated semiconductor back surface a step of backing; a step of cutting the semiconductor wafer; a step of picking up the obtained semiconductor element; and a step of flip-chip bonding the semiconductor element to the adherend.

以下,一面參照圖5一面對本實施形態之半導體裝置之製造方法進行說明。圖5為表示使用本實施形態之切晶帶一體型半導體背面用膜1之半導體裝置之製造方法之一例之剖面模式圖。 Hereinafter, a method of manufacturing a semiconductor device of the present embodiment will be described with reference to FIG. 5. FIG. 5 is a cross-sectional schematic view showing an example of a method of manufacturing a semiconductor device using the dicing tape-integrated semiconductor back surface film 1 of the present embodiment.

[貼裝(mount)步驟] [mounting step]

首先,如圖5之(a)所示,將任意設置於切晶帶一體型半導體背面用膜1之半導體背面用膜2上之分隔件適當地剝離,於該半導體背面用 膜2上貼著半導體晶圓4,使其保持接著並固定(貼裝步驟)。此時,上述半導體背面用膜2處於未硬化狀態(包括半硬化狀態)。又,切晶帶一體型半導體背面用膜1貼著於半導體晶圓4之背面。所謂半導體晶圓4之背面,係指與電路面相反側之面(亦稱為非電路面、非電極形成面等)。貼著方法並無特別限定,較佳為利用壓接之方法。壓接通常係藉由壓接輥等按壓機構一面按壓一面進行。 First, as shown in FIG. 5(a), the separator which is arbitrarily provided on the film 2 for semiconductor back surface of the film for dicing tape-integrated semiconductor back surface 1 is appropriately peeled off, and is used for the back surface of the semiconductor. The semiconductor wafer 4 is attached to the film 2 to be held and fixed (mounting step). At this time, the film 2 for semiconductor back surface is in an uncured state (including a semi-hardened state). Further, the film-integrated semiconductor back surface film 1 is placed on the back surface of the semiconductor wafer 4. The back surface of the semiconductor wafer 4 is a surface opposite to the circuit surface (also referred to as a non-circuit surface, a non-electrode forming surface, etc.). The bonding method is not particularly limited, and it is preferably a method using pressure bonding. The crimping is usually performed while pressing the pressing mechanism such as a pressure roller.

[切割步驟] [Cutting step]

繼而,如圖5之(b)所示,進行半導體晶圓4之切割。藉此,將半導體晶圓4切斷成特定之尺寸而實現單片化(小片化),製造作為半導體元件之半導體晶片5。切割係於使切晶帶3真空吸附於吸附台110之狀態下,例如自半導體晶圓4之電路面側依據常法進行。又,於本步驟中,例如可採用將切入進行至切晶帶一體型半導體背面用膜1之被稱為全切(full cut)之切斷方式等。作為於本步驟中使用之切割裝置,並無特別限定,可使用先前公知者。又,由於半導體晶圓4以更優異之密接性接著固定於包含半導體背面用膜之切晶帶一體型半導體背面用膜1,因此能夠抑制晶片缺損或晶片飛出,並且亦能夠抑制半導體晶圓4之破損。再者,若半導體背面用膜2係由含有環氧樹脂之樹脂組合物形成,則即使藉由切割被切斷,亦能夠抑制或防止於其切斷面產生半導體背面用膜之接著劑層之糊劑滲出。其結果,能夠抑制或防止切斷面彼此再附著(黏連),而可進一步良好地進行後述之拾取。 Then, as shown in FIG. 5(b), the semiconductor wafer 4 is cut. Thereby, the semiconductor wafer 4 is cut into a specific size to achieve singulation (small piece), and the semiconductor wafer 5 as a semiconductor element is manufactured. The cutting is performed in a state where the dicing tape 3 is vacuum-adsorbed to the adsorption stage 110, for example, from the circuit surface side of the semiconductor wafer 4 in accordance with a conventional method. Moreover, in this step, for example, a cutting method called a full cut which cuts into the film 1 for the dicing tape-integrated semiconductor back surface can be used. The cutting device used in this step is not particularly limited, and those known in the prior art can be used. In addition, since the semiconductor wafer 4 is then fixed to the film-integrated semiconductor back surface film 1 including the film for semiconductor back surface with more excellent adhesion, it is possible to suppress wafer defects or wafer flying out, and it is also possible to suppress semiconductor wafers. 4 damage. In addition, when the film 2 for semiconductor back surface is formed of a resin composition containing an epoxy resin, it is possible to suppress or prevent the occurrence of an adhesive layer of a film for semiconductor back surface on the cut surface thereof even if it is cut by dicing. The paste oozes out. As a result, it is possible to suppress or prevent the cut surfaces from reattaching (adhesion) to each other, and the pick-up described later can be performed more satisfactorily.

再者,於進行切晶帶一體型半導體背面用膜1之擴展之情形時,該擴展可使用先前公知之擴展裝置進行。擴展裝置包含:可經由切割環將切晶帶一體型半導體背面用膜1向下方壓下之甜甜圈狀之外環;及直徑小於外環且支持切晶帶一體型半導體背面用膜之內環。藉由該擴展步驟,於後述之拾取步驟中,能夠防止相鄰之半導體晶片彼此接觸而破損。 Further, in the case of expanding the film 1 for the dicing tape-integrated semiconductor back surface, the expansion can be carried out using a previously known expansion device. The expansion device includes a doughnut-shaped outer ring that can be pressed downward by the dicing tape-integrated semiconductor back surface film 1 through a dicing ring, and a film having a diameter smaller than the outer ring and supporting the dicing tape-integrated semiconductor back surface film. ring. By this expansion step, it is possible to prevent adjacent semiconductor wafers from coming into contact with each other and being damaged in the pickup step described later.

[拾取步驟] [pickup step]

為了回收接著固定於切晶帶一體型半導體背面用膜1之半導體晶片5,如圖5之(c)所示,進行半導體晶片5之拾取,將半導體晶片5與半導體背面用膜2一起自切晶帶3剝離。作為拾取之方法,並無特別限定,可採用先前公知之各種方法。例如可列舉自切晶帶一體型半導體背面用膜1之基材31側,將各個半導體晶片5藉由頂針上頂,並藉由拾取裝置拾取被上頂之半導體晶片5之方法等。再者,被拾取之半導體晶片5之背面由半導體背面用膜2所保護。 In order to recover the semiconductor wafer 5 which is then fixed to the dicing tape-integrated semiconductor back surface film 1, as shown in FIG. 5(c), the semiconductor wafer 5 is picked up, and the semiconductor wafer 5 and the semiconductor back surface film 2 are self-cut. The ribbon 3 is peeled off. The method of picking up is not particularly limited, and various methods known in the prior art can be employed. For example, a method of picking up the semiconductor wafer 5 that has been topped by the pick-up device from the side of the substrate 31 of the film-integrated semiconductor back surface film 1 and the top of each of the semiconductor wafers 5 by the ejector is mentioned. Further, the back surface of the semiconductor wafer 5 to be picked up is protected by the film 2 for semiconductor back surface.

[倒裝晶片連接步驟] [Flip Chip Connection Step]

如圖5之(d)所示,所拾取之半導體晶片5藉由倒裝晶片接合方式(倒裝晶片安裝方式)固定於基板等被黏著體。具體而言,依據常法,使半導體晶片5以半導體晶片5之電路面(亦稱為表面、電路圖案形成面、電極形成面等)與被黏著體6相對之形態固定於被黏著體6。例如,使形成於半導體晶片5之電路面側之凸塊51與被黏著於被黏著體6之連接焊墊之接合用之導電材料(焊錫等)61接觸,一面按壓一面使導電材料熔融,藉此可確保半導體晶片5與被黏著體6之電氣導通,能夠將半導體晶片5固定於被黏著體6(倒裝晶片接合步驟)。此時,於半導體晶片5與被黏著體6之間形成有空隙,該空隙間距離一般為30μm~300μm左右。再者,於將半導體晶片5倒裝晶片接合(倒裝晶片連接)於被黏著體6上後,重要的是清洗半導體晶片5與被黏著體6之相對面或間隙,並向該間隙填充密封材料(密封樹脂等)而進行密封。 As shown in FIG. 5(d), the picked-up semiconductor wafer 5 is fixed to an adherend such as a substrate by flip chip bonding (flip-chip mounting). Specifically, the semiconductor wafer 5 is fixed to the adherend 6 by a circuit surface (also referred to as a surface, a circuit pattern forming surface, an electrode forming surface, and the like) of the semiconductor wafer 5 so as to face the adherend 6 in accordance with a conventional method. For example, the bump 51 formed on the circuit surface side of the semiconductor wafer 5 is brought into contact with a conductive material (solder or the like) 61 to be bonded to the bonding pad of the adherend 6, and the conductive material is melted while being pressed. This ensures electrical conduction between the semiconductor wafer 5 and the adherend 6, and the semiconductor wafer 5 can be fixed to the adherend 6 (flip-chip bonding step). At this time, a gap is formed between the semiconductor wafer 5 and the adherend 6, and the distance between the gaps is generally about 30 μm to 300 μm. Further, after flip-chip bonding (flip-chip bonding) of the semiconductor wafer 5 onto the adherend 6, it is important to clean the opposite surface or gap of the semiconductor wafer 5 and the adherend 6, and fill the gap with the gap. The material (sealing resin, etc.) is sealed.

作為被黏著體6,可使用引線框架或電路基板(配線電路基板等)等各種基板。作為此種基板之材質,並無特別限定,可列舉陶瓷基板或塑膠基板。作為塑膠基板,例如可列舉環氧基板、雙順丁烯二醯亞胺三基板、聚醯亞胺基板等。 As the adherend 6, various substrates such as a lead frame or a circuit board (such as a printed circuit board) can be used. The material of such a substrate is not particularly limited, and examples thereof include a ceramic substrate and a plastic substrate. As the plastic substrate, for example, an epoxy substrate or a bis-xenylene diimide III can be cited. A substrate, a polyimide substrate, or the like.

於倒裝晶片接合步驟中,作為凸塊或導電材料之材質,並無特別 限定,例如可列舉:錫-鉛系金屬材、錫-銀系金屬材、錫-銀-銅系金屬材、錫-鋅系金屬材、錫-鋅-鉍系金屬材等焊錫類(合金)、或金系金屬材、銅系金屬材等。 In the flip chip bonding step, there is no special material for the bump or conductive material. Examples of the limitation include tin-lead metal materials, tin-silver metal materials, tin-silver-copper metal materials, tin-zinc metal materials, and tin-zinc-bismuth metal materials such as solders (alloys). Or gold-based metal materials, copper-based metal materials, and the like.

再者,於倒裝晶片接合步驟中,將導電材料熔融,使半導體晶片5之電路面側之凸塊與被黏著體6之表面之導電材料連接,作為該導電材料之熔融時之溫度,通常為260℃左右(例如,250℃~300℃)。第1本發明之切晶帶一體型半導體背面用膜藉由利用環氧樹脂等形成半導體背面用膜,能夠形成具有亦可耐受該倒裝晶片接合步驟中之高溫之耐熱性者。 Further, in the flip chip bonding step, the conductive material is melted to connect the bump on the circuit surface side of the semiconductor wafer 5 to the conductive material on the surface of the adherend 6, as the temperature at which the conductive material is melted, usually It is about 260 ° C (for example, 250 ° C ~ 300 ° C). In the film for a semiconductor back surface of the dicing tape-integrated semiconductor of the first aspect of the invention, a film for semiconductor back surface can be formed by using an epoxy resin or the like, and a heat resistance which can withstand the high temperature in the flip chip bonding step can be formed.

於本步驟中,較佳為進行半導體晶片5與被黏著體6之相對面(電極形成面)或間隙之清洗。作為該清洗所使用之清洗液,並無特別限定,例如可列舉有機系之清洗液、或水系之清洗液。第1本發明之切晶帶一體型半導體背面用膜之半導體背面用膜具有對清洗液之耐溶劑性,對於該等清洗液基本上不具有溶解性。因此,如上所述,作為清洗液,可使用各種清洗液,無需特別之清洗液,可藉由先前之方法進行清洗。 In this step, cleaning of the opposite surface (electrode forming surface) or gap of the semiconductor wafer 5 and the adherend 6 is preferably performed. The cleaning liquid used for the cleaning is not particularly limited, and examples thereof include an organic cleaning liquid or a water cleaning liquid. The film for semiconductor back surface of the film for dicing tape-integrated semiconductor back surface of the first aspect of the present invention has solvent resistance to a cleaning liquid, and has substantially no solubility to the cleaning liquid. Therefore, as described above, various cleaning liquids can be used as the cleaning liquid, and no special cleaning liquid is required, and the cleaning can be performed by the conventional method.

繼而,進行用於將經倒裝晶片接合之半導體晶片5與被黏著體6之間之間隙密封之密封步驟。密封步驟使用密封樹脂進行。作為此時之密封條件,並無特別限定,通常藉由在175℃下進行60秒~90秒之加熱而進行密封樹脂之熱硬化,但第1本發明不限定於此,例如可以165℃~185℃進行數分鐘固化。此時,由於半導體背面用膜2相對於半導體背面用膜2整體含有70重量%以上之無機填充材料,因此拉伸儲存彈性模數相對較高。其結果,能夠有效地抑制或防止於密封樹脂之熱硬化時可能產生之半導體晶片之翹曲。又,藉由該步驟,可使半導體背面用膜2完全或大致完全地熱硬化,能夠以優異之密接性貼著於半導體晶片之背面。進而,第1本發明之半導體背面用膜2即使為未硬化 狀態,亦能夠於該密封步驟時與密封材料一起熱硬化,因此無需重新追加用於使半導體背面用膜2熱硬化之步驟。 Then, a sealing step for sealing the gap between the wafer wafer 5 bonded by the flip chip and the adherend 6 is performed. The sealing step is performed using a sealing resin. The sealing condition at this time is not particularly limited, and the sealing resin is usually thermally cured by heating at 175 ° C for 60 seconds to 90 seconds. However, the first invention is not limited thereto, and may be, for example, 165 ° C. Curing was carried out at 185 ° C for several minutes. At this time, since the film 2 for semiconductor back surface contains 70% by weight or more of the inorganic filler with respect to the entire film 2 for semiconductor back surface, the tensile storage elastic modulus is relatively high. As a result, it is possible to effectively suppress or prevent warpage of the semiconductor wafer which may occur when the sealing resin is thermally hardened. Moreover, by this step, the film 2 for semiconductor back surface can be completely or substantially completely thermally cured, and can be adhered to the back surface of the semiconductor wafer with excellent adhesion. Further, the film 2 for semiconductor back surface of the first invention is uncured even if it is The state can also be thermally hardened together with the sealing material at the sealing step, so that it is not necessary to newly add a step for thermally hardening the film 2 for semiconductor back surface.

作為上述密封樹脂,只要為具有絕緣性之樹脂(絕緣樹脂),則並無特別限定,可自公知之密封樹脂等密封材料中適當地選擇使用,更佳為具有彈性之絕緣樹脂。作為密封樹脂,例如可列舉含有環氧樹脂之樹脂組合物等。作為環氧樹脂,可列舉上述例示之環氧樹脂等。又,作為由含有環氧樹脂之樹脂組合物構成之密封樹脂,樹脂成分除了環氧樹脂以外,亦可含有環氧樹脂以外之熱硬化性樹脂(酚樹脂等)或熱塑性樹脂等。再者,作為酚樹脂,亦可作為環氧樹脂之硬化劑使用,作為此種酚樹脂,可列舉上述例示之酚樹脂等。 The sealing resin is not particularly limited as long as it is an insulating resin (insulating resin), and can be appropriately selected from known sealing materials such as a sealing resin, and more preferably an insulating resin having elasticity. The sealing resin may, for example, be a resin composition containing an epoxy resin. Examples of the epoxy resin include the epoxy resins exemplified above. In addition, the resin component may contain a thermosetting resin (such as a phenol resin) other than an epoxy resin or a thermoplastic resin, in addition to the epoxy resin, in addition to the epoxy resin. In addition, the phenol resin can also be used as a curing agent for an epoxy resin, and examples of such a phenol resin include the above-exemplified phenol resins.

使用上述切晶帶一體型半導體背面用膜1所製造之半導體裝置(倒裝晶片安裝之半導體裝置)由於在半導體晶片之背面貼著有半導體背面用膜,因此能夠以優異之視認性施加各種標記。尤其是,即使標記方法為鐳射標記方法,亦能夠以優異之對比度施加標記,可良好地視認藉由鐳射標記施加之各種資訊(文字資訊、圖研資訊等)。再者,於進行鐳射標記時,可利用公知之鐳射標記裝置。又,作為鐳射,可利用氣體鐳射、固體鐳射、液體鐳射等各種鐳射。具體而言,作為氣體鐳射,並無特別限定,可利用公知之氣體鐳射,適宜為二氧化碳鐳射(CO2鐳射)、準分子鐳射(ArF鐳射、KrF鐳射、XeCl鐳射、XeF鐳射等)。又,作為固體鐳射,並無特別限定,可利用公知之固體鐳射,適宜為YAG鐳射(Nd:YAG鐳射等)、YVO4鐳射。 In the semiconductor device (flip-chip mounted semiconductor device) manufactured by using the dicing tape-integrated semiconductor back surface film 1 described above, a film for semiconductor back surface is adhered to the back surface of the semiconductor wafer, so that various marks can be applied with excellent visibility. . In particular, even if the marking method is a laser marking method, it is possible to apply a mark with excellent contrast, and it is possible to satisfactorily recognize various kinds of information (text information, graphic research information, and the like) applied by the laser mark. Further, a known laser marking device can be used for laser marking. Further, as the laser, various kinds of lasers such as gas laser, solid laser, and liquid laser can be used. Specifically, the gas laser is not particularly limited, and a known gas laser can be used, and it is preferably carbon dioxide laser (CO 2 laser) or excimer laser (ArF laser, KrF laser, XeCl laser, XeF laser, or the like). Further, the solid laser is not particularly limited, and a known solid laser can be used, and it is preferably YAG laser (Nd: YAG laser or the like) or YVO 4 laser.

使用第1本發明之切晶帶一體型半導體背面用膜或半導體背面用膜所製造之半導體裝置係以倒裝晶片安裝方式安裝之半導體裝置,因此與以黏晶(die bonding)安裝方式安裝之半導體裝置相比,形成為更薄型化、小型化之形狀。因此,可作為各種電子設備.電子零件或該等之材料.構件適宜地使用。具體而言,作為利用第1本發明之倒裝晶 片安裝之半導體裝置之電子設備,可列舉:所謂之「行動電話」或「PHS」(Personal Handy-phone System,個人手持式電話系統)、小型電腦(例如,所謂之「PDA」(個人數位助理)、所謂之「筆記型電腦」、所謂之「Netbook(商標)」、所謂之「隨身電腦」(wearable computer)等)、「行動電話」及電腦一體化而成之小型之電子設備、所謂之「數位相機(商標)」、所謂之「數位視訊攝影機」、小型之電視、小型之遊戲機、小型之數位影音播放器、所謂之「電子記事本」、所謂之「電子辭典」、所謂之「電子書」用電子設備終端、小型之數位型之鐘錶等移動型之電子設備(可攜帶之電子設備)等,當然亦可為移動型以外(設置型等)之電子設備(例如,所謂之「桌上型個人電腦」、薄型電視、錄像-播放用電子設備(硬碟記錄器(hard disk recorder)、DVD播放器等)、投影儀、微機械等)等。又,作為電子零件、或電子設備.電子零件之材料.構件,例如可列舉所謂之「CPU」(Central Processing Unit,中央處理單元)之構件、各種記憶裝置(所謂之「記憶體」、硬碟等)之構件等。 The semiconductor device manufactured by using the dicing tape-integrated semiconductor back surface film or the semiconductor back surface film of the first aspect of the invention is a flip-chip mounted semiconductor device, and thus is mounted by die bonding. Compared with a semiconductor device, it is formed into a shape that is thinner and smaller. Therefore, it can be used as a variety of electronic devices. Electronic parts or such materials. The member is suitably used. Specifically, as a flip chip using the first invention The electronic devices of the semiconductor device mounted on the chip include a so-called "mobile phone" or "PHS" (Personal Handy-phone System), and a small computer (for example, a so-called "PDA" (personal digital assistant) ), the so-called "notebook computer", the so-called "Netbook (trademark)", the so-called "wearable computer" (wearable computer), etc., the "mobile phone" and the computer integrated small electronic device, so-called "Digital Cameras (Trade Marks)", so-called "Digital Video Cameras", small TVs, small game consoles, small digital video players, so-called "electronic notebooks", so-called "electronic dictionaries", so-called " For electronic books, electronic devices such as electronic device terminals and small digital watches (portable electronic devices), etc., of course, electronic devices other than mobile devices (such as setting type) (for example, so-called " A desktop personal computer, a thin television, a video-playback electronic device (hard disk recorder, a DVD player, etc.), a projector, a micromachine, etc.). Also, as an electronic part, or an electronic device. Material for electronic parts. The members include, for example, members of a so-called "CPU" (Central Processing Unit), members of various memory devices (so-called "memory", hard disk, etc.).

於上述實施形態中,對第1本發明之接著片材為倒裝晶片型半導體背面用膜2之情形進行了說明,但第1本發明之接著片材不限定於該例。作為第1本發明之接著片材,只要為能夠形成於切晶帶上而使用者,則並無特別限定,例如可列舉黏晶膜或底部填充片材。 In the above embodiment, the case where the subsequent sheet of the first invention is the film for flip chip type semiconductor back surface 2 has been described. However, the sheet of the first invention is not limited to this example. The back sheet of the first aspect of the invention is not particularly limited as long as it can be formed on the dicing tape, and examples thereof include a die bond film or an underfill sheet.

於第1本發明之接著片材為黏晶膜之情形時,可於將組成或含量變更至具有作為黏晶膜之功能之程度之基礎上,採用與上述倒裝晶片型半導體背面用膜同樣之構成。又,關於半導體裝置之製造方法,代替上述倒裝晶片連接步驟,而進行經由黏晶膜將半導體元件(例如,半導體晶片)向被黏著體進行黏晶之步驟,除此以外,與使用切晶帶一體型半導體背面用膜1之半導體裝置之製造方法相同。即,使用切晶帶一體型黏晶膜之半導體裝置之製造方法包含以下步驟:於切晶帶 一體型黏晶膜之黏晶膜上貼著半導體晶圓之步驟;切割上述半導體晶圓而形成半導體元件之步驟;將上述半導體元件與上述黏晶膜一起自切晶帶之黏著劑層拾取之步驟;以及經由上述黏晶膜將半導體元件向被黏著體進行黏晶之步驟。 In the case where the adhesive sheet of the first invention is a die-bonding film, the composition or content can be changed to have a function as a die-bonding film, and the film can be used in the same manner as the above-mentioned film for flip chip type semiconductor back surface. The composition. Further, in the method of manufacturing a semiconductor device, instead of the above-described flip chip bonding step, a step of performing die bonding of a semiconductor element (for example, a semiconductor wafer) to an adherend via an adhesive film is performed, and The manufacturing method of the semiconductor device with the integrated film 1 for semiconductor back surface is the same. That is, a method of manufacturing a semiconductor device using a dicing tape-integrated die-bonding film includes the following steps: in a dicing tape a step of attaching a semiconductor wafer to the die-bonding film of the integrated die-bonding film; and cutting the semiconductor wafer to form a semiconductor component; and picking up the semiconductor component together with the die-bonding film from the adhesive layer of the dicing tape a step of: bonding the semiconductor element to the adherend via the above-mentioned die film;

又,於第1本發明之接著片材為底部填充片材之情形時,可於將組成或含量變更至具有作為底部填充片材之功能之程度之基礎上,採用與上述倒裝晶片型半導體背面用膜同樣之構成。又,關於半導體裝置之製造方法,於上述貼裝步驟中,代替將作為切晶帶一體型接著片材之切晶帶一體型半導體背面用膜1貼著於半導體晶圓之背面,而將作為切晶帶一體型接著片材之切晶帶一體型底部填充片材貼著於半導體晶圓之電路面側,除此以外,與使用切晶帶一體型半導體背面用膜1之半導體裝置之製造方法相同。即,使用切晶帶一體型底部填充片材之半導體裝置之製造方法包含以下步驟:於切晶帶一體型底部填充片材之底部填充片材上貼著半導體晶圓之電路面側之步驟;切割上述半導體晶圓而形成半導體元件之步驟;將上述半導體元件與上述底部填充片材一起自切晶帶之黏著劑層拾取之步驟;以及將半導體元件於介存上述底部填充片材之狀態下倒裝晶片連接於被黏著體上之步驟。 Further, in the case where the succeeding sheet of the first invention is an underfill sheet, the flip chip type semiconductor can be used in addition to changing the composition or content to have a function as an underfill sheet. The film for the back surface is similarly constructed. In the mounting method of the semiconductor device, the dicing tape-integrated semiconductor back surface film 1 as a dicing tape-integrated sheet is placed on the back surface of the semiconductor wafer instead of the dicing tape-integrated sheet. Manufacture of a semiconductor device using a dicing tape-integrated semiconductor back surface film 1 in addition to the dicing tape-integrated underfill sheet of the dicing tape-integrated sheet. The method is the same. That is, a method of manufacturing a semiconductor device using a dicing tape-integrated underfill sheet includes the steps of: attaching a circuit surface side of a semiconductor wafer to an underfill sheet of a diced tape-integrated underfill sheet; a step of cutting the semiconductor wafer to form a semiconductor element; a step of picking up the semiconductor element from the adhesive layer of the dicing tape together with the underfill sheet; and placing the semiconductor element in the state of depositing the underfill sheet The step of flip chip bonding to the adherend.

<第2本發明> <2nd invention>

以下,關於第2本發明之實施形態,對與第1本發明不同之方面進行說明。第2本發明之切晶帶一體型接著片材除了特別於本第2本發明之項中進行了說明以外,可與第1本發明設為同樣之構成。因此,省略與第1本發明共通之部分之說明。 Hereinafter, an embodiment different from the first invention will be described with respect to the second embodiment of the present invention. The diced tape-integrated sheet of the second aspect of the present invention can be configured in the same manner as in the first aspect of the invention, except that it is described in particular in the second aspect of the invention. Therefore, the description of the parts common to the first invention will be omitted.

(切晶帶一體型半導體背面用膜) (Cutting tape integrated semiconductor back surface film)

作為第2本發明之切晶帶一體型半導體背面用膜之實施形態(以下,亦稱為第2實施形態),可列舉與第1本發明之切晶帶一體型半導體背面用膜之實施形態同樣之構成,即,如圖1所示之切晶帶一體型 半導體背面用膜1。由於切晶帶一體型半導體背面用膜1之層構成於第1本發明之項中進行了說明,因此此處省略說明。 The embodiment of the dicing tape-integrated semiconductor back surface film of the second aspect of the invention (hereinafter, also referred to as the second embodiment), and the embodiment of the dicing tape-integrated semiconductor back surface film of the first aspect of the invention The same structure, that is, the dicing tape integrated type as shown in FIG. Film 1 for semiconductor back surface. Since the layer structure of the film 1 for the dicing tape-integrated semiconductor back surface has been described in the first aspect of the invention, the description thereof is omitted here.

於第2實施形態之切晶帶一體型半導體背面用膜1中,基材31、以及黏著劑層32中之至少一個表面之表面電阻率值為1.0×1011Ω以下,較佳為1.0×1010Ω以下,更佳為1.0×109Ω以下。 In the film 1 for a dicing tape-integrated semiconductor back surface according to the second embodiment, the surface resistivity of at least one of the substrate 31 and the adhesive layer 32 is 1.0 × 10 11 Ω or less, preferably 1.0 ×. 10 10 Ω or less, more preferably 1.0 × 10 9 Ω or less.

尤其是,於基材31中含有抗靜電劑之情形時,基材31之表面之表面電阻率值較佳為1.0×1011Ω以下,更佳為1.0×1010Ω以下,進而較佳為1.0×109Ω以下。尤其是,於基材31具有多層結構,且於上述多層結構之基材31之至少一個最外層中含有抗靜電劑之情形時,含有抗靜電劑之最外層之表面之表面電阻率值較佳為1.0×1011Ω以下,更佳為1.0×1010Ω以下,進而較佳為1.0×109Ω以下。 In particular, when the substrate 31 contains an antistatic agent, the surface resistivity value of the surface of the substrate 31 is preferably 1.0 × 10 11 Ω or less, more preferably 1.0 × 10 10 Ω or less, and further preferably 1.0 × 10 9 Ω or less. In particular, when the substrate 31 has a multilayer structure and the antistatic agent is contained in at least one of the outermost layers of the substrate 31 of the multilayer structure, the surface resistivity of the surface of the outermost layer containing the antistatic agent is preferably It is 1.0 × 10 11 Ω or less, more preferably 1.0 × 10 10 Ω or less, further preferably 1.0 × 10 9 Ω or less.

又,於黏著劑層32中含有抗靜電劑之情形時,黏著劑層32之表面之表面電阻率值較佳為1.0×1011Ω以下,更佳為1.0×1010Ω以下,進而較佳為1.0×109Ω以下。 Further, when the antistatic agent is contained in the adhesive layer 32, the surface resistivity value of the surface of the adhesive layer 32 is preferably 1.0 × 10 11 Ω or less, more preferably 1.0 × 10 10 Ω or less, and further preferably It is 1.0 × 10 9 Ω or less.

又,於基材31與黏著劑層32兩者中含有抗靜電劑之情形時,基材31之表面之表面電阻率值較佳為1.0×1011Ω以下,更佳為1.0×1010Ω以下,進而較佳為1.0×109Ω以下,且黏著劑層32之表面之表面電阻率值較佳為1.0×1011Ω以下,更佳為1.0×1010Ω以下,進而較佳為1.0×109Ω以下。 Further, when the antistatic agent is contained in both of the substrate 31 and the adhesive layer 32, the surface resistivity of the surface of the substrate 31 is preferably 1.0 × 10 11 Ω or less, more preferably 1.0 × 10 10 Ω. Further, it is preferably 1.0 × 10 9 Ω or less, and the surface resistivity value of the surface of the adhesive layer 32 is preferably 1.0 × 10 11 Ω or less, more preferably 1.0 × 10 10 Ω or less, further preferably 1.0. ×10 9 Ω or less.

又,上述表面電阻率值越小越佳,但可列舉例如1.0×105Ω以上、1.0×106Ω以上、1.0×107Ω以上。由於上述表面電阻率值為1.0×1011Ω以下,因此不易帶電。因此,更能發揮抗靜電效果。再者,於本發明中,所謂基材、以及前黏著劑層中之至少一個表面之表面電阻率值,係指基材之黏著劑層側之表面、基材之與黏著劑層相反側之表面、黏著劑層之基材側之表面、以及黏著劑層之與基材相反側之表面中之至少一個表面之表面電阻率值。上述表面電阻率值係指藉 由實施例中記載之方法測定之值。 Further, the surface resistivity value is preferably as small as possible, and examples thereof include 1.0 × 10 5 Ω or more, 1.0 × 10 6 Ω or more, and 1.0 × 10 7 Ω or more. Since the surface resistivity value is 1.0 × 10 11 Ω or less, it is not easily charged. Therefore, it is more effective to exert an antistatic effect. Furthermore, in the present invention, the surface resistivity values of at least one of the substrate and the front adhesive layer refer to the surface of the adhesive layer side of the substrate, and the opposite side of the substrate and the adhesive layer. The surface resistivity value of at least one of the surface, the surface of the substrate side of the adhesive layer, and the surface of the adhesive layer opposite to the substrate. The surface resistivity value is a value measured by the method described in the examples.

第2實施形態之切晶帶一體型半導體背面用膜1於剝離速度10m/min、剝離角度150°之剝離試驗中,黏著劑層32與接著片材2之剝離力較佳為0.02~0.5N/20mm,更佳為0.02~0.3N/20mm,進而較佳為0.02~0.2N/20mm。若上述剝離力為0.02N/20mm以上,則於切割時,能夠固定半導體晶圓。又,若上述剝離力為0.5N/20mm以下,則於拾取時,能夠容易地將附接著片材2之半導體元件自黏著劑層32剝離。 In the peeling test of the film-integrated semiconductor back surface film 1 of the second embodiment at a peeling speed of 10 m/min and a peeling angle of 150°, the peeling force of the adhesive layer 32 and the succeeding sheet 2 is preferably 0.02 to 0.5 N. /20 mm, more preferably 0.02 to 0.3 N/20 mm, further preferably 0.02 to 0.2 N/20 mm. When the peeling force is 0.02 N/20 mm or more, the semiconductor wafer can be fixed at the time of dicing. Moreover, when the peeling force is 0.5 N/20 mm or less, the semiconductor element attached to the sheet 2 can be easily peeled off from the adhesive layer 32 at the time of picking up.

又,於第2實施形態之切晶帶一體型半導體背面用膜1中,根據上述剝離試驗之條件,將黏著劑層32與接著片材2剝離時之剝離靜電壓之絕對值較佳為0.5kV以下(-0.5kV~+0.5kV),更佳為0.3kV以下(-0.3kV~+0.3kV),進而較佳為0.2kV以下(-0.2kV~+0.2kV)。若根據上述剝離試驗之條件,將黏著劑層32與接著片材2剝離時之剝離靜電壓之絕對值為0.5kV以下,則能進一步發揮抗靜電效果。其結果,可防止由於拾取時之剝離靜電導致半導體元件被破壞,提高作為器件之可靠性。 Further, in the film 1 for dicing tape-integrated semiconductor back surface of the second embodiment, the absolute value of the peeling static voltage when the adhesive layer 32 and the succeeding sheet 2 are peeled off is preferably 0.5 according to the conditions of the peeling test. Below kV (-0.5 kV to +0.5 kV), more preferably 0.3 kV or less (-0.3 kV to +0.3 kV), further preferably 0.2 kV or less (-0.2 kV to +0.2 kV). According to the conditions of the peeling test, when the absolute value of the peeling static voltage when the adhesive layer 32 and the adhesive sheet 2 are peeled off is 0.5 kV or less, the antistatic effect can be further exhibited. As a result, it is possible to prevent the semiconductor element from being broken due to the peeling of static electricity at the time of picking up, and the reliability as a device is improved.

<第3本發明> <3rd invention>

以下,關於第3本發明之實施形態,對與第1本發明不同之方面進行說明。第3本發明之切晶帶一體型接著片材除了特別於本第3本發明之項中進行了說明以外,可與第1本發明設為同樣之構成。因此,省略與第1本發明共通之部分之說明。 Hereinafter, an embodiment different from the first invention will be described with respect to the third embodiment of the present invention. The diced tape-integrated sheet of the third aspect of the present invention can be configured in the same manner as the first invention except that it is described in particular in the third aspect of the invention. Therefore, the description of the parts common to the first invention will be omitted.

(切晶帶一體型半導體背面用膜) (Cutting tape integrated semiconductor back surface film)

作為第3本發明之切晶帶一體型半導體背面用膜之實施形態(以下,亦稱為第3實施形態),可列舉與第1本發明之切晶帶一體型半導體背面用膜之實施形態同樣之構成,即,如圖1所示之切晶帶一體型半導體背面用膜1。由於切晶帶一體型半導體背面用膜1之層構成於第 1本發明之項中進行了說明,因此此處省略說明。 The embodiment of the dicing tape-integrated semiconductor back surface film of the third aspect of the present invention (hereinafter also referred to as the third embodiment) is an embodiment of the film for dicing tape-integrated semiconductor back surface of the first aspect of the invention. In the same manner, the film 1 for dicing tape-integrated semiconductor back surface shown in Fig. 1 is used. The layer of the film 1 for the dicing tape-integrated semiconductor back surface is formed in the first 1 has been described in the item of the present invention, and thus the description thereof is omitted here.

第3實施形態之切晶帶一體型半導體背面用膜1於基材31、以及黏著劑層32中之至少一者中含有高分子型抗靜電劑。切晶帶一體型半導體背面用膜1由於基材31、以及黏著劑層32中之至少一者中含有高分子型抗靜電劑,因此不易帶電。因此,能夠發揮抗靜電效果。又,由於使用高分子型抗靜電劑作為抗靜電劑,因此不易自基材31或黏著劑層32滲出。其結果,能夠抑制經時導致之抗靜電功能之降低。尤其是,若於基材31中含有高分子型抗靜電劑,則能夠抑制自固定切晶帶3之吸附台取下時之基材31與吸附台之間之剝離靜電。其中,若基材31具有多層結構,且於多層結構之基材31之黏著劑層32側之最外層中含有高分子型抗靜電劑,則能夠抑制基材31與黏著劑層32兩者之靜電。又,若於多層結構之基材31之與黏著劑層32相反側之最外層中含有高分子型抗靜電劑,則能夠更有效地抑制基材31與吸附台之間之剝離靜電。 The dicing tape-integrated semiconductor back surface film 1 of the third embodiment contains a polymer type antistatic agent in at least one of the base material 31 and the adhesive layer 32. In the film 1 for dicing tape-integrated semiconductor back surface, since at least one of the base material 31 and the adhesive layer 32 contains a polymer type antistatic agent, it is difficult to charge. Therefore, an antistatic effect can be exerted. Further, since a polymer type antistatic agent is used as an antistatic agent, it is less likely to bleed out from the substrate 31 or the adhesive layer 32. As a result, it is possible to suppress a decrease in the antistatic function caused by the passage of time. In particular, when the polymer type antistatic agent is contained in the substrate 31, it is possible to suppress the peeling static electricity between the substrate 31 and the adsorption stage when the adsorption stage of the fixed dicing tape 3 is removed. When the base material 31 has a multilayer structure and the polymer type antistatic agent is contained in the outermost layer on the side of the adhesive layer 32 of the base material 31 of the multilayer structure, both the base material 31 and the adhesive layer 32 can be suppressed. Static electricity. Further, when the polymer-type antistatic agent is contained in the outermost layer on the side opposite to the adhesive layer 32 of the substrate 31 of the multilayer structure, the peeling static electricity between the substrate 31 and the adsorption stage can be more effectively suppressed.

再者,於半導體背面用膜2中可含有高分子型抗靜電劑。若於半導體背面用膜2中含有高分子型抗靜電劑,則自切晶帶3剝離後亦具有抗靜電效果。其結果,自切晶帶3剝離後,亦能夠抑制由靜電導致之半導體元件之破壞。尤其是,若半導體背面用膜2具有多層結構,且於多層結構之半導體背面用膜2之切晶帶3側之最外層中含有高分子型抗靜電劑,則能夠進一步有效地抑制將黏著劑層32與半導體背面用膜2剝離時之剝離靜電。再者,關於高分子型抗靜電劑,如於第1本發明之項中所說明。 Further, a polymer type antistatic agent may be contained in the film 2 for semiconductor back surface. When the polymer type antistatic agent is contained in the film 2 for semiconductor back surface, it has an antistatic effect after peeling from the dicing tape 3. As a result, after the dicing tape 3 is peeled off, the destruction of the semiconductor element due to static electricity can also be suppressed. In particular, when the film 2 for semiconductor back surface has a multilayer structure and a polymer type antistatic agent is contained in the outermost layer on the side of the dicing tape 3 of the film 2 for semiconductor back surface of the multilayer structure, the adhesive can be further effectively suppressed. When the layer 32 is peeled off from the film 2 for semiconductor back surface, the static electricity is peeled off. Further, the polymer type antistatic agent is as described in the item of the first invention.

於第3實施形態之切晶帶一體型半導體背面用膜1中,基材31、以及黏著劑層32中之至少一個表面之表面電阻率值較佳為1.0×1011Ω以下,更佳為1.0×1010Ω以下,進而較佳為1.0×109Ω以下。 In the film 1 for a dicing tape-integrated semiconductor back surface according to the third embodiment, the surface resistivity of at least one of the substrate 31 and the adhesive layer 32 is preferably 1.0 × 10 11 Ω or less, more preferably 1.0 × 10 10 Ω or less, further preferably 1.0 × 10 9 Ω or less.

尤其是,於基材31中含有高分子型抗靜電劑之情形時,基材31之 表面之表面電阻率值較佳為1.0×1011Ω以下,更佳為1.0×1010Ω以下,進而較佳為1.0×109Ω以下。尤其是,於基材31具有多層結構,且於上述多層結構之基材31之至少一個最外層中含有高分子型抗靜電劑之情形時,含有高分子型抗靜電劑之最外層之表面之表面電阻率值較佳為1.0×1011Ω以下,更佳為1.0×1010Ω以下,進而較佳為1.0×109Ω以下。 In particular, when the polymerizable antistatic agent is contained in the substrate 31, the surface resistivity of the surface of the substrate 31 is preferably 1.0 × 10 11 Ω or less, more preferably 1.0 × 10 10 Ω or less. It is preferably 1.0 × 10 9 Ω or less. In particular, when the substrate 31 has a multilayer structure and the polymer type antistatic agent is contained in at least one outermost layer of the substrate 31 of the multilayer structure, the surface of the outermost layer of the polymer type antistatic agent is contained. The surface resistivity value is preferably 1.0 × 10 11 Ω or less, more preferably 1.0 × 10 10 Ω or less, still more preferably 1.0 × 10 9 Ω or less.

又,於黏著劑層32中含有高分子型抗靜電劑之情形時,黏著劑層32之表面之表面電阻率值較佳為1.0×1011Ω以下,更佳為1.0×1010Ω以下,進而較佳為1.0×109Ω以下。 When the polymer type antistatic agent is contained in the adhesive layer 32, the surface resistivity value of the surface of the adhesive layer 32 is preferably 1.0 × 10 11 Ω or less, more preferably 1.0 × 10 10 Ω or less. Further, it is preferably 1.0 × 10 9 Ω or less.

又,於基材31與黏著劑層32兩者中含有高分子型抗靜電劑之情形時,基材31之表面之表面電阻率值較佳為1.0×1011Ω以下,更佳為1.0×1010Ω以下,進而較佳為1.0×109Ω以下,且黏著劑層32之表面之表面電阻率值較佳為1.0×1011Ω以下,更佳為1.0×1010Ω以下,進而較佳為1.0×109Ω以下。 Further, when a polymer type antistatic agent is contained in both of the base material 31 and the adhesive layer 32, the surface resistivity value of the surface of the base material 31 is preferably 1.0 × 10 11 Ω or less, more preferably 1.0 ×. 10 10 Ω or less, more preferably 1.0 × 10 9 Ω or less, and the surface resistivity value of the surface of the adhesive layer 32 is preferably 1.0 × 10 11 Ω or less, more preferably 1.0 × 10 10 Ω or less, and further Preferably, it is 1.0 × 10 9 Ω or less.

又,上述表面電阻率值越小越佳,但可列舉例如1.0×105Ω以上、1.0×106Ω以上、1.0×107Ω以上。若上述表面電阻率值為1.0×1011Ω以下,則不易帶電。因此,能進一步發揮抗靜電效果。再者,於第3本發明中,所謂基材、以及前黏著劑層中之至少一個表面之表面電阻率值,係指基材之黏著劑層側之表面、基材之與黏著劑層相反側之表面、黏著劑層之基材側之表面、以及黏著劑層之與基材相反側之表面中之至少一個表面之表面電阻率值。上述表面電阻率值係指藉由實施例中記載之方法測定之值。 Further, the surface resistivity value is preferably as small as possible, and examples thereof include 1.0 × 10 5 Ω or more, 1.0 × 10 6 Ω or more, and 1.0 × 10 7 Ω or more. When the surface resistivity value is 1.0 × 10 11 Ω or less, charging is not easy. Therefore, the antistatic effect can be further exerted. Further, in the third invention, the surface resistivity value of at least one of the substrate and the front adhesive layer means the surface of the adhesive layer side of the substrate, and the substrate is opposite to the adhesive layer. The surface resistivity value of the surface of the side, the surface of the substrate side of the adhesive layer, and at least one of the surfaces of the adhesive layer opposite to the substrate. The surface resistivity value is a value measured by the method described in the examples.

第3實施形態之切晶帶一體型半導體背面用膜1於剝離速度10m/min、剝離角度150°之剝離試驗中,黏著劑層32與接著片材2之剝離力較佳為0.02~0.5N/20mm,更佳為0.02~0.3N/20mm,進而較佳為0.02~0.2N/20mm。若上述剝離力為0.02N/20mm以上,則於切割 時,能夠固定半導體晶圓。又,若上述剝離力為0.5N/20mm以下,則於拾取時,能夠容易地將附接著片材2之半導體元件自黏著劑層32剝離。 In the peeling test of the film-integrated semiconductor back surface film 1 of the third embodiment at a peeling speed of 10 m/min and a peeling angle of 150°, the peeling force of the adhesive layer 32 and the succeeding sheet 2 is preferably 0.02 to 0.5 N. /20 mm, more preferably 0.02 to 0.3 N/20 mm, further preferably 0.02 to 0.2 N/20 mm. If the peeling force is 0.02 N/20 mm or more, the cutting is performed. At the time, the semiconductor wafer can be fixed. Moreover, when the peeling force is 0.5 N/20 mm or less, the semiconductor element attached to the sheet 2 can be easily peeled off from the adhesive layer 32 at the time of picking up.

又,於第3實施形態之切晶帶一體型半導體背面用膜1中,根據上述剝離試驗之條件,將黏著劑層32與接著片材2剝離時之剝離靜電壓之絕對值較佳為0.5kV以下(-0.5kV~+0.5kV),更佳為0.3kV以下(-0.3kV~+0.3kV),進而較佳為0.2kV以下(-0.2kV~+0.2kV)。若根據上述剝離試驗之條件,將黏著劑層32與接著片材2剝離時之剝離靜電壓之絕對值為0.5kV以下,則能進一步發揮抗靜電效果。其結果,可防止由於拾取時之剝離靜電導致半導體元件被破壞,提高作為器件之可靠性。 Further, in the film 1 for dicing tape-integrated semiconductor back surface of the third embodiment, the absolute value of the peeling static voltage when the adhesive layer 32 and the succeeding sheet 2 are peeled off is preferably 0.5 according to the conditions of the peeling test. Below kV (-0.5 kV to +0.5 kV), more preferably 0.3 kV or less (-0.3 kV to +0.3 kV), further preferably 0.2 kV or less (-0.2 kV to +0.2 kV). According to the conditions of the peeling test, when the absolute value of the peeling static voltage when the adhesive layer 32 and the adhesive sheet 2 are peeled off is 0.5 kV or less, the antistatic effect can be further exhibited. As a result, it is possible to prevent the semiconductor element from being broken due to the peeling of static electricity at the time of picking up, and the reliability as a device is improved.

<第4本發明> <4th invention>

以下,關於第4本發明之實施形態,對與第1本發明不同之方面進行說明。第4本發明之切晶帶一體型接著片材除了特別於本第4本發明之項中進行了說明以外,可與第1本發明設為同樣之構成。因此,省略與第1本發明共通之部分之說明。 Hereinafter, an embodiment different from the first invention will be described with respect to the fourth embodiment of the present invention. The diced tape-integrated sheet of the fourth aspect of the present invention can be configured in the same manner as the first aspect of the invention, except that it is described in particular in the fourth aspect of the invention. Therefore, the description of the parts common to the first invention will be omitted.

(切晶帶一體型半導體背面用膜) (Cutting tape integrated semiconductor back surface film)

作為第4本發明之切晶帶一體型半導體背面用膜之實施形態(以下,亦稱為第4實施形態),可列舉與第1本發明之切晶帶一體型半導體背面用膜之實施形態同樣之構成,即,如圖1所示之切晶帶一體型半導體背面用膜1。由於切晶帶一體型半導體背面用膜1之層構成於第1本發明之項中進行了說明,因此此處省略說明。 In the embodiment of the dicing tape-integrated semiconductor back surface film of the fourth aspect of the invention (hereinafter also referred to as the fourth embodiment), the embodiment of the dicing tape-integrated semiconductor back surface film of the first aspect of the invention is exemplified. In the same manner, the film 1 for dicing tape-integrated semiconductor back surface shown in Fig. 1 is used. Since the layer structure of the film 1 for the dicing tape-integrated semiconductor back surface has been described in the first aspect of the invention, the description thereof is omitted here.

第4實施形態之半導體背面用膜2之任一表面之表面電阻率值為1.0×1011Ω以下,較佳為1.0×1010Ω以下,更佳為1.0×109Ω以下。於半導體背面用膜2具有多層結構,且於任一個最外層中含有抗靜電劑之情形時,含有抗靜電劑之最外層之表面之表面電阻率值較佳為 1.0×1011Ω以下,更佳為1.0×1010Ω以下,進而較佳為1.0×109Ω以下。又,上述表面電阻率值越小越佳,但可列舉例如1.0×105Ω以上、1.0×106Ω以上、1.0×107Ω以上。由於上述表面電阻率值為1.0×1011Ω以下,因此不易帶電。因此,更能發揮抗靜電效果。上述表面電阻率值係指藉由實施例中記載之方法測定之值。 The surface resistivity of any surface of the film 2 for semiconductor back surface of the fourth embodiment is 1.0 × 10 11 Ω or less, preferably 1.0 × 10 10 Ω or less, more preferably 1.0 × 10 9 Ω or less. When the film 2 for semiconductor back surface has a multilayer structure and the antistatic agent is contained in any of the outermost layers, the surface resistivity of the surface of the outermost layer containing the antistatic agent is preferably 1.0 × 10 11 Ω or less. It is preferably 1.0 × 10 10 Ω or less, more preferably 1.0 × 10 9 Ω or less. Further, the surface resistivity value is preferably as small as possible, and examples thereof include 1.0 × 10 5 Ω or more, 1.0 × 10 6 Ω or more, and 1.0 × 10 7 Ω or more. Since the surface resistivity value is 1.0 × 10 11 Ω or less, it is not easily charged. Therefore, it is more effective to exert an antistatic effect. The surface resistivity value is a value measured by the method described in the examples.

第4實施形態之切晶帶一體型半導體背面用膜1於剝離速度10m/min、剝離角度150°之剝離試驗中,黏著劑層32與接著片材2之剝離力較佳為0.02~0.5N/20mm,更佳為0.02~0.3N/20mm,進而較佳為0.02~0.2N/20mm。若上述剝離力為0.02N/20mm以上,則於切割時,能夠固定半導體晶圓。又,若上述剝離力為0.5N/20mm以下,則於拾取時,能夠容易地將附接著片材2之半導體元件自黏著劑層32剝離。 In the peeling test of the film-integrated semiconductor back surface film 1 of the fourth embodiment at a peeling speed of 10 m/min and a peeling angle of 150°, the peeling force of the adhesive layer 32 and the succeeding sheet 2 is preferably 0.02 to 0.5 N. /20 mm, more preferably 0.02 to 0.3 N/20 mm, further preferably 0.02 to 0.2 N/20 mm. When the peeling force is 0.02 N/20 mm or more, the semiconductor wafer can be fixed at the time of dicing. Moreover, when the peeling force is 0.5 N/20 mm or less, the semiconductor element attached to the sheet 2 can be easily peeled off from the adhesive layer 32 at the time of picking up.

又,於第4實施形態之切晶帶一體型半導體背面用膜1中,根據上述剝離試驗之條件,將黏著劑層32與接著片材2剝離時之剝離靜電壓之絕對值較佳為0.5kV以下(-0.5kV~+0.5kV),更佳為0.3kV以下(-0.3kV~+0.3kV),進而較佳為0.2kV以下(-0.2kV~+0.2kV)。若根據上述剝離試驗之條件,將黏著劑層32與接著片材2剝離時之剝離靜電壓之絕對值為0.5kV以下,則能進一步發揮抗靜電效果。其結果,可防止由於拾取時之剝離靜電導致半導體元件被破壞,提高作為器件之可靠性。 Further, in the film 1 for dicing tape-integrated semiconductor back surface of the fourth embodiment, the absolute value of the peeling static voltage when the adhesive layer 32 and the succeeding sheet 2 are peeled off is preferably 0.5 according to the conditions of the peeling test. Below kV (-0.5 kV to +0.5 kV), more preferably 0.3 kV or less (-0.3 kV to +0.3 kV), further preferably 0.2 kV or less (-0.2 kV to +0.2 kV). According to the conditions of the peeling test, when the absolute value of the peeling static voltage when the adhesive layer 32 and the adhesive sheet 2 are peeled off is 0.5 kV or less, the antistatic effect can be further exhibited. As a result, it is possible to prevent the semiconductor element from being broken due to the peeling of static electricity at the time of picking up, and the reliability as a device is improved.

於第4實施形態之半導體背面用膜2未積層於切晶帶3之情形時,半導體背面用膜2可以使用1片於兩面包含剝離層之分隔件而捲繞成輥狀之形態,藉由在兩面包含剝離層之分隔件進行保護,亦可藉由在至少一個面包含剝離層之分隔件進行保護。 When the film 2 for semiconductor back surface of the fourth embodiment is not laminated on the dicing tape 3, the film for semiconductor back surface 2 can be wound into a roll shape by using a separator having a peeling layer on both sides. The separator is provided on both sides with a release layer for protection, and may also be protected by a separator comprising a release layer on at least one side.

再者,第4實施形態之半導體背面用膜2藉由貼附於切晶帶,與切晶帶一體型半導體背面用膜1同樣地,可對倒裝晶片安裝之半導體裝 置(半導體晶片以倒裝晶片接合方式固定於基板等被黏著體之狀態或形態之半導體裝置)使用。 In addition, the film 2 for semiconductor back surface of the fourth embodiment can be attached to a flip-chip mounted semiconductor device by attaching it to a dicing tape in the same manner as the dicing tape-integrated semiconductor back surface film 1 . The semiconductor wafer is used in a semiconductor device in a state or a state in which the semiconductor wafer is fixed to an adherend such as a substrate by flip chip bonding.

又,於使用倒裝晶片型半導體背面用膜(例如,半導體背面用膜2)而製造半導體裝置之情形時,可藉由依據使用切晶帶一體型半導體背面用膜1之情形時之半導體裝置之製造方法之方法而製造半導體裝置。即,第4本發明之半導體裝置之製造方法為至少包含以下步驟之半導體裝置之製造方法:準備於基材上積層有黏著劑層之切晶帶之步驟;於上述切晶帶之上述黏著劑層上貼附上述接著片材,獲得切晶帶一體型接著片材之步驟;於上述切晶帶一體型接著片材中之接著片材上貼著半導體晶圓之步驟;切割上述半導體晶圓而形成半導體元件之步驟;以及將上述半導體元件與上述接著片材一起自切晶帶之黏著劑層拾取之步驟。 In the case of manufacturing a semiconductor device using a film for flip chip type semiconductor back surface (for example, film 2 for semiconductor back surface), the semiconductor device can be used in the case of using the film 1 for dicing tape-integrated semiconductor back surface. A semiconductor device is manufactured by the method of the manufacturing method. That is, the method of manufacturing a semiconductor device according to the fourth aspect of the present invention is a method of manufacturing a semiconductor device including at least a step of preparing a dicing tape in which an adhesive layer is laminated on a substrate; and the above-mentioned adhesive in the dicing tape a step of attaching the above-mentioned succeeding sheet to the layer to obtain a diced strip-integrated sheet; and a step of attaching a semiconductor wafer to the succeeding sheet in the dicing strip-integrated sheet; cutting the semiconductor wafer And a step of forming a semiconductor element; and picking up the semiconductor element from the adhesive layer of the dicing tape together with the succeeding sheet.

尤其是,於第4本發明之接著片材為半導體背面用膜之情形時,上述半導體裝置之製造方法至少包含以下步驟:準備於基材上積層有黏著劑層之切晶帶之步驟;於上述切晶帶之上述黏著劑層上貼附上述半導體背面用膜,獲得切晶帶一體型半導體背面用膜之步驟;於上述切晶帶一體型半導體背面用膜上貼著半導體晶圓之背面之步驟;切割上述半導體晶圓之步驟;拾取藉由切割所得之半導體元件之步驟;以及將上述半導體元件倒裝晶片連接於被黏著體上之步驟。 In particular, in the case where the adhesive sheet of the fourth aspect of the invention is a film for semiconductor back surface, the method for producing the semiconductor device includes at least the step of preparing a dicing tape having an adhesive layer laminated on a substrate; The film for semiconductor back surface is attached to the adhesive layer of the dicing tape to obtain a film for a dicing tape-integrated semiconductor back surface; and the back surface of the semiconductor wafer is attached to the film for the dicing tape-integrated semiconductor back surface a step of cutting the semiconductor wafer; a step of picking up the obtained semiconductor element; and a step of flip-chip bonding the semiconductor element to the adherend.

<第5本發明> <5th invention>

以下,關於第5本發明之實施形態,對與第1本發明不同之方面進行說明。第5本發明之切晶帶一體型接著片材除了特別於本第5本發明之項中進行了說明以外,可與第1本發明設為同樣之構成。因此,省略與第1本發明共通之部分之說明。 Hereinafter, an embodiment different from the first invention will be described with respect to the fifth embodiment of the present invention. The diced tape-integrated sheet of the fifth aspect of the present invention can be configured in the same manner as in the first aspect of the invention, except that it is described in particular in the fifth aspect of the invention. Therefore, the description of the parts common to the first invention will be omitted.

(切晶帶一體型半導體背面用膜) (Cutting tape integrated semiconductor back surface film)

作為第5本發明之切晶帶一體型半導體背面用膜之實施形態(以 下,亦稱為第5實施形態),可列舉與第1本發明之切晶帶一體型半導體背面用膜之實施形態同樣之構成,即,如圖1所示之切晶帶一體型半導體背面用膜1。由於切晶帶一體型半導體背面用膜1之層構成於第1本發明之項中進行了說明,因此此處省略說明。 An embodiment of the film for a dicing tape-integrated semiconductor back surface according to the fifth aspect of the present invention In the fifth embodiment, the dicing tape-integrated semiconductor back surface film of the first embodiment of the present invention has the same configuration as that of the first embodiment. Use membrane 1. Since the layer structure of the film 1 for the dicing tape-integrated semiconductor back surface has been described in the first aspect of the invention, the description thereof is omitted here.

於第5實施形態之半導體背面用膜2中含有高分子型抗靜電劑。由於在半導體背面用膜2中含有高分子型抗靜電劑,因此不易帶電。又,由於使用高分子型抗靜電劑作為抗靜電劑,因此不易自半導體背面用膜2滲出。其結果,能夠抑制經時導致之抗靜電功能之降低。又,由於在半導體背面用膜2中含有高分子型抗靜電劑,因此於貼附於切晶帶而作為切晶帶一體型接著片材使用時,自切晶帶剝離後亦具有抗靜電效果。其結果,自切晶帶剝離後,亦能夠抑制由靜電導致之半導體元件之破壞。尤其是,若半導體背面用膜2具有多層結構,且於多層結構之半導體背面用膜2之切晶帶3側之最外層中含有高分子型抗靜電劑,則能夠進一步有效地抑制將黏著劑層32與半導體背面用膜2剝離時之剝離靜電。 The film for semiconductor back surface 2 of the fifth embodiment contains a polymer type antistatic agent. Since the polymer type antistatic agent is contained in the film 2 for semiconductor back surface, it is hard to charge. Moreover, since a polymer type antistatic agent is used as an antistatic agent, it is hard to bleed out from the film 2 for semiconductor back surface. As a result, it is possible to suppress a decrease in the antistatic function caused by the passage of time. In addition, since the polymer-type antistatic agent is contained in the film 2 for semiconductor back surface, when it is attached to a dicing tape and used as a dicing tape-integrated sheet, it also has an antistatic effect after being peeled off from the dicing tape. . As a result, the destruction of the semiconductor element due to static electricity can be suppressed even after the dicing tape is peeled off. In particular, when the film 2 for semiconductor back surface has a multilayer structure and a polymer type antistatic agent is contained in the outermost layer on the side of the dicing tape 3 of the film 2 for semiconductor back surface of the multilayer structure, the adhesive can be further effectively suppressed. When the layer 32 is peeled off from the film 2 for semiconductor back surface, the static electricity is peeled off.

再者,切晶帶一體型半導體背面用膜1可於基材31、以及黏著劑層32中之至少一者中含有高分子型抗靜電劑。若於基材31、以及黏著劑層32中之至少一者中含有高分子型抗靜電劑,則更加不易帶電。因此,能進一步發揮抗靜電效果。又,由於使用高分子型抗靜電劑作為抗靜電劑,因此不易自基材31或黏著劑層32滲出。其結果,能夠抑制經時導致之抗靜電功能之降低。尤其是,若於基材31中含有高分子型抗靜電劑,則能夠抑制自固定切晶帶3之吸附台取下時之基材31與吸附台之間之剝離靜電。其中,若基材31具有多層結構,且於多層結構之基材31之黏著劑層32側之最外層中含有高分子型抗靜電劑,則能夠抑制基材31與黏著劑層32兩者之靜電。又,若於多層結構之基材31之與黏著劑層32相反側之最外層中含有高分子型抗靜電劑,則能夠更有 效地抑制基材31與吸附台之間之剝離靜電。再者,關於高分子型抗靜電劑,如於第1本發明之項中所說明。 Further, the film-integrated semiconductor back surface film 1 may contain a polymer type antistatic agent in at least one of the substrate 31 and the adhesive layer 32. When at least one of the base material 31 and the adhesive layer 32 contains a polymer type antistatic agent, it is more difficult to charge. Therefore, the antistatic effect can be further exerted. Further, since a polymer type antistatic agent is used as an antistatic agent, it is less likely to bleed out from the substrate 31 or the adhesive layer 32. As a result, it is possible to suppress a decrease in the antistatic function caused by the passage of time. In particular, when the polymer type antistatic agent is contained in the substrate 31, it is possible to suppress the peeling static electricity between the substrate 31 and the adsorption stage when the adsorption stage of the fixed dicing tape 3 is removed. When the base material 31 has a multilayer structure and the polymer type antistatic agent is contained in the outermost layer on the side of the adhesive layer 32 of the base material 31 of the multilayer structure, both the base material 31 and the adhesive layer 32 can be suppressed. Static electricity. Further, if a polymer type antistatic agent is contained in the outermost layer of the substrate 31 of the multilayer structure opposite to the adhesive layer 32, it is possible to further The peeling static electricity between the substrate 31 and the adsorption stage is effectively suppressed. Further, the polymer type antistatic agent is as described in the item of the first invention.

第5實施形態之半導體背面用膜2之任一表面之表面電阻率值較佳為1.0×1011Ω以下,更佳為1.0×1010Ω以下,進而較佳為1.0×109Ω以下。於半導體背面用膜2具有多層結構,且於任一個最外層中含有高分子型抗靜電劑之情形時,含有高分子型抗靜電劑之最外層之表面之表面電阻率值較佳為1.0×1011Ω以下,更佳為1.0×1010Ω以下,進而較佳為1.0×109Ω以下。又,上述表面電阻率值越小越佳,但可列舉例如1.0×105Ω以上、1.0×106Ω以上、1.0×107Ω以上。若上述表面電阻率值為1.0×1011Ω以下,則不易帶電。因此,更能發揮抗靜電效果。上述表面電阻率值係指藉由實施例中記載之方法測定之值。 The surface resistivity value of any surface of the film 2 for semiconductor back surface of the fifth embodiment is preferably 1.0 × 10 11 Ω or less, more preferably 1.0 × 10 10 Ω or less, still more preferably 1.0 × 10 9 Ω or less. When the film 2 for semiconductor back surface has a multilayer structure and the polymer type antistatic agent is contained in any of the outermost layers, the surface resistivity value of the surface of the outermost layer containing the polymer type antistatic agent is preferably 1.0 ×. 10 11 Ω or less, more preferably 1.0 × 10 10 Ω or less, further preferably 1.0 × 10 9 Ω or less. Further, the surface resistivity value is preferably as small as possible, and examples thereof include 1.0 × 10 5 Ω or more, 1.0 × 10 6 Ω or more, and 1.0 × 10 7 Ω or more. When the surface resistivity value is 1.0 × 10 11 Ω or less, charging is not easy. Therefore, it is more effective to exert an antistatic effect. The surface resistivity value is a value measured by the method described in the examples.

第5實施形態之切晶帶一體型半導體背面用膜1於剝離速度10m/min、剝離角度150°之剝離試驗中,黏著劑層32與接著片材2之剝離力較佳為0.02~0.5N/20mm,更佳為0.02~0.3N/20mm,進而較佳為0.02~0.2N/20mm。若上述剝離力為0.02N/20mm以上,則於切割時,能夠固定半導體晶圓。又,若上述剝離力為0.5N/20mm以下,則於拾取時,能夠容易地將附接著片材2之半導體元件自黏著劑層32剝離。 In the peeling test of the film-integrated semiconductor back surface film 1 of the fifth embodiment at a peeling speed of 10 m/min and a peeling angle of 150°, the peeling force of the adhesive layer 32 and the succeeding sheet 2 is preferably 0.02 to 0.5 N. /20 mm, more preferably 0.02 to 0.3 N/20 mm, further preferably 0.02 to 0.2 N/20 mm. When the peeling force is 0.02 N/20 mm or more, the semiconductor wafer can be fixed at the time of dicing. Moreover, when the peeling force is 0.5 N/20 mm or less, the semiconductor element attached to the sheet 2 can be easily peeled off from the adhesive layer 32 at the time of picking up.

又,於第5實施形態之切晶帶一體型半導體背面用膜1中,根據上述剝離試驗之條件,將黏著劑層32與接著片材2剝離時之剝離靜電壓之絕對值較佳為0.5kV以下(-0.5kV~+0.5kV),更佳為0.3kV以下(-0.3kV~+0.3kV),進而較佳為0.2kV以下(-0.2kV~+0.2kV)。若根據上述剝離試驗之條件,將黏著劑層32與接著片材2剝離時之剝離靜電壓之絕對值為0.5kV以下,則更能發揮抗靜電效果。其結果,可防止由於拾取時之剝離靜電導致半導體元件被破壞,提高作為器件之可靠性。 Further, in the film 1 for dicing tape-integrated semiconductor back surface of the fifth embodiment, the absolute value of the peeling static voltage when the adhesive layer 32 and the succeeding sheet 2 are peeled off is preferably 0.5 according to the conditions of the peeling test. Below kV (-0.5 kV to +0.5 kV), more preferably 0.3 kV or less (-0.3 kV to +0.3 kV), further preferably 0.2 kV or less (-0.2 kV to +0.2 kV). According to the conditions of the peeling test, when the absolute value of the peeling static voltage when the adhesive layer 32 and the adhesive sheet 2 are peeled off is 0.5 kV or less, the antistatic effect can be more exhibited. As a result, it is possible to prevent the semiconductor element from being broken due to the peeling of static electricity at the time of picking up, and the reliability as a device is improved.

於第5實施形態之半導體背面用膜2未積層於切晶帶3之情形時,半導體背面用膜2可以使用1片於兩面包含剝離層之分隔件而捲繞成輥狀之形態,藉由在兩面包含剝離層之分隔件進行保護,亦可藉由在至少一個面包含剝離層之分隔件進行保護。 When the film 2 for semiconductor back surface of the fifth embodiment is not laminated on the dicing tape 3, the film for semiconductor back surface 2 can be wound into a roll shape by using one separator having a peeling layer on both sides. The separator is provided on both sides with a release layer for protection, and may also be protected by a separator comprising a release layer on at least one side.

再者,第5實施形態之半導體背面用膜2藉由貼附於切晶帶,與切晶帶一體型半導體背面用膜1同樣地,可對倒裝晶片安裝之半導體裝置(半導體晶片以倒裝晶片接合方式固定於基板等被黏著體之狀態或形態之半導體裝置)使用。 In addition, the semiconductor back surface film 2 of the fifth embodiment can be attached to the dicing tape, and can be mounted on a flip-chip mounted semiconductor device (the semiconductor wafer is poured down) similarly to the dicing tape-integrated semiconductor back surface film 1 It is used by a semiconductor device in which a wafer bonding method is fixed to a state or a form of an adherend such as a substrate.

又,於使用倒裝晶片型半導體背面用膜(例如,半導體背面用膜2)而製造半導體裝置之情形時,可藉由依據使用切晶帶一體型半導體背面用膜1之情形時之半導體裝置之製造方法之方法而製造半導體裝置。即,第5本發明之半導體裝置之製造方法為至少包含以下步驟之半導體裝置之製造方法:準備於基材上積層有黏著劑層之切晶帶之步驟;於上述切晶帶之上述黏著劑層上貼附上述接著片材,獲得切晶帶一體型接著片材之步驟;於上述切晶帶一體型接著片材中之接著片材上貼著半導體晶圓之步驟;切割上述半導體晶圓而形成半導體元件之步驟;以及將上述半導體元件與上述接著片材一起自切晶帶之黏著劑層拾取之步驟。 In the case of manufacturing a semiconductor device using a film for flip chip type semiconductor back surface (for example, film 2 for semiconductor back surface), the semiconductor device can be used in the case of using the film 1 for dicing tape-integrated semiconductor back surface. A semiconductor device is manufactured by the method of the manufacturing method. That is, the method of manufacturing a semiconductor device according to a fifth aspect of the present invention is a method of manufacturing a semiconductor device comprising at least a step of preparing a dicing tape in which an adhesive layer is laminated on a substrate; and the above-mentioned adhesive in the dicing tape a step of attaching the above-mentioned succeeding sheet to the layer to obtain a diced strip-integrated sheet; and a step of attaching a semiconductor wafer to the succeeding sheet in the dicing strip-integrated sheet; cutting the semiconductor wafer And a step of forming a semiconductor element; and picking up the semiconductor element from the adhesive layer of the dicing tape together with the succeeding sheet.

尤其是,於第5本發明之接著片材為半導體背面用膜之情形時,上述半導體裝置之製造方法至少包含以下步驟:準備於基材上積層有黏著劑層之切晶帶之步驟;於上述切晶帶之上述黏著劑層上貼附上述半導體背面用膜,獲得切晶帶一體型半導體背面用膜之步驟;於上述切晶帶一體型半導體背面用膜上貼著半導體晶圓之背面之步驟;切割上述半導體晶圓之步驟;拾取藉由切割所得之半導體元件之步驟;以及將上述半導體元件倒裝晶片連接於被黏著體上之步驟。 In particular, in the case where the adhesive sheet of the fifth aspect of the invention is a film for semiconductor back surface, the method for producing the semiconductor device includes at least the step of preparing a dicing tape having an adhesive layer laminated on a substrate; The film for semiconductor back surface is attached to the adhesive layer of the dicing tape to obtain a film for a dicing tape-integrated semiconductor back surface; and the back surface of the semiconductor wafer is attached to the film for the dicing tape-integrated semiconductor back surface a step of cutting the semiconductor wafer; a step of picking up the obtained semiconductor element; and a step of flip-chip bonding the semiconductor element to the adherend.

[實施例] [Examples]

以下,例示性地對該發明之較佳之實施例進行詳細說明。其中,該實施例中記載之材料或調配量等只要並無特別限定性之記載,則並不旨在將該發明之範圍僅限定於該等。又,份表示重量份。 Hereinafter, preferred embodiments of the invention will be described in detail. However, the materials, the blending amounts, and the like described in the examples are not intended to limit the scope of the invention to those of the invention, unless otherwise specified. Further, parts represent parts by weight.

實施例1~23對應於第1本發明。 Examples 1 to 23 correspond to the first invention.

實施例1~5及實施例13~17對應於第2本發明及第3本發明。 Examples 1 to 5 and Examples 13 to 17 correspond to the second invention and the third invention.

實施例6~7及實施例18~20對應於第4本發明及第5本發明。 Examples 6 to 7 and Examples 18 to 20 correspond to the fourth invention and the fifth invention.

(實施例1) (Example 1) <切晶帶之製作> <Production of dicing tape>

首先,製作3層結構之基材。製作依序積層有最外層(厚度:20μm,聚烯烴系基材)、中間層(厚度:40μm,聚烯烴系基材)、及最內層(厚度:40μm,聚烯烴系基材)之基材(有時稱為「積層基材A」)。再者,於最外層中,相對於最外層之全部樹脂成分而含有作為抗靜電劑之製品名:PELESTAT(三洋化成公司製造)30重量%。再者,於本實施例中,所謂最內層,係指於其上形成黏著劑層之層,所謂最外層,係指與形成有黏著劑層之側相反側之層。 First, a substrate having a three-layer structure was produced. The basis of the outermost layer (thickness: 20 μm, polyolefin-based substrate), the intermediate layer (thickness: 40 μm, polyolefin-based substrate), and the innermost layer (thickness: 40 μm, polyolefin-based substrate) were laminated. Material (sometimes referred to as "layered substrate A"). In addition, in the outermost layer, the product name of the antistatic agent is contained in the outermost layer of the outermost layer: PELESTAT (manufactured by Sanyo Chemical Co., Ltd.), 30% by weight. Further, in the present embodiment, the innermost layer means a layer on which an adhesive layer is formed, and the outermost layer means a layer on the side opposite to the side on which the adhesive layer is formed.

繼而,於具備冷凝管、氮氣導入管、溫度計以及攪拌裝置之反應容器中,放入丙烯酸2-乙基己酯(以下,稱為「2EHA」)88.8份、丙烯酸2-羥基乙酯(以下稱為「HEA」)11.2份、過氧化苯甲醯0.2份以及甲苯65份,於氮氣氣流中以61℃進行6小時聚合處理,獲得重量平均分子量85萬之丙烯酸系聚合物A。2EHA與HEA之莫耳比設為100mol:20mol。 Then, 88.8 parts of 2-ethylhexyl acrylate (hereinafter referred to as "2EHA") and 2-hydroxyethyl acrylate (hereinafter referred to as "2EHA") were placed in a reaction vessel equipped with a condenser, a nitrogen gas introduction tube, a thermometer, and a stirring device. 11.2 parts of "HEA", 0.2 parts of benzamidine peroxide, and 65 parts of toluene were subjected to polymerization treatment at 61 ° C for 6 hours in a nitrogen gas stream to obtain an acrylic polymer A having a weight average molecular weight of 850,000. The molar ratio of 2EHA to HEA was set to 100 mol: 20 mol.

向該丙烯酸系聚合物A中加入2-丙烯醯氧基乙基異氰酸酯(以下稱為「MOI」)12份(相對於HEA為80mol%),於空氣氣流中以50℃進行48小時加成反應處理,獲得丙烯酸系聚合物A'。 12 parts of 2-propenylmethoxyethyl isocyanate (hereinafter referred to as "MOI") (80 mol% with respect to HEA) was added to the acrylic polymer A, and an addition reaction was carried out at 50 ° C for 48 hours in an air stream. The acrylic polymer A' was obtained by treatment.

繼而,相對於丙烯酸系聚合物A' 100份,加入聚異氰酸酯化合物(商品名「CORONATE L」,Nippon Polyurethane股份有限公司製造)8 份、以及光聚合起始劑(商品名「IRGACURE 651」,Ciba Specialty Chemicals公司製造)5份,製作黏著劑溶液(有時稱為「黏著劑溶液A」)。 Then, a polyisocyanate compound (trade name "CORONATE L", manufactured by Nippon Polyurethane Co., Ltd.) was added to 100 parts of the acrylic polymer A'. 5 parts of a photopolymerization initiator (trade name "IRGACURE 651", manufactured by Ciba Specialty Chemicals Co., Ltd.) was prepared to prepare an adhesive solution (sometimes referred to as "adhesive solution A").

將上述製備之黏著劑溶液A塗佈於PET剝離襯墊之實施有聚矽氧處理之面上,於120℃下進行2分鐘加熱交聯,形成厚度30μm之黏著劑層。繼而,使該黏著劑層面貼合於上述積層基材A之最內層面,於50℃下保存24小時。然後,僅對搭載半導體晶圓之區域使用紫外線照射裝置(日東精機製造,商品名,UM-810),自上述積層基材A側照射300mJ/cm2之紫外線,獲得切割膜(有時稱為「切晶帶A」)。 The adhesive solution A prepared above was applied onto a surface of a PET release liner which was subjected to polyfluorination treatment, and heat-crosslinked at 120 ° C for 2 minutes to form an adhesive layer having a thickness of 30 μm. Then, the adhesive layer was bonded to the innermost layer of the laminated substrate A, and stored at 50 ° C for 24 hours. Then, an ultraviolet ray irradiation device (manufactured by Nitto Seiki Co., Ltd., trade name, UM-810) is used for the region in which the semiconductor wafer is mounted, and ultraviolet rays of 300 mJ/cm 2 are irradiated from the side of the laminated substrate A to obtain a dicing film (sometimes called "Cutting Tape A").

<接著片材之製作> <Next sheet production>

相對於以丙烯酸乙酯-甲基丙烯酸甲酯為主成分之丙烯酸酯系聚合物(商品名「Paracron W-197CM」,根上工業股份有限公司製造):100份,將環氧樹脂(商品名「EPIKOTE 1004」,JER股份有限公司製造):113份、酚樹脂(商品名「Milex XLC-4L」,三井化學股份有限公司製造):121份、球狀二氧化矽(商品名「SO-25R」,ADMATECHS股份有限公司製造):246份、染料1(商品名「OIL GREEN 502」,ORIENT CHEMICAL INDUSTRIES股份有限公司製造):5份、染料2(商品名「OIL BLACK BS」,ORIENT CHEMICAL INDUSTRIES股份有限公司製造):5份溶解於甲基乙基酮中,製備固形物成份濃度為23.6重量%之接著劑組合物溶液A。 An epoxy resin (trade name "product name" is used for 100 parts of acrylate-based polymer (trade name "Paracron W-197CM", manufactured by Gensei Industrial Co., Ltd.) containing ethyl acrylate-methyl methacrylate as a main component. EPIKOTE 1004", manufactured by JER Co., Ltd.): 113 parts, phenol resin (trade name "Milex XLC-4L", manufactured by Mitsui Chemicals, Inc.): 121 parts, spherical cerium oxide (trade name "SO-25R" , manufactured by ADMATECHS Co., Ltd.): 246 parts, dye 1 (trade name "OIL GREEN 502", manufactured by ORIENT CHEMICAL INDUSTRIES Co., Ltd.): 5 parts, dye 2 (trade name "OIL BLACK BS", limited stock of ORIENT CHEMICAL INDUSTRIES Manufactured by the company: 5 parts were dissolved in methyl ethyl ketone to prepare an adhesive composition solution A having a solid content concentration of 23.6% by weight.

將接著劑組合物溶液A塗佈於作為剝離襯墊(分隔件)之由經聚矽氧脫模處理之厚度為50μm之聚對苯二甲酸乙二酯膜形成之脫模處理膜上,然後於130℃下乾燥2分鐘,藉此製作厚度(平均厚度)20μm之接著片材A。 The adhesive composition solution A is applied onto a release-treated film formed of a poly(ethylene terephthalate) film having a thickness of 50 μm which is subjected to polysilicon-oxygen release treatment as a release liner (separator), and then The film was dried at 130 ° C for 2 minutes to prepare a sheet A having a thickness (average thickness) of 20 μm.

<切晶帶一體型接著片材之製作> <Production of dicing tape integrated type and subsequent sheet>

使用手壓輥,將接著片材A貼合於切晶帶A之黏著劑層上,製作 切晶帶一體型接著片材A。 Using the hand roller, the bonding sheet A is attached to the adhesive layer of the dicing tape A, and is produced. The dicing tape integrated type is followed by the sheet A.

(實施例2) (Example 2) <切晶帶之製作> <Production of dicing tape>

首先,製作3層結構之基材。製作依序積層有最外層(厚度:20μm,聚烯烴系基材)、中間層(厚度:40μm,聚烯烴系基材)、及最內層(厚度:40μm,聚烯烴系基材)之基材(有時稱為「積層基材B」)。再者,於最外層中,相對於最外層之全部樹脂成分而含有作為抗靜電劑之製品名:PELESTAT(三洋化成公司製造)25重量%。 First, a substrate having a three-layer structure was produced. The basis of the outermost layer (thickness: 20 μm, polyolefin-based substrate), the intermediate layer (thickness: 40 μm, polyolefin-based substrate), and the innermost layer (thickness: 40 μm, polyolefin-based substrate) were laminated. Material (sometimes referred to as "layered substrate B"). In addition, in the outermost layer, the product name of the antistatic agent was contained in the outermost layer of the outermost layer: PELESTAT (manufactured by Sanyo Chemical Co., Ltd.) of 25% by weight.

作為黏著劑溶液,使用上述黏著劑溶液A。 As the adhesive solution, the above adhesive solution A was used.

將上述製備之黏著劑溶液A塗佈於PET剝離襯墊之實施有聚矽氧處理之面上,於120℃下進行2分鐘加熱交聯,形成厚度30μm之黏著劑層。繼而,使該黏著劑層面與上述積層基材B之最內層面貼合,於50℃下保存24小時。然後,僅對搭載半導體晶圓之區域使用紫外線照射裝置(日東精機製,商品名,UM-810),自上述積層基材B側照射300mJ/cm2之紫外線,獲得切割膜(有時稱為「切晶帶B」)。 The adhesive solution A prepared above was applied onto a surface of a PET release liner which was subjected to polyfluorination treatment, and heat-crosslinked at 120 ° C for 2 minutes to form an adhesive layer having a thickness of 30 μm. Then, the adhesive layer was bonded to the innermost layer of the laminated substrate B, and stored at 50 ° C for 24 hours. Then, an ultraviolet ray irradiation device (Nitto Seiki Co., Ltd., trade name, UM-810) was used for the region in which the semiconductor wafer was mounted, and ultraviolet rays of 300 mJ/cm 2 were irradiated from the side of the laminated substrate B to obtain a dicing film (sometimes called "Cutting Tape B").

<接著片材之製作> <Next sheet production>

作為接著片材,使用與實施例1相同之接著片材A。 As the subsequent sheet, the same sheet A as in Example 1 was used.

<切晶帶一體型接著片材之製作> <Production of dicing tape integrated type and subsequent sheet>

使用手壓輥,將接著片材A貼合於切晶帶B之黏著劑層上,製作切晶帶一體型接著片材B。 The bonding sheet A was bonded to the adhesive layer of the dicing tape B using a hand roll, and a dicing tape-integrated type sheet B was produced.

(實施例3) (Example 3) <切晶帶之製作> <Production of dicing tape>

首先,製作3層結構之基材。製作依序積層有最外層(厚度:20μm,聚烯烴系基材)、中間層(厚度:40μm,聚烯烴系基材)、及最內層(厚度:40μm,聚烯烴系基材)之基材(有時稱為「積層基材C」)。再者,於最外層中,相對於最外層之全部樹脂成分而含有作為抗靜電 劑之製品名:PELESTAT(三洋化成公司製造)20重量%。 First, a substrate having a three-layer structure was produced. The basis of the outermost layer (thickness: 20 μm, polyolefin-based substrate), the intermediate layer (thickness: 40 μm, polyolefin-based substrate), and the innermost layer (thickness: 40 μm, polyolefin-based substrate) were laminated. Material (sometimes referred to as "layered substrate C"). Furthermore, in the outermost layer, it is contained as an antistatic against all the resin components of the outermost layer. Product name of the agent: PELESTAT (manufactured by Sanyo Chemical Co., Ltd.) 20% by weight.

作為黏著劑溶液,使用上述黏著劑溶液A。 As the adhesive solution, the above adhesive solution A was used.

將上述製備之黏著劑溶液A塗佈於PET剝離襯墊之實施有聚矽氧處理之面上,於120℃下進行2分鐘加熱交聯,形成厚度30μm之黏著劑層。繼而,使該黏著劑層面與上述積層基材C之最內層面貼合,於50℃下保存24小時。然後,僅對搭載半導體晶圓之區域使用紫外線照射裝置(日東精機製造,商品名,UM-810),自上述積層基材C側照射300mJ/cm2之紫外線,獲得切割膜(有時稱為「切晶帶C」)。 The adhesive solution A prepared above was applied onto a surface of a PET release liner which was subjected to polyfluorination treatment, and heat-crosslinked at 120 ° C for 2 minutes to form an adhesive layer having a thickness of 30 μm. Then, the adhesive layer was bonded to the innermost layer of the laminated substrate C, and stored at 50 ° C for 24 hours. Then, an ultraviolet ray irradiation device (manufactured by Nitto Seiki Co., Ltd., trade name, UM-810) is used for the region in which the semiconductor wafer is mounted, and ultraviolet rays of 300 mJ/cm 2 are irradiated from the side of the laminated substrate C to obtain a dicing film (sometimes called "Cutting Tape C").

<接著片材之製作> <Next sheet production>

作為接著片材,使用與實施例1相同之接著片材A。 As the subsequent sheet, the same sheet A as in Example 1 was used.

<切晶帶一體型接著片材之製作> <Production of dicing tape integrated type and subsequent sheet>

使用手壓輥,將接著片材A貼合於切晶帶C之黏著劑層上,製作切晶帶一體型接著片材C。 The bonding sheet A was bonded to the adhesive layer of the dicing tape C using a hand roll, and a dicing tape-integrated type sheet C was produced.

(實施例4) (Example 4) <切晶帶之製作> <Production of dicing tape>

首先,製作3層結構之基材。製作依序積層有最外層(厚度:20μm,聚烯烴系基材)、中間層(厚度:40μm,聚烯烴系基材)、及最內層(厚度:40μm,聚烯烴系基材)之基材(有時稱為「積層基材D」)。 First, a substrate having a three-layer structure was produced. The basis of the outermost layer (thickness: 20 μm, polyolefin-based substrate), the intermediate layer (thickness: 40 μm, polyolefin-based substrate), and the innermost layer (thickness: 40 μm, polyolefin-based substrate) were laminated. Material (sometimes referred to as "layered substrate D").

繼而,於最外層上塗佈抗靜電劑層形成用溶液D,然後於60℃下進行1分鐘加熱乾燥,形成厚度約100nm之抗靜電劑層。再者,抗靜電劑層形成用溶液D係使用作為抗靜電劑之製品名:SEPLEGYDA(化合物名:聚噻吩),以1%之濃度分散於甲基乙基酮(MEK)溶劑中而製備。 Then, the antistatic agent layer-forming solution D was applied onto the outermost layer, and then dried by heating at 60 ° C for 1 minute to form an antistatic agent layer having a thickness of about 100 nm. Further, the antistatic agent layer-forming solution D was prepared by using a product name: SEPLEGYDA (Compound Name: Polythiophene) as an antistatic agent, and dispersing it in a methyl ethyl ketone (MEK) solvent at a concentration of 1%.

繼而,作為黏著劑溶液,使用上述黏著劑溶液A。 Then, as the adhesive solution, the above-mentioned adhesive solution A was used.

將上述製備之黏著劑溶液A塗佈於PET剝離襯墊之實施有聚矽氧處理之面上,於120℃下進行2分鐘加熱交聯,形成厚度30μm之黏著 劑層。繼而,使該黏著劑層面與上述積層基材D之最內層面貼合,於50℃下保存24小時。然後,僅對搭載半導體晶圓之區域使用紫外線照射裝置(日東精機製造,商品名,UM-810),自上述積層基材D側照射300mJ/cm2之紫外線,獲得切割膜(有時稱為「切晶帶D」)。該切晶帶D於基材之最外層上形成有抗靜電劑層。 The adhesive solution A prepared above was applied onto a surface of a PET release liner which was subjected to polyfluorination treatment, and heat-crosslinked at 120 ° C for 2 minutes to form an adhesive layer having a thickness of 30 μm. Then, the adhesive layer was bonded to the innermost layer of the laminated substrate D, and stored at 50 ° C for 24 hours. Then, an ultraviolet ray irradiation device (manufactured by Nitto Seiki Co., Ltd., trade name, UM-810) is used for the region in which the semiconductor wafer is mounted, and ultraviolet rays of 300 mJ/cm 2 are irradiated from the side of the laminated substrate D to obtain a dicing film (sometimes called "Cutting Tape D"). The dicing tape D is formed with an antistatic agent layer on the outermost layer of the substrate.

<接著片材之製作> <Next sheet production>

作為接著片材,使用與實施例1相同之接著片材A。 As the subsequent sheet, the same sheet A as in Example 1 was used.

<切晶帶一體型接著片材之製作> <Production of dicing tape integrated type and subsequent sheet>

使用手壓輥,將接著片材A貼合於切晶帶D之黏著劑層上,製作切晶帶一體型接著片材D。 The bonding sheet A was bonded to the adhesive layer of the dicing tape D using a hand roller, and a dicing tape-integrated sheet D was produced.

(實施例5) (Example 5) <切晶帶之製作> <Production of dicing tape>

首先,製作3層結構之基材。製作依序積層有最外層(厚度:20μm,聚烯烴系基材)、中間層(厚度:40μm,聚烯烴系基材)、及最內層(厚度:40μm,聚烯烴系基材)之基材(有時稱為「積層基材E」)。 First, a substrate having a three-layer structure was produced. The basis of the outermost layer (thickness: 20 μm, polyolefin-based substrate), the intermediate layer (thickness: 40 μm, polyolefin-based substrate), and the innermost layer (thickness: 40 μm, polyolefin-based substrate) were laminated. Material (sometimes referred to as "layered substrate E").

繼而,於最外層上塗佈抗靜電劑層形成用溶液E,然後於60℃下進行1分鐘加熱乾燥,形成厚度約50nm之抗靜電劑層。抗靜電劑層形成用溶液E係使用作為抗靜電劑之製品名:SEPLEGYDA(化合物名:聚噻吩),以1%之濃度分散於MEK溶劑中而製備。 Then, the solution E for forming an antistatic agent layer was applied onto the outermost layer, and then dried by heating at 60 ° C for 1 minute to form an antistatic agent layer having a thickness of about 50 nm. The solution E for forming an antistatic agent layer was prepared by using a product name: SEPLEGYDA (Compound Name: Polythiophene) as an antistatic agent, and dispersing it in a MEK solvent at a concentration of 1%.

繼而,作為黏著劑溶液,使用上述黏著劑溶液A。 Then, as the adhesive solution, the above-mentioned adhesive solution A was used.

將上述製備之黏著劑溶液A塗佈於PET剝離襯墊之實施有聚矽氧處理之面上,於120℃下進行2分鐘加熱交聯,形成厚度30μm之黏著劑層。繼而,使該黏著劑層面與上述積層基材E之最內層面貼合,於50℃下保存24小時。然後,僅對搭載半導體晶圓之區域使用紫外線照射裝置(日東精機製造,商品名,UM-810),自上述積層基材E側照射300mJ/cm2之紫外線,獲得切割膜(有時稱為「切晶帶E」)。該切晶帶 E於基材之最外層上形成有抗靜電劑層。 The adhesive solution A prepared above was applied onto a surface of a PET release liner which was subjected to polyfluorination treatment, and heat-crosslinked at 120 ° C for 2 minutes to form an adhesive layer having a thickness of 30 μm. Then, the adhesive layer was bonded to the innermost layer of the laminated substrate E, and stored at 50 ° C for 24 hours. Then, an ultraviolet ray irradiation device (manufactured by Nitto Seiki Co., Ltd., trade name, UM-810) is used for the region in which the semiconductor wafer is mounted, and ultraviolet rays of 300 mJ/cm 2 are irradiated from the side of the laminated substrate E to obtain a dicing film (sometimes called "Cutting Tape E"). The dicing tape E is formed with an antistatic agent layer on the outermost layer of the substrate.

<接著片材之製作> <Next sheet production>

作為接著片材,使用與實施例1相同之接著片材A。 As the subsequent sheet, the same sheet A as in Example 1 was used.

<切晶帶一體型接著片材之製作> <Production of dicing tape integrated type and subsequent sheet>

使用手壓輥,將接著片材A貼合於切晶帶E之黏著劑層上,製作切晶帶一體型接著片材E。 The bonding sheet A was bonded to the adhesive layer of the dicing tape E using a hand roller, and a dicing tape-integrated sheet E was produced.

(實施例6) (Example 6) <切晶帶之製作> <Production of dicing tape>

首先,製作3層結構之基材。製作依序積層有最外層(厚度:20μm,聚烯烴系基材)、中間層(厚度:40μm,聚烯烴系基材)、及最內層(厚度:40μm,聚烯烴系基材)之基材(有時稱為「積層基材F」)。 First, a substrate having a three-layer structure was produced. The basis of the outermost layer (thickness: 20 μm, polyolefin-based substrate), the intermediate layer (thickness: 40 μm, polyolefin-based substrate), and the innermost layer (thickness: 40 μm, polyolefin-based substrate) were laminated. Material (sometimes referred to as "layered substrate F").

繼而,作為黏著劑溶液,使用上述黏著劑溶液A。 Then, as the adhesive solution, the above-mentioned adhesive solution A was used.

將上述製備之黏著劑溶液A塗佈於PET剝離襯墊之實施有聚矽氧處理之面上,於120℃下進行2分鐘加熱交聯,形成厚度30μm之黏著劑層。繼而,使該黏著劑層面與上述積層基材F之最內層面貼合,於50℃下保存24小時。然後,僅對搭載半導體晶圓之區域使用紫外線照射裝置(日東精機製造,商品名,UM-810),自上述積層基材F側照射300mJ/cm2之紫外線,獲得切割膜(有時稱為「切晶帶F」)。 The adhesive solution A prepared above was applied onto a surface of a PET release liner which was subjected to polyfluorination treatment, and heat-crosslinked at 120 ° C for 2 minutes to form an adhesive layer having a thickness of 30 μm. Then, the adhesive layer was bonded to the innermost layer of the laminated substrate F, and stored at 50 ° C for 24 hours. Then, an ultraviolet ray irradiation device (manufactured by Nitto Seiki Co., Ltd., trade name, UM-810) was used for the region in which the semiconductor wafer was mounted, and ultraviolet rays of 300 mJ/cm 2 were irradiated from the side of the laminated substrate F to obtain a dicing film (sometimes called "Cutting Tape F").

<接著片材之製作> <Next sheet production>

相對於以丙烯酸乙酯-甲基丙烯酸甲酯為主成分之丙烯酸酯系聚合物(商品名「Paracron W-197CM」,根上工業股份有限公司製造):100份,將環氧樹脂(商品名「EPIKOTE 1004」,JER股份有限公司製造):113份、酚樹脂(商品名「Milex XLC-4L」,三井化學股份有限公司製造):121份、球狀二氧化矽(商品名「SO-25R」,ADMATECHS股份有限公司製造):246份、染料1(商品名「OIL GREEN 502」,ORIENT CHEMICAL INDUSTRIES股份有限公司製造):5份、染料 2(商品名「OIL BLACK BS」,ORIENT CHEMICAL INDUSTRIES股份有限公司製造):5份、及相對於全部樹脂成分為30重量%之作為抗靜電劑之製品名:PELESTAT(三洋化成公司製造)溶解於甲基乙基酮中,製備固形物成份濃度為23.6重量%(扣除抗靜電劑)之接著劑組合物溶液F。 An epoxy resin (trade name "product name" is used for 100 parts of acrylate-based polymer (trade name "Paracron W-197CM", manufactured by Gensei Industrial Co., Ltd.) containing ethyl acrylate-methyl methacrylate as a main component. EPIKOTE 1004", manufactured by JER Co., Ltd.): 113 parts, phenol resin (trade name "Milex XLC-4L", manufactured by Mitsui Chemicals, Inc.): 121 parts, spherical cerium oxide (trade name "SO-25R" , manufactured by ADMATECHS Co., Ltd.): 246 parts, dye 1 (trade name "OIL GREEN 502", manufactured by ORIENT CHEMICAL INDUSTRIES Co., Ltd.): 5 parts, dye 2 (trade name "OIL BLACK BS", manufactured by ORIENT CHEMICAL INDUSTRIES CO., LTD.): 5 parts and 30% by weight of all resin components as an antistatic agent. Product name: PELESTAT (manufactured by Sanyo Chemical Co., Ltd.) dissolved in In methyl ethyl ketone, an adhesive composition solution F having a solid content concentration of 23.6% by weight (excluding an antistatic agent) was prepared.

將接著劑組合物溶液F塗佈於作為剝離襯墊(分隔件)之由經聚矽氧脫模處理之厚度為50μm之聚對苯二甲酸乙二酯膜形成之脫模處理膜上,然後於130℃下乾燥2分鐘,藉此製作厚度(平均厚度)為20μm,且相對於全部樹脂成分而含有作為抗靜電劑之製品名:PELESTAT(三洋化成公司製造)30重量%之接著片材F。 The adhesive composition solution F is applied onto a release-treated film formed of a polyethylene terephthalate film having a thickness of 50 μm which is subjected to polysilicon oxide release treatment as a release liner (separator), and then After drying at 130 ° C for 2 minutes, the thickness (average thickness) was 20 μm, and the product name of the product as an antistatic agent was contained in an amount of 30% by weight of PELESTAT (manufactured by Sanyo Chemical Co., Ltd.). .

<切晶帶一體型接著片材之製作> <Production of dicing tape integrated type and subsequent sheet>

使用手壓輥,將接著片材F貼合於切晶帶F之黏著劑層上,製作切晶帶一體型接著片材F。 The bonding sheet F was bonded to the adhesive layer of the dicing tape F using a hand roller, and a dicing tape-integrated sheet F was produced.

(實施例7) (Example 7) <切晶帶之製作> <Production of dicing tape>

首先,製作3層結構之基材。製作依序積層有最外層(厚度:20μm,聚烯烴系基材)、中間層(厚度:40μm,聚烯烴系基材)、及最內層(厚度:40μm,聚烯烴系基材)之基材(有時稱為「積層基材G」)。 First, a substrate having a three-layer structure was produced. The basis of the outermost layer (thickness: 20 μm, polyolefin-based substrate), the intermediate layer (thickness: 40 μm, polyolefin-based substrate), and the innermost layer (thickness: 40 μm, polyolefin-based substrate) were laminated. Material (sometimes referred to as "layered substrate G").

繼而,作為黏著劑溶液,使用上述黏著劑溶液A。 Then, as the adhesive solution, the above-mentioned adhesive solution A was used.

將上述製備之黏著劑溶液A塗佈於PET剝離襯墊之實施有聚矽氧處理之面上,於120℃下進行2分鐘加熱交聯,形成厚度30μm之黏著劑層。繼而,使該黏著劑層面與上述積層基材G之最內層面貼合,於50℃下保存24小時。然後,僅對搭載半導體晶圓之區域使用紫外線照射裝置(日東精機製造,商品名,UM-810),自上述積層基材G側照射300mJ/cm2之紫外線,獲得切割膜(有時稱為「切晶帶G」)。 The adhesive solution A prepared above was applied onto a surface of a PET release liner which was subjected to polyfluorination treatment, and heat-crosslinked at 120 ° C for 2 minutes to form an adhesive layer having a thickness of 30 μm. Then, the adhesive layer was bonded to the innermost layer of the laminated substrate G, and stored at 50 ° C for 24 hours. Then, an ultraviolet ray irradiation device (manufactured by Nitto Seiki Co., Ltd., trade name, UM-810) is used for the region in which the semiconductor wafer is mounted, and ultraviolet rays of 300 mJ/cm 2 are irradiated from the side of the laminated substrate G to obtain a dicing film (sometimes called "Cutting Tape G").

<接著片材之製作> <Next sheet production>

相對於以丙烯酸乙酯-甲基丙烯酸甲酯為主成分之丙烯酸酯系聚合物(商品名「Paracron W-197CM」,根上工業股份有限公司製造):100份,將環氧樹脂(商品名「EPIKOTE 1004」,JER股份有限公司製造):113份、酚樹脂(商品名「Milex XLC-4L」,三井化學股份有限公司製造):121份、球狀二氧化矽(商品名「SO-25R」,ADMATECHS股份有限公司製造):246份、染料1(商品名「OIL GREEN 502」,ORIENT CHEMICAL INDUSTRIES股份有限公司製造):5份、染料2(商品名「OIL BLACK BS」,ORIENT CHEMICAL INDUSTRIES股份有限公司製造):5份、及相對於全部樹脂成分為25重量%之作為抗靜電劑之製品名:PELESTAT(三洋化成公司製造)溶解於甲基乙基酮中,製備固形物成份濃度為23.6重量%(扣除抗靜電劑)之接著劑組合物溶液G。 An epoxy resin (trade name "product name" is used for 100 parts of acrylate-based polymer (trade name "Paracron W-197CM", manufactured by Gensei Industrial Co., Ltd.) containing ethyl acrylate-methyl methacrylate as a main component. EPIKOTE 1004", manufactured by JER Co., Ltd.): 113 parts, phenol resin (trade name "Milex XLC-4L", manufactured by Mitsui Chemicals, Inc.): 121 parts, spherical cerium oxide (trade name "SO-25R" , manufactured by ADMATECHS Co., Ltd.): 246 parts, dye 1 (trade name "OIL GREEN 502", manufactured by ORIENT CHEMICAL INDUSTRIES Co., Ltd.): 5 parts, dye 2 (trade name "OIL BLACK BS", limited stock of ORIENT CHEMICAL INDUSTRIES Manufactured by the company: 5 parts, and 25% by weight of the total resin component as an antistatic agent: PELESTAT (manufactured by Sanyo Chemical Co., Ltd.) dissolved in methyl ethyl ketone to prepare a solid content of 23.6 by weight. % (without antistatic agent) of the binder composition solution G.

將接著劑組合物溶液G塗佈於作為剝離襯墊(分隔件)之由經聚矽氧脫模處理之厚度為50μm之聚對苯二甲酸乙二酯膜形成之脫模處理膜上,然後於130℃下乾燥2分鐘,藉此製作厚度(平均厚度)為20μm,且相對於全部樹脂成分而含有作為抗靜電劑之製品名:PELESTAT(三洋化成公司製造)25重量%之接著片材G。 The adhesive composition solution G is applied onto a release-treated film formed of a polyethylene terephthalate film having a thickness of 50 μm which is subjected to polysilicon-oxygen release treatment as a release liner (separator), and then After drying at 130 ° C for 2 minutes, the thickness (average thickness) was 20 μm, and the product name of the product as an antistatic agent was contained in an amount of 25% by weight of PELESTAT (manufactured by Sanyo Chemical Co., Ltd.). .

<切晶帶一體型接著片材之製作> <Production of dicing tape integrated type and subsequent sheet>

使用手壓輥,將接著片材G貼合於切晶帶G之黏著劑層上,製作切晶帶一體型接著片材G。 The bonding sheet G was bonded to the adhesive layer of the dicing tape G using a hand roller, and a dicing tape-integrated sheet G was produced.

(實施例8) (Example 8) <切晶帶一體型接著片材之製作> <Production of dicing tape integrated type and subsequent sheet>

使用手壓輥,將實施例6中製作之接著片材F貼合於實施例1中製作之切晶帶A之黏著劑層上,製作切晶帶一體型接著片材H。 The adhesive sheet F produced in Example 6 was bonded to the adhesive layer of the dicing tape A produced in Example 1 by using a hand roll to prepare a diced tape-integrated sheet H.

(實施例9) (Example 9) <切晶帶一體型接著片材之製作> <Production of dicing tape integrated type and subsequent sheet>

使用手壓輥,將實施例7中製作之接著片材G貼合於實施例2中製作之切晶帶B之黏著劑層上,製作切晶帶一體型接著片材I。 The adhesive sheet G produced in Example 7 was bonded to the adhesive layer of the dicing tape B produced in Example 2 by using a hand roll, and a dicing tape-integrated sheet I was produced.

(實施例10) (Embodiment 10) <切晶帶一體型接著片材之製作> <Production of dicing tape integrated type and subsequent sheet>

使用手壓輥,將實施例6中製作之接著片材F貼合於實施例4中製作之切晶帶D之黏著劑層上,製作切晶帶一體型接著片材J。 The adhesive sheet F produced in Example 6 was bonded to the adhesive layer of the dicing tape D produced in Example 4 by using a hand roll, and a diced tape-integrated sheet J was produced.

(實施例11) (Example 11) <切晶帶之製作> <Production of dicing tape>

首先,製作3層結構之基材。製作依序積層有最外層(厚度:20μm,聚烯烴系基材)、中間層(厚度:40μm,聚烯烴系基材)、及最內層(厚度:40μm,聚烯烴系基材)之基材(有時稱為「積層基材K」)。 First, a substrate having a three-layer structure was produced. The basis of the outermost layer (thickness: 20 μm, polyolefin-based substrate), the intermediate layer (thickness: 40 μm, polyolefin-based substrate), and the innermost layer (thickness: 40 μm, polyolefin-based substrate) were laminated. Material (sometimes referred to as "layered substrate K").

繼而,相對於全部樹脂成分,添加作為抗靜電劑之製品名:PELESTAT(三洋化成公司製造)30重量%,除此以外,以與上述黏著劑溶液A同樣之方式製備黏著劑溶液K。 Then, the adhesive solution K was prepared in the same manner as the above-mentioned adhesive solution A, except that the product name of the antistatic agent: PELESTAT (manufactured by Sanyo Chemical Co., Ltd.) was added in an amount of 30% by weight.

將上述製備之黏著劑溶液K塗佈於PET剝離襯墊之實施有聚矽氧處理之面上,於120℃下進行2分鐘加熱交聯,形成厚度30μm之黏著劑層。繼而,使該黏著劑層面與上述積層基材K之最內層面貼合,於50℃下保存24小時。然後,僅對搭載半導體晶圓之區域使用紫外線照射裝置(日東精機製造,商品名,UM-810),自上述積層基材K側照射300mJ/cm2之紫外線,獲得切割膜(有時稱為「切晶帶K」)。 The adhesive solution K prepared above was applied onto a surface of a PET release liner which was subjected to polyfluorination treatment, and heat-crosslinked at 120 ° C for 2 minutes to form an adhesive layer having a thickness of 30 μm. Then, the adhesive layer was bonded to the innermost layer of the laminated substrate K, and stored at 50 ° C for 24 hours. Then, an ultraviolet ray irradiation device (manufactured by Nitto Seiki Co., Ltd., trade name, UM-810) is used for the region in which the semiconductor wafer is mounted, and ultraviolet rays of 300 mJ/cm 2 are irradiated from the side of the laminated substrate K to obtain a dicing film (sometimes called "Cutting Tape K").

<接著片材之製作> <Next sheet production>

作為接著片材,使用與實施例1相同之接著片材A。 As the subsequent sheet, the same sheet A as in Example 1 was used.

<切晶帶一體型接著片材之製作> <Production of dicing tape integrated type and subsequent sheet>

使用手壓輥,將接著片材A貼合於切晶帶K之黏著劑層上,製作切晶帶一體型接著片材K。 The bonding sheet A was bonded to the adhesive layer of the dicing tape K using a hand roller, and a dicing tape-integrated sheet K was produced.

(實施例12) (Embodiment 12) <切晶帶之製作> <Production of dicing tape>

首先,製作3層結構之基材。製作依序積層有最外層(厚度:20μm,聚烯烴系基材)、中間層(厚度:40μm,聚烯烴系基材)、及最內層(厚度:40μm,聚烯烴系基材)之基材(有時稱為「積層基材L」)。 First, a substrate having a three-layer structure was produced. The basis of the outermost layer (thickness: 20 μm, polyolefin-based substrate), the intermediate layer (thickness: 40 μm, polyolefin-based substrate), and the innermost layer (thickness: 40 μm, polyolefin-based substrate) were laminated. Material (sometimes referred to as "layered substrate L").

繼而,相對於全部樹脂成分,添加作為抗靜電劑之製品名:PELESTAT(三洋化成公司製造)25重量%,除此以外,以與上述黏著劑溶液A同樣之方式製備黏著劑溶液L。 Then, the adhesive solution L was prepared in the same manner as the above-mentioned adhesive solution A, except that the product name of the antistatic agent: PELESTAT (manufactured by Sanyo Chemical Co., Ltd.) was added in an amount of 25% by weight.

將上述製備之黏著劑溶液L塗佈於PET剝離襯墊之實施有聚矽氧處理之面上,於120℃下進行2分鐘加熱交聯,形成厚度30μm之黏著劑層。繼而,使該黏著劑層面與上述積層基材L之最內層面貼合,於50℃下保存24小時。然後,僅對搭載半導體晶圓之區域使用紫外線照射裝置(日東精機製造,商品名,UM-810),自上述積層基材L側照射300mJ/cm2之紫外線,獲得切割膜(有時稱為「切晶帶L」)。 The adhesive solution L prepared above was applied onto a surface of a PET release liner which was subjected to polyfluorination treatment, and heat-crosslinked at 120 ° C for 2 minutes to form an adhesive layer having a thickness of 30 μm. Then, the adhesive layer was bonded to the innermost layer of the laminated substrate L, and stored at 50 ° C for 24 hours. Then, an ultraviolet ray irradiation device (manufactured by Nitto Seiki Co., Ltd., trade name, UM-810) is used for the region in which the semiconductor wafer is mounted, and ultraviolet rays of 300 mJ/cm 2 are irradiated from the laminated substrate L side to obtain a dicing film (sometimes referred to as "Cutting Tape L").

<接著片材之製作> <Next sheet production>

作為接著片材,使用與實施例1相同之接著片材A。 As the subsequent sheet, the same sheet A as in Example 1 was used.

<切晶帶一體型接著片材之製作> <Production of dicing tape integrated type and subsequent sheet>

使用手壓輥,將接著片材A貼合於切晶帶L之黏著劑層上,製作切晶帶一體型接著片材L。 The bonding sheet A was bonded to the adhesive layer of the dicing tape L using a hand roller, and a dicing tape-integrated sheet L was produced.

(實施例13) (Example 13)

將基材之最外層所含有之抗靜電劑之量變更為相對於最外層之全部樹脂成分為5重量%,除此以外,以與實施例1同樣之方式製作本實施例13之切晶帶一體型接著片材。將其作為切晶帶一體型接著片材M。 The dicing tape of the present Example 13 was produced in the same manner as in Example 1 except that the amount of the antistatic agent contained in the outermost layer of the substrate was changed to 5% by weight based on the total resin component of the outermost layer. The integrated type is followed by a sheet. This was taken as a dicing tape-integrated type sheet M.

(實施例14) (Example 14)

將基材之最外層所含有之抗靜電劑之量變更為相對於最外層之全部樹脂成分為10重量%,除此以外,以與實施例1同樣之方式製作 本實施例14之切晶帶一體型接著片材。將其作為切晶帶一體型接著片材N。 The same procedure as in Example 1 was carried out except that the amount of the antistatic agent contained in the outermost layer of the substrate was changed to 10% by weight based on the total resin component of the outermost layer. The diced tape-integrated type of the sheet of Example 14 was followed by a sheet. This was taken as a dicing tape-integrated type sheet N.

(實施例15) (Example 15)

將基材之最外層所含有之抗靜電劑之量變更為相對於最外層之全部樹脂成分為50重量%,除此以外,以與實施例1同樣之方式製作本實施例15之切晶帶一體型接著片材。將其作為切晶帶一體型接著片材O。 The dicing tape of the fifteenth embodiment was produced in the same manner as in the first embodiment except that the amount of the antistatic agent contained in the outermost layer of the substrate was changed to 50% by weight based on the total resin component of the outermost layer. The integrated type is followed by a sheet. This was taken as a dicing tape-integrated type followed by a sheet O.

(實施例16) (Embodiment 16)

將抗靜電劑層之厚度形成為約20nm,除此以外,以與實施例4同樣之方式製作本實施例16之切晶帶一體型接著片材。將其作為切晶帶一體型接著片材P。 A diced tape-integrated sheet of the present Example 16 was produced in the same manner as in Example 4 except that the thickness of the antistatic agent layer was changed to about 20 nm. This was taken as a dicing tape-integrated type sheet P.

(實施例17) (Example 17)

將抗靜電劑層之厚度形成為約150nm,除此以外,以與實施例4同樣之方式製作本實施例17之切晶帶一體型接著片材。將其作為切晶帶一體型接著片材Q。 A diced tape-integrated sheet of the present Example 17 was produced in the same manner as in Example 4 except that the thickness of the antistatic agent layer was changed to about 150 nm. This was taken as a dicing tape-integrated type and then a sheet Q.

(實施例18) (Embodiment 18)

將接著片材所含有之抗靜電劑之量設為相對於接著片材之全部樹脂成分為5重量%,除此以外,以與實施例6同樣之方式製作本實施例18之切晶帶一體型接著片材。將其作為切晶帶一體型接著片材R。 The dicing tape of the ninth embodiment was produced in the same manner as in Example 6 except that the amount of the antistatic agent contained in the sheet was 5% by weight based on the total resin component of the sheet. The body shape follows the sheet. This was taken as a dicing tape-integrated type of sheet R.

(實施例19) (Embodiment 19)

將接著片材所含有之抗靜電劑之量設為相對於接著片材之全部樹脂成分為10重量%,除此以外,以與實施例6同樣之方式製作本實施例19之切晶帶一體型接著片材。將其作為切晶帶一體型接著片材S。 A dicing tape of the present Example 19 was produced in the same manner as in Example 6 except that the amount of the antistatic agent contained in the sheet was 10% by weight based on the total resin component of the sheet. The body shape follows the sheet. This was taken as a dicing tape-integrated type sheet S.

(實施例20) (Embodiment 20)

將接著片材所含有之抗靜電劑之量設為相對於接著片材之全部 樹脂成分為50重量%,除此以外,以與實施例6同樣之方式製作本實施例20之切晶帶一體型接著片材。將其作為切晶帶一體型接著片材T。 The amount of the antistatic agent contained in the subsequent sheet is set to be relative to the entire sheet. A diced tape-integrated sheet of the present Example 20 was produced in the same manner as in Example 6 except that the resin component was 50% by weight. This was taken as a dicing tape-integrated type sheet T.

(實施例21) (Example 21) <切晶帶之製作> <Production of dicing tape>

首先,製作3層結構之基材。製作依序積層有最外層(厚度:20μm,聚烯烴系基材)、中間層(厚度:40μm,聚烯烴系基材)、及最內層(厚度:40μm,聚烯烴系基材)之基材(有時稱為「積層基材U」)。 First, a substrate having a three-layer structure was produced. The basis of the outermost layer (thickness: 20 μm, polyolefin-based substrate), the intermediate layer (thickness: 40 μm, polyolefin-based substrate), and the innermost layer (thickness: 40 μm, polyolefin-based substrate) were laminated. (sometimes referred to as "layered substrate U").

繼而,相對於全部樹脂成分添加作為抗靜電劑之製品名:PELESTAT(三洋化成公司製造)5重量%,除此以外,以與上述黏著劑溶液A同樣之方式製備黏著劑溶液U。 Then, the adhesive solution U was prepared in the same manner as the above-mentioned adhesive solution A except that the product name of the antistatic agent: PELESTAT (manufactured by Sanyo Chemical Co., Ltd.) was added in an amount of 5% by weight.

將上述製備之黏著劑溶液U塗佈於PET剝離襯墊之實施有聚矽氧處理之面上,於120℃下進行2分鐘加熱交聯,形成厚度30μm之黏著劑層。繼而,使該黏著劑層面與上述積層基材U之最內層面貼合,於50℃下保存24小時。然後,僅對搭載半導體晶圓之區域使用紫外線照射裝置(日東精機製造,商品名,UM-810),自上述積層基材U側照射300mJ/cm2之紫外線,獲得切割膜(有時稱為「切晶帶U」)。 The adhesive solution U prepared above was applied onto a surface of a PET release liner which was subjected to polyfluorination treatment, and heat-crosslinked at 120 ° C for 2 minutes to form an adhesive layer having a thickness of 30 μm. Then, the adhesive layer was bonded to the innermost layer of the laminated substrate U, and stored at 50 ° C for 24 hours. Then, an ultraviolet ray irradiation device (manufactured by Nitto Seiki Co., Ltd., trade name, UM-810) is used for the region in which the semiconductor wafer is mounted, and ultraviolet rays of 300 mJ/cm 2 are irradiated from the side of the laminated substrate U to obtain a dicing film (sometimes called "Cutting Tape U").

<接著片材之製作> <Next sheet production>

作為接著片材,使用與實施例1相同之接著片材A。 As the subsequent sheet, the same sheet A as in Example 1 was used.

<切晶帶一體型接著片材之製作> <Production of dicing tape integrated type and subsequent sheet>

使用手壓輥,將接著片材A貼合於切晶帶U之黏著劑層上,製作切晶帶一體型接著片材U。 The bonding sheet A was bonded to the adhesive layer of the dicing tape U using a hand roller, and a dicing tape-integrated sheet U was produced.

(實施例22) (Example 22) <切晶帶之製作> <Production of dicing tape>

首先,製作3層結構之基材。製作依序積層有最外層(厚度:20μm,聚烯烴系基材)、中間層(厚度:40μm,聚烯烴系基材)、及最內 層(厚度:40μm,聚烯烴系基材)之基材(有時稱為「積層基材V」)。 First, a substrate having a three-layer structure was produced. The outermost layer (thickness: 20 μm, polyolefin-based substrate), intermediate layer (thickness: 40 μm, polyolefin-based substrate), and innermost layer are sequentially laminated. A substrate (thickness: 40 μm, polyolefin-based substrate) (sometimes referred to as "laminated substrate V").

繼而,相對於全部樹脂成分添加作為抗靜電劑之製品名:PELESTAT(三洋化成公司製造)10重量%,除此以外,以與上述黏著劑溶液A同樣之方式製備黏著劑溶液V。 Then, the adhesive solution V was prepared in the same manner as the above-mentioned adhesive solution A except that the product name of the antistatic agent: PELESTAT (manufactured by Sanyo Chemical Co., Ltd.) was added in an amount of 10% by weight.

將上述製備之黏著劑溶液V塗佈於PET剝離襯墊之實施有聚矽氧處理之面上,於120℃下進行2分鐘加熱交聯,形成厚度30μm之黏著劑層。繼而,使該黏著劑層面與上述積層基材V之最內層面貼合,於50℃下保存24小時。然後,僅對搭載半導體晶圓之區域使用紫外線照射裝置(日東精機製造,商品名,UM-810),自上述積層基材V側照射300mJ/cm2之紫外線,獲得切割膜(有時稱為「切晶帶V」)。 The adhesive solution V prepared above was applied onto a surface of a PET release liner which was subjected to polyfluorination treatment, and heat-crosslinked at 120 ° C for 2 minutes to form an adhesive layer having a thickness of 30 μm. Then, the adhesive layer was bonded to the innermost layer of the laminated substrate V, and stored at 50 ° C for 24 hours. Then, an ultraviolet ray irradiation device (manufactured by Nitto Seiki Co., Ltd., trade name, UM-810) is used for the region in which the semiconductor wafer is mounted, and ultraviolet rays of 300 mJ/cm 2 are irradiated from the side of the laminated substrate V to obtain a dicing film (sometimes called "Cutting Tape V").

<接著片材之製作> <Next sheet production>

作為接著片材,使用與實施例1相同之接著片材A。 As the subsequent sheet, the same sheet A as in Example 1 was used.

<切晶帶一體型接著片材之製作> <Production of dicing tape integrated type and subsequent sheet>

使用手壓輥,將接著片材A貼合於切晶帶V之黏著劑層上,製作切晶帶一體型接著片材V。 The bonding sheet A was bonded to the adhesive layer of the dicing tape V using a hand roll, and a dicing tape-integrated type sheet V was produced.

(實施例23) (Example 23) <切晶帶之製作> <Production of dicing tape>

首先,製作3層結構之基材。製作依序積層有最外層(厚度:20μm,聚烯烴系基材)、中間層(厚度:40μm,聚烯烴系基材)、及最內層(厚度:40μm,聚烯烴系基材)之基材(有時稱為「積層基材W」)。 First, a substrate having a three-layer structure was produced. The basis of the outermost layer (thickness: 20 μm, polyolefin-based substrate), the intermediate layer (thickness: 40 μm, polyolefin-based substrate), and the innermost layer (thickness: 40 μm, polyolefin-based substrate) were laminated. Material (sometimes referred to as "layered substrate W").

繼而,相對於全部樹脂成分添加作為抗靜電劑之製品名:PELESTAT(三洋化成公司製造)50重量%,除此以外,以與上述黏著劑溶液A同樣之方式製備黏著劑溶液W。 Then, the adhesive solution W was prepared in the same manner as the above-mentioned adhesive solution A except that the product name of the antistatic agent was changed to 50% by weight of PELESTAT (manufactured by Sanyo Chemical Co., Ltd.).

將上述製備之黏著劑溶液W塗佈於PET剝離襯墊之實施有聚矽氧處理之面上,於120℃下進行2分鐘加熱交聯,形成厚度30μm之黏著劑層。繼而,使該黏著劑層面與上述積層基材W之最內層面貼合,於 50℃下保存24小時。然後,僅對搭載半導體晶圓之區域使用紫外線照射裝置(日東精機製造,商品名,UM-810),自上述積層基材W側照射300mJ/cm2之紫外線,獲得切割膜(有時稱為「切晶帶W」)。 The adhesive solution W prepared above was applied onto a surface of a PET release liner which was subjected to polyfluorination treatment, and heat-crosslinked at 120 ° C for 2 minutes to form an adhesive layer having a thickness of 30 μm. Then, the adhesive layer was bonded to the innermost layer of the laminated substrate W, and stored at 50 ° C for 24 hours. Then, an ultraviolet ray irradiation device (manufactured by Nitto Seiki Co., Ltd., trade name, UM-810) is used for the region in which the semiconductor wafer is mounted, and ultraviolet rays of 300 mJ/cm 2 are irradiated from the side of the laminated substrate W to obtain a dicing film (sometimes called "Cutting Tape W").

<接著片材之製作> <Next sheet production>

作為接著片材,使用與實施例1相同之接著片材A。 As the subsequent sheet, the same sheet A as in Example 1 was used.

<切晶帶一體型接著片材之製作> <Production of dicing tape integrated type and subsequent sheet>

使用手壓輥,將接著片材A貼合於切晶帶W之黏著劑層上,製作切晶帶一體型接著片材W。 The bonding sheet A was bonded to the adhesive layer of the dicing tape W using a hand roller, and a dicing tape-integrated sheet W was produced.

<剝離靜電壓之測定> <Measurement of peeling static voltage>

將切晶帶一體型接著片材貼合於經預先除電之丙烯酸系板(厚度:1mm,寬度:70mm,長度:100mm)上。於貼合時,使用手壓輥,以使丙烯酸系板與切晶帶一體型接著片材之基材介隔雙面膠帶相對之方式進行。 The diced tape-integrated sheet was attached to a pre-removed acrylic plate (thickness: 1 mm, width: 70 mm, length: 100 mm). At the time of bonding, a hand roller is used so that the acrylic plate and the substrate of the dicing tape-integrated sheet are opposed to each other by a double-sided tape.

於23℃、50%RH之環境下放置一天,然後於特定之位置設置樣品(參照圖2)。將接著片材之端部固定於自動捲取機,以剝離角度成為150°、剝離速度成為10m/min之方式進行剝離。藉由固定於特定之位置之電位測定機(春日電機公司製造,KSD-0103)測定此時產生之黏著劑層側之面之電位。測定係於23℃、50%RH之環境下進行。將結果示於表1。 Place in a 23 ° C, 50% RH environment for one day, and then set the sample at a specific location (refer to Figure 2). The end portion of the succeeding sheet was fixed to an automatic reel, and peeling was performed so that the peeling angle was 150° and the peeling speed was 10 m/min. The potential of the surface on the side of the adhesive layer generated at this time was measured by a potential measuring machine (KSD-0103, manufactured by Kasuga Electric Co., Ltd.) fixed at a specific position. The measurement was carried out in an environment of 23 ° C and 50% RH. The results are shown in Table 1.

<剝離力之測定> <Measurement of peeling force>

自切晶帶一體型接著片材切出長度100mm、寬度20mm之短條狀之試驗片。將該試驗片襯裏於SUS板,然後使用剝離試驗機(商品名「Autograph AGS-J」,島津製作所公司製造),於溫度23℃之條件下,且於剝離角度:90°、拉伸速度:300mm/min之條件下,自切晶帶(即,自切晶帶之黏著劑層)撕拉剝離(於接著片材與切晶帶之黏著劑層之界面剝離)接著片材,測定該撕拉剝離時之荷重之最大荷重(扣除 測定初期之峰頂的荷重之最大值),將該最大荷重作為接著片材與切晶帶之黏著劑層間之剝離力(切晶帶之黏著劑層之對接著片材之接著力)(接著力:N/20mm寬)求出。將結果示於表1。 A strip of test piece having a length of 100 mm and a width of 20 mm was cut out from the dicing tape-integrated sheet. The test piece was lining the SUS plate, and then using a peeling tester (trade name "Autograph AGS-J", manufactured by Shimadzu Corporation) at a temperature of 23 ° C, and at a peeling angle of 90 °, a stretching speed: Under the condition of 300 mm/min, the self-cutting tape (ie, the adhesive layer from the dicing tape) is peeled and peeled off (the interface between the sheet and the adhesive layer of the dicing tape is peeled off), and then the sheet is determined. The maximum load of the load when peeling off (deduction Measuring the maximum value of the load at the peak of the initial peak), the maximum load is used as the peeling force between the adhesive layer of the sheet and the dicing tape (the adhesion of the adhesive layer of the dicing tape to the bonding force of the sheet) (continued) Force: N/20mm width). The results are shown in Table 1.

<表面電阻率值之測定> <Measurement of surface resistivity value>

對於實施例1~5、以及13~17,測定切晶帶最外層側之表面之表面電阻率;對於實施例6、7、以及18~20,測定接著片材之與切晶帶接觸之側之面之表面之表面電阻率;對於實施例8、9、10,測定切晶帶最外層、晶圓背面保護膜之與切晶帶接觸之側之表面之表面電阻率;對於實施例11、12、以及21~23,測定切晶帶之黏著劑層表面之表面電阻率。再者,表面電阻率係使用ADVANTEST公司製造之High Megohm meter TR-8601之超高電阻測定用試樣箱TR-42,於23℃、60%RH之條件下施加1分鐘100V之直流電壓而測定。將結果示於表1。 For Examples 1 to 5 and 13 to 17, the surface resistivity of the surface on the outermost layer side of the dicing tape was measured; for Examples 6, 7, and 18 to 20, the side of the sheet in contact with the dicing tape was measured. The surface resistivity of the surface of the surface; for Examples 8, 9, and 10, the surface resistivity of the outermost layer of the dicing tape and the surface of the wafer back surface protective film on the side in contact with the dicing tape was measured; 12, and 21 to 23, the surface resistivity of the surface of the adhesive layer of the dicing tape was measured. In addition, the surface resistivity was measured by using a high-resistance measurement sample box TR-42 of High Megohm meter TR-8601 manufactured by ADVANTEST Co., Ltd., and applying a DC voltage of 100 V for 1 minute under conditions of 23 ° C and 60% RH. . The results are shown in Table 1.

1‧‧‧切晶帶一體型半導體背面用膜 1‧‧‧Cutting Tape Integrated Semiconductor Backside Film

2‧‧‧倒裝晶片型半導體背面用膜(半導體背面用膜) 2‧‧‧Flip-chip type semiconductor back surface film (film for semiconductor back surface)

3‧‧‧切晶帶 3‧‧‧Cutting Tape

31‧‧‧基材 31‧‧‧Substrate

32‧‧‧黏著劑層 32‧‧‧Adhesive layer

33‧‧‧與半導體晶圓之貼著部分對應之部分 33‧‧‧Parts corresponding to the adhesive portion of the semiconductor wafer

Claims (9)

一種切晶帶一體型接著片材,其特徵在於,其係包含於基材上積層有黏著劑層之切晶帶、及形成於上述黏著劑層上之接著片材者,且於剝離速度10m/min、剝離角度150°之剝離試驗中,上述黏著劑層與上述接著片材之剝離力為0.02~0.5N/20mm,根據上述剝離試驗之條件,將上述黏著劑層與上述接著片材剝離時之剝離靜電壓之絕對值為0.5kV以下。 A dicing tape-integrated splicing sheet, which comprises a dicing tape having an adhesive layer laminated on a substrate, and a subsequent sheet formed on the adhesive layer, and the peeling speed is 10 m. In the peeling test of /min and the peeling angle of 150°, the peeling force of the adhesive layer and the adhesive sheet was 0.02 to 0.5 N/20 mm, and the adhesive layer was peeled off from the adhesive sheet according to the conditions of the peeling test. The absolute value of the peeling static voltage at this time is 0.5 kV or less. 如請求項1之切晶帶一體型接著片材,其中上述接著片材為用於在倒裝晶片連接於被黏著體上之半導體元件之背面形成之倒裝晶片型半導體背面用膜。 The dicing tape-integrated lining sheet of claim 1, wherein the contiguous sheet is a film for flip chip type semiconductor back surface formed on a back surface of a semiconductor element to which a flip chip is attached to an adherend. 如請求項1之切晶帶一體型接著片材,其中於上述基材中含有抗靜電劑。 A dicing tape-integrated sheet according to claim 1, wherein the substrate contains an antistatic agent. 如請求項3之切晶帶一體型接著片材,其中上述基材具有多層結構,且於上述多層結構之基材之至少一個最外層中含有抗靜電劑。 The dicing tape-integrated lining sheet of claim 3, wherein the substrate has a multilayer structure, and an antistatic agent is contained in at least one outermost layer of the substrate of the multilayer structure. 如請求項1之切晶帶一體型接著片材,其中於上述基材之至少一個面上形成有含有抗靜電劑之抗靜電劑層。 A dicing tape-integrated sheet according to claim 1, wherein an antistatic agent layer containing an antistatic agent is formed on at least one surface of the substrate. 如請求項1之切晶帶一體型接著片材,其中於上述黏著劑層中含有抗靜電劑。 A dicing tape-integrated sheet according to claim 1, wherein the adhesive layer contains an antistatic agent. 如請求項1之切晶帶一體型接著片材,其中於上述接著片材中含有抗靜電劑。 A dicing tape-integrated sheet according to claim 1, wherein the above-mentioned succeeding sheet contains an antistatic agent. 一種半導體裝置之製造方法,其特徵在於,其係使用如請求項1至7中任一項之切晶帶一體型接著片材之半導體裝置之製造方法,且包括如下步驟: 於上述切晶帶一體型接著片材中之接著片材上貼著半導體晶圓之步驟;切割上述半導體晶圓而形成半導體元件之步驟;及將上述半導體元件與上述接著片材一起自切晶帶之黏著劑層拾取之步驟。 A method of manufacturing a semiconductor device using the method of manufacturing a semiconductor device of a dicing tape-integrated sheet according to any one of claims 1 to 7, and comprising the steps of: a step of attaching a semiconductor wafer to the subsequent sheet in the dicing tape-integrated sheet; cutting the semiconductor wafer to form a semiconductor element; and self-cutting the semiconductor element together with the succeeding sheet The step of picking up the adhesive layer. 一種半導體裝置,其特徵在於,其係使用如請求項1至7中任一項之切晶帶一體型接著片材而製造。 A semiconductor device manufactured using the diced tape-integrated lining sheet according to any one of claims 1 to 7.
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TWI666293B (en) * 2014-08-07 2019-07-21 日商藤森工業股份有限公司 Surface-protective film for transparent conductive film, and transparent conductive film using the same
TWI708825B (en) * 2017-12-14 2020-11-01 南韓商Lg化學股份有限公司 Dicing die-bonding film
TWI715586B (en) * 2015-05-27 2021-01-11 日商日東電工股份有限公司 Dicing wafer bonding film, manufacturing method of semiconductor device, and semiconductor device
TWI821492B (en) * 2018-12-25 2023-11-11 日商積水化學工業股份有限公司 Adhesive tape

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JP2003306654A (en) * 2002-04-16 2003-10-31 Furukawa Electric Co Ltd:The Radiation-curable adhesive tape
JP4275522B2 (en) * 2003-12-26 2009-06-10 日東電工株式会社 Dicing die bond film

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI666293B (en) * 2014-08-07 2019-07-21 日商藤森工業股份有限公司 Surface-protective film for transparent conductive film, and transparent conductive film using the same
TWI690583B (en) * 2014-08-07 2020-04-11 日商藤森工業股份有限公司 Surface-protective film for transparent conductive film, and transparent conductive film using the same
TWI715586B (en) * 2015-05-27 2021-01-11 日商日東電工股份有限公司 Dicing wafer bonding film, manufacturing method of semiconductor device, and semiconductor device
TWI708825B (en) * 2017-12-14 2020-11-01 南韓商Lg化學股份有限公司 Dicing die-bonding film
US11404301B2 (en) 2017-12-14 2022-08-02 Lg Chem, Ltd. Dicing die-bonding film
TWI821492B (en) * 2018-12-25 2023-11-11 日商積水化學工業股份有限公司 Adhesive tape

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