TW201426915A - 利用簡化的一次頂部接觸溝槽刻蝕製備mosfet與肖特基二極體集成的方法 - Google Patents

利用簡化的一次頂部接觸溝槽刻蝕製備mosfet與肖特基二極體集成的方法 Download PDF

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TW201426915A
TW201426915A TW102147567A TW102147567A TW201426915A TW 201426915 A TW201426915 A TW 201426915A TW 102147567 A TW102147567 A TW 102147567A TW 102147567 A TW102147567 A TW 102147567A TW 201426915 A TW201426915 A TW 201426915A
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Ji Pan
Daniel Ng
Sung-Shan Tai
Anup Bhalla
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Alpha & Omega Semiconductor
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Abstract

本發明公開了用於製備與肖特基二極體集成的MOSFET的方法。閘極溝槽形成在與半導體襯底重疊的外延層中，閘極材料沉積在其中。本體、源極、電介質區相繼形成在外延層和閘極溝槽上方。刻蝕頂部接觸溝槽，垂直側壁限定了肖特基二極體剖面寬度肖特基二極體剖面寬度，透過電介質和源極區限定了源極-接觸深度；部分深入到本體區中，其深度為總本體-接觸深度。在頂部接觸溝槽側壁中和源極-接觸深度以下，製備重摻雜嵌入式本體注入區。在頂部接觸溝槽底面下方的子接觸溝槽區中，製備一個嵌入式香農注入區。製備一個金屬層，與嵌入式香農注入區、本體和源極區相接觸。金屬層還填充頂部接觸溝槽並且覆蓋電介質區，從而僅僅透過一次刻蝕頂部接觸溝槽，就完成了MOSFET/SKY。

Description

利用簡化的一次頂部接觸溝槽刻蝕製備MOSFET與肖特基二極體集成的方法
本發明係一種半導體器件結構領域。更確切地說，本發明係有關於一種MOSFET器件與肖特基二極體集成（MOSFET/SKY）的製備方法。
美國專利（申請號：11/056,346，主題名稱為“功率MOS器件”）提出了一種半導體MOSFET器件及其製備方法，其中閘極溝槽穿過其源極和本體延伸到汲極中，閘極沉積在閘極溝槽中，源極本體接觸溝槽具有一個溝槽壁和防穿通注入物，防穿通注入物沿溝槽壁沉積。對應閘極溝槽和源極本體接觸溝槽，器件的製備過程需要進行兩次接觸刻蝕。
美國專利（申請號：12/005,146，主題名稱為“在主動區接觸溝槽中與肖特基二極體集成的MOS器件”）提出了一種形成在半導體襯底上的半導體MOSFET器件及其製備方法。該器件包括一個汲極、一個覆蓋著汲極的外延層以及一個主動區。有源區包括一個閘極溝槽，延伸到外延層中，以及一個主動區接觸溝槽，穿過MOSFET源極延伸，至少一部分MOSFET本體延伸到汲極中。如第4O圖（第一接觸刻蝕）和第4R圖（第二接觸刻蝕）所示，並參照12/005,146中的說明，器件的製備需要兩次接觸刻蝕。
美國專利（申請號：12/005,166，主題名稱為“帶有肖特基勢壘控制層的MOS器件”）提出了一種MOS器件與集成肖特基勢壘控制層，美國專利（申請號：12/005,130，主題名稱為“帶有低注入二極體的MOS器件”）提出了一種MOS器件與集成低注入二極體。
因此，雖然本領域中已知MOSFET器件與肖特基二極體集成（MOSFET/SKY）的結構，但是本發明主要涉及其簡化後的製備方法，所製備的器件具有更加穩定的器件性能。更確切地說，對於本領域的技術人員來說，接觸刻蝕引起的基本溝槽形狀公差在+/-10%左右是常見的。多次接觸刻蝕過程以及複雜的製備技術，與單獨的接觸刻蝕相比，會增加從而加劇已有的基本溝槽形狀公差。因此，本發明提出利用簡化後的一次頂部接觸溝槽刻蝕，製備MOSFET/SKY。
本發明的目的是提供一種已知MOSFET器件與肖特基二極體集成（MOSFET/SKY）的結構簡化後的製備方法，僅僅透過一次刻蝕頂部接觸溝槽製備MOSFET/SKY，所製備的器件具有更加穩定的器件性能。
為達到上述目的，本發明提供了一種用於與肖特基二極體集成的MOSFET（MOSFET/SKY）的製備方法，用X-Y-Z笛卡爾坐標系表示，X-Y平面平行於其主半導體晶片平面，該方法包括：
a) 在與半導體襯底重疊的外延層中，製備一個閘極溝槽，並且在其中沉積閘極材料；
b) 在外延層中，製備一個本體區，在本體區上方製備一個源極區，在閘極溝槽和源極區上方，製備一個電介質區；
c) 刻蝕頂部接觸溝槽(TCT)，其垂直側壁限定了肖特基二極體剖面寬度SDCW：其中,
c1）頂部接觸溝槽透過電介質區和源極區，從而定義了一個源極-接觸深度(SCD)；並且
c2）頂部接觸溝槽部分深入到本體區中預定的一個總本體-接觸深度(TBCD)；
d) 製備：
d1）在頂部接觸溝槽及源極-接觸深度以下的側壁中，製備一個重摻雜嵌入式本體注入區(EBIR)，其有一本體-接觸深度(BCD)<總本體-接觸深度(TBCD)；並且
d2）在頂部接觸溝槽底面下方的子接觸溝槽區(SCTZ)中，製備一個嵌入式香農注入區(ESIR, embedded Shannon implant region)；並且
e) 製備一個金屬層：
e1）與嵌入式香農注入區、本體區以及源極區接觸；並且
e2）填充頂部接觸溝槽，並且覆蓋電介質區
從而僅僅透過一次刻蝕頂部接觸溝槽，就完成了與肖特基二極體集成的MOSFET的製備。
上述的方法，其中，製備重摻雜的嵌入式本體注入區和嵌入式香農注入區包括：
d11）注入重摻雜嵌入式本體注入區，同時保持子接觸溝槽區不含任何伴生本體-接觸注入物；並且
d21） 在子接觸溝槽區中注入嵌入式香農注入區。
上述的方法，其中，注入重摻雜嵌入式本體注入區，同時保持子接觸溝槽區不含任何伴生本體-接觸注入物包括：
d111) 在頂部接觸溝槽的側壁上，製備水平壁厚為HWTLS的較低隔片子層（LSSL），在頂部接觸溝槽的底面上和電介質區上，較低隔片子層的垂直壁厚為VWTLS，其中VWTLS與HWTLS基本相等；
d112) 在較低隔片子層上，製備一個上部隔片子層(USSL)，在頂部接觸溝槽的側壁上方上部隔片子層具有水平壁厚HWTUS，在頂部接觸溝槽的底面上方，上部隔片子層具有一個底部垂直壁厚（LVWTUS），在電介質區上方，上部隔片子層具有一個上部垂直壁厚（UVWTUS），其中UVWTUS與HWTUS基本相等，且LVWTUS>>HWTUS；
d113) 選擇較低隔片子層材料和上部隔片子層材料使：
較低隔片子層會使之後的本體-注入束通過傳輸，然而上部隔片子層憑藉較大的層厚，會阻止之後的本體-注入束通過傳輸；並且
較低隔片子層作為後續的上部隔片子層-刻蝕過程的刻蝕終點；
d114) 本體-注入束與Z軸呈本體-注入傾斜角BITA，透過HWTUS + HWTLS的組合壁厚，注入重摻雜嵌入式本體注入區，同時，由於LVWTU S >> HWTUS的關係，保持子接觸溝槽區不含任何伴生的本體-接觸注入物，從而避免因伴生的本體-接觸注入物在子接觸溝槽區中橋接嵌入式本體注入區而必須使用一個額外刻蝕過程加以除去；並且
d115) 接下來透過上部隔片子層-刻蝕技術和較低隔片子層-刻蝕技術，除去上部隔片子層和較低隔片子層。
上述的方法，其中，LVWTUS>3*HWTUS。
上述的方法，其中：
較低隔片子層材料為氮化矽，上部隔片子層材料為高密度等離子沉積氧化矽（HDPSO）；
VWTLS為100至500埃；
UVWTUS小於0.1微米，而LVWTUS為0.3至0.4微米；並且
本體-注入傾斜角為15至30度。
上述的方法，其中，在子接觸溝槽區中注入嵌入式香農注入區包括透過香農-注入束，在與Z軸呈香農注入傾斜角(SITA)的方向上，將嵌入式香農注入區注入到子接觸溝槽區中。
上述的方法，其中，香農注入傾斜角為7度至15度。
上述的方法，其中，製備金屬層包括沉積鈦/氮化鈦（Ti/TiN），製備矽化鈦，並且填充金屬層。
本發明僅僅透過一次刻蝕頂部接觸溝槽，就完成了MOSFET/SKY；該技術相對於多次接觸刻蝕過程以及複雜的製備技術，能降低已有的基本溝槽形狀公差；所製備的器件具有更加穩定的器件性能。
5．．．肖特基二極體
103．．．半導體襯底
104．．．N--半導體的外延層
111．．．閘極溝槽
113．．．閘極溝槽
115．．．閘極溝槽
121．．．閘極氧化層
131、133、135．．．閘極
160．．．電介質材料層
112a．．．溝槽
150b-150c．．．源極區
140b-140c．．．本體區
117．．．閘極接觸溝槽
172a．．．金屬層
111、113、115．．．閘極溝槽
133、135．．．主動閘極
172b．．．金屬層
642．．．勢壘層
170b-170c．．．P+-型區域
170a．．．P+-型區域
720a．．．嵌入式P-型香農注入區
720b．．．嵌入式P-型香農注入區
652．．．肖特基二極體
140a,140b、140c、140d、140e．．．本體區
150a、150b、150c、150d．．．源極區
362．．．氧化層
150a、150bc、150d．．．源極區
700a、700b．．．溝槽
150bc．．．源極區
720a、720b．．．嵌入式香農注入區
710a、710b．．．本體注入區
620．．．較低隔片子層
160a、160b、160c．．．絕緣區
622．．．上部隔片子層
616．．．本體-注入束
640．．．金屬層
642．．．勢壘層
652．．．肖特基二極體
參見附圖，提出了本發明的多種實施例。然而，這些附圖僅用於解釋說明，並不用於局限本發明的範圍。
第1圖係為MOSFET/SKY器件的平面剖面圖；以及
第2A-2H圖係為用於製備第1圖所示的MOSFET/SKY器件本發明提出的技術步驟。
以下結合實施例與附圖對本發明的技術方案作進一步地說明。
上述說明及所含附圖僅涉及本發明的一個或多個現有較佳實施例，並且還提出了一些示例可選功能和/或可選實施例。文中的說明及附圖僅用於解釋說明，不用於局限本發明。因此，本領域的技術人員應明確變化、修正及可選方案。這些變化、修正及可選方案也應認為在本發明的範圍內。
第1圖表示與肖特基二極體5集成的MOSFET的平面剖面圖。為了便於描述器件內空間、結構的關係，使用了X-Y-Z笛卡爾坐標系，其中X-Y平面平行於主半導體晶片平面。MOSFET/SKY 5包括一個形成在肖特基二極體5背部的汲極。汲極區延伸到與SCST 103重疊的N--半導體的外延層104中。在EPIL 104中，刻蝕閘極溝槽，例如111、113和115。閘極氧化層121形成在閘極溝槽中。閘極131、133和135分別沉積在閘極溝槽111、113和115中，並且透過閘極氧化層121，與EPIL 104絕緣。閘極131、133和135由多晶矽等導電材料構成，閘極氧化層121由熱氧化物等絕緣材料構成。確切地說，閘極溝槽111位於閘極接觸區中，而閘極溝槽113和115位於主動器件區中。
源極區150b-150d分別嵌入在本體區140b-140d中。源極區從本體的頂面開始向下延伸到本體中。本體區在沿所有閘極溝槽的側面注入，而源極區僅在主動閘極溝槽附近注入。在本例中，閘極（例如133）具有一個閘極頂面，延伸到本體的頂面上方，源極就嵌入在本體中。這種結構確保閘極和源極重疊，使源極區比帶有凹進閘極的器件源極區更淺，從而提高了器件的效率和性能。對於不同的實施例，閘極多晶矽頂面延伸到源極-本體結上方的延伸量可能不同。在一些實施例中，器件的閘極並沒有延伸到源極-本體區的頂面上方。
在操作過程中，汲極區和本體區一起作為二極體，稱為體二極體。電介質材料層160沉積在閘極上方，使閘極與源極-本體接頭絕緣。電介質材料構成絕緣區，例如160a-160c，在閘極上方以及本體和源極區上方。適合做電介質的材料包括熱氧化物、低溫氧化物（LTO）、含有硼酸的矽玻璃（BPSG）等等。
許多接觸溝槽（例如112a）形成在源極和本體區附近的有源閘極溝槽之間。由於這些溝槽鄰近源極和本體區形成的器件有源區，因此稱為主動區接觸溝槽。例如，接觸溝槽112a穿過源極，延伸到本體中，構成溝槽附近的源極區150b-150c和本體區140b-140c。與之相反，形成在閘極131上方的閘極接觸溝槽117並不位於主動區附近，因此閘極接觸溝槽117不是主動區接觸溝槽。由於連接閘極信號的金屬層172a沉積在閘極接觸溝槽117中，因此溝槽117稱為閘極接觸溝槽或閘極滑道接觸溝槽。透過第三維度上閘極溝槽111、113和115之間的互連（圖中沒有表示出），將閘極信號饋送到主動閘極133和135。金屬層172a與金屬層172b分開，金屬層172b通過接觸溝槽112a連接到源極和本體區，提供電源。在本例中，主動區接觸溝槽和閘極接觸溝槽的深度大致相同。要注意的是，接觸勢壘層642位於金屬層172a和172b的下部。對於本領域的技術人員來說，這些接觸勢壘層可以由Ti/TiN構成，用於在它們各自的金屬-半導體交界面處提供更好地、更加可靠地電接觸。
在本例中，在本體中和沿主動區接觸溝槽壁的區域（例如170b-170c），重摻雜P型材料，構成P+-型區域，稱為本體接觸注入區。含有這些本體接觸注入物，可以確保在本體和源極金屬之間形成歐姆接觸，從而使源極和本體具有相同的電勢。而且，另一個重摻雜的P+-型區域170a位於閘極131中和沿閘極接觸溝槽117壁，以實現歐姆接觸。
導電材料沉積在接觸溝槽112a以及閘極接觸溝槽117中，以形成歐姆電極。在接觸溝槽112a和EPIL 104之間的交界面處有一個嵌入式P-型香農注入區720a。而且，在閘極接觸溝槽117和閘極131的交界面處有另一個嵌入式P-型香農注入區720b。雖然，嵌入式香農注入區 720b無法提供顯著的電氣功能，對於本領域的技術人員類似，與體二極體並聯的肖特基二極體652形成在主動區中，沿接觸溝槽112a-嵌入式香農注入區 720a-外延層 104的通路。肖特基二極體652降低了體二極體的正向電壓降，使儲存的電荷達到最小，從而使MOSFET的效率更高。一個單獨的金屬就可以在形成到N-汲極（104）的肖特基接觸的同時，形成到P+本體良好的歐姆接觸，利用N+源極填充接觸溝槽112a以及閘極接觸溝槽117。可以使用鈦（Ti）、鉑（Pt）、鈀（Pd）、鎢（W）或其他任意適合的金屬。在一些實施例中，金屬層172是由鋁（Al）或Ti/TiN/Al堆疊構成的。
第2A圖-第2H圖表示依據本發明，製備第1圖所示的MOSFET/SKY器件的技術步驟。第2A圖表示以下步驟的結果：
a) 在與半導體襯底103重疊的外延層104中，製備閘極溝槽111、113和115。製備閘極氧化層121，然後在閘極溝槽111、113和115中分別沉積閘極材料131、133和135。
b) 在EPIL 104中製備本體區140a、140b、140c、140d和140e。透過離子注入，在本體區140b、140c和140d上方，製備源極區150a、150b、150c和150d。在氧化層362上方、閘極溝槽111、113和115以及源極區150a、150bc和150d上方，製備氧化層362，然後製備電介質材料層160。
一般來說，對於離子注入的器件尺寸控制，其中注入厚度/深度由注入能量及其內驅熱平衡決定。例如，製備源極區150a、150bc和150d，可以使用大劑量的砷（As）離子注入到半導體矽表面內。然後，源極內驅技術使As離子擴散到矽內部，深度約為0.2~0.5微米。為了更加詳細全面地說明以上技術，請參照第3A圖至第3N圖及其APOM063的說明書。
第2B圖表示以下技術的結果：
c) 各向異性地刻蝕具有相同的頂部接觸溝槽深度的頂部接觸溝槽700a和700b，使得：
c1) 頂部接觸溝槽 700a貫穿電介質材料層160和源極區150bc。因此，源極區150bc被分成源極區150b和150c，各自帶有源極-接觸深度。另外，電介質材料層160被分成絕緣區160a、160b和160c。
c2）頂部接觸溝槽 700a部分深入到本體區140b、140c中，深度為預定義的總本體-接觸深度。
另外，頂部接觸溝槽 700a的垂直側壁定義了肖特基二極體剖面寬度，下文將詳細介紹。
第2C圖至第2G圖說明以下步驟：
d1) 在頂部接觸溝槽 700a和700b的側壁內和源極-接觸深度以下，製備本體-接觸深度＜總本體-接觸深度的多個重摻雜嵌入式本體注入區710a、710b。
d2) 在頂部接觸溝槽 700a和700b的底面下方的子接觸溝槽區中，製備多個嵌入式香農注入區720a、720b。
其中第2C圖至第2F圖說明以下步驟：
d11) 注入重摻雜嵌入式本體注入區 710a、710b，同時保持子接觸溝槽區基本不含任何伴生的本體-接觸注入物。
第2C圖表示以下步驟：
d111) 在頂部接觸溝槽 700a和700b的側壁上方，製備水平壁厚HWTLS的較低隔片子層620，以及在頂部接觸溝槽 700a和700b的底面上方和絕緣區160a、160b和160c上方，製備垂直壁厚為VWTLS的較低隔片子層620。VWTLS與HWTLS基本相等。
第2D圖說明以下步驟：
d112) 在較低隔片子層620上方，製備一個上部隔片子層622。上部隔片子層 622在頂部接觸溝槽（700a和700b）的側壁上方具有水平壁厚HWTUS。上部隔片子層 622在頂部接觸溝槽的底面上方，具有一個底部垂直壁厚LVWTUS，在電介質材料層160上方，具有一個上部垂直壁厚UVWTUS。必須指出的是，雖然UVWTUS與HWTUS基本相等，但是LVWTUS比HWTUS大得多。
d113) 此外，選擇較低隔片子層材料和上部隔片子層材料使：
較低隔片子層 620會使之後的本體-注入束通過傳輸，然而上部隔片子層 622憑藉較大的層厚，會阻止之後的本體-注入束通過傳輸；較低隔片子層 620作為後續的上部隔片子層-刻蝕過程的刻蝕終點。
在一個滿足上述技術步驟的典型實施例中，較低隔片子層材料為氮化矽，上部隔片子層材料為高密度等離子沉積氧化矽（HDPSO），由於其沉積技術，自動滿足以下標準LVWTUS >> HWTUS。作為一個器件結構的較典型實施例，VWTLS可以為100至500埃，UVWTUS可以小於0.1微米，而LVWTUS可以為0.3至0.4微米。
第2E圖說明以下步驟：
d114) 在頂部接觸溝槽700a和700b的底部附近，透過HWTUS + HWTLS的組合壁厚，注入多個重摻雜嵌入式本體注入區710a和710b。同時，由於LVWTUS >> HWTUS的關係，保持頂部接觸溝槽 700a的底面下方子接觸溝槽區不含任何伴生的本體-接觸注入物。
附加的注入束表示為本體-注入束616取向，指向嵌入式本體注入區 710a和710b，與Z軸呈本體-注入傾斜角。在一個實施例中，本體-注入傾斜角為15至30度，嵌入式本體注入區 710a和710b以P+型腔的形式，位於頂部接觸溝槽 700a和700b的矽側壁上，透過注入重硼束，製備嵌入式本體注入區 710a和710b。然後，透過熱啟動驅動，將P+型腔擴散到矽中。
一個重要說明，P+型嵌入式本體注入區 710a和710b不能隨之觸及，橋接並短接至子接觸溝槽區。否則，必須使用一個額外的、不必要的頂部接觸溝槽刻蝕技術，以除去橋接P+型嵌入式本體注入區。在一個實施例中，說明了這一點的重要性，重摻雜嵌入式本體注入區 710a的硼離子注入劑量約為1×e15cm-2，以形成最終的P+型本體接觸。然而，對於穿過它的肖特基勢壘的控制汲電流來說，之後的嵌入式香農注入區 720a的硼離子注入劑量，僅僅約為1×e12cm-2，比1×e15cm-2小三個數量級。因此，頂部接觸溝槽 700a底面下面的子接觸溝槽區應保持不含任何重大的伴生本體-接觸注入物。回顧第2D圖，說明LVWTUS>>HWTUS。雖然，上部和下部極限邊界（HWTUS和HWTLS）的組合厚度並不大，無法阻止本體-注入束616隨後注入到頂部接觸溝槽 700a和子接觸溝槽區的下部拐角區中，由HDP製成的厚LVWTUS足夠大，可以阻止本體-注入束616隨後注入到頂部接觸溝槽 700a和子接觸溝槽區的下部拐角區中。在一個較佳實施例中，LVWTUS / HWTUS的比應大於3/1。
第2F圖表示以下步驟：
d115) 接下來透過上部隔片子層-刻蝕技術，除去上部隔片子層 622，透過較低隔片子層-刻蝕技術，除去較低隔片子層 620。
雖然，如上所述僅僅需要HDP就能防止本體-注入束616觸及子接觸溝槽區，但是仍然需要較低隔片子層 620作為上部隔片子層-刻蝕的刻蝕終點。在一個典型實施例中，較低隔片子層 620由氮化矽製成。
第2G圖表示以下步驟：
d21) 在子接觸溝槽區中注入P-型嵌入式香農注入區 720a，同時在閘極131中，注入P-型嵌入式香農注入區 720b。
附加的注入束表示為香農-注入束720取向，指向嵌入式香農注入區 720a和720b，與Z軸呈香農-注入傾斜角。在一個實施例中，香農-注入傾斜角為7至15度，嵌入式香農注入區 720a和720b以P-型腔的形式，位於頂部接觸溝槽 700a和700b的底面下方，透過在N-型EPIL 104中輕注入硼束，製備嵌入式香農注入區 720a。然後，透過熱啟動驅動，將P+型腔擴散到矽中。
第2H圖表示製備金屬層640，透過接觸勢壘層642，與嵌入式香農注入區（720a、720b）、重摻雜嵌入式本體注入區（710a、710b）、本體區（140b、140c）以及源極區（150b、150c）相接觸。此外，金屬層640填充了頂部接觸溝槽（700a、700b），覆蓋了絕緣區（160a、160b、160c）。因此，透過頂部接觸溝槽 700a、700b的一次刻蝕，形成與肖特基二極體集成的MOSFET（MOSFET/SKY），其中集成的肖特基二極體652的邊界用虛線表示，作為金屬層640、嵌入式香農注入區 720a和EPIL 104的串聯。因此，頂部接觸溝槽 700a的垂直側壁限定了肖特基二極體剖面寬度。要注意的是，金屬層640被分成各個部分，分別連接有源MOSFET和閘極131。另外，閘極131中的P+型嵌入式本體注入區 710b轉換成閘極接觸電極。
製備金屬層640本身的技術已為本領域的技術人員所熟知，包括沉積鈦/氮化鈦（Ti/TiN），製備矽化鈦並且填充金屬層。肖特基二極體652向上的垂直剖面將陸續穿過以下金屬層：
1. N+型矽SCST 103。
2. N-型矽EPIL 104。
3. P-型矽嵌入式香農注入區 720a。
4. 矽化物。
5. 氮化鈦TiN。
6. 金屬（鋁、銅等）。
在上述說明中，（系統二極體652的）肖特基勢壘形成在層4和3之間。
雖然上述說明包含許多具體參數，但是這些參數僅僅作為對本發明現有的較佳實施例做出的解釋說明，不應據此局限本發明的範圍。透過上述說明及附圖，給出了各個典型實施例的具體結構。本領域的技術人員應明確，本發明還可以用各種其他的形式體現，無需過度實驗，本領域的技術人員就可以實施本發明中的實施例。因此，本發明的範圍不應局限於以上說明，而應由所附的申請專利範圍及其全部等效內容決定。在申請專利範圍中等效的意義和範圍內的任何以及全部修正都應認為屬於本發明的意義和範圍。
5．．．肖特基二極體
103．．．半導體襯底
104．．．N--半導體的外延層
111．．．閘極溝槽
112a．．．溝槽
113．．．閘極溝槽
115．．．閘極溝槽
117．．．閘極接觸溝槽
121．．．閘極氧化層
131．．．閘極
133．．．閘極
135．．．主動閘極
140a．．．本體區
140b．．．本體區
140c．．．本體區
140d．．．本體區
150a．．．源極區
150b．．．源極區
150d．．．源極區
150c．．．源極區
160．．．電介質材料層
160a．．．絕緣區
160c．．．絕緣區
160b．．．絕緣區
170a．．．P+-型區域
170b．．．P+-型區域
170c．．．P+-型區域
172a．．．金屬層
172b．．．金屬層
362．．．氧化層
642．．．勢壘層
652．．．肖特基二極體
720a．．．嵌入式香農注入區
720b．．．嵌入式P-型香農注入區

Claims (8)

  1. 【第1項】
    一種用於與肖特基二極體集成的MOSFET的製備方法，用X-Y-Z笛卡爾坐標系表示，X-Y平面平行於其主半導體晶片平面，該方法包括：
    a）在與半導體襯底重疊的外延層中，製備一個閘極溝槽，並且在其中沉積閘極材料；
    b）在外延層中，製備一個本體區，在該本體區上方製備一個源極區，在該閘極溝槽和該源極區上方，製備一個電介質區；
    c）刻蝕頂部接觸溝槽，其垂直側壁限定了肖特基二極體剖面寬度：其中，
    c1）該頂部接觸溝槽透過電介質區和源極區，從而定義了一個源極-接觸深度；並且
    c2）該頂部接觸溝槽部分深入到該本體區中預定的一個總本體-接觸深度；
    d）製備：
    d1）在該頂部接觸溝槽及源極-接觸深度以下的側壁中，製備一個重摻雜嵌入式本體注入區，其有一本體-接觸深度<總本體-接觸深度；並且
    d2）在該頂部接觸溝槽底面下方的子接觸溝槽區中，製備一個嵌入式香農注入區；並且
    e）製備一個金屬層：
    e1）與該嵌入式香農注入區、該本體區以及該源極區接觸；並且
    e2）填充頂部接觸溝槽，並且覆蓋電介質區
  2. 【第2項】
    如申請專利範圍第1項所述的方法，其中製備該重摻雜的嵌入式本體注入區和該嵌入式香農注入區包括：
    d11）注入該重摻雜嵌入式本體注入區，同時保持該子接觸溝槽區不含任何伴生本體-接觸注入物；並且
  3. 【第3項】
    如申請專利範圍第2項所述的方法，其中注入該重摻雜嵌入式本體注入區，同時保持該子接觸溝槽區不含任何伴生該本體-接觸注入物包括：
    d111) 在該頂部接觸溝槽的側壁上，製備水平壁厚為HWTLS的較低隔片子層，在該頂部接觸溝槽的底面上和該電介質區上，該較低隔片子層的垂直壁厚為VWTLS，其中VWTLS與HWTLS基本相等；
    d112) 在該較低隔片子層上，製備一個上部隔片子層，在該頂部接觸溝槽的側壁上方上部隔片子層具有水平壁厚HWTUS，在該頂部接觸溝槽的底面上方，上部隔片子層具有一個底部垂直壁厚LVWTUS，在該電介質區上方，該上部隔片子層具有一個上部垂直壁厚UVWTUS，其中UVWTUS與HWTUS基本相等，且LVWTUS>>HWTUS；
    d113) 選擇該較低隔片子層材料和該上部隔片子層材料使：
    該較低隔片子層會使之後的本體-注入束通過傳輸，然而該上部隔片子層憑藉較大的層厚，會阻止之後的該本體-注入束通過傳輸；並且
    該較低隔片子層作為後續的該上部隔片子層-刻蝕過程的刻蝕終點；
    d114)本體-注入束與Z軸呈本體-注入傾斜角BITA，透過HWTUS + HWTLS的組合壁厚，注入該重摻雜嵌入式本體注入區，同時，由於LVWTU S >> HWTUS的關係，保持該子接觸溝槽區不含任何伴生的該本體-接觸注入物，從而避免因伴生的該本體-接觸注入物在該子接觸溝槽區中橋接該嵌入式本體注入區而必須使用一個額外刻蝕過程加以除去；並且
  4. 【第4項】
    如申請專利範圍第3項所述的方法，其中LVWT US >3*HWT US 。
  5. 【第5項】
    如申請專利範圍第3項所述的方法，其中：
    該較低隔片子層材料為氮化矽，該上部隔片子層材料為高密度等離子沉積氧化矽；
    VWTLS為100至500埃；
    UVWTUS小於0.1微米，而LVWTUS為0.3至0.4微米；並且
  6. 【第6項】
    如申請專利範圍第2項所述的方法，其中在該子接觸溝槽區中注入該嵌入式香農注入區包括透過香農-注入束，在與Z軸呈香農注入傾斜角的方向上，將該嵌入式香農注入區注入到該子接觸溝槽區中。
  7. 【第7項】
    如申請專利範圍第6項所述的方法，其中該香農注入傾斜角為7度至15度。
  8. 【第8項】
    如申請專利範圍第1項所述的方法，其中該製備金屬層包括沉積鈦/氮化鈦，製備矽化鈦，並且填充金屬層。
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US9230957B2 (en) 2013-03-11 2016-01-05 Alpha And Omega Semiconductor Incorporated Integrated snubber in a single poly MOSFET
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US9385224B2 (en) * 2014-08-13 2016-07-05 Northrop Grumman Systems Corporation Method of forming an integrated multichannel device and single channel device structure
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US10403712B2 (en) * 2016-06-02 2019-09-03 Infineon Technologies Americas Corp. Combined gate trench and contact etch process and related structure
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US10325908B2 (en) 2017-04-26 2019-06-18 Alpha And Omega Semiconductor Incorporated Compact source ballast trench MOSFET and method of manufacturing
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