TW201426860A - Method for forming through hole or contact hole - Google Patents

Abstract

The embodiment of the invention provides a method for forming a through hole or a contact hole. The method comprises the following step of etching a first dielectric layer; and etching an etching barrier layer positioned below the first dielectric layer so as to expose a metal structure in a second dielectric layer positioned below the etching barrier layer. The method is characterized in that the step of etching the etching barrier layer positioned below the first dielectric layer comprises the following steps of repeatedly executing a first etching process, wherein the first etching process consists of the following step of (a) applying high radio-frequency power into a reaction chamber in a first period so as to perform dry etching on the etching barrier layer; and (b) applying low radio-frequency power into the reaction chamber in a second period so as to deposit polymers to protect the side wall of the through hole or the contact hole. Compared with the prior art, the method for forming the through hole or the contact hole has the advantage that the electrical performance of semiconductor structures of the through hole or the contact hole is higher.

Description

Method for forming through hole or contact hole

The invention belongs to the technical field of semiconductor manufacturing, and in particular relates to a method for forming a through hole or a contact hole.

In the process of making a through hole connecting a metal structure and a dielectric or a contact hole connecting a metal structure and a metal structure by dry etching, in order to reduce the influence of plasma etching on the metal structure, and ensuring uniformity of etching of the dielectric material Generally, an etch stop layer is formed on the metal structure to protect the metal structure during the plasma etching process (see FIG. 1), wherein the structure in FIG. 1 includes: a photoresist 101, The first dielectric layer 102, the etch stop layer 103, the second dielectric layer 104, and the metal structure 105 located inside the second dielectric layer 104. The etch stop layer 103 over the metal structure generally selects a higher dielectric material (such as SiN, carbon-doped SiN) than the material used for the dielectric layer (such as the first dielectric layer 102) to be etched away. Or SiC or the like) so that the first dielectric layer 102 has sufficient overetch to ensure that the first dielectric layer 102 can be completely opened, penetrate the first dielectric layer 102 and the etch stop layer 103 and form a metal Through holes or contact holes connected to the structure, as shown in Figures 2 and 3.

However, conventional etching methods for forming via holes or contact holes have the following disadvantages: on the one hand, conventional etching methods are performed in an etch barrier layer. The undercut is easy to occur in the process, that is, the width of the bottom of the through hole or the contact hole is larger than the width of the metal structure, and the etching barrier layer is excessively removed (the A area shown in FIG. 3); Due to the high self-biasing method, the etching method usually causes metal structures (such as Cu or Al) to be sputtered during dry etching, resulting in plasma induced damage (PID). Therefore, in the conventional etching process, after the metal is exposed to the plasma, the living radicals in the plasma cause the modification of the metal surface, and the physical bombardment of the positive ions causes the sputtering of the metal, thus affecting the structure of the semiconductor. Electrical performance.

In order to solve the problem that the electrical performance of the semiconductor structure fabricated by the conventional method is not high due to the through hole or the contact hole in the prior art, the embodiment of the present invention provides a method for forming a via hole or a contact hole, the method comprising: etching the first a dielectric layer; etching an etch barrier layer under the first dielectric layer to expose a metal structure in the second dielectric layer under the etch barrier layer; wherein the etch is located The etch barrier layer under the first dielectric layer includes: repeatedly performing a first etching process; wherein the first etching process is composed of the following steps (a) and (b): (a) at the first time In the segment, a high RF power is applied to the reaction chamber to dry etch the etch barrier; (b) a low RF power is applied to the reaction chamber during the second time period to deposit the polymer. A sidewall for protecting the through hole or the contact hole.

Preferably, the etching the first dielectric layer comprises repeatedly performing a second etching process; wherein the second etching process is performed by the following step (c) And (d) consisting of: (c) applying a high RF power to the reaction chamber during the third time period to dry etch the first dielectric layer; (d) during the fourth time period, A low RF power is applied within the reaction chamber to deposit a polymer to protect the sidewalls of the via or contact hole.

Preferably, the first time period and the second time period constitute a first pulse period, the first pulse frequency is 10 kHz-500 kHz; and/or, the third time period and the The fourth period of time constitutes a second pulse period, and the second pulse frequency is 10 kHz to 500 kHz.

Preferably, when the etching is located on the etch barrier layer under the first dielectric layer, the first duty ratio is between 10% and 90%; wherein the first duty ratio is in one of the The ratio of the first time period to the sum of the first time period and the second time period in the first etching process.

Preferably, the etching the etch barrier under the first dielectric layer is performed by using a plasma RF source power and a plasma RF bias power; wherein, in the different first etching processes, The first time period and the second time period remain unchanged, and the first duty ratio is between 40% and 90%.

Preferably, the etching the etch barrier under the first dielectric layer is performed by using a plasma RF source power and a plasma RF bias power; wherein the etching is located in the first dielectric layer During the underlying etch stop, the first duty cycle is gradually reduced.

Preferably, the etching the etch barrier layer under the first dielectric layer is completed by using a plasma RF source power; wherein, in the different first etching processes, the first time period and The second The time period remains unchanged, and the first duty cycle is between 50% and 90%.

Preferably, the etching the etch barrier under the first dielectric layer is performed by using a plasma RF source power; wherein the etching the etch barrier under the first dielectric layer During the process, the first duty cycle gradually decreases.

Preferably, when the first dielectric layer is etched, the second duty ratio is between 10% and 90%; wherein the second duty ratio is the first one in the second etching process The ratio of the three time periods to the sum of the third time period and the fourth time period.

Preferably, the etching the first dielectric layer is performed by using a plasma RF source power and a plasma RF bias power; wherein, in the different the second etching process, the third time period and the The fourth time period remains unchanged, and the second duty ratio is between 40% and 90%.

Preferably, the etching the first dielectric layer is performed by using a plasma RF source power and a plasma RF bias power; wherein, in the etching the first dielectric layer, the second duty cycle is gradually Reduced.

Preferably, the etching the first dielectric layer is performed by using a plasma RF source power; wherein, in different the second etching processes, the third time period and the fourth time period are not maintained The second duty ratio is between 50% and 90%.

Preferably, the etching the first dielectric layer is performed by using a plasma RF source power; wherein, in the etching the first dielectric layer, the second duty ratio is gradually decreased.

Preferably, when the etching is located on the etch barrier layer under the first dielectric layer, the ratio of the material used for the etch barrier layer to the material used for the first dielectric layer is 1.5:1~1: Between 3

Preferably, the etching the etch barrier layer under the first dielectric layer comprises: performing a main etch on the etch barrier layer to remove the first portion of the via hole or the contact hole Etching the barrier layer; etching the etch stop layer to remove the remaining portion of the via or the contact etch stop layer, and exposing the portion located in the second dielectric layer Metal structure.

Preferably, the etching the first dielectric layer comprises: performing a main etch on the first dielectric layer to remove the first portion of the first dielectric layer in the via or contact hole; A dielectric layer is overetched to remove the remaining portion of the first dielectric layer in the via or contact hole and expose the etch stop.

Preferably, the gas used for etching the etch barrier layer under the first dielectric layer comprises one or more of CF ₄ , C ₄ F ₈ , C ₄ F ₆ , CHF ₃ , CH ₂ F ₂ The combination.

In the method for forming a via hole or a contact hole provided by an embodiment of the present invention, when etching the etch barrier layer, repeating the loop performs dry etching of the etch barrier layer in the first period of time, and in the second The etch stop layer is dry etched during the time period. In this method, a polymer is deposited on the sidewalls of the first dielectric layer and the etch barrier during the second period of time, and these polymers can protect the sidewalls of the etch barrier during the etching process, thereby reducing the occurrence of undercuts; At the same time, during the second period of time during which the etching process is stopped, the charge accumulated on the surface of the cymbal and the charge trapped inside the cymbal sheet are released, so that the PID can be fundamentally reduced. It can be seen that the method for forming the through hole or the contact hole provided by the embodiment of the present invention can improve the adoption of the pass as a whole. Electrical properties of a semiconductor structure of a hole or contact hole.

101‧‧‧Photolithography

102‧‧‧First dielectric layer

103‧‧‧etch barrier

104‧‧‧Second dielectric layer

105‧‧‧Metal structure

BRIEF DESCRIPTION OF THE DRAWINGS In order to more clearly illustrate the embodiments of the present invention or the prior art, the drawings in which the embodiments or the prior art description are used will be briefly described. The drawings in the following description are some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any creative work. The same reference numerals are used throughout the drawings to refer to the same parts. The drawings are not intended to be scaled to scale in actual size, with emphasis on the gist of the present invention.

1 is a schematic structural view of a through hole or a contact hole before forming; FIG. 2 is a schematic view of a structure formed by etching a first dielectric layer when a via hole or a contact hole is formed by a conventional method; and FIG. 3 is a through hole or contact formed by a conventional method; FIG. 4 is a flow chart of a method for fabricating a through hole or a contact hole according to Embodiment 1 of the present invention; and FIG. 5 is a through hole formed by using the through hole or contact hole provided by Embodiment 1 of the present invention; Or a schematic diagram of the structure of the contact hole; FIG. 6 is a waveform diagram of the plasma RF power used in the fabrication of the via hole or the contact hole according to the embodiment of the present invention; FIGS. 7-8 are plasma RF signals according to the first example of the first embodiment of the present invention. FIG. 9 is a waveform diagram of plasma RF power according to a second example of the first embodiment of the present invention; FIG. 11 is a method for fabricating a through hole or a contact hole according to Embodiment 2 of the present invention; 12 to 15 are schematic structural views of various stages in the process of fabricating through holes or contact holes by using the manufacturing method provided by the second embodiment of the present invention.

The technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the embodiments of the present invention. It is a partial embodiment of the invention, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

In order to fabricate a semiconductor structure of high electrical performance, the following technical solutions are proposed in the embodiments of the present invention.

To this end, the first embodiment of the present invention provides a method for fabricating a through hole or a contact hole, and FIG. 4 shows a flow chart of the manufacturing method. The method includes the following steps:

Step S401: etching the first dielectric layer 102;

Specifically, before performing step S401, the photoresist 101 may be first coated on a predetermined region of the first dielectric layer 102 to protect the first dielectric layer 102 during the subsequent etching process, wherein the predetermined region may be formed. A hole or area outside the contact hole.

In the process of etching the first dielectric layer 102, a conventional dry etching may be employed, or other suitable etching methods may be employed.

It should be noted that the dry etching in step S401 can be performed by using a dual-frequency power source to drive the discharge, that is, etching the first dielectric layer 102. The process can be performed using plasma RF source power and/or plasma RF bias power, which can be done by plasma RF source power alone or by plasma RF bias power alone. This is accomplished by a combination of plasma RF source power and plasma RF bias power. The frequency of the plasma RF source power in the embodiment of the present invention may be in the range of 25 MHz to 120 MHz. The plasma RF source power of the frequency is mainly used to control the density of the plasma; the frequency of the plasma RF bias power may be In the range of 2MHz~15MHz, the plasma RF bias power of this frequency is mainly used to control the energy of the plasma.

Step S402: etching the etch barrier layer 103 under the first dielectric layer 102 to expose the metal structure 105 in the second dielectric layer 104 underneath; wherein step S402 can repeatedly perform the first etching process To complete, the first etching process can be composed of the following two steps (a) and (b):

(a) applying a high RF power to the reaction chamber during the first time period t1, and performing dry etching on the etch barrier layer 103; wherein the power of the high RF power may be in the range of 500-1200 W, which is high. The frequency of the radio frequency power may be above 2 MHz; (b) applying a low RF power to the reaction chamber during the second time period t2, the frequency of the low RF power may be 40% or less of the high RF power value, in addition, The low RF power can also be in the range of 0-300 W. At this time, the etch stop layer 103 is stopped from being dry etched to deposit a polymer to protect the sidewalls of the via or contact hole.

The high RF power and the low RF power in the embodiment of the present invention refer to the same frequency output by the same RF power source, and have two functions. Rate output state, the only change in the two phases is the size of the power.

The dry etching of the etch stop layer 103 can be performed by repeating the first etching process, that is, by continuously performing the steps (a) and (b) continuously. In the actual operation, step (a) and step (b) may be alternately performed, that is, step (a) - step (b) - step (a) - step (b) ... step (a) - step ( b) way. Performing one step (a) and one step (b) continuously is a first etching process, wherein each first etching process may always start with step (a), end with step (b), and each The total time experienced by the first etching process (the total time t=t1+t2) may be fixed; that is, the first time period t1 may change, the second time period t2 may change, but the value of t is Changeless. In this step S402, a high RF power is applied in the first time period t1 to perform a dry etching operation, and a low RF power is applied in the second time period t2 to deposit a polymer to protect the through hole or the contact hole. The sidewalls; that is, the dry etching of the etch barrier layer 103 is performed in a pulsed manner. The length of the first time period t1 and the second time period t2 may satisfy the following relationship: the ratio of the first time period t1 to the sum of the first time period t1 and the second time period t2 is between 0.1 and 0.9, that is, the first A duty cycle is between 10% and 90%, wherein the first duty cycle M1 = t1/(t1 + t2) = t1/t.

In addition, a first time period t1 and a second time period t2 form a first pulse period, and the first pulse frequency may be 10 kHz to 500 kHz.

The dry etching in the step S402 can be performed by applying high RF power to the reaction chamber. Specifically, the dual-frequency power source can be used to drive the discharge, that is, the etching of the etch barrier layer 103 can be performed. Plasma RF source power and / or plasma RF bias power is completed The process can be completed by using the plasma RF source power alone or by using the plasma RF bias power alone, or by combining the plasma RF source power and the plasma RF bias power. The frequency of the plasma RF source power in the embodiment of the present invention may be in the range of 25 MHz to 120 MHz. The plasma RF source power of the frequency is mainly used to control the density of the plasma, and the frequency of the plasma RF bias power may be In the range of 2MHz~15MHz), the plasma RF bias power of this frequency is mainly used to control the energy of the plasma.

In the actual operation process, the plasma RF power (including the plasma RF source power and/or the plasma RF bias power) may be in a high RF power state during the first time period t1, and plasma dry etching may be performed. Operating; during the second time period t2, the RF power is placed in a low RF power state to deposit a polymer to protect the sidewalls of the via or contact hole. That is, during the etching of the etch barrier layer, the plasma RF frequency can be changed according to the pulse waveform as shown by b in FIG. 6: during the first time period t1, the plasma RF power is at a high RF power. State, during the second time period t2, the plasma RF power is in a low RF power state, and in one embodiment, the power of the low RF power state may be zero. The waveform diagram in a in Fig. 6 is a microscopic pulse waveform diagram, and the actual waveform when the normal pulse is turned on may be a sine wave, so a in Fig. 6 and b in Fig. 6 are actually equivalent pulse diagrams. In addition, in the first time period t1, the plasma RF power may be a constant value or may change with time, which is not limited by the present invention.

In the second time period t2, although the plasma RF power is in a low RF power state, there are still a large number of rading particles in the process chamber, and these priming particles have high reactivity and will be in the process. The intracavity reaction forms a polymer which is deposited on the sidewalls of the first dielectric layer 102 and the etch stop layer 103. When the plasma RF power returns to a high RF power state (i.e., an etching operation is performed), the polymer deposited on the sidewalls of the etch barrier layer 103 protects the sidewalls of the etch barrier layer 103, thereby reducing the occurrence of undercuts. The through hole or the contact hole formed by the method for forming the through hole or the contact hole provided by the first embodiment of the present invention may have a structure as shown in FIG. 5, the through hole or the contact hole just completely exposing the metal structure 105, and there is no Excessive etching of the etch barrier layer 103 occurs without undercutting.

Under the traditional plasma etching conditions, the positive charge will be injected into the surface and inside of the dielectric material under the acceleration of the electric field. As time increases, the charge accumulates more and more, and in the case of potential difference, current will be formed, causing damage to the device. This plasma induced damage (PID) is still severe even when the plasma RF bias power is zero. In the first embodiment of the present invention, the pulse plasma is used for etching. During the second time period t2, the plasma RF power is turned off. At this time, the accumulated charge on the surface of the cymbal and the internal trap of the cymbal (trap) The charge will be released, so the PID can be radically reduced.

It should be noted that in the process of over etching the etch barrier layer, that is, during the process of exposing the metal to the plasma, a pulsed plasma can be used to form a layer of polymer on the metal surface, which can reduce the engraving. The sputtering effect of active radicals such as F and O on the metal surface during etching and the physical bombardment of ions on the metal surface.

A method for forming a via hole or a contact hole according to Embodiment 1 of the present invention, when etching the etch barrier layer, repeating the loop to perform dry etching of the etch barrier layer by using high RF power in the first period of time Etching, using a low RF power to deposit a polymer to protect vias or contacts during the second time period The sidewalls of the holes are dry etched. In this method, a polymer is deposited on the sidewalls of the first dielectric layer and the etch barrier during the second period of time, and these polymers can protect the sidewalls of the etch barrier during the etching process, thereby reducing the occurrence of undercuts; At the same time, during the second period of time during which the etching process is stopped, the charge accumulated on the surface of the cymbal and the charge trapped inside the cymbal sheet are released, so that the PID can be fundamentally reduced. It can be seen that the method for forming the via hole or the contact hole provided by the embodiment of the present invention can improve the electrical properties of the semiconductor structure using the via hole or the contact hole as a whole.

It should be noted that, in the above etching process (including step S401 and/or step S402), the etching gas used may include CF ₄ , C ₄ F ₈ , C ₄ F ₆ , CHF ₃ , CH ₂ F _{2 .} One or a combination of the two, in addition, the etching gas may also contain a certain amount of Ar and O _{2 ,} etc., wherein Ar can be used to dilute the etching gas, and O ₂ contributes to the production of the polymer during the etching process. . In a preferred embodiment of the present invention, the etching gas may be a mixed gas composed of CF ₄ , Ar and O ₂ , and a certain amount of C ₄ F ₈ and C ₄ F ₆ may be added to the mixed gas. One or several of CHF ₃ and CH ₂ F ₂ to further improve the etching effect.

In fact, the process of etching the etch barrier layer in the embodiment of the present invention may be implemented in various manners. The following describes the manners by taking several specific examples as an example. It should be noted that the embodiment of the present invention blocks the etch. The manner in which the layer is etched is not limited to the following manners, and those skilled in the art may also adopt other suitable methods based on the technical solutions of the present invention.

First example

In the process of etching the etch barrier layer, plasma RF source power and plasma RF bias power can be simultaneously used, and is equally spaced The daughter body RF bias power can be set in a pulsed manner, that is, the plasma RF bias power is greater than zero for a period of time, and the plasma RF bias power is equal to zero at a later period; for example, the plasma RF during the first time period t1 The bias power is a high RF power state, and the plasma RF bias power is a low RF power state during the second time period t2, as shown by b in FIG. 7; and in this process, the plasma RF source power can be maintained. It is greater than zero and remains constant, as shown by a in Figure 7.

In this manner, the time of step (a) is performed during the entire etching process of the etch barrier layer, that is, during the repeated execution of steps (a) and (b) in a plurality of repeated loops. The time for performing step (b) once may be kept constant, that is, the first time period t1 and the second time period t2 may both be constant values. At this time, in the first etching process, that is, during the continuous execution of one step (a) and one step (b), the first duty ratio may be between 40% and 90%, that is, t1/(t1+). T2) is between 40% and 90%, as shown by b in FIG.

In addition, when the etching operation is performed by combining the plasma RF source power and the plasma RF bias power, the first duty ratio can be gradually reduced during the etching of the etch barrier layer, that is, As the etching process proceeds, the first duty cycle may be gradually reduced during successively performing different first etching processes, that is, t1/(t1+t2) in different first etching processes. The value keeps decreasing, but the first duty cycle is still between 10% and 90%. Since the total time (t1+t2) used for each first etching process remains unchanged, this is equivalent to the time for performing step (a) decreases as the etching of the etch barrier layer proceeds. The time for performing step (b) is continuously increased, that is, during the different first etching processes that are continuously performed, the first time period t1 is continuously decreased, and the second time period t2 is continuously increased, as shown in FIG. continuously In the two first etching processes, the period t1' is smaller than the period t1. As shown by b in Figure 8; during this process, the plasma RF source power can remain greater than zero and remain constant, as shown by a in Figure 8.

Second example

In the process of etching the etch barrier layer, the plasma RF source power can also be used only, and the plasma RF source power is set in a pulse manner, that is, the plasma RF source power is in a high RF power state for a period of time. At a later time, the plasma RF source power is in a low RF power state; for example, the plasma RF source power is greater than zero during the first time period t1 and the plasma RF source power is equal to zero during the second time period t2.

At this time, in different first etching processes, the time for performing step (a) may be completely the same, and the time for performing step (b) may be completely the same, that is, the entire process of etching the etching barrier layer. The first time period t1 remains unchanged, and the second time period t2 remains unchanged, as shown in FIG. At this time, the first duty ratio remains unchanged, but the first duty ratio needs to be maintained between 50% and 90%.

In addition, when only the plasma RF source power is used, the first duty cycle can be gradually reduced during the etching of the etch barrier layer, that is, t1/(t1+) in different first etching processes. The value of t2) keeps decreasing, but the first duty cycle is still between 10% and 90%. Since the total time (t1+t2) used for each first etching process remains unchanged, this is equivalent to the time for performing step (a) decreases as the etching of the etch barrier layer proceeds. The time for performing step (b) is continuously increased, that is, during the different first etching processes that are continuously performed, the first time period t1 is continuously decreased, and the second time period t2 is continuously increased, as shown in FIG. In the two consecutive first etching processes, the time period t1' is smaller than the time period t1.

In addition, in the first embodiment of the present invention, the through hole or the contact hole can be formed only by using the plasma RF bias power, and details are not described herein again.

It should be noted that, in order to reduce the bombardment of the metal structure by the etching process and thereby cause metal sputtering, the plasma RF bias power in the embodiment of the present invention should be low, for example, in the range of 0 to 500 W; It is necessary to ensure a certain plasma RF source power, for example, in the range of 200 to 1000 W; in addition, a certain chamber pressure, such as 20 to 200 Mt, needs to be ensured during the formation of the via hole or the contact hole. These parameters may be determined according to specific process requirements, and are not limited herein.

The foregoing specific examples provide several implementations for etching the etch barrier layer. It should be noted that these implementations can be combined with other processes or parameters in the embodiments of the present invention to obtain other technical solutions. Within the scope of protection of the embodiments of the present invention, they are not enumerated here.

In addition, the process of etching the first dielectric layer in the embodiment of the present invention may also have various implementations.

For example, this step can be accomplished in a combination of plasma RF source power and plasma RF bias power. Wherein, in each second etching process, the third time period t3 and the fourth time period t4 remain unchanged, and the second duty ratio is between 40% and 90%; in addition, in a different second During the etching process, the second duty cycle can also be gradually reduced, that is, the time for performing step (c) is continuously decreased, and the time for performing step (d) is continuously increased, but the second duty ratio is still at 10%. Between ~90%, the situation is similar to the case of the first example above, and details are not described herein again.

As another example, this step can also be accomplished using only plasma RF source power. Wherein, in each second etching process, the third time period t3 and the first The four time periods t4 can all remain unchanged, and the second duty ratio is between 0.4 and 0.9. In addition, during the second etching process, the second duty cycle can also be gradually reduced, that is, the steps are performed ( The time of c) is continuously decreasing, and the time for performing step (d) is continuously increased, which is similar to the case of the second example described above, and will not be described herein.

In addition, in the embodiment of the present invention, a third time period t3 and a fourth time period t4 constitute a second pulse period, and the second pulse frequency may be 10 kHz to 500 kHz.

It should be noted that, in order to better prevent the undercut in the formation of the via hole or the contact hole, in the embodiment of the present invention, during the etching of the etch barrier layer 103 under the first dielectric layer 102, etching is performed. The etching selectivity of the material used for the barrier layer 103 to the material used for the first dielectric layer 102 may be between 1.5:1 and 1:3; in addition, the etching barrier layer 103 also needs to have a certain overetch rate (OE). %) to ensure that the etch stop layer 103 can be fully opened during the formation of the via or contact hole.

In addition, the method for forming the via hole or the contact hole in the embodiment of the present invention may also be implemented in other manners.

Embodiment 2

Embodiment 2 of the present invention provides a method for forming a through hole or a contact hole, FIG. 11 shows a flow chart of the method, and FIGS. 12 to 15 show a schematic structural view of each stage when a through hole or a contact hole is formed by the method. . For the sake of brevity, the second embodiment of the present invention is only described in the same manner as the first embodiment of the present invention, and is not described herein again.

Referring to Figures 11-15 together, the method includes the following steps:

Step S1101: performing main etching on the first dielectric layer 102, The first dielectric layer in the first portion of the via or contact hole is removed, as shown in FIG.

Step S1102: etching the first dielectric layer to remove the remaining portion of the first dielectric layer in the via hole or the contact hole, and exposing the etch barrier layer, as shown in FIG. .

Step S1103: performing main etching on the etch barrier layer to remove the first portion of the etch barrier layer in the via hole or the contact hole to expose the metal structure. As shown in Figure 14.

Step S1104: etching the etch stop layer to ensure complete removal of the remaining portion of the via hole or the etch stop layer in the contact hole, as shown in FIG.

The technical solutions of the second embodiment of the present invention are also applicable to the technical solutions of the second embodiment of the present invention. For example, each of the etching steps (including the step S1101, the step S1102, the step S1102, and the step S1104) in the second embodiment of the present invention can be performed by using the pulse etching method mentioned in the first embodiment of the present invention, and the present invention can also be used. The plasma RF source power and/or plasma RF bias power pulse etching is performed in the first embodiment. Those skilled in the art can obtain other technical solutions in combination with the first embodiment on the basis of the second embodiment, which are all within the protection scope of the present invention.

The above is only a preferred embodiment of the present invention, and it should be noted that those skilled in the art can make several improvements and retouchings without departing from the principles of the present invention. It should also be considered as the scope of protection of the present invention.

102‧‧‧First dielectric layer

103‧‧‧etch barrier

Claims (17)

A method for forming a via hole or a contact hole, the method comprising: etching a first dielectric layer; etching an etch barrier layer under the first dielectric layer to expose the etch barrier a metal structure in a second dielectric layer under the layer; wherein etching the etch barrier layer under the first dielectric layer comprises: repeatedly performing a first etching process; wherein the first etching The process consists of the following steps (a) and (b); (a) applying a high RF power to a reaction chamber during the first period of time to dry etch the etch stop layer; b) applying a low RF power to the reaction chamber during the second time period to deposit a polymer to protect the sidewalls of the via or contact hole. The forming method according to claim 1, wherein the etching the first dielectric layer comprises repeatedly performing a second etching process; wherein the second etching process is composed of the following steps (c) and (d): c) applying a high RF power to the reaction chamber to dry etch the first dielectric layer during a third period of time; (d) applying a low RF to the reaction chamber during a fourth period of time Power is used to deposit a polymer to protect the sidewalls of the via or contact hole. The forming method according to claim 1, wherein the first time period and the second time period constitute a first pulse period, and the first pulse frequency is 10 kHz to 500 kHz; and/or The third period of time and the fourth period of time constitute a second pulse period, and the second pulse frequency is 10 kHz to 500 kHz. The forming method according to claim 1, wherein the etching is located between the etch barrier layer under the first dielectric layer, the first duty ratio is between 10% and 90%; wherein the first A duty cycle is a ratio of the first time period to the sum of the first time period and the second time period in one of the first etching processes. The forming method of claim 4, wherein etching the etch barrier layer under the first dielectric layer is performed using plasma RF source power and plasma RF bias power; wherein, in different During the first etching process, the first time period and the second time period remain unchanged, and the first duty ratio is between 40% and 90%. The forming method of claim 4, wherein etching the etch barrier layer under the first dielectric layer is performed using plasma RF source power and plasma RF bias power; wherein, in the etching The first duty cycle is gradually reduced during the etch stop layer under the first dielectric layer. The forming method of claim 4, wherein etching the etch barrier layer under the first dielectric layer is performed using a plasma RF source power; wherein, in the different first etching processes, The first time period and the second time period remain unchanged, and the first duty ratio is between 50% and 90%. The forming method of claim 4, wherein etching the etch barrier layer under the first dielectric layer uses plasma RF source power Finishing; wherein, in the etching the etch barrier layer under the first dielectric layer, the first duty cycle is gradually decreased. The forming method according to claim 1, wherein the second duty ratio is between 10% and 90% when the first dielectric layer is etched; wherein the second duty ratio is at the second moment The ratio of the third time period to the sum of the third time period and the fourth time period within the eclipse process. The forming method of claim 9, wherein etching the first dielectric layer is performed using plasma RF source power and plasma RF bias power; wherein, in the different second etching process, the The three time periods and the fourth time period remain unchanged, and the second duty ratio is between 40% and 90%. The forming method of claim 9, wherein etching the first dielectric layer is performed using plasma RF source power and plasma RF bias power; wherein, in the etching the first dielectric layer, The second duty cycle is gradually reduced. The forming method of claim 9, wherein etching the first dielectric layer is performed using a plasma radio frequency source power; wherein, in the different the second etching process, the third time period and the The four time periods remain unchanged, and the second duty ratio is between 50% and 90%. The forming method of claim 9, wherein etching the first dielectric layer is performed using a plasma RF source power; wherein, in the etching the first dielectric layer, the second duty cycle is gradually Reduced. The forming method according to any one of claims 1 to 13, wherein when the etch barrier layer under the first dielectric layer is etched, the moment The ratio of the material used for the etch barrier to the material used for the first dielectric layer is between 1.5:1 and 1:3. The forming method according to any one of claims 1 to 13, wherein the etching the etch barrier layer under the first dielectric layer comprises: performing main etching on the etch barrier layer to remove The etch stop layer is formed in the first portion of the via hole or the contact hole; the etch stop layer is over etched to completely remove the remaining portion of the via hole or the contact hole Etching the barrier layer and exposing the metal structure in the second dielectric layer. The forming method according to any one of claims 1 to 13, wherein the etching the first dielectric layer comprises: performing main etching on the first dielectric layer to remove the through hole or the contact hole Part of the first dielectric layer; etching the first dielectric layer to completely remove the remaining portion of the via or contact hole, and exposing the first dielectric layer Etching the barrier layer. The forming method according to any one of claims 1 to 13, wherein the gas for etching the etch barrier layer under the first dielectric layer comprises CF ₄ , C ₄ F ₈ , C ₄ F ₆ , CHF _3. One or a combination of several of CH ₂ F ₂ .