CN106653594B - A method of for improving side wall etching effect in depth-width ratio silicon etching - Google Patents
A method of for improving side wall etching effect in depth-width ratio silicon etching Download PDFInfo
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- CN106653594B CN106653594B CN201510721444.9A CN201510721444A CN106653594B CN 106653594 B CN106653594 B CN 106653594B CN 201510721444 A CN201510721444 A CN 201510721444A CN 106653594 B CN106653594 B CN 106653594B
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- 238000005530 etching Methods 0.000 title claims abstract description 92
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 75
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 75
- 239000010703 silicon Substances 0.000 title claims abstract description 75
- 238000000034 method Methods 0.000 title claims abstract description 30
- 230000000694 effects Effects 0.000 title claims abstract description 25
- 238000002161 passivation Methods 0.000 claims abstract description 58
- 229920000642 polymer Polymers 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims description 25
- 238000009832 plasma treatment Methods 0.000 claims description 15
- 239000003085 diluting agent Substances 0.000 claims description 7
- 230000001737 promoting effect Effects 0.000 claims description 3
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 claims description 2
- 239000007789 gas Substances 0.000 description 62
- 238000006243 chemical reaction Methods 0.000 description 9
- 230000008021 deposition Effects 0.000 description 4
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 4
- 239000000376 reactant Substances 0.000 description 4
- 238000009623 Bosch process Methods 0.000 description 2
- 230000001939 inductive effect Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 229920000140 heteropolymer Polymers 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
- H01L21/30655—Plasma etching; Reactive-ion etching comprising alternated and repeated etching and passivation steps, e.g. Bosch process
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Plasma & Fusion (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The method that the invention discloses a kind of in depth-width ratio silicon etching for improving side wall etching effect, by being passivated twice to silicon is etched before each etching, and the first passivation step is to carry out under high pressure, and the second passivation step is carried out under conditions of low pressure high bias power；It can ensure that polymer is rapidly distributed on the opening sidewalls for the silicon that is etched by the first passivation step, can ensure that polymer is evenly distributed in the open bottom for the silicon that is etched by the second passivation step.A kind of method in depth-width ratio silicon etching for improving side wall etching effect disclosed by the invention, by being passivated twice in etching money every time, it can ensure that polymer is evenly distributed on the opening sidewalls for the silicon that is etched, bottom, so that it is guaranteed that the sidewall silicon after etching again is not in the rough surface of striated or hole shape, the side wall smoothness of the silicon after improving etching.
Description
Technical field
The present invention relates to the methods of the silicon crystal anisotropic etching depth in semiconductor equipment manufacturing field, and in particular to
A method of for improving side wall etching effect in depth-width ratio silicon etching.
Background technique
Bosch etching (Bosch Process) is widely used in TSV (through silicon via) manufacturing field, main
3-D integrated circuit, 3-D packaging applications are used for due to high silicon etching rate, the selectivity of exposure mask of Bosch Process.So
And especially in the etching of high pressure etching technics such as deep hole silicon, the unevenness that is passivated from the top to the bottom on etched hole side wall
Even property.When etching gas and deposition gases fast exchange, since deposition gases have the extremely low residence time, deposition is logical
Higher at the top of road, with extending downwardly for etching through hole, only less deposition gases can reach bottom.Therefore, in Bosch
In Process, it can be distributed due to passivation layer inconsistent, it is easy to which ground is formed in channel side wall has like aperture, hole or stripe-shaped
Shape, so that sidewall roughness is uneven.
Summary of the invention
The method that the purpose of the present invention is to provide a kind of in depth-width ratio silicon etching for improving side wall etching effect is led to
It crosses and is passivated twice to silicon is etched before each etching, and the first passivation step is to carry out under high pressure, second
Passivation step is carried out under conditions of low pressure high bias power；It can ensure that polymer rapidly divides by the first passivation step
Cloth can ensure that polymer is evenly distributed in the silicon that is etched on the opening sidewalls for being etched silicon, through the second passivation step
Open bottom.A kind of method in depth-width ratio silicon etching for improving side wall etching effect disclosed by the invention, by every
Secondary etching money is passivated twice, it can be ensured that and polymer is evenly distributed on the opening sidewalls for the silicon that is etched, bottom, so that it is guaranteed that
Sidewall silicon after etching is not in the rough surface of striated or hole shape, the side wall smoothness of the silicon after improving etching.
In order to achieve the above object, the invention is realized by the following technical scheme:
A method of for improving side wall etching effect in depth-width ratio silicon etching, this method includes multiple repeats
Etching period, each etching period includes:
S1, etch step perform etching silicon, are formed and are open in silicon face；
S2, the first passivation step, is filled with polymer gas in the opening, carries out first time passivation to the opening；
In the first passivation step, the above-mentioned mixed gas in the plasma treatment appts has at second air pressure
While, which carries out first time Passivation Treatment after applying second substrate bias power, so that the opening
The polymer of side wall upper part is more than the polymer of open bottom；
S3, the second passivation step；
In the second passivation step, while above-mentioned mixed gas has third air pressure, the plasma treatment appts are applied
Add a third substrate bias power, the polymer of the opening sidewalls bottom is enabled to be more than the polymer of open top；
Wherein, the second air pressure is greater than the third air pressure, and the second substrate bias power is less than third substrate bias power；
S4 repeats step S1-S3, until reaching target call to the etching depth of silicon.
The step S1 includes:
The processing is utilized using the first air pressure, the first substrate bias power by processing gas is full of in plasma treatment appts
Gas performs etching to form the opening in silicon face.
The duration in the first passivation step period is greater than the duration in the second passivation step period.
Diluent gas is for promoting polymer gas diffusion in the mixed gas and being evenly distributed in the mixed gas
Inner wall and bottom in the opening, and promote the progress of first passivation step, second passivation step.
Polymer gas is carbon fluoride gas in the mixed gas.
The third substrate bias power is pulsed bias power, which can allow for high spike bias power
And keep mean power.
The range of the second air pressure setting is 90mT-160mT；The range of second substrate bias power is 0-10W；
The range of the third air pressure setting is 60mT-90mT；The range of the third substrate bias power setting is 50-
200W。
Compared with the prior art, the present invention has the following advantages:
It is disclosed by the invention it is a kind of in depth-width ratio silicon etching for the method that improves side wall etching effect, by being carved
Erosion silicon is passivated twice before each etching, and the first passivation step is to carry out under high pressure, the second passivation step
It is to be carried out under conditions of low pressure high bias power；It can ensure that polymer is rapidly distributed in by the first passivation step to be carved
On the opening sidewalls for losing silicon, it can ensure that polymer is evenly distributed in the open bottom for the silicon that is etched by the second passivation step
Portion.A kind of method in depth-width ratio silicon etching for improving side wall etching effect disclosed by the invention, by etching every time
Money is passivated twice, it can be ensured that polymer is evenly distributed on the opening sidewalls for the silicon that is etched, bottom, so that it is guaranteed that after etching
Sidewall silicon be not in striated or hole shape rough surface so that uniformity to bottom is more preferable at the top of silicon after etching.
Detailed description of the invention
Fig. 1 is that a kind of overall flow of the method in depth-width ratio silicon etching for improving side wall etching effect of the present invention is shown
It is intended to.
Fig. 2, which is that the present invention is a kind of, to be illustrated in depth-width ratio silicon etching for improving the device of the method for side wall etching effect
Figure.
Fig. 3, which is that the present invention is a kind of, to be illustrated in depth-width ratio silicon etching for improving the embodiment of the method for side wall etching effect
Figure.
Specific embodiment
The present invention is further elaborated by the way that a preferable specific embodiment is described in detail below in conjunction with attached drawing.
A kind of method in depth-width ratio silicon etching for improving side wall etching effect disclosed by the invention is used such as Fig. 2 institute
The inductive type plasma treatment appts shown.The inductive type plasma treatment appts include a reaction chamber 100, reaction
Intracavitary includes a pedestal 120, includes lower electrode in pedestal.It include electrostatic chuck 121, silicon wafer to be processed above pedestal
122 are arranged on electrostatic chuck 121.One radio-frequency power supply 40 with lower frequency (such as 2Mhz ~ 400Khz) passes through one
Orchestration 50 is connected to lower electrode.It include top plate made of an insulating materials at the top of reaction chamber 100, an inductance coil 70 is arranged
It is unfolded above insulating materials top plate.One radio-frequency power supply 60 is connected to inductance coil 70, inductor wire by match circuit 80
The other end ground connection of circle 70.One is connected by a valve 95 with reactant gas source equipment 110 for gas nozzle 90.Inductance coil
70 can be the combination etc. of a variety of coil shapes of involute or circular concentric or rushton turbine.Radio-frequency current
Inductance coil, which is flowed into, from the input terminal of coil 70 flows into ground terminal from the other end.
As shown in Figure 1, a kind of method in depth-width ratio silicon etching for improving side wall etching effect, this method includes more
A etching period repeated, each etching period include:
S1, etch step perform etching silicon, are formed and are open in silicon face.
Processing gas is utilized using the first air pressure, the first substrate bias power by processing gas is full of in plasma treatment appts
It performs etching to form opening in silicon face.
In the present invention, silicon wafer 122 to be etched is arranged on pedestal 120 by electrostatic chuck 121.Processing gas passes through anti-
It answers air machinery 110, valve 95 and is filled in reaction chamber 100 for gas nozzle 90, be 122 surface of silicon wafer by radio-frequency power supply 40
It performs etching and the first air pressure, the first bias power is provided.In this step, one is formed after the surface of silicon wafer 122 is etched
Opening.
It is mixed for SF6 that in the present embodiment, the first air pressure is set as 120mT, the first bias power is set as 80W, etching gas
Rare gas (such as He gas etc.) is closed to perform etching silicon wafer 122.
S2, the first passivation step, is filled with polymer gas in opening, carries out first time passivation to the opening.
After plasma treatment appts mix polymer gas with diluent gas, mixed gas is filled in opening.This hair
In bright, the mixed gas that polymer gas and diluent gas are formed is by reactant gas source equipment 110, valve 95 and for gas nozzle
90 are filled in reaction chamber 100.
In the present invention, polymer gas is carbon fluoride gas in mixed gas.Diluent gas is for promoting in mixed gas
Inner wall and the bottom of opening are spread and be evenly distributed in into polymer gas in the mixed gas, and promote the first of step S2
The progress of passivation step, the second passivation step of step S3.
In the first passivation step, plasma treatment appts, which apply the second air pressure to above-mentioned gas, to be carried out at first time passivation
Reason, it is ensured that polymer is evenly distributed on the side wall in opening.
In the present invention, step S2 also includes: the above-mentioned mixed gas in the first passivation step, in plasma treatment appts
While at the second air pressure, which carries out at first time passivation after applying second substrate bias power
Reason, so that the polymer on opening sidewalls top is more than the polymer of open bottom.
In the present invention, the range of the second air pressure is 90mT-160mT；The range of second substrate bias power is 0-10W.Using upper
Passivation voltage is stated, the polymer rapidly covered in mixed gas to the side wall of the opening formed in step S1 is can be realized, mentions
High passivation efficiency.
S3, the second passivation step.
In the second passivation step, plasma treatment appts apply third air pressure to above-mentioned mixed gas.In the second passivation
In step, while above-mentioned mixed gas has third air pressure, plasma treatment appts apply a third substrate bias power, so that
The polymer of opening sidewalls bottom can be more than the polymer of open top；
Wherein, the second air pressure is greater than third air pressure, and the second substrate bias power is less than third substrate bias power.
In this step, continue the mixed gas for forming polymer gas and diluent gas by reactant gas source equipment 110,
It valve 95 and is filled in reaction chamber 100 for gas nozzle 90.In the present invention, the range of third air pressure is 60mT-90mT；Third bias
The range of power is 50-200W.
In this step, although third air pressure is lower than the second air pressure, so that mixed gas is distributed in the opening of silicon wafer 122
Inner wall slows, but since the downward of polymer can be increased under the collective effect of third air pressure, third substrate bias power
Mobile efficiency, so that more heteropolymer is evenly distributed in the open bottom of silicon wafer 122.
In the present invention, third substrate bias power is pulsed bias power, which can allow for higher spike
Bias power simultaneously keeps mean power.
In the present invention, the duration of the first passivation step T1 is greater than the duration of the second passivation step T2.Due to the first passivation step
The passivation efficiency of rapid T1 is higher than the passivation efficiency of the second passivation step T2, therefore, in order to improve the whole efficiency of passivation, it is desirable that the
The duration of one passivation step T1 is greater than the duration of the second passivation step T2.
S4 repeats step S1-S3, until reaching target call to the etching depth of silicon.
Plasma treatment appts are filled with processing gas in opening, and are being open using the first air pressure, the first substrate bias power
It is inside etched, by the depth down of opening.
In the present invention, when the step S2-S3 completion of first time, illustrates to be passivated for the first time and complete, then will can handle again
Gas is filled with reaction chamber 100 in by reactant gas source equipment 110, valve 95 and for gas nozzle 90, passes through radio-frequency power supply 40, etching
First air pressure, the first bias power are provided, etched again in the opening of silicon wafer 122.
After executing the etching of step S1 again, the opening depth of silicon wafer 122 becomes larger, then needs to repeat step
S2-S3, the depth newly formed to the opening of silicon wafer 122 are passivated again, it is ensured that the opening sidewalls of silicon wafer 122, bottom
It can uniform fold polymer.The etching such as step S1 is carried out again to the opening of silicon wafer 122 immediately, until silicon wafer
Until 122 opening depth reaches target call.
In one embodiment of the present of invention, in first time passivation step, the second air pressure is 120mT, the second bias power
For 10W, polymer C4F8 gas is filled in reaction chamber 110 with the diluent gas He mixed gas formed carry out it is blunt for the first time
Change.In second of passivation step, third air pressure is 90mT, third bias power is 80W, by polymer C4F8 gas and dilution
The mixed gas that gas He is formed, which is filled in reaction chamber 110, carries out second of passivation.In etching process, the first air pressure is set as
120mT, the first bias power are set as 80W and perform etching to silicon wafer 122.
As shown in figure 3, through a kind of side for being used to improve side wall etching effect in depth-width ratio silicon etching disclosed by the invention
Method, from the etching effect of silicon wafer 122 it is found that by being passivated twice in etching money every time, it can be ensured that polymer is equal
The even opening sidewalls for being distributed in the silicon that is etched, bottom, so that it is guaranteed that the sidewall silicon after etching is not in striated or hole shape
Rough surface, so that uniformity of the silicon top to bottom after etching is more preferable.
It is discussed in detail although the contents of the present invention have passed through above preferred embodiment, but it should be appreciated that above-mentioned
Description is not considered as limitation of the present invention.After those skilled in the art have read above content, for of the invention
A variety of modifications and substitutions all will be apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (7)
1. it is a kind of in high-aspect-ratio silicon etching for the method that improves side wall etching effect, which is characterized in that this method includes
Multiple etching periods repeated, each etching period include:
S1, etch step perform etching silicon, are formed and are open in silicon face；
S2, the first passivation step, is filled with polymer gas in the opening, carries out first time passivation to the opening；
In the first passivation step, while the mixed gas in plasma treatment appts has the second air pressure, at the plasma
It manages after device applies second substrate bias power and carries out first time Passivation Treatment, so that the polymer on the opening sidewalls top is more
In the polymer of open bottom；
S3, the second passivation step；
In the second passivation step, while above-mentioned mixed gas has third air pressure, the plasma treatment appts apply one
A third substrate bias power enables the polymer of the opening sidewalls bottom to be more than the polymer of open top；
Wherein, the second air pressure is greater than the third air pressure, and the second substrate bias power is less than third substrate bias power；
S4 repeats step S1-S3, until reaching target call to the etching depth of silicon.
2. the method in high-aspect-ratio silicon etching for improving side wall etching effect, feature exist as described in claim 1
In the step S1 includes:
The processing gas is utilized using the first air pressure, the first substrate bias power by processing gas is full of in plasma treatment appts
It performs etching to form the opening in silicon face.
3. the method in high-aspect-ratio silicon etching for improving side wall etching effect, feature exist as described in claim 1
In the duration in the first passivation step period is greater than the duration in the second passivation step period.
4. the method in high-aspect-ratio silicon etching for improving side wall etching effect, feature exist as described in claim 1
In diluent gas is for promoting polymer gas diffusion in the mixed gas and being evenly distributed in described in the mixed gas
The inner wall of opening and bottom, and promote the progress of first passivation step, second passivation step.
5. the method in high-aspect-ratio silicon etching for improving side wall etching effect, feature exist as described in claim 1
In polymer gas is carbon fluoride gas in the mixed gas.
6. the method in high-aspect-ratio silicon etching for improving side wall etching effect, feature exist as described in claim 1
In the third substrate bias power is pulsed bias power, which can allow for high spike bias power and protect
Hold mean power.
7. the method in high-aspect-ratio silicon etching for improving side wall etching effect, feature exist as described in claim 1
In the range of the second air pressure setting is 90mT-160mT；The range of second substrate bias power is 0-10W；
The range of the third air pressure setting is 60mT-90mT；The range of the third substrate bias power setting is 50-200W.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1047122A2 (en) * | 1999-04-21 | 2000-10-25 | Alcatel | Method of anisotropic etching of substrates |
| JP2001015489A (en) * | 1999-06-29 | 2001-01-19 | New Japan Radio Co Ltd | Dry etching method |
| WO2013008824A1 (en) * | 2011-07-12 | 2013-01-17 | 東京エレクトロン株式会社 | Plasma etching method |
| CN103021934A (en) * | 2012-12-20 | 2013-04-03 | 中微半导体设备(上海)有限公司 | Method for forming through hole or contact hole |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10131704A1 (en) * | 2001-06-29 | 2003-01-16 | Atmel Germany Gmbh | Method for doping a semiconductor body |
-
2015
- 2015-10-30 CN CN201510721444.9A patent/CN106653594B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1047122A2 (en) * | 1999-04-21 | 2000-10-25 | Alcatel | Method of anisotropic etching of substrates |
| JP2001015489A (en) * | 1999-06-29 | 2001-01-19 | New Japan Radio Co Ltd | Dry etching method |
| WO2013008824A1 (en) * | 2011-07-12 | 2013-01-17 | 東京エレクトロン株式会社 | Plasma etching method |
| CN103021934A (en) * | 2012-12-20 | 2013-04-03 | 中微半导体设备(上海)有限公司 | Method for forming through hole or contact hole |
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