TW201424498A - A circuit board - Google Patents

A circuit board Download PDF

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Publication number
TW201424498A
TW201424498A TW101147612A TW101147612A TW201424498A TW 201424498 A TW201424498 A TW 201424498A TW 101147612 A TW101147612 A TW 101147612A TW 101147612 A TW101147612 A TW 101147612A TW 201424498 A TW201424498 A TW 201424498A
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TW
Taiwan
Prior art keywords
test pad
circuit board
test
circuit
mils
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Application number
TW101147612A
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Chinese (zh)
Inventor
Yung-Lung Chang
Cheng-Hung Wu
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Inventec Corp
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Priority to TW101147612A priority Critical patent/TW201424498A/en
Publication of TW201424498A publication Critical patent/TW201424498A/en

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Abstract

A circuit board includes a substrate, a circuit, and a solder resist layer. The circuit is located on the substrate. The circuit includes a first test pad and a second test pad. There is a default separation between the first test pad and the second test pad. The solder resist layer is located on the circuit. The solder resist layer has two holes which expose the first test pad and the second test pad, respectively.

Description

電路板 Circuit board

本發明係關於一種電路板,特別是一種具有高速訊號量測接點的電路板。 The present invention relates to a circuit board, and more particularly to a circuit board having a high speed signal measuring contact.

這些年來,手持式電子產品(例如行動電話或導航裝置等)均朝向輕薄短小化之方向設計,使得產品內部零件密集度越來越高,相對地在製造這類電子產品過程中之ICT(In-Circuit Test)測試也日趨重要。 Over the years, handheld electronic products (such as mobile phones or navigation devices) have been designed to be light and thin, making the internal parts of the product more and more dense, relatively in the process of manufacturing such electronic products ICT (In -Circuit Test) Testing is also becoming more and more important.

一般PCB(Printed Circuit Board,印刷電路板)在電子零件的周邊具有測試線路,以透過測試線路上的測試點進行高速訊號的功能量測,以藉由量測結果進而分析電路設計的特性。傳統ICT測試方式係自電路板走線(trace)上設計單點式的測試墊來量測高速訊號,再透過ICT設備上之探針接觸測試墊以進行電子零件之電路特性測試。但在進行測試時,所測得之訊號容易受到測試墊影響而產生雜訊,而單點式的測試墊也易造成高速訊號量測不準確的異常現象,進而降低ICT的測試良率。 A printed circuit board (PCB) has test lines around the electronic components to perform high-speed signal measurement through test points on the test lines to analyze the characteristics of the circuit design by measuring the results. The traditional ICT test method is to design a single-point test pad from a circuit board trace to measure the high-speed signal, and then touch the test pad through the probe on the ICT device to perform circuit characteristic test of the electronic part. However, when the test is performed, the measured signal is easily affected by the test pad to generate noise, and the single-point test pad is also likely to cause an inaccurate phenomenon of high-speed signal measurement, thereby reducing the ICT test yield.

有鑑於先前技術所遭遇之問題,本發明係揭露一種電路板,俾以具有第一測試墊與第二測試墊的電路板,以提升高速訊號量測之準確率,以達高速訊號之測試高良率的效果。 In view of the problems encountered in the prior art, the present invention discloses a circuit board with a circuit board having a first test pad and a second test pad to improve the accuracy of high-speed signal measurement, so as to test high-speed signals. The effect of the rate.

根據本發明之一實施例之一種電路板,包括有一基板、一線 路、及一防銲層。線路設置於基板上且線路包含一第一測試墊以及一第二測試墊,第一測試墊與第二測試墊間隔一預設距離。防銲層設置於線路上且防銲層具有二開孔,此二開孔分別曝露第一測試墊與第二測試墊。 A circuit board according to an embodiment of the invention includes a substrate and a line Road, and a solder mask. The circuit is disposed on the substrate and the circuit includes a first test pad and a second test pad. The first test pad is spaced apart from the second test pad by a predetermined distance. The solder resist layer is disposed on the line and the solder resist layer has two openings, and the two openings respectively expose the first test pad and the second test pad.

由於此電路板具有彼此相間隔的第一測試墊與第二測試墊,是以,相較於習知的單點式測試墊而言,當測試治具上的探針接觸此第一測試墊與第二測試墊時,上述實施例的電路板可提升高速訊號量測之準確率。 Since the circuit board has the first test pad and the second test pad spaced apart from each other, the probe on the test fixture contacts the first test pad compared to the conventional single-point test pad. When the second test pad is used, the circuit board of the above embodiment can improve the accuracy of high-speed signal measurement.

以上之關於本發明內容之說明及以下之實施方式之說明係用以示範與解釋本發明之精神與原理,並且提供本發明之專利申請範圍更進一步之解釋。 The above description of the present invention and the following description of the embodiments of the present invention are intended to illustrate and explain the spirit and principles of the invention.

以下在實施方式中詳細敘述本發明之詳細特徵以及優點,其內容足以使任何熟習相關技藝者了解本發明之技術內容並據以實施,且根據本說明書所揭露之內容、申請專利範圍及圖式,任何熟習相關技藝者可輕易地理解本發明相關之目的及優點。以下之實施例係進一步詳細說明本發明之觀點,但非以任何觀點限制本發明之範疇。 The detailed features and advantages of the present invention are set forth in the Detailed Description of the Detailed Description of the <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> <RTIgt; The objects and advantages associated with the present invention can be readily understood by those skilled in the art. The following examples are intended to describe the present invention in further detail, but are not intended to limit the scope of the invention.

請參照『第1A圖』,係為根據本發明之一實施例之一種電路板100,包括有一基板101、一線路102、及一防銲層103。線路102設置於基板101上且線路102包含一第一測試墊120及一第二測試墊140。第一測試墊120與第二測試墊140間隔一預設距離x, 在部分實施例中,x可為10密爾。 Referring to FIG. 1A, a circuit board 100 according to an embodiment of the present invention includes a substrate 101, a line 102, and a solder resist layer 103. The line 102 is disposed on the substrate 101 and the line 102 includes a first test pad 120 and a second test pad 140. The first test pad 120 is spaced apart from the second test pad 140 by a predetermined distance x, In some embodiments, x can be 10 mils.

請接著參照『第1B圖』,係為『第1A圖』之電路板100的側視圖,如『第1B圖』所示,防銲層103覆蓋基板101與線路102,並且具有二開孔104、105,此二開孔104、105分別曝露第一測試墊120與第二測試墊140,此防銲層103之二開孔104、105係用以定義出第一測試墊120與第二測試墊140之銲錫區域,換言之,此具有二開孔104、105之防銲層103可防止銲錫溢流至電路板100的其他區域。 Please refer to FIG. 1B for a side view of the circuit board 100 of FIG. 1A. As shown in FIG. 1B, the solder resist layer 103 covers the substrate 101 and the line 102, and has two openings 104. The first test pad 120 and the second test pad 140 are respectively exposed by the two openings 104 and 105. The two openings 104 and 105 of the solder resist layer 103 are used to define the first test pad 120 and the second test. The solder region of the pad 140, in other words, the solder mask layer 103 having the two openings 104, 105 prevents solder from overflowing to other areas of the circuit board 100.

在本實施例中,第一測試墊120與第二測試墊140的形狀為半橢圓且第一測試墊120的面積與第二測試墊140的面積相等。在部份實施例中,第一測試墊120與第二測試墊140的形狀亦可為橢圓或是矩形,但不以此為限。此外,第一測試墊120與第二測試墊140間隔一預設距離x,在部分實施例中,x可為10密爾。 In this embodiment, the shapes of the first test pad 120 and the second test pad 140 are semi-elliptical and the area of the first test pad 120 is equal to the area of the second test pad 140. In some embodiments, the shape of the first test pad 120 and the second test pad 140 may be elliptical or rectangular, but not limited thereto. In addition, the first test pad 120 is spaced apart from the second test pad 140 by a predetermined distance x, and in some embodiments, x may be 10 mils.

請參照『第2圖』,其繪示將銲錫植入『第1A圖』的電路板100的示意圖。錫膏是透過鋼板而被塗佈在『第1A圖』的電路板100上,之後,再經由高溫錫爐的製程,使二錫球210、220分別形成於防銲層103的二開孔處104、105且此二錫球210、220分別電性連接於『第1A圖』的第一測試墊120與第二測試墊140。在部分實施例中,此線路102的材質可為銅,但不以此為限,此材質用以增加與錫球之間的附著力。而鋼板的開孔孔徑可為4毫米,以提升『第1A圖』的第一測試墊120與第二測試墊140與銲錫之間的接觸面積。 錫之間的接觸面積。 Please refer to FIG. 2, which shows a schematic diagram of the soldering of the circuit board 100 of FIG. 1A. The solder paste is applied to the circuit board 100 of FIG. 1A through the steel sheet, and then the solder balls 210 and 220 are respectively formed at the two openings of the solder resist layer 103 via the high-temperature solder furnace process. 104, 105 and the two solder balls 210 and 220 are electrically connected to the first test pad 120 and the second test pad 140 of FIG. 1A. In some embodiments, the material of the line 102 can be copper, but not limited thereto. The material is used to increase the adhesion with the solder ball. The opening diameter of the steel plate can be 4 mm to improve the contact area between the first test pad 120 and the second test pad 140 of "Fig. 1A" and the solder. The contact area between the tin.

另一方面,此植入銲錫的電路板100可搭配測試治具上的探針設計,使二錫球210、220與探針彼此接觸以量測高速訊號。在部分實施例中,此探針可為平爪針或是星形針,其中平爪針可具有十六個爪數且針頭直徑可為35密爾,而星形針可具有八個邊且針頭直徑亦可為35密爾。 On the other hand, the solder-implanted circuit board 100 can be used with the probe design on the test fixture to bring the tin balls 210, 220 and the probe into contact with each other to measure the high-speed signal. In some embodiments, the probe can be a flat or star needle, wherein the flat needle can have sixteen jaws and the needle diameter can be 35 mils, while the star can have eight sides and The needle diameter can also be 35 mils.

為了提升高速訊號量測的準確率,在部分實施例中,『第1A圖』的第一測試墊120與第二測試墊140的長度y及寬度z可設計為以下的組合。第一組長度y可為6.5密爾、寬度z可介於7.5密爾至8密爾,第二組長度y可為7.35密爾、寬度z可介於6.5密爾至7密爾,第三組長度y可為8密爾、寬度z可介於5.5密爾至6密爾,第四組長度y可為10密爾、寬度z可介於4.5密爾至5密爾,第五組長度y可為12密爾、寬度z可介於3.5密爾至4密爾。 In order to improve the accuracy of the high-speed signal measurement, in some embodiments, the length y and the width z of the first test pad 120 and the second test pad 140 of FIG. 1A can be designed as the following combinations. The first set of lengths y may be 6.5 mils, the width z may be between 7.5 mils and 8 mils, the second set of lengths y may be 7.35 mils, and the width z may be between 6.5 mils to 7 mils, the third The group length y can be 8 mils, the width z can be between 5.5 mils to 6 mils, the fourth set length y can be 10 mils, the width z can be between 4.5 mils to 5 mils, and the fifth set length y can be 12 mils and width z can range from 3.5 mils to 4 mils.

將此具有如『第1A圖』所示的第一測試墊120與第二測試墊140的電路板100載入一測試機台的測試治具上,搭配測試治具上之平爪針或是星形針的探針設計,如此組合的測試方法可稱為MECA(micro-embedded component access,微型嵌入式元件量測)。經過測試製程的良率統計後,此具有第一測試墊120與第二測試墊140的電路板100可提升高速訊號量測之準確率。 The circuit board 100 having the first test pad 120 and the second test pad 140 as shown in FIG. 1A is loaded on a test fixture of a test machine, and is matched with a flat claw on the test fixture or The probe design of the star needle, the test method thus combined can be called MECA (micro-embedded component access). After the yield statistics of the test process, the circuit board 100 having the first test pad 120 and the second test pad 140 can improve the accuracy of the high-speed signal measurement.

綜上所述,由於本實施例的電路板具有彼此相間隔的第一測試墊與第二測試墊,是以,相較於習知的單點式測試墊而言,當 測試治具上的探針接觸此第一測試墊與第二測試墊時,上述實施例的電路板可提升高速訊號量測之準確率。 In summary, since the circuit board of the embodiment has the first test pad and the second test pad spaced apart from each other, compared with the conventional single-point test pad, when When the probe on the test fixture contacts the first test pad and the second test pad, the circuit board of the above embodiment can improve the accuracy of the high-speed signal measurement.

雖然本發明以前述之實施例揭露如上,然其並非用以限定本發明。在不脫離本發明之精神和範圍內,所為之更動與潤飾,均屬本發明之專利保護範圍。關於本發明所界定之保護範圍請參考所附之申請專利範圍。 Although the present invention has been disclosed above in the foregoing embodiments, it is not intended to limit the invention. It is within the scope of the invention to be modified and modified without departing from the spirit and scope of the invention. Please refer to the attached patent application for the scope of protection defined by the present invention.

100‧‧‧電路板 100‧‧‧ boards

101‧‧‧基板 101‧‧‧Substrate

102‧‧‧線路 102‧‧‧ lines

103‧‧‧防銲層 103‧‧‧ solder mask

104、105‧‧‧二開孔 104, 105‧‧‧ two openings

120‧‧‧第一測試墊 120‧‧‧First test pad

140‧‧‧第二測試墊 140‧‧‧Second test pad

210、220‧‧‧二錫球 210, 220‧‧‧ two tin balls

x‧‧‧預設距離 x‧‧‧Preset distance

y‧‧‧第一測試墊長度、第二測試墊長度 y‧‧‧First test pad length, second test pad length

z‧‧‧第一測試墊寬度、第二測試墊寬度 z‧‧‧First test pad width, second test pad width

第1A圖係為根據本發明之一實施例之一種電路板。 Figure 1A is a circuit board in accordance with an embodiment of the present invention.

第1B圖係為第1A圖之電路板的側視圖。 Fig. 1B is a side view of the circuit board of Fig. 1A.

第2圖係為將銲錫植入第1A圖的電路板的示意圖。 Fig. 2 is a schematic view showing the implantation of solder into the circuit board of Fig. 1A.

100‧‧‧電路板 100‧‧‧ boards

101‧‧‧基板 101‧‧‧Substrate

102‧‧‧線路 102‧‧‧ lines

103‧‧‧防銲層 103‧‧‧ solder mask

120‧‧‧第一測試墊 120‧‧‧First test pad

140‧‧‧第二測試墊 140‧‧‧Second test pad

x‧‧‧預設距離 x‧‧‧Preset distance

y‧‧‧第一測試墊長度、第二測試墊長度 y‧‧‧First test pad length, second test pad length

z‧‧‧第一測試墊寬度、第二測試墊寬度 z‧‧‧First test pad width, second test pad width

Claims (6)

一種電路板,包括有:一基板;一線路,設置於該基板上,該線路包含一第一測試墊以及一第二測試墊,該第一測試墊與該第二測試墊間隔一預設距離;以及一防銲層,設置於該線路上,該防銲層具有二開孔,該二開孔分別曝露該第一測試墊與該第二測試墊。 A circuit board includes: a substrate; a circuit disposed on the substrate, the circuit comprising a first test pad and a second test pad, the first test pad being spaced apart from the second test pad by a predetermined distance And a solder resist layer disposed on the circuit, the solder resist layer having two openings, the two openings respectively exposing the first test pad and the second test pad. 如請求項1所述的電路板,其中該預設距離為10密爾。 The circuit board of claim 1, wherein the predetermined distance is 10 mils. 如請求項1所述的電路板,其中該第一測試墊與該第二測試墊的形狀為半橢圓。 The circuit board of claim 1, wherein the first test pad and the second test pad are semi-elliptical in shape. 如請求項1所述的電路板,其中該第一測試墊與該第二測試墊的形狀為橢圓。 The circuit board of claim 1, wherein the first test pad and the second test pad are elliptical in shape. 如請求項1所述的電路板,其中該第一測試墊與該第二測試墊的形狀為矩形。 The circuit board of claim 1, wherein the first test pad and the second test pad are rectangular in shape. 如請求項1所述的電路板,其中該線路的材質為銅。 The circuit board of claim 1, wherein the circuit is made of copper.
TW101147612A 2012-12-14 2012-12-14 A circuit board TW201424498A (en)

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