KR101142340B1 - Substrate for semiconductor package and method for fabricating the same - Google Patents

Substrate for semiconductor package and method for fabricating the same Download PDF

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Publication number
KR101142340B1
KR101142340B1 KR1020100093221A KR20100093221A KR101142340B1 KR 101142340 B1 KR101142340 B1 KR 101142340B1 KR 1020100093221 A KR1020100093221 A KR 1020100093221A KR 20100093221 A KR20100093221 A KR 20100093221A KR 101142340 B1 KR101142340 B1 KR 101142340B1
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KR
South Korea
Prior art keywords
substrate
substrate body
semiconductor package
electrically connected
resistors
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KR1020100093221A
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Korean (ko)
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KR20120031687A (en
Inventor
이웅선
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에스케이하이닉스 주식회사
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Priority to KR1020100093221A priority Critical patent/KR101142340B1/en
Publication of KR20120031687A publication Critical patent/KR20120031687A/en
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Publication of KR101142340B1 publication Critical patent/KR101142340B1/en

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Automation & Control Theory (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)

Abstract

The present invention discloses a substrate for a semiconductor package and a method of manufacturing the same. According to an aspect of the present invention, there is provided a semiconductor package substrate including: a substrate body having one surface and the other surface facing the one surface, the substrate body being divided into a chip mounting portion and an outer portion; A plurality of first circuit patterns formed on the one surface of the substrate body; A plurality of second circuit patterns formed on the other surface of the substrate body and electrically connected to each of the first circuit patterns and including a ball land; A plurality of resistors embedded in the substrate body and electrically connected to the first circuit pattern and the second circuit pattern, respectively; And a probe pad formed on one surface of the substrate body and electrically connected to the plurality of resistors.

Description

Substrate for semiconductor package and method for fabricating the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package substrate and a method for manufacturing the same, and more particularly, to a semiconductor package substrate and a method for manufacturing the same, capable of measuring a resistance value of a resistor embedded in the substrate.

As the size of various electric and electronic products is miniaturized, many studies are being conducted to achieve a small size and high capacity by mounting a larger number of chips on a limited sized substrate.

Accordingly, the size and thickness of the semiconductor package mounted on the printed circuit board (PCB) is gradually reduced. For example, research and development on how to reduce the size of the PCB is being actively conducted, and methods are used that can make fine lines finer and reduce space for electrical connection on the PCB.

Among them, a technology for forming an embedded resistor is a useful technique for reducing the size of a PCB, and after forming a hole in which an electronic device is embedded in an insulator, the electronic device is positioned and fixed using a filler or the like.

According to such a process, since the electric element is not mounted on the surface of the substrate but is mounted inside the substrate, not only can the substrate be made smaller and higher in density, but also the performance of the substrate can be improved.

On the other hand, Figure 1 is a view showing for measuring the resistance value of the conventional built-in resistance.

As shown, in order to measure the resistance value of the resistor 102 embedded in the substrate 100, first, a resistor 102 to be measured at a desired portion of a plurality of resistors embedded in the substrate 100 is selected. . Then, probe pads 104 are formed on each of the resistors 102 selected from the plurality of resistors to measure resistance values, respectively. In this case, the probe pad 104 is formed to have a size larger than, for example, five times or more than a wiring (not shown) connected to the selected resistor 102.

Subsequently, probe pins P1 and P2 connected to a resistance measuring device are connected to the probe pad 104 so as to measure the resistance value of the selected resistor 102, respectively. Measure the resistance value of 102). Here, reference numeral P1, which is not described, refers to the first probe pin, and P2 refers to the second probe pin.

However, since the probe pad 104 is five times larger in size than the wiring as described above, the probe pad 104 cannot be formed in a space in which many wirings of an actual package substrate enter.

Therefore, due to the lack of space for forming the probe pad, it is often impossible to measure the resistance value of the resistance of the desired portion, and often the characteristics of the device cannot be properly evaluated.

The present invention provides a substrate for a semiconductor package that can measure a resistance value of a resistance to be measured in the substrate.

Moreover, this invention provides the manufacturing method of the board | substrate for semiconductor packages which has the said board | substrate.

According to an embodiment of the present invention, a semiconductor package substrate includes: a substrate body having one surface and the other surface opposite to the one surface and divided into a chip mounting portion and an outer portion; A plurality of first circuit patterns formed on the one surface of the substrate body; A plurality of second circuit patterns formed on the other surface of the substrate body and electrically connected to each of the first circuit patterns and including a ball land; A plurality of resistors embedded in the substrate body and electrically connected to the first circuit pattern and the second circuit pattern, respectively; And a probe pad formed on one surface of the substrate body and electrically connected to the plurality of resistors.

And a plurality of bond fingers on one surface of the substrate body, wherein the plurality of bond fingers are each electrically connected to the corresponding plurality of first circuit patterns.

Further comprising a plurality of electroplating lines on one surface of the substrate body, the electroplating lines electrically connect the plurality of bond fingers and the probe pad.

The probe pad is formed on an outer portion of the substrate body.

The plurality of resistors are formed on the chip mounting portion of the substrate body.

According to another aspect of the present invention, there is provided a method of manufacturing a substrate for a semiconductor package, the substrate body having one surface and the other surface facing the one surface and divided into a chip mounting portion and an outer portion, and a plurality of agents formed on the surface of the substrate body. One circuit pattern, a plurality of second circuit patterns formed on the other surface of the substrate body and electrically connected to each of the first circuit patterns, each of the second circuit patterns including a borland, and embedded in the substrate body, respectively; And forming a substrate including a plurality of resistors electrically connected to a second circuit pattern and a probe pad formed on the surface of the substrate body, the probe pads electrically connected to the plurality of resistors. And connecting a first probe pin to the probe pad formed on the one surface of the substrate body, and connecting a second probe pin to a second circuit pattern connected to any one selected from among the plurality of resistors. Measuring a value.

The forming of the substrate further includes forming a plurality of bond fingers on one surface of the substrate body, wherein the plurality of bond fingers are electrically connected to the corresponding plurality of first circuit patterns, respectively. It is characterized by forming.

In the forming of the substrate, the method may further include forming a plurality of electroplating lines on one surface of the substrate body, wherein the electroplating lines are formed to electrically connect the plurality of bond fingers and the probe pad. Characterized in that.

In the forming of the substrate, the probe pad may be formed at an outer portion of the substrate body.

In the forming of the substrate, the plurality of resistors may be formed in a chip mounting part of the substrate body.

After the step of measuring the resistance value, the step of separating the electroplating lines formed on one surface of the substrate body; characterized in that it further comprises.

The present invention can measure a resistance value of a resistance to be measured embedded in the substrate using a substrate including a probe pad electrically connected to a plurality of embedded resistors.

In addition, the present invention can improve the problem caused by the lack of space for forming the probe pad because it is not necessary to form a separate probe pad around the resistance to be measured in order to measure the resistance value of the desired portion. .

As a result, the present invention can measure the resistance value of the resistance of the desired site, it is possible to properly evaluate the characteristics of the device.

1 is a diagram for measuring the resistance value of a conventional built-in resistance.
2A and 2B illustrate a semiconductor package substrate according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A and 2B illustrate a semiconductor package substrate according to an embodiment of the present invention.

As shown, the semiconductor package substrate 250 according to an embodiment of the present invention is the substrate body 200, the first circuit pattern 204a, the second circuit pattern 204b, the resistor (R) and the probe pad (P).

Hereinafter, the semiconductor package substrate 250 will be described.

First, the substrate body 200 has one surface (a) and the other surface (b) facing the one surface (a) and is divided into a chip mounting portion and an outer portion. The chip mounting portion represents a portion where the chip is mounted, and the outer portion represents a portion where the bond finger 202 is formed. Here, the substrate body 200 may be, for example, a printed circuit board.

A plurality of bond fingers 202 are formed on one surface a of the substrate body 200, and a plurality of electroplating lines (not shown) are further formed on one surface a of the substrate body 200. .

Subsequently, a plurality of first circuit patterns 204a are formed on the one surface a of the substrate body 200. The plurality of first circuit patterns 204a are electrically connected to the plurality of bond fingers 202, respectively.

A plurality of second circuit patterns 204b are formed on the other surface b of the substrate body 200 to be electrically connected to each of the first circuit patterns 204a and include the ball lands 206.

The resistor R is embedded in the substrate body 200, and a plurality of resistors R are formed to be electrically connected to the first circuit pattern 204a and the second circuit pattern 204b, respectively. The plurality of resistors R are formed in the chip mounting portion of the substrate body 200.

Alternatively, the plurality of resistors R may also be formed on the outer portion of the substrate body 200.

The probe pad P is formed on one surface a of the substrate body 200, and preferably, formed on an outer portion of the substrate body 200. Here, the probe pad P has a size of 100 μm × 100 μm, for example.

The probe pad P is electrically connected to the plurality of resistors R, and is electrically connected to the plurality of bond fingers 202 and the electroplating lines.

Although not shown in detail, the first circuit pattern 204a and the second circuit pattern 204b are preferably electrically connected through the via 208.

Since each of the ball lands 206 formed on the other surface b of the substrate body 200 cannot be connected to each other collectively through an electrolytic plating line, each ball land 206 is provided through an electroless plating line without a plating line. Connect it.

That is, since each borland 206 is not connected through the electroplating line, the second circuit pattern 204b of each borland 206 is connected to the via 208 from the one surface a of the substrate body 200. It is connected through) can be electrically connected to the bond finger 202.

As described above, the present invention forms a plurality of resistors by forming the probe pad P so as to be electrically connected to the first and second circuit patterns 204a and 204b on the outer portion of the substrate body 200. Since a separate probe pad forming process for measuring the resistance value of the selected resistance can be omitted, the process for measuring the resistance value and the additional cost can be reduced.

In addition, the present invention can secure the formation space of the probe pad for measuring the resistance value can increase the utilization of the space in the package.

In addition, since the present invention uses the probe pad P and the borland 206, the resistance value of the resistance to be measured can be accurately and easily measured.

Meanwhile, although not shown in detail below, the resistance probing method using the semiconductor package substrate 250 will be briefly described with reference to FIGS. 2A and 2B.

First, the substrate 250 is prepared. In order to measure the resistance (C) of any one selected from the plurality of resistors (R) embedded in the substrate 250, the probe pad (P) formed on the one surface (a) of the substrate body 200 Connect probe 1 (P1).

Then, the second probe pin P2 is connected to the second circuit pattern 204b connected to the plurality of resistors R to measure the resistance value of the selected resistor C. At this time, in order to measure the resistance value of the selected resistor (C), it is preferable to connect the second probe pin (P2) to the portion corresponding to the borland 206.

As described above, the present invention may measure the resistance value of the resistance to be measured embedded in the substrate by using a substrate including a probe pad electrically connected to a plurality of embedded resistors.

In addition, the present invention can improve the problem caused by the lack of space for forming the probe pad because it is not necessary to form a separate probe pad around the resistance to be measured in order to measure the resistance value of the desired portion. .

As a result, the present invention can measure the resistance value of the resistance of the desired site, it is possible to properly evaluate the characteristics of the device.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

200: substrate body 204a: first circuit pattern
204b: second circuit pattern R: resistance
P: probe pad 250: substrate

Claims (11)

A substrate body having one surface and the other surface opposite to the one surface and divided into a chip mounting portion and an outer portion;
A plurality of first circuit patterns formed on the one surface of the substrate body;
A plurality of second circuit patterns formed on the other surface of the substrate body and electrically connected to each of the first circuit patterns and including a ball land;
A plurality of resistors embedded in the substrate body and electrically connected to the first circuit pattern and the second circuit pattern, respectively; And
A probe pad formed on one surface of the substrate body and electrically connected to the plurality of resistors;
Substrate for semiconductor package comprising a. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1,
And a plurality of bond fingers on one surface of the substrate body, wherein the plurality of bond fingers are electrically connected to the corresponding plurality of first circuit patterns, respectively. Claim 3 was abandoned when the setup registration fee was paid. The method of claim 2,
And a plurality of electroplating lines on one surface of the substrate body, wherein the electroplating lines electrically connect the plurality of bond fingers and the probe pad. Claim 4 was abandoned when the registration fee was paid. The method of claim 1,
The probe pad is a semiconductor package substrate, characterized in that formed on the outer portion of the substrate body. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 1,
The plurality of resistors are formed in the chip mounting portion of the substrate body substrate for a semiconductor package. A substrate body having one surface and the other surface opposite to the one surface and divided into a chip mounting portion and an outer portion, a plurality of first circuit patterns formed on the one surface of the substrate body, and formed on the other surface of the substrate body. A plurality of second circuit patterns electrically connected to one circuit pattern, each of which includes a borland, a plurality of resistors embedded in the substrate body and electrically connected to the first circuit pattern and the second circuit pattern, respectively; Forming a substrate formed on the surface of the substrate, the substrate including a probe pad electrically connected to the plurality of resistors; And
A first probe pin is connected to the probe pad formed on the one surface of the substrate body, and a second probe pin is connected to a second circuit pattern connected to any one selected from among the plurality of resistors to form a resistance value of the selected resistor; Measuring;
Method of manufacturing a substrate for a semiconductor package comprising a. Claim 7 was abandoned upon payment of a set-up fee. The method according to claim 6,
The forming of the substrate further includes forming a plurality of bond fingers on one surface of the substrate body, wherein the plurality of bond fingers are electrically connected to the corresponding plurality of first circuit patterns, respectively. The manufacturing method of the board | substrate for semiconductor packages characterized by the above-mentioned. Claim 8 was abandoned when the registration fee was paid. The method of claim 7, wherein
In the forming of the substrate, the method may further include forming a plurality of electroplating lines on one surface of the substrate body, wherein the electroplating lines are formed to electrically connect the plurality of bond fingers and the probe pad. A method of manufacturing a substrate for a semiconductor package, characterized in that. Claim 9 was abandoned upon payment of a set-up fee. The method according to claim 6,
In the step of forming the substrate, the probe pad is a manufacturing method for a semiconductor package substrate, characterized in that formed on the outer portion of the substrate body. Claim 10 was abandoned upon payment of a setup registration fee. The method according to claim 6,
In the forming of the substrate, the plurality of resistors are formed in the chip mounting portion of the substrate body, characterized in that the manufacturing method for a substrate for a semiconductor package. Claim 11 was abandoned upon payment of a setup registration fee. The method according to claim 6 or 8,
After measuring the resistance value,
Separating the electroplating lines formed on one surface of the substrate body;
Method of manufacturing a substrate for a semiconductor package, characterized in that it further comprises.
KR1020100093221A 2010-09-27 2010-09-27 Substrate for semiconductor package and method for fabricating the same KR101142340B1 (en)

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KR1020100093221A KR101142340B1 (en) 2010-09-27 2010-09-27 Substrate for semiconductor package and method for fabricating the same

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Application Number Priority Date Filing Date Title
KR1020100093221A KR101142340B1 (en) 2010-09-27 2010-09-27 Substrate for semiconductor package and method for fabricating the same

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KR101142340B1 true KR101142340B1 (en) 2012-05-17

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02163990A (en) * 1988-12-16 1990-06-25 Toshiba Corp Hybrid integrated circuit device
JP2000171500A (en) 1998-12-07 2000-06-23 Matsushita Electric Ind Co Ltd Resistance-measuring device of printed wiring board and resistance measurement method using it
JP2006237299A (en) 2005-02-25 2006-09-07 Kyocera Corp Wiring board
KR20100009055A (en) * 2008-07-17 2010-01-27 삼성전자주식회사 Printed circuit board for accomplishing a narrow scribe lane and semiconductor package having the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02163990A (en) * 1988-12-16 1990-06-25 Toshiba Corp Hybrid integrated circuit device
JP2000171500A (en) 1998-12-07 2000-06-23 Matsushita Electric Ind Co Ltd Resistance-measuring device of printed wiring board and resistance measurement method using it
JP2006237299A (en) 2005-02-25 2006-09-07 Kyocera Corp Wiring board
KR20100009055A (en) * 2008-07-17 2010-01-27 삼성전자주식회사 Printed circuit board for accomplishing a narrow scribe lane and semiconductor package having the same

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