TW201419472A - Semiconductor packaging structure - Google Patents

Abstract

A semiconductor packaging structure including a substrate, a plurality of flip chips, at least one wire bond chip and a plurality of wires is provided. The substrate includes a first surface and a second surface opposite to each other, an opening and a plurality of pads. The substrate is passed through by the opening, and the pads are disposed on the first surface and the second surface. The flip chips are disposed on the first surface of the substrate and electrically connected to the pads disposed on the first surface. The wire bond chip is disposed on the flip chips. The wires are electrically connected to a part of pads disposed on the first or second surfaces of the substrate and the wire bond chip.

Description

Semiconductor package structure

The present invention relates to a semiconductor package structure, and more particularly to a multi-wafer stacked semiconductor package structure.

With the proliferation of mobile multimedia products and their urgent need for higher digital signal processing, new storage architectures with higher storage capacity and flexibility, multi-chip stacked semiconductor package structures, such as stacked package on (stacked package on) Package, PoP), its application is growing rapidly.

1 is a schematic diagram of a conventional multi-wafer stacked semiconductor package structure. Referring to FIG. 1 , the conventional semiconductor package structure 10 includes a lower package 20 , an upper package 30 , a plurality of first solder balls 40 , and a plurality of second solder balls 50 .

The lower package 20 includes a first substrate 22, a plurality of first pads 24, and a flip chip 26. The first substrate 22 includes a first surface 22a and a second surface 22b. The first pad 24 is located on the first surface 22a and the second surface 22b of the first substrate 22. The flip chip 26 is disposed on the first substrate 22. The first surface 22a is electrically connected to the first pad 24 on the first surface 22a of the first substrate 22. The first solder ball 40 is connected to the first pad 24 on the second surface 22b of the first substrate 22 to be connected to an external circuit 60.

The upper package 30 includes a second substrate 32, a plurality of second pads 34, and a bonding wire wafer 36. The second substrate 32 includes a first surface 32a and a second surface 32b, and the second pad 34 is located at the first of the second substrate 32. The wire 32 is disposed on the first surface 32a of the second substrate 32 and is electrically connected to the second pad on the first surface 32a of the second substrate 32 by at least one bonding wire 70. 34. The second solder ball 50 is located between the first pad 24 of the first surface 22a of the first substrate 22 and the second pad 34 of the second surface 32b of the second substrate 32 to make the first substrate 22 and the second substrate 32 electrical connection.

In FIG. 1, flip chip 26 is a high density digital or mixed signal logic element, and bond wire wafer 36 is a high density or combined memory. By laminating the flip chip 26 and the bond wire wafer 36, it is possible to integrate the two functions to provide better performance.

However, as shown in FIG. 1 , the lower package 20 and the upper package 30 of the conventional semiconductor package structure 10 are connected through the first solder ball 40 , which may cause the lower package 20 due to thermal stress and the like. The occurrence of a warpage mismatch with the upper package 30 occurs, causing the first solder balls 40 to be poorly connected, resulting in electrical disconnection or reduced reliability. In addition, the electrical connection path between the flip chip 26, the bonding wire wafer 36 and the external circuit 60 is long, which also makes its performance difficult to improve.

The present invention provides a semiconductor package structure which can reduce warpage caused by a package structure when a plurality of wafers are stacked, and can provide a short electrical connection path between each wafer and an external circuit.

The invention provides a semiconductor package structure comprising a substrate, a plurality of flip chip, one or more bond wire wafers and a plurality of bonding wires. The substrate includes a first surface and a second surface, a slot and a plurality of pads The substrate is disposed on the first surface and the second surface. The flip chip is respectively disposed on the first surface of the substrate and electrically connected to the pads on the first surface. Wire bond wafers are placed on these flip chip wafers. The plurality of bonding wires are electrically connected to the first surface of the substrate or the partial pads of the second surface and the bonding wire wafer.

In an embodiment of the invention, the bonding wires are electrically connected to the partial pads of the second surface of the substrate and the bonding wire wafer.

In an embodiment of the invention, the semiconductor package structure further includes a plurality of metal bumps electrically connected to the pads and the flip chip of the first surface of the substrate.

In one embodiment of the present invention, the semiconductor package structure further includes a plurality of solder balls or a plurality of pins, and a plurality of pads disposed on the second surface of the substrate, and the semiconductor package structure is electrically connected to the first through the solder balls or pins. External circuit.

In an embodiment of the invention, the substrate comprises a plurality of layers of wires, the layers of the wires comprising the pads on the first surface and the second surface.

In an embodiment of the invention, the flip chip is disposed on the first surface of the substrate with an active side.

In an embodiment of the invention, the wire bond wafer is disposed on an inactive side of each of the flip chip on an active side.

In an embodiment of the invention, the wire bonding die includes a plurality of pads, wherein the pads of the bonding wire wafer are on the active side, and projections of the pads of the bonding wire wafer on the first surface of the substrate overlap groove.

In an embodiment of the invention, the semiconductor package structure further includes a weight Configuring a circuit layer, the reconfiguration circuit layer is disposed on one active side of the bonding wire wafer, the bonding wire wafer includes a plurality of pads, and the projections of the pads of the bonding wire wafer on the first surface of the substrate do not overlap the slot, the bonding wire The pads are connected to the reconfiguration circuit layer and the reconfiguration circuit layer extends to the pads of the wire bond wafer to electrically connect the substrate to the wire bond wafer.

In an embodiment of the invention, the semiconductor package structure further includes an adhesive layer between the flip chip and the bonding wire wafer.

In an embodiment of the invention, the semiconductor package structure further includes an encapsulant that encapsulates the flip chip, the bonding wire wafer, the bonding wires, the first surface of the substrate, the groove, and a portion of the second surface.

In one embodiment of the invention, the encapsulant protruding from the second surface of the substrate extends into a recess in an external circuit.

In one embodiment of the present invention, the wire bonding wafers include a first bonding wire wafer and a second bonding wire wafer, and one of the second bonding wire wafers is non-actively stacked on one of the first bonding wire wafers. Inactive side.

Based on the above, compared with the conventional semiconductor package structure, due to the influence of the inconsistent structure of the upper and lower packages, the warpage mismatch occurs due to the influence of thermal stress. In the semiconductor package structure substrate of the present invention, the bonding wire wafer is directly disposed on the flip chip, and the substrate, the flip chip and the bonding wire wafer are integrated in a single encapsulant, and the structure is symmetrical to reduce the warpage. In addition, the semiconductor package structure of the present invention is directly disposed on the flip chip by the bonding wire wafer, and the bonding wire is electrically connected to the pads of the first surface or the second surface of the substrate by the bonding wires. The path of electrical connection with an external circuit can be shortened, and the thickness of the semiconductor package structure can also be reduced.

The above described features and advantages of the present invention will be more apparent from the following description.

2 is a schematic diagram of a semiconductor package structure in accordance with an embodiment of the present invention. Referring to FIG. 2 , the semiconductor package structure 100 of the present embodiment includes a substrate 110 , a plurality of flip chip 120 , one or more bond wire wafers 130 , and a plurality of bonding wires 140 .

The substrate 110 includes a first surface 112 and a second surface 114, a slot 116 and a plurality of layers of wires 117. The slot 116 penetrates through the substrate 110. The wire layers 117 include a plurality of pads 118 formed on the first surface 112 and the second surface 114 of the substrate 110.

The flip chip 120 is disposed on the first surface 112 of the substrate 110 and on both sides of the slot 116. The flip chip 120 is electrically connected to the pads 118 on the first surface 112 of the substrate 110. The semiconductor package structure 100 of the present embodiment further includes a plurality of metal bumps 150. The flip chip 120 is disposed on the first surface 112 of the substrate 110 by an active side 122. The metal bumps 150 are connected to the first surface 112 of the substrate 110. The pads 124 and the pads 124 on the active side 122 of the flip chip 120 electrically connect the flip chip 120 to the substrate 110. In the present embodiment, the number of the flip chip 120 of the semiconductor package structure 100 is exemplified by two, but the number of the flip chip 120 is not limited thereto, and may be two or more.

In the present embodiment, one wire bonding die 130 is taken as an example, but in other embodiments, the number of bonding wire wafers 130 may be plural. The wire bond wafer 130 is disposed on the flip chip 120. In the embodiment, the semiconductor package structure 100 Further, an adhesive layer 160 is disposed between the flip chip 120 and the bonding wire wafer 130, and the flip chip 120 and the bonding wire wafer 130 are fixed to each other through the adhesive layer 160. In addition, in the present embodiment, the wire bond wafer 130 is disposed on one of the active side 126 of each flip chip 120 with an active side 132. The bonding wire wafer 130 includes a plurality of pads 134. The pads 134 of the bonding wire wafer 130 are located on a region of the active side 132 that does not overlap the flip chip 120. In FIG. 2, since the two sides of the bonding wire wafer 130 are respectively The flip chip 120 contacts, and the pads 134 of the bond wafer 130 are intermediate regions on the active side 132. Of course, in other embodiments, the position of the pads 134 of the bonding wire 130 may be changed depending on the number of the bonding wires 130 and the flip chip 120 and the arrangement position, and is not limited thereto.

The plurality of bonding wires 140 pass through the slot 116. The two ends of the bonding wire 140 are respectively connected to the partial pads 118 of the second surface 114 of the substrate 110 and the pads 134 of the bonding wire wafer 130, so that the bonding wire wafer 130 is electrically connected. The substrate 110 is connected to the substrate. In the present embodiment, in order to shorten the length of the bonding wire 140 to reduce the circuit connection path between the bonding wire wafer 130 and the substrate 110, the projection of the pad 134 of the bonding wire wafer 130 on the first surface 112 of the substrate 110 may overlap. The groove 116 is sloted so that the bonding wire 140 can pass through the slot 116 with a minimum length, and the pad 118 connected to the bonding wire 140 on the second surface 114 of the substrate 110 is located near the slot 116 to reduce the bonding wire. 140 length.

In addition, in the embodiment, the semiconductor package structure 100 further includes an encapsulant 170. As shown in FIG. 2, the encapsulant 170 encapsulates the flip chip 120, the bonding wire 130, the bonding wires 140, and the substrate 110. a surface 112, a trench 116 and a portion of the second surface 114 to fix the semiconductor The component locations of the package structure 100 form the semiconductor package structure 100 of the present embodiment.

In order to enable the semiconductor package structure 100 of the present embodiment to be electrically connected to an external circuit 180, in the embodiment, the semiconductor package structure 100 further includes a plurality of solder balls 190 disposed on the second substrate 110. A portion of the surface 114 of the surface 114 is such that the semiconductor package structure 100 is electrically connected to the external circuit 180 (for example, a printed circuit board) through the solder balls 190. The material of the solder ball 190 may be tin, but is not limited thereto.

In this embodiment, the flip chip 120 can be a high density digital or mixed signal logic element, and the wire wafer 130 can be a memory element. The semiconductor package structure 100 of the present embodiment integrates wafers of different functions into a single package structure to improve performance. Of course, the types of the flip chip 120 and the wire bonding wafer 130 are not limited thereto.

Referring back to FIG. 1 , in the conventional semiconductor package structure 10 , the first substrate 22 of the lower package 20 and the second substrate 32 of the upper package 30 are connected through the first solder ball 40 , and the upper and lower structures are not Matching is more susceptible to thermal stress and warpage is inconsistent or excessive, resulting in electrical disconnection or reduced reliability. As shown in FIG. 1 , the bonding wire wafer 36 in the upper package 30 is connected to the pad above the bonding wire wafer 36 and the first surface 32 a of the second substrate 32 via the bonding wire 70 to be electrically connected to the first surface 32 a. Two substrates 32. Between the first substrate 22 and the second substrate 32 and between the first substrate 22 and the external circuit 60 are respectively connected by solder balls 70. Therefore, the electrical connection path between the bonding wire wafer 36 and the external circuit 60 is long, which affects the performance.

In the present embodiment, the semiconductor package structure 100 will bond the wire wafer 130. The substrate 110, the flip chip 120 and the bonding wire wafer 130 are directly disposed in the single encapsulant 170, and the structure is symmetrically coupled with the slot 116, thereby effectively reducing the thermal expansion coefficient mismatch. In the conventional semiconductor package structure 10, the semiconductor package structure 100 of the present embodiment can reduce the warpage thereof. In addition, the semiconductor package structure 100 is directly electrically connected to the second surface 114 of the substrate 110 by the bonding wire 140 passing through the slot 116, and the flip chip 120 directly penetrates the substrate through the metal bump 150. The first surface 112 of the 110 is electrically connected. Moreover, the substrate 110, the flip chip 120 and the bonding wire wafer 130 are integrated in a single package glue body, and the upper and lower packages are not connected by solder balls, so that the product is not electrically disconnected, the reliability is increased, and the external circuit can be shortened. The path between the electrical connections is 180 and the thickness of the semiconductor package structure 100 can be reduced.

3 is a schematic diagram of a semiconductor package structure in accordance with another embodiment of the present invention. Referring to FIG. 3 , the main difference between the semiconductor package structure 200 of FIG. 3 and the semiconductor package structure of FIG. 2 is that, in FIG. 2 , the semiconductor package structure 100 is electrically connected to the external circuit 180 by solder balls 190 , that is, a ball. A manner of a ball grid array (BGA) is connected to the external circuit 180. In FIG. 3, the semiconductor package structure 200 is provided with a plurality of pins 292 on a portion of the pads 218 of the second surface 214 of the substrate 210. The pins 292 are electrically connected to the external circuit 280 through the pins 292. A pin grid array (PGA) is connected to the external circuit 280. In addition, in FIG. 3, the external circuit 280 includes a recess 282 through which the encapsulant 270 protruding from the second surface 214 of the substrate 210 can extend into the recess 282 of the external circuit 280 to achieve a foolproof effect.

4 is a schematic diagram of a semiconductor package structure in accordance with still another embodiment of the present invention. Referring to FIG. 4 , the main difference between the semiconductor package structure 300 of FIG. 4 and the semiconductor package structure 100 of FIG. 2 is that the semiconductor package structure 300 of FIG. 4 is a land grid array (LGA) and an external circuit 380 . connection. Of course, the manner in which the semiconductor package structure is connected to the external circuit is not limited to the above.

FIG. 5 is a schematic diagram of a semiconductor package structure in accordance with still another embodiment of the present invention. Referring to FIG. 5, the main difference between the semiconductor package structure 400 of FIG. 5 and the semiconductor package structure 100 of FIG. 2 is that the bonding wires 440 of the semiconductor package structure 400 of FIG. 5 (in the form of a lead frame in FIG. 5) are not Through the slot 416, it is directly connected to the pad 418 of the first surface 412 of the substrate 410 and the wire bond wafer 430. The bonding wire wafer 430 can be electrically connected to the external circuit 480 via the bonding wire 440, the internal circuit of the substrate 410, and the solder balls 490. In other embodiments, the type of conductor connected between the pad 418 of the first surface 412 of the substrate 410 and the wire bond wafer 430 is not limited to the above, as long as the electrical property between the wire bond wafer 430 and the substrate 410 can be provided. Just connect.

6 is a schematic diagram of a semiconductor package structure in accordance with another embodiment of the present invention. Referring to FIG. 6, the main difference between the semiconductor package structure 500 of FIG. 6 and the semiconductor package structure 400 of FIG. 5 is that the semiconductor package structure 500 of FIG. 6 further includes a redistribution layer (RDL). The reconfiguration wiring layer 595 is disposed on one of the active side 532 of the bonding wire wafer 530, and the bonding wire wafer 530 includes a plurality of pads 534.

Since the pads of different kinds of wire bonding wafers have different positions, as shown in Figure 2 For example, the pad 118 is located at the center of the wire bonding die 130, and the bonding wire 140 passing through the slot 116 is directly connected to the pad 134 of the bonding wire wafer 130. However, in this embodiment, the pads 534 are positioned around the wire bond wafer 530 (ie, the projections of the pads 534 of the bond wire wafer 530 on the first surface 512 of the substrate 510 do not overlap the slot 516). The bond wires 540 of the slot 516 cannot be directly connected to the pads 534 of the bond wire wafer 530. The semiconductor package structure 500 of the present embodiment extends from the central position of the active side 532 of the bonding wire wafer 530 to the pad 534 at the periphery of the bonding wire wafer 530 by the reconfiguring wiring layer 595, so that the bonding wire passing through the opening 516 The 540 can be electrically connected to the substrate 510 and the wire bond wafer 530 through the reconfiguration circuit layer 595. Of course, the rewiring circuit layer may have different forms depending on the wire bonding wafer of different types and different pad positions, and is not limited to the above.

FIG. 7 is a schematic diagram of a semiconductor package structure in accordance with still another embodiment of the present invention. Referring to FIG. 7, the semiconductor package structure 600 of FIG. 7 and the semiconductor package structure 100 of FIG. 2 are connected to the second surfaces 614, 114 of the substrates 610, 110 through the bonding wires 640, 140 through the bonding wires 640, 140, respectively. The main difference between the semiconductor package structure 600 of FIG. 7 and the semiconductor package structure 100 of FIG. 2 is that the semiconductor package structure 600 of FIG. 7 electrically connects the bonding wires 640 and the pads 634 of the bonding wire wafer 630 by reconfiguring the wiring layer 695. Further, the substrate 610 and the bonding wire wafer 630 are electrically connected to each other. This section is explained in the previous embodiment and will not be described here.

FIG. 8 is a schematic diagram of a semiconductor package structure in accordance with still another embodiment of the present invention. Referring to FIG. 8, the main difference between the semiconductor package structure 700 of FIG. 8 and the semiconductor package structure 100 of FIG. 2 is that the semiconductor of FIG. The body package structure 700 includes a first wire bond wafer 730a and a second wire bond wafer 730b. One active side 732a of the first bonding wire wafer 730a is disposed on the inactive side 726 of the two flip chip 720, and one of the second bonding wire wafer 730b is uninitiated on one of the first bonding wire wafers 730a. Side 736a. As shown in FIG. 8 , the first bonding wire wafer 730 a and the second bonding wire wafer 730 b are electrically connected to the second surface 714 of the substrate 710 and the pads 718 on the first surface 712 through the bonding wires 740 . In this embodiment, the pads 734a, 734b of the first bonding wire wafer 730a and the second bonding wire wafer 730b are both located at the center of the active sides 732a, 732b (that is, the projection of the first surface 712 of the substrate 710 overlaps The position of the slot 716). Accordingly, the bond wires 740 connected to the first bond wire wafer 730a can be connected directly to the pads 718 on the second surface 714 of the substrate 710 through the slots 716. For the second bonding wire wafer 730b, the bonding wire 740 can be electrically connected by reconfiguring the wiring layer 795 on the active side 732b of the second bonding wire wafer 730b. The second bonding wire wafer 730b is electrically connected to the substrate 710 by being connected to the pad 734b of the second bonding wire wafer 730b. In summary, the semiconductor package structure of the present invention can reduce the warpage of the semiconductor package structure due to the structural symmetry and the slot setting, thereby effectively reducing the thermal expansion coefficient mismatch. In addition, the semiconductor package structure of the present invention directly places the bonding wire wafer on the flip chip, and the substrate, the flip chip and the bonding wire wafer are integrated in a single package glue body, and do not need to be connected by solder balls, so the product is not electrically generated. Break the road and increase reliability. In addition, the semiconductor package structure of the present invention is directly disposed on the flip chip by the bonding wire wafer, and the bonding wire is electrically connected to the pads of the first surface or the second surface of the substrate by the bonding wires. The path of electrical connection with an external circuit can be shortened, and the thickness of the semiconductor package structure can also be reduced.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧General semiconductor package structure

20‧‧‧ lower package

22‧‧‧First substrate

22a‧‧‧ first surface

22b‧‧‧ second surface

24‧‧‧First mat

26‧‧‧Flip chip

30‧‧‧Upper package

32‧‧‧second substrate

32a‧‧‧ first surface

32b‧‧‧ second surface

34‧‧‧second mat

36‧‧‧Wire wire wafer

40‧‧‧First solder ball

50‧‧‧second solder ball

60‧‧‧External circuit

70‧‧‧welding line

100, 200, 300, 400, 500, 600, 700‧‧‧ semiconductor package structure

110, 210, 410, 510, 610, 710‧‧‧ substrates

112, 412, 512, 712‧‧‧ first surface

114, 214, 614, 714‧‧‧ second surface

116, 416, 516, 616, 716‧‧‧ slotting

117‧‧‧ wire layer

118, 218, 418, 718‧‧‧ pads

120, 720‧‧‧ flip chip

122‧‧‧Active side

124‧‧‧ pads

126, 726‧‧‧ non-active side

130, 430, 530, 630‧‧‧ wire bonding wafer

132, 532‧‧‧ active side

134, 534, 634‧‧‧ pads

140, 440, 540, 640, 740‧‧ ‧ wire bonding

150‧‧‧Metal bumps

160‧‧‧Adhesive layer

170, 270‧‧‧Package colloid

180, 280, 380, 480‧‧‧ external circuits

190, 490‧‧‧ solder balls

282‧‧‧ recesses

292‧‧‧ stitches

595, 695, 795‧‧‧ reconfigured circuit layers

730a‧‧‧First wire bond wafer

732a‧‧‧active side

734a‧‧‧ pads

736a‧‧‧Inactive side

730b‧‧‧second wire bond wafer

732b‧‧‧active side

736b‧‧‧Inactive side

734b‧‧‧ pads

1 is a schematic diagram of a conventional semiconductor package structure.

2 is a schematic diagram of a semiconductor package structure in accordance with an embodiment of the present invention.

3 is a schematic diagram of a semiconductor package structure in accordance with another embodiment of the present invention.

4 is a schematic diagram of a semiconductor package structure in accordance with still another embodiment of the present invention.

FIG. 5 is a schematic diagram of a semiconductor package structure in accordance with still another embodiment of the present invention.

6 is a schematic diagram of a semiconductor package structure in accordance with another embodiment of the present invention.

FIG. 7 is a schematic diagram of a semiconductor package structure in accordance with still another embodiment of the present invention.

FIG. 8 is a schematic diagram of a semiconductor package structure in accordance with still another embodiment of the present invention.

100‧‧‧Semiconductor package structure

110‧‧‧Substrate

112‧‧‧ first surface

114‧‧‧ second surface

116‧‧‧ slotting

117‧‧‧ wire layer

118‧‧‧ pads

120‧‧‧Flip chip

122‧‧‧Active side

124‧‧‧ pads

126‧‧‧Inactive side

130‧‧‧ wire bonding wafer

132‧‧‧Active side

134‧‧‧ pads

140‧‧‧welding line

150‧‧‧Metal bumps

160‧‧‧Adhesive layer

170‧‧‧Package colloid

180‧‧‧External circuit

190‧‧‧ solder balls

Claims (13)

A semiconductor package structure comprising: a substrate including a first surface and a second surface, a slot and a plurality of pads, the slot extending through the substrate, the pads being located on the first surface and the a second surface; a plurality of flip chip, respectively disposed on the first surface of the substrate and electrically connected to the pads on the first surface; one or more wire bonding wafers disposed on the flip chip And a plurality of bonding wires electrically connected to the first surface of the substrate or a portion of the second surface and the bonding wire wafer. The semiconductor package structure of claim 1, wherein the bonding wires are electrically connected to the partial pads of the second surface of the substrate and the bonding wire wafer. The semiconductor package structure of claim 1, further comprising a plurality of metal bumps electrically connected to the pads of the first surface of the substrate and the flip chip. The semiconductor package structure of claim 1, further comprising a plurality of solder balls or a plurality of pins, a plurality of pads disposed on the second surface of the substrate, the semiconductor package structure transmitting the solder balls or The pins are electrically connected to an external circuit. The semiconductor package structure of claim 1, wherein the substrate comprises a plurality of layers of wires, the layer of wires comprising the pads on the first surface and the second surface. The semiconductor package structure according to claim 1, wherein The flip chip is disposed on the first surface of the substrate with an active side. The semiconductor package structure of claim 1, wherein the wire bond wafer is disposed on an inactive side of each of the flip chip on an active side. The semiconductor package structure of claim 7, wherein the wire bonding die comprises a plurality of pads, the pads of the bonding wire wafer are located on the active side, and the pads of the bonding wire wafer are A projection of the first surface of the substrate overlaps the slot. The semiconductor package structure of claim 1, further comprising a reconfigurable circuit layer disposed on one active side of the bonding wire wafer, the bonding wire wafer comprising a plurality of pads, the bonding wires of the bonding wire The projection of the pad on the first surface of the substrate does not overlap the slot, the bonding wire is connected to the reconfigured circuit layer and the reconfigurable circuit layer extends to the pads of the bonding wire wafer to be electrically connected The substrate and the wire bonding wafer. The semiconductor package structure of claim 1, further comprising an adhesive layer between the flip chip and the bonding wire wafer. The semiconductor package structure of claim 1, further comprising an encapsulant covering the flip chip, the bonding wire wafer, the bonding wires, the first surface of the substrate, and the Slotting and partially the second surface. The semiconductor package structure of claim 1, wherein the encapsulant protruding from the second surface of the substrate protrudes into a recess of an external circuit. The semiconductor package structure of claim 1, wherein the wire bonding die comprises a first bonding wire wafer and a second bonding wire wafer, wherein one of the second bonding wire wafers is non-actively stacked on the side One of the first wire bonding wafers is on the inactive side.