TWI835546B - Semiconductor package - Google Patents

Abstract

A semiconductor package is provided. The semiconductor package includes: a package substrate; a first semiconductor chip, attached to the package substrate by a back side; a second semiconductor chip and a third semiconductor chip, separately stacked on the first semiconductor chip, and respectively attached to an active side of the first semiconductor chip and the package substrate by an active side; and a fourth semiconductor chip, stacked on the second semiconductor chip and the third semiconductor chip while extending across a gap between the second semiconductor chip and the third semiconductor chip, and attached to the active side of the first semiconductor chip by an active side.

Description

Semiconductor packaging

The present invention relates to a semiconductor package, and in particular to a multi-wafer semiconductor package.

With the development of the electronics industry, the chip packaging structure with a single chip can no longer fully meet today's requirements for maximum performance, low manufacturing cost, and high integration density of integrated circuits. Therefore, multi-die packages including multiple dies stacked on top of each other were developed. Currently, multi-chip packaging structures generally use wire bonding technology to connect multiple chips stacked on top of each other to a carrier substrate. To avoid obscuring each die's bonding pads for contact bonding wires, the multiple die must be offset relative to each other. In the case of relatively thin wafers, this may cause unsupported portions of each wafer to deform or even break. Furthermore, the need to arrange relatively dense bonding wires increases the chance of short circuiting of adjacent bonding wires.

An aspect of the present disclosure provides a semiconductor package, including: a packaging substrate; a first semiconductor chip attached to the packaging substrate with a back side; a second semiconductor chip and a third semiconductor chip stacked laterally separated from each other. on the first semiconductor wafer and attached to the active side of the first semiconductor wafer and the packaging substrate with active sides respectively; and a fourth semiconductor wafer to cross the second semiconductor wafer and the third semiconductor wafer. Three semiconductor wafers are stacked on the second semiconductor wafer and the third semiconductor wafer with a gap between them, and are attached with an active side to the active side of the first semiconductor wafer.

In some embodiments, the active side of the first semiconductor wafer faces away from the packaging substrate, and the active side of the second semiconductor wafer and the active side of the third semiconductor wafer are connected to the active side of the first semiconductor wafer. The active sides of the fourth semiconductor chip all face the packaging substrate.

In some embodiments, the second semiconductor wafer overlaps a first peripheral area of the first semiconductor wafer along a first side, and the third semiconductor wafer overlaps a first peripheral area of the first semiconductor wafer along a second side. a second peripheral area on the side, and the fourth semiconductor wafer is attached to a central area of the first semiconductor wafer located between the first peripheral area and the second peripheral area.

In some embodiments, the first semiconductor wafer is connected to the second semiconductor wafer and the third semiconductor wafer respectively via a first electrical connection, and the second semiconductor wafer is connected to the second semiconductor wafer via a second electrical connection. The packaging substrate, the third semiconductor chip is connected to the packaging substrate via a third electrical connector, and the fourth semiconductor chip is connected to the first semiconductor chip via a fourth connector.

In some embodiments, the first electrical connector is smaller in height than the second electrical connector, the third electrical connector and the fourth electrical connector.

In some embodiments, the semiconductor package further includes: a first support member disposed on the packaging substrate and supporting the second semiconductor chip from the active side of the second semiconductor chip and located on the second between the electrical connector and the first semiconductor chip; and a second support member disposed on the packaging substrate and supporting the third semiconductor chip from the active side of the third semiconductor chip and located at the between the third electrical connection and the first semiconductor chip.

In some embodiments, the first support member is equal in height to the second electrical connector, and the second support member is equal in height to the third electrical connector.

In some embodiments, a first original pad on the active side of the first semiconductor die is connected to the first electrical connection attached to the first electrical connection and the fourth electrical connection via a first rewiring. a first redistribution pad of the device, a second original pad on the active side of the second semiconductor die connected via a second redistribution to a second redistribution attached to the second connection pads, and a third original pad on the active side of the third semiconductor die is connected to a third redistribution pad attached to the third electrical connector via a third rewiring.

In some embodiments, the first semiconductor die is attached to the packaging substrate via a first die adhesive, and the fourth semiconductor die is attached to the second semiconductor die and the package substrate via a second die adhesive. The third semiconductor wafer.

In some embodiments, the first wafer adhesive fully covers the backside of the first semiconductor wafer, and the second wafer adhesive only partially covers the active side of the fourth semiconductor wafer.

FIG. 1 is a schematic cross-sectional view of a semiconductor package 10 according to some embodiments of the present disclosure. For purposes of illustration, not all components of the semiconductor package 10 are shown in FIG. 1 . Some components not shown in Figure 1 will be at least partially shown in Figures 2-5.

Referring to FIG. 1 , a semiconductor package 10 includes a packaging substrate 100 for carrying a semiconductor chip. Package substrate 100 may be a circuit board and may include conductive features 102 embedded therein. In some embodiments, the packaging substrate 100 is a core substrate. In this embodiment, the packaging substrate 100 includes a core layer 104 and insulating build-up layers 106 formed on opposite sides of the core layer 104 . Additionally, conductive features 102 may include wires and vias (not shown in detail) distributed in insulating build-up layer 106 , and may include through-holes through core layer 104 . In an alternative embodiment, packaging substrate 100 is a coreless substrate. In these alternative embodiments, the packaging substrate 100 does not have a core layer, but instead includes a stack of insulating build-up layers. Additionally, conductive features 102, including wires and vias, may be distributed in the stack of insulating build-up layers.

Semiconductor wafers 110, 120, 130, 140 are stacked on the packaging substrate 100. The other semiconductor wafers 120, 130, and 140 above the bottom semiconductor wafer 110 are bonded to the semiconductor wafer 110 and the packaging substrate 100 by flip chip bonding. As will be described in greater detail subsequently, the semiconductor dies 110, 120, 130, 140 are each connected to the conductive features 102 in the packaging substrate 100 via direct or indirect conductive paths. These conductive features 102 are used to wire the semiconductor wafers 110 , 120 , 130 , 140 to the underside of the packaging substrate 100 . As an example, the semiconductor wafers 110, 120, 130, and 140 may respectively be memory wafers. However, the semiconductor wafers 110, 120, 130, and 140 may each be a semiconductor wafer having any function. This disclosure is not limited to the functions of the semiconductor chips 110, 120, 130, and 140.

The integrated circuits of each semiconductor die are formed in a dielectric layer stack on one side of the semiconductor substrate and are connected to electrical connectors serving as input/output terminals of the die via pads in the outermost dielectric layer. In this article, the side of each semiconductor chip with the pads exposed is defined as the active surface (or active side) of the semiconductor chip, and the side of each semiconductor chip opposite to the active surface is defined as the back side of the semiconductor chip (or active side). or dorsal). For the sake of simplicity, FIG. 1 does not illustrate the semiconductor substrate, dielectric layer stack, integrated circuits and pads of each semiconductor chip. Nonetheless, the orientation of each semiconductor chip can still be known from the position of the corresponding electrical connector.

Among the semiconductor wafers 110, 120, 130, and 140, the semiconductor wafer 110 is located at the lowest layer. The backside of the semiconductor chip 110 faces the package substrate 100 , and the active side faces the other semiconductor chips 120 , 130 , 140 . In this manner, the integrated circuits in the semiconductor die 110 are indirectly connected to the conductive features 102 in the packaging substrate 100 . In some embodiments, the backside of the semiconductor die 110 is attached to the top surface of the packaging substrate 100 via die glue 112 . In such embodiments, the wafer adhesive 112 may fully cover the backside of the semiconductor wafer 110 .

The semiconductor wafers 120, 130 are stacked on the semiconductor wafer 110 with the active side oriented toward the packaging substrate 100 and are laterally spaced apart from each other. Specifically, each of the semiconductor wafers 120 and 130 does not completely overlap the semiconductor wafer 110, but each overlaps a peripheral area of the semiconductor wafer 110 with a peripheral area. For example, the semiconductor wafer 120 overlaps the first peripheral area along the first side of the semiconductor wafer 110 with a peripheral area along one side, and the semiconductor wafer 130 overlaps the semiconductor wafer with a peripheral area along one side. A second peripheral area of 110 along a second side opposite the first side. On the other hand, the central region of the semiconductor wafer 110 does not overlap with any of the semiconductor wafers 120 and 130 , and other portions of the semiconductor wafers 120 and 130 do not overlap the semiconductor wafer 110 .

Regarding signal connections, the semiconductor chip 120 is directly connected to the conductive features 102 in the packaging substrate 100 via the electrical connectors 122 through the portion located outside the semiconductor chip 110 . Similarly, semiconductor die 130 is directly connected to conductive features 102 in package substrate 100 via electrical connections 132 with portions located outside semiconductor die 110 . On the other hand, as the first signal transmission path, the semiconductor chip 110 is connected to the semiconductor chip 120 through the electrical connectors 114 on the first peripheral area, and then indirectly connected to the conductive features 102 in the packaging substrate 100 through the electrical connectors 122 . As a second signal transmission path, the semiconductor chip 110 is connected to the semiconductor chip 130 through the electrical connectors 116 on the second peripheral area, and then indirectly connected to the conductive features 102 in the packaging substrate 100 through the electrical connectors 132 . Since the semiconductor wafers 120 and 130 are stacked on the semiconductor wafer 110 , the electrical connectors 122 and 132 that directly connect the semiconductor wafers 120 and 130 to the packaging substrate 100 are larger in height than those used to establish the semiconductor wafer 110 and the semiconductor wafers 120 and 130 The electrical connectors 114 and 116 are electrically connected between them. As an example, electrical connections 122, 132, 114, 116 may each be solder bumps. However, in other examples, the electrical connectors 122, 132, 114, and 116 may also be electrical connectors of other forms and materials.

In addition to providing electrical connections, the electrical connectors 122 and 114 may provide support for the peripheral area of the semiconductor wafer 120 . In order to strengthen the support of the central area of the semiconductor wafer 120 , a support member 124 may be provided between the central area of the semiconductor wafer 120 and the packaging substrate 100 . The support member 124 is located between the electrical connector 122 and the electrical connector 114, and may be identical to the electrical connectors 122 and 114 in terms of structure and material. Since both extend from the package substrate 100 to the semiconductor wafer 120 , the support 124 and the electrical connector 122 may have the same height, and the height is greater than the height of the electrical connector 114 extending from the semiconductor wafer 110 to the semiconductor wafer 120 . As a difference from the electrical connectors 122, 114, the support member 124 may not be used to transmit signals. That is, the support member 124 may not be electrically connected to the integrated circuit in the semiconductor chip 120 . In some embodiments, the support 124 may be attached to a dummy pad 108a in the package substrate 100. The dummy pad 108a may be a conductive pattern, but may not be electrically connected to other conductive features 102 in the package substrate 100 . As a result, the support member 124 and the dummy pad 108 a may only provide support for the semiconductor chip 120 , but will not participate in signal transmission between the semiconductor chip 120 and the conductive features 102 in the packaging substrate 100 .

Similarly, in order to strengthen the support of the central area of the semiconductor wafer 130 , a support member 134 may be provided between the central area of the semiconductor wafer 130 and the packaging substrate 100 . The support member 134 is located between the electrical connector 132 and the electrical connector 116 , and may be identical to the electrical connectors 122 , 132 , 114 , 116 and the support member 124 in terms of structure and material. In terms of size, the height of the support member 134 is substantially equal to the heights of the electrical connectors 122 and 132 and the support member 124 and is greater than the height of the electrical connectors 114 and 116 . Similar to the support member 124, the support member 134 may not be used to transmit signals. That is, the support member 134 may not be electrically connected to the integrated circuit in the semiconductor chip 130 . In some embodiments, the support 134 may be attached to a dummy pad 108b in the package substrate 100. The dummy pad 108b is a conductive pattern, but may not be electrically connected to other conductive features 102 in the package substrate 100. As a result, the support 134 and the dummy pad 108 b may only provide support for the semiconductor chip 130 , but will not participate in signal transmission between the semiconductor chip 130 and the conductive features 102 in the packaging substrate 100 .

Based on the fact that the semiconductor wafers 120 and 130 overlap the first and second peripheral regions of the semiconductor wafer 110 extending along opposite sides in a laterally spaced manner from each other, the semiconductor wafer 110 is located between the first and second peripheral regions. The central area is free and available for attachment to semiconductor wafer 140 . In detail, the semiconductor wafer 140 is stacked on the semiconductor wafers 120 and 130 and spans the gap between the semiconductor wafers 120 and 130 . In this way, the semiconductor wafer 140 can be attached to the central area of the semiconductor wafer 110 through the electrical connector 142 through the portion above the gap, thereby achieving electrical connection between the semiconductor wafers 110 and 140 . In this way, the active side of the semiconductor chip 140 needs to face the active side of the semiconductor chip 110 . Since the active side of the semiconductor chip 110 faces away from the packaging substrate 100, the semiconductor chip 140 is oriented such that the active side faces the packaging substrate 100. In addition, since the active sides of the semiconductor wafers 120 and 130 face the packaging substrate 100 and the semiconductor wafer 140 is stacked on the semiconductor wafers 120 and 130 , the active side of the semiconductor wafer 140 also faces the backside of the semiconductor wafers 120 and 130 .

Regarding signal connection, the semiconductor chip 140 is connected to the semiconductor chip 110 via the electrical connector 142 in a central area between the semiconductor chips 120 and 130, and is further connected to the semiconductor chips 120 and 130 via the electrical connectors 114 and 116. The final connection is made to the conductive features 102 in the package substrate 100 via electrical connections 122, 132. In short, the semiconductor wafer 140 is indirectly connected to the packaging substrate 100 via the semiconductor wafer 110 and the semiconductor wafers 120 and 130 .

Since the semiconductor wafer 140 is stacked on the semiconductor wafers 120 and 130 , the electrical connectors 142 connecting the semiconductor wafer 140 to the semiconductor wafer 110 are larger in height than the electrical connectors 114 and 114 used to connect the semiconductor wafers 120 and 130 to the semiconductor wafer 110 . 116. Additionally, the electrical connectors 142 may be equal in height to, slightly larger than, or slightly smaller than the electrical connectors 122 , 132 used to connect the semiconductor wafers 120 , 130 to the packaging substrate 100 . The relationship between the heights of the electrical connector 142 and the electrical connectors 122 and 132 may vary depending on the thickness of the semiconductor wafers 110 , 120 and 130 . In addition, like the electrical connectors 122, 132, 114, 116 and the support members 124, 134, the electrical connector 142 can also be a solder bump. However, the electrical connector 142 may also be an electrical connector of other forms and materials.

In some embodiments, semiconductor wafer 140 is attached to semiconductor wafers 120 , 130 via wafer glue 144 . The wafer adhesive 144 may not completely cover the active surface of the semiconductor wafer 140 , but only cover the two peripheral areas of the overlapping semiconductor wafers 120 and 130 on the active surface of the semiconductor wafer 140 . In this way, the electrical connector 142 located between the semiconductor wafers 120 and 130 can contact the active surface of the semiconductor wafer 140 without the wafer adhesive 144 therebetween. As an example, before stacking the semiconductor wafer 140 onto the semiconductor wafers 120 and 130 , two strips of colloidal material may be formed by dispensing on portions of the semiconductor wafers 120 and 130 that are to be attached to the semiconductor wafer 140 . When the semiconductor wafer 140 is placed on the semiconductor wafers 120 and 130 , the colloidal materials are extruded to form the wafer glue 144 shown in FIG. 1 , and the semiconductor wafer 140 is attached to the semiconductor wafers 120 and 130 via the wafer glue 144 .

As stated above, the semiconductor wafers 110, 120, 130, 140 are stacked on the packaging substrate 100 and are respectively connected to the packaging substrate 100 in an indirect or direct manner. In order to protect the semiconductor wafers 110, 120, 130, and 140, an encapsulation body 150 encapsulating the semiconductor wafers 110, 120, 130, and 140 may be formed on the packaging substrate 100. In conjunction, the electrical connectors 122 , 132 , 114 , 116 , 142 , the support members 124 , 134 and the chip glues 112 , 144 that are in contact with the semiconductor wafers 110 , 120 , 130 , 140 are also encapsulated by the encapsulating body 150 . After the singulation process, the side walls of the encapsulation body 150 can be flush with the side walls of the packaging substrate 100 . As an example, the encapsulation body 150 may include a resin material and filler particles distributed in the resin material. Those with ordinary knowledge in the art can select appropriate resin materials and filler particles based on actual heat dissipation and stress conditions, and the present disclosure is not limited thereto. Furthermore, in alternative embodiments, the filler particles in the enclosure 150 may be omitted.

As an input/output terminal of the semiconductor package 10, the electrical connector 160 may be disposed on the bottom side of the package substrate 100. The integrated circuits in the semiconductor wafers 110 , 120 , 130 , 140 are directly or indirectly connected to the conductive features 102 in the packaging substrate 100 , and are routed via the conductive features 102 to the electrical connectors 160 on the bottom side of the packaging substrate 100 . In this way, the semiconductor chips 110, 120, 130, and 140 can transmit signals to or receive signals from external components through the electrical connector 160. As an example, the electrical connections 160 may be solder bumps or other forms of electrical connections.

In order to realize the interconnection between the semiconductor wafers 110, 120, 130, 140 and the connection with the packaging substrate 100, the pads on the active surfaces of the semiconductor wafers 110, 120, 130, 140 may need to be reconfigured, or re-configured. Distribution.

FIG. 2 is a schematic plan view of the active surface of the semiconductor wafer 110; FIG. 3 is a schematic plan view of the active surface of the semiconductor wafer 120; FIG. 4 is a schematic plan view of the active surface of the semiconductor wafer 130; and FIG. 5 is a schematic plan view of the active surface of the semiconductor wafer 140. Plane diagram.

Please refer to FIGS. 1 and 2 . In the original design of the semiconductor chip 110 , the pads P ₁₁₀ connected to the integrated circuit in the semiconductor chip 110 may be arranged in two rows in the central area of the active surface of the semiconductor chip 110 . As can be seen from FIG. 1 , the semiconductor chip 110 requires two rows of pads to achieve electrical connection with the semiconductor chip 140 , and also requires another two rows of pads to achieve electrical connection with the semiconductor wafers 120 and 130 . Therefore, in order to achieve electrical connection with the semiconductor chips 120, 130, and 140, the semiconductor chip 110 may require four rows of pads. Therefore, the two rows of original pads P ₁₁₀ need to be reconfigured.

As shown in FIG. 2 , the redistribution wire W _{110 a} connects the first row of original pads P ₁₁₀ (for example, the right row of original pads P ₁₁₀ ) to the two rows of redistribution pads RP ₁₁₀ . Similarly, the rewiring W _110b connects the second row of original pads P ₁₁₀ (for example, the left row of original pads P ₁₁₀ ) to the other two rows of redistributed pads RP ₁₁₀ . In this way, electrical connections 114 , 116 , and 142 can be formed on the four rows of redistribution pads RP ₁₁₀ and can be used to connect the semiconductor chip 110 to the semiconductor chips 120 , 130 , and 140 . The electrical connectors 142 are formed on the two rows of redistribution pads RP ₁₁₀ close to the original pads P ₁₁₀ and can be used to connect the semiconductor chip 110 to the semiconductor chip 140 . On the other hand, electrical connections 114 and 116 are formed on the other two rows of redistribution pads RP ₁₁₀ away from the original pads P ₁₁₀ and can be used to connect the semiconductor chip 110 to the semiconductor chips 120 and 130 .

In some embodiments, the redistribution line W _110a extends from the first row of original pads P ₁₁₀ (e.g., the right row of original pads P ₁₁₀ ) and bypasses the second row of original pads P ₁₁₀ (e.g., the left row of original pads P ₁₁₀ ) to connect to the first and second rows of redistribution pads RP ₁₁₀ , and the redistribution line W _110b extends from the second row of original pads P ₁₁₀ (e.g., the left row of original pads P ₁₁₀ ) and bypasses the first row of original pads P ₁₁₀ (e.g., the right row of original pads P ₁₁₀ ) to connect to the third and fourth rows of redistribution pads RP ₁₁₀ . In these embodiments, the first and second rows of redistribution pads RP ₁₁₀ are closer to the second row of original pads P ₁₁₀ (e.g., the left row of original pads P ₁₁₀ ), and the third and fourth rows of redistribution pads RP ₁₁₀ are closer to the first row of original pads P ₁₁₀ (e.g., the right row of original pads P ₁₁₀ ).

In addition, the rewiring W _110a may each have two line segments. The first line segment of the rewiring W _110a extends from the first row of original pads P ₁₁₀ to the first row of redistribution pads RP ₁₁₀ , and the second line segment of the rewiring W _110a extends from the first row of redistribution pads RP ₁₁₀ extends to the second row of redistribution pads RP ₁₁₀ . Similarly, the rewiring W _110b may each have two line segments. The first line segment of the rewiring W _110b extends from the second row of original pads P ₁₁₀ to the third row of redistributed pads RP ₁₁₀ , and the second line segment of the rerouted W _110b extends from the third row of redistributed pads RP ₁₁₀ extends to the fourth row of redistribution pads RP ₁₁₀ .

Referring to FIGS. 1 and 3 , the original pads P ₁₂₀ connected to the integrated circuits in the semiconductor chip 120 may also be arranged in two rows in the central area of the active surface of the semiconductor chip 120 . As can be seen from FIG. 1 , the semiconductor chip 120 needs to be connected to the semiconductor chip 110 and the packaging substrate 100 from the peripheral areas on both sides. As a result, the two rows of original pads P ₁₂₀ need to be repositioned.

As shown in FIG. 3 , the redistribution wire W _{120 a} connects the first row of original pads P ₁₂₀ to the first row of redistribution pads RP _{120 close to the first side of the semiconductor wafer 120} . In addition, the rewiring W _{120 b} connects the second row of original pads P ₁₂₀ to the second row of redistributed pads RP ₁₂₀ close to the second side of the semiconductor die 120 . In this way, the electrical connectors 122 and 114 can be attached to the two rows of redistribution pads RP ₁₂₀ and can be used to connect the semiconductor chip 120 to the packaging substrate 100 and the semiconductor chip 110 . Wherein, the electrical connector 122 can be attached to the first row of redistribution pads RP ₁₂₀ connected to the redistribution wire W _120a , and the electrical connector 114 can be attached to the second row of redistribution pads RP 120 connected to the redistribution wire W _120b . Wire connection pad RP ₁₂₀ . In some embodiments, the redistribution wire W _120a extends straight from the first row of original pads P ₁₂₀ to the first row of redistribution pads RP ₁₂₀ without bypassing the second row of original pads P ₁₂₀ . Similarly, the redistribution wire W _120b extends linearly from the second row of original pads P ₁₂₀ to the second row of redistribution pads RP ₁₂₀ without bypassing the first row of original pads P ₁₂₀ .

In addition, a row of dummy pads DP ₁₂₀ can be provided on the active surface of the semiconductor chip 120 . The support 124 illustrated with reference to FIG. 1 to reinforce the support for the semiconductor wafer 120 may be attached to the dummy pad DP ₁₂₀ . The dummy pad DP ₁₂₀ may not be electrically connected to the integrated circuit in the semiconductor chip 120 . Therefore, the dummy pad DP ₁₂₀ may be electrically isolated from the original pad P ₁₂₀ of the integrated circuit connected to the semiconductor die 120 , the rewiring W _{120 a} , W _{120 b} and the redistribution pad RP ₁₂₀ . In some embodiments, the dummy pad DP ₁₂₀ may be disposed between the first row of original pads P ₁₂₀ and the first row of redistributed pads RP ₁₂₀ connected via the rewiring W _120a .

Referring to FIGS. 1 and 4 , similar to the pad configuration and redistribution of the semiconductor chip 120 , the original pads P ₁₃₀ connected to the integrated circuits in the semiconductor chip 130 may be arranged in the central area of the active surface of the semiconductor chip 130 into two rows and connected to two rows of redistribution pads RP ₁₃₀ arranged along opposite sides of the semiconductor chip 130 via redistribution wires W _130a and W _130b . Electrical connectors 132 and 116 can be attached to the two rows of redistribution pads RP ₁₃₀ and can be used to connect the semiconductor chip 130 to the packaging substrate 100 and the semiconductor chip 110 . Among them, the electrical connector 132 can be attached to the first row of redistribution pads RP ₁₃₀ connected to the redistribution wire W _130a , and the electrical connector 116 can be attached to the second row of redistribution pads RP 130 connected to the redistribution wire W _130b . Wire connection pad RP ₁₃₀ . In some embodiments, the redistribution wire W _130a extends straight from the first row of original pads P ₁₃₀ to the first row of redistribution pads RP ₁₃₀ without bypassing the second row of original pads P ₁₃₀ . Similarly, the redistribution wire W _130b may extend linearly from the second row of original pads P ₁₃₀ to the second row of redistribution pads RP ₁₃₀ without bypassing the first row of original pads P ₁₃₀ .

Furthermore, a row of dummy pads DP ₁₃₀ can be provided on the active surface of the semiconductor chip 130 . The support 134 illustrated with reference to FIG. 1 to reinforce the support for the semiconductor wafer 130 may be attached to the dummy pad DP ₁₃₀ . The dummy pad DP ₁₃₀ may not be electrically connected to the integrated circuit in the semiconductor chip 130 . Therefore, the dummy pad DP ₁₃₀ may be electrically isolated from the original pad P ₁₃₀ of the integrated circuit connected to the semiconductor die 130 , the redistribution pads W _{130 a} , W _{130 b} and the redistribution pad RP ₁₃₀ . In some embodiments, the dummy pad DP ₁₃₀ may be disposed between the first row of original pads P ₁₃₀ and the first row of redistributed pads RP ₁₃₀ connected via the rewiring W _130a .

Please refer to FIG. 1 and FIG _. 4. In some embodiments, two rows of original lines arranged in the central area of the active surface of the semiconductor chip 140 and connected to the integrated circuits in the semiconductor chip 140 are redistributed by W _140a and W 140b. Pad P ₁₄₀ is connected to two rows of redistribution pads RP ₁₄₀ . Electrical connectors 142 may be attached to the two rows of redistribution pads RP ₁₄₀ to establish interconnections between the semiconductor dies 140 and 110 .

As can be seen from FIG. 4 , the redistribution pads W _140a and W _140b reposition the original pads P ₁₄₀ to the redistribution pads RP ₁₄₀ on both sides. Specifically, the first row of redistributed pads RP ₁₄₀ is located between the first row of original pads P ₁₄₀ and the first side of the semiconductor wafer 140 , and is spaced apart from the first side of the semiconductor wafer 140 . Similarly, the second row of redistributed pads RP ₁₄₀ is located between the second row of original pads P ₁₄₀ and the second side of the semiconductor wafer 140 and is spaced apart from the second side of the semiconductor wafer 140 . Although not shown in FIG. 4 , the open area between the two rows of redistribution pads RP ₁₄₀ and the first and second sides of the semiconductor chip 140 may be covered with pads for attaching the semiconductor chip 140 to the semiconductor wafers 120 and 130 . Wafer glue 144.

By reconfiguring the original pads of the semiconductor wafers 110, 120, 130, and 140 in the above manner, the interconnection between the semiconductor wafers 110, 120, 130, and 140 can be realized in conjunction with the stacking method shown in Figure 1. Connections between semiconductor wafers 110, 120, 130, 140 and package substrate 100. However, those with ordinary knowledge in the art can adjust the pad redistribution method of each semiconductor chip according to actual conditions, and the present disclosure is not limited thereto.

In summary, embodiments of the present disclosure provide a semiconductor package including a plurality of semiconductor wafers. A plurality of semiconductor wafers are stacked on the packaging substrate. Wherein, the first semiconductor wafer of the lowest layer is attached to the packaging substrate with its back side. The second and third semiconductor wafers located on the first semiconductor wafer are laterally spaced apart from each other, and are bonded to the first semiconductor wafer and the packaging substrate in a flip-chip bonding manner. In addition, the fourth semiconductor wafer is stacked on the second and third semiconductor wafers across the gap between the second and third semiconductor wafers, and is bonded to the first semiconductor wafer at the second and third semiconductor wafers by flip-chip bonding. The portion between the third semiconductor wafer. Compared with using wire bonding to realize the interconnection between multiple semiconductor chips and the connection between each of them and the packaging substrate, the multiple semiconductor chips in the semiconductor package of the embodiment of the present disclosure are each connected through, for example, solder. The bumps are interconnected by electrical connections and directly or indirectly connected to the package substrate. Therefore, the problem of short-circuiting adjacent bonding wires caused by densely arranging the bonding wires can be avoided. In addition, in the embodiments of the present disclosure, the electrical connectors can provide support for each semiconductor chip to avoid the problem of deformation or even breakage of the semiconductor chip.

10:Semiconductor packaging

100:Package substrate

102: Conductive characteristics

104:Core layer

106:Insulation layer

108a, 108b: Dummy pad

110, 120, 130, 140: Semiconductor wafer

112, 144: Chip glue

114, 116, 122, 132, 142, 160: Electrical connectors

124, 134: Support piece

150: Encapsulated body

DP ₁₂₀ , DP ₁₃₀ : Dummy pads

P ₁₁₀ , P ₁₂₀ , P ₁₃₀ , P ₁₄₀ : pads

RP ₁₁₀ , RP ₁₂₀ , RP ₁₃₀ , RP ₁₄₀ : redistribution pads

W _110a , W _110b , W _120a , W 120b, W _130a , W _130b , _{W 140a ,} W _140b : Rewiring

FIG. 1 is a schematic cross-sectional view of a semiconductor package according to some embodiments of the present disclosure. 2 is a schematic plan view of an active surface of a first semiconductor chip in a semiconductor package. 3 is a schematic plan view of the active surface of the second semiconductor chip in the semiconductor package. 4 is a schematic plan view of an active surface of a third semiconductor chip in a semiconductor package. 5 is a schematic plan view of an active surface of a fourth semiconductor chip in a semiconductor package.

10:Semiconductor packaging

100:Package substrate

102: Conductive characteristics

104:Core layer

106:Insulation layer

108a, 108b: Dummy pad

110, 120, 130, 140: Semiconductor wafer

112, 144: Chip glue

114, 116, 122, 132, 142, 160: Electrical connectors

124, 134: Support piece

150: Encapsulated body

Claims (10)

A semiconductor package, comprising: a packaging substrate; a first semiconductor wafer attached to the packaging substrate with a back side; a second semiconductor wafer and a third semiconductor wafer stacked on the first semiconductor wafer laterally separated from each other , and are respectively attached to the active side of the first semiconductor wafer and the packaging substrate with an active side; and a fourth semiconductor wafer to cross the gap between the second semiconductor wafer and the third semiconductor wafer. is stacked on the second semiconductor wafer and the third semiconductor wafer, and is attached to the active side of the first semiconductor wafer with an active side. The semiconductor package of claim 1, wherein the active side of the first semiconductor chip faces away from the packaging substrate, and the active side of the second semiconductor chip and all of the third semiconductor chip Both the active side and the active side of the fourth semiconductor chip face the packaging substrate. The semiconductor package of claim 1, wherein the second semiconductor wafer overlaps a first peripheral area of the first semiconductor wafer along the first side, and the third semiconductor wafer overlaps the first semiconductor wafer. a second peripheral area of the wafer along a second side, and the fourth semiconductor wafer is attached to a central area of the first semiconductor wafer between the first peripheral area and the second peripheral area. The semiconductor package of claim 1, wherein the first semiconductor chip is connected to the second semiconductor chip and the second semiconductor chip via a first electrical connector respectively. a third semiconductor wafer, the second semiconductor wafer is connected to the packaging substrate via a second electrical connector, the third semiconductor wafer is connected to the packaging substrate via a third electrical connector, and the fourth semiconductor wafer Connected to the first semiconductor die via a fourth electrical connection. The semiconductor package of claim 4, wherein the first electrical connector is smaller in height than the second electrical connector, the third electrical connector and the fourth electrical connector. The semiconductor package of claim 4, further comprising: a first support member disposed on the packaging substrate and supporting the second semiconductor chip from the active side of the second semiconductor chip and located on the between a second electrical connection and the first semiconductor chip; and a second support member disposed on the packaging substrate and supporting the third semiconductor chip from the active side of the third semiconductor chip, and Located between the third electrical connector and the first semiconductor chip. The semiconductor package of claim 6, wherein the first support member is equal in height to the second electrical connector, and the second support member is equal in height to the third electrical connector. The semiconductor package of claim 4, wherein the first original pad on the active side of the first semiconductor chip is connected to the first electrical connector attached to the first electrical connector via a first rewiring. The first redistributed pad of the fourth electrical connection, the second original pad on the active side of the second semiconductor die is connected to the second electrical connection via a second redistribution second distribution pad of the component, And a third original pad on the active side of the third semiconductor die is connected to a third redistribution pad attached to the third electrical connector via a third rewiring. The semiconductor package of claim 1, wherein the first semiconductor wafer is attached to the packaging substrate via a first wafer adhesive, and the fourth semiconductor wafer is attached to the first wafer via a second wafer adhesive. two semiconductor wafers and the third semiconductor wafer. The semiconductor package of claim 9, wherein the first wafer adhesive fully covers the backside of the first semiconductor wafer, and the second wafer adhesive only partially covers the fourth semiconductor wafer. The active side.

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