TW201417656A - Manufacturing method of circuit-component built-in substrate - Google Patents

Manufacturing method of circuit-component built-in substrate Download PDF

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TW201417656A
TW201417656A TW102133636A TW102133636A TW201417656A TW 201417656 A TW201417656 A TW 201417656A TW 102133636 A TW102133636 A TW 102133636A TW 102133636 A TW102133636 A TW 102133636A TW 201417656 A TW201417656 A TW 201417656A
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Taiwan
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hole
insulating substrate
circuit element
circuit
manufacturing
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TW102133636A
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Chinese (zh)
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TWI513387B (en
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Yoshitake Hayashi
Norihito Tsukahara
Kohichi Tanda
Yosuke Maeba
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Panasonic Corp
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Abstract

The present invention provides a manufacturing method of a circuit-component built-in substrate using a prepreg material utilizing epoxy resin as the main ingredient and having electrical connection reliability. The method comprises: a circuit component installation step that forms one or more than one through holes in the direction of the thickness of a first insulation substrate material, and inserting circuit components into all or a part of through holes to make both the electrode terminals above or below it are orientated toward the thickness direction; an internal through hole formation step that forms one or more than one first through holes in the direction of the thickness of a second insulation substrate material and fills a first conductive composition into the first through hole(s) to form the first internal through holes for electrical connection; and a laminate pressing/heating step that allocates the second insulation substrate material with the first internal through hole(s) to both sides of the first insulation substrate material with inserted circuit component, and furthermore allocates and laminates wiring elements at the outer lateral surface of the second insulation substrate material and proceeds with pressing and heating.

Description

電路元件內藏基板之製造方法 Method for manufacturing built-in substrate of circuit component 技術領域 Technical field

本發明係有關於一種電路元件內藏基板之製造方法。 The present invention relates to a method of fabricating a substrate embedded in a circuit component.

背景技術 Background technique

近年來隨著電子機器之小型化.薄型化、高機能化,對安裝於印刷基板之電子元件的高密度安裝化、及安裝有電子元件之電路基板的高機能化之要求係與日俱增。於如此之情況中,有人正在開發於基板中填入有電子元件的電路元件內藏基板。 In recent years, with the miniaturization of electronic machines. The demand for high-density mounting of electronic components mounted on a printed circuit board and high performance of a circuit board on which an electronic component is mounted is increasing with the increase in thickness and performance. In such a case, a substrate is embedded in a circuit component in which an electronic component is filled in a substrate.

電路元件內藏基板,通常,因將安裝於印刷基板表面之主動元件(例如,半導體零件)或被動元件(例如,電阻或電容器)填入基板中,故可減少基板面積。又,因相較於表面安裝,可提高配置電路元件之自由度,故亦可預期藉由電路元件間配線之最適化改善高頻特性等。 The circuit component houses a substrate. Usually, an active component (for example, a semiconductor component) or a passive component (for example, a resistor or a capacitor) mounted on the surface of the printed substrate is filled in the substrate, so that the substrate area can be reduced. Further, since the degree of freedom in arranging circuit elements can be improved as compared with the surface mounting, it is also expected to improve the high-frequency characteristics and the like by optimizing the wiring between the circuit elements.

可輕易地將電路元件填入基板之電路元件內藏基板的製造方法,有人提出了一種於預先表面安裝有電路元件之既存多層印刷基板之間,配置形成有用以得到電氣 導通之內通孔的絕緣片材,並藉由加壓加熱處理一體化之方法(例如,參照專利文獻1)。該製造方法中,不需蝕刻或電鍍等濕處理,可輕易地製造多層電路元件內藏基板。 A method of manufacturing a substrate in which a circuit component can be easily filled in a circuit component, and a method of forming an existing electrical circuit between the plurality of printed circuit boards on which a circuit component is preliminarily mounted is provided. The insulating sheet of the through hole is electrically connected and integrated by pressure heat treatment (for example, refer to Patent Document 1). In this manufacturing method, the multilayer substrate can be easily fabricated without the need of wet processing such as etching or plating.

此外,為提高元件之內藏密度,有人提出了一種於多層印刷基板間配置於厚度方向上縱向地填入有預先內藏之元件的絕緣片材,並藉由加壓加熱處理一體化之方法(例如,參照專利文獻2)。 Further, in order to increase the built-in density of the element, an insulating sheet in which a pre-built component is longitudinally filled in the thickness direction between the multilayer printed boards and integrated by pressure heating treatment has been proposed. (For example, refer to Patent Document 2).

接著,一面參照圖8(a)~圖8(i),一面說明專利文獻2所揭示之電路元件內藏基板之製造方法。圖8(a)~圖8(i)係顯示用以說明專利文獻2所記載之習知電路元件內藏基板之製造方法之各步驟的截面構造圖。 Next, a method of manufacturing the circuit element-embedded substrate disclosed in Patent Document 2 will be described with reference to FIGS. 8(a) to 8(i). (a) to (i) of FIG. 8 are cross-sectional structural views for explaining respective steps of a method of manufacturing a conventional circuit element-embedded substrate described in Patent Document 2.

首先,如圖8(a)所示,於以未硬化之熱硬化性樹脂與無機填料之混合物所構造的複合板202兩面貼附覆膜201。接著,如圖8(b)所示,形成用以相對於複合板202之厚度方向縱向插入電路元件之貫通孔203與用以形成內通孔之通孔204。 First, as shown in FIG. 8(a), a film 201 is attached to both surfaces of a composite sheet 202 constructed of a mixture of an uncured thermosetting resin and an inorganic filler. Next, as shown in FIG. 8(b), a through hole 203 for inserting the circuit element in the longitudinal direction with respect to the thickness direction of the composite board 202 and a through hole 204 for forming the inner through hole are formed.

然後,如圖8(c)所示,於貫通孔203縱向地插入電路元件206,如圖8(d)所示,藉由進行加熱處理使貫通孔203收縮,阻塞複合板202與電路元件206之間的間隙。接著,如圖8(e)及圖8(f)所,於通孔204與電路元件206之電極端子部的兩側分別藉由印刷填充導電性組成物205a。並且,如圖8(g)所示,藉由進行加熱處理使導電性組成物205a乾燥柱(post)化後,剝離覆膜201。 Then, as shown in FIG. 8(c), the circuit component 206 is inserted longitudinally in the through hole 203, and as shown in FIG. 8(d), the through hole 203 is shrunk by heat treatment to block the composite board 202 and the circuit component 206. The gap between them. Next, as shown in FIGS. 8(e) and 8(f), the conductive composition 205a is filled by printing on both sides of the via hole 204 and the electrode terminal portion of the circuit element 206. Then, as shown in FIG. 8(g), the conductive composition 205a is dried by post-heating treatment, and then the film 201 is peeled off.

並且,如圖8(h)所示,於填入有電路元件206並 形成有內通孔205b之複合板221的兩主面,配置並積層形成有用以與內通孔205b進行電連接之通孔區域(via land)232的多層印刷基板231,如圖8(i)所示,藉由加壓加熱處理一體化,以製造電路元件內藏基板241。 And, as shown in FIG. 8(h), the circuit component 206 is filled in and The two main faces of the composite plate 221 having the inner through holes 205b are formed, and are laminated and formed with a multilayer printed substrate 231 having a via land 232 electrically connected to the inner through holes 205b, as shown in Fig. 8(i). As shown in the figure, the circuit board built-in substrate 241 is manufactured by integration by pressure heat treatment.

先前技術文獻 Prior technical literature 專利文獻 Patent literature

專利文獻1:日本專利特開2003-197849號公報 Patent Document 1: Japanese Patent Laid-Open Publication No. 2003-197849

專利文獻2:日本專利特開2011-204811號公報 Patent Document 2: Japanese Patent Laid-Open No. 2011-204811

發明概要 Summary of invention

然而,前述之習知製造方法中,無法使用通用材料之低成本的預浸材料等作為內藏電路元件的基板。 However, in the above-described conventional manufacturing method, a low-cost prepreg or the like of a general-purpose material cannot be used as a substrate of a built-in circuit element.

於以下說明該理由。 The reason will be explained below.

於圖9(a)~圖9(c)中顯示專利文獻2所記載之電路元件內藏基板之製造方法的各步驟之部分平面圖及截面構造圖。 9(a) to 9(c) are a partial plan view and a cross-sectional structural view showing respective steps of a method of manufacturing a circuit element-embedded substrate described in Patent Document 2.

圖9(a)係顯示如圖8(c)所示之於貫通孔203插入有電路元件206時的部分平面圖及截面構造圖。圖9(b)係顯示如圖8(d)所示之藉由加熱處理使貫通孔203收縮時的部分平面圖及截面構造圖。圖9(c)係顯示如圖8(e)及圖8(f)所示之藉由印刷填充有導電性組成物205a時的部分平面圖及截面構造圖。 Fig. 9(a) is a partial plan view and a cross-sectional structural view showing the insertion of the circuit component 206 into the through hole 203 as shown in Fig. 8(c). Fig. 9(b) is a partial plan view and a cross-sectional structural view showing a state in which the through hole 203 is contracted by heat treatment as shown in Fig. 8(d). Fig. 9(c) is a partial plan view and a cross-sectional structural view showing a state in which the conductive composition 205a is filled by printing as shown in Figs. 8(e) and 8(f).

前述之習知製造方法中,如圖9(a)所示,於形成 於複合板202之貫通孔203插入電路元件206後,如圖9(b)所示,藉由加熱處理使貫通孔203收縮,阻塞複合板202與電路元件206之間的間隙。藉由阻塞複合板202與電路元件206之間的間隙,如圖9(c)所示,即使於電路元件206之電極端子部分填充導電性組成物205a,仍可防止短路產生。此處,為藉由圖9(b)之加熱處理得到貫通孔203之收縮效果,需以衝孔機打穿貫通孔203留下加工應變、或包含丙烯酸橡膠等橡膠成分作為複合板202之材料構造。 In the above conventional manufacturing method, as shown in FIG. 9(a), in formation After the circuit element 206 is inserted into the through hole 203 of the composite board 202, as shown in FIG. 9(b), the through hole 203 is shrunk by heat treatment to block the gap between the composite board 202 and the circuit component 206. By blocking the gap between the composite board 202 and the circuit component 206, as shown in FIG. 9(c), even if the electrode terminal portion of the circuit component 206 is filled with the conductive composition 205a, the occurrence of a short circuit can be prevented. Here, in order to obtain the shrinkage effect of the through hole 203 by the heat treatment of FIG. 9(b), it is necessary to punch the through hole 203 with a punch to leave a processing strain or a rubber component such as acrylic rubber as a material of the composite sheet 202. structure.

此處所使用之複合板202係客製材料且高成本。 The composite panel 202 used herein is a custom material and is costly.

於圖10(a)~圖10(c)顯示專利文獻2所記載之電路元件內藏基板之製造方法中,使用以通用之基板材料,即熱硬化性環氧樹脂作為主成分的預浸材料302作為複合板202時,各步驟的部分平面圖及截面構造圖。圖10(a)~圖10(c)之各步驟係顯示各別對應於圖9(a)~圖9(c)的步驟。 In the method of manufacturing the circuit element-embedded substrate described in Patent Document 2, a prepreg using a common substrate material, that is, a thermosetting epoxy resin as a main component, is used in the method of manufacturing the circuit element-embedded substrate described in Patent Document 2 (a) to (c). 302 is a partial plan view and a cross-sectional structural view of each step when the composite plate 202 is used. The steps of Figs. 10(a) to 10(c) show the steps corresponding to Figs. 9(a) to 9(c), respectively.

此時,如圖10(a)所示,於形成有預浸材料302之貫通孔203插入電路元件206後,如圖10(b)所示,即使進行加熱處理貫通孔203仍未收縮。因此,於電路元件206之電極端子部分印刷填充導電性組成物205a時,如圖10(c)所示,糊狀之導電性組成物205a將進入預浸材料302與電路元件206間之間隙,造成電路元件206之電極端子間短路。 At this time, as shown in FIG. 10(a), after the circuit element 206 is inserted into the through hole 203 in which the prepreg 302 is formed, as shown in FIG. 10(b), the through hole 203 is not shrunk even if the heat treatment is performed. Therefore, when the conductive composition 205a is printed on the electrode terminal portion of the circuit component 206, as shown in FIG. 10(c), the paste-like conductive composition 205a enters the gap between the prepreg 302 and the circuit component 206. This causes a short circuit between the electrode terminals of the circuit component 206.

又,該製造方法中,因於電路元件206之電極端子部需自兩面印刷填充糊狀之導電性組成物205a,故填充表面側後,於填充裡面側時表面側已填充之糊將容易附著於放置複合板的支撐體(一般而言,係於基板上配置襯紙) 等,亦有步驟之處理困難等課題。 Further, in this manufacturing method, since the electrode terminal portion of the circuit element 206 is required to be printed with the paste-like conductive composition 205a from both sides, the paste which has been filled on the surface side when filling the back side is easily attached after filling the surface side. a support for placing the composite panel (generally, a liner is placed on the substrate) Etc. There are also problems such as difficulty in handling steps.

本發明考量到前述習知課題,目的係提供一種使用以熱硬化性之環氧樹脂作為主成分的預浸材料等,更加提升電連接信賴性之電路元件內藏基板之製造方法。 The present invention has been made in view of the above-mentioned conventional problems, and an object of the invention is to provide a method for producing a circuit element-embedded substrate which is improved in electrical connection reliability by using a prepreg which is a thermosetting epoxy resin as a main component.

為達成前述目的,第1本發明的電路元件內藏基板之製造方法具有:安裝電路元件步驟,於第1絕緣基板之材料的厚度方向上形成1或複數個貫通孔,並於全部或一部分之前述貫通孔插入電路元件,使其上下之電極端子朝向前述厚度方向、形成內通孔步驟,於第2絕緣基板之材料的厚度方向上形成1或複數個第1通孔,並於前述第1通孔填充第1導電性組成物,形成用以進行電連接之第1內通孔、及積層加壓加熱步驟,於插入有前述電路元件之前述第1絕緣基板的材料兩面,配置分別形成有前述第1內通孔之前述第2絕緣基板的材料,更於前述第2絕緣基板之材料的外側面分別配置並積層配線元件,進行加壓及加熱,前述積層加壓加熱步驟中,前述電路元件之電極端子與前述第1內通孔配置於分別對應之位置,且前述第1內通孔與形成於前述配線元件之電極端子配置於分別對應之位置。 In order to achieve the above object, a method of manufacturing a circuit element-embedded substrate according to a first aspect of the present invention includes the step of mounting a circuit element, wherein one or a plurality of through holes are formed in a thickness direction of a material of the first insulating substrate, and all or a part thereof The through hole is inserted into the circuit element, and the upper and lower electrode terminals are formed in the thickness direction to form an inner through hole, and one or a plurality of first through holes are formed in the thickness direction of the material of the second insulating substrate, and the first through hole is formed. The through hole is filled with the first conductive composition, and the first inner via hole for electrical connection and the laminated pressure heating step are formed, and the first insulating substrate on which the circuit element is inserted is disposed on both surfaces of the material. The material of the second insulating substrate of the first inner via hole is disposed on the outer surface of the material of the second insulating substrate, and the wiring member is laminated and pressurized, and the substrate is pressurized and heated. The electrode terminal of the element and the first inner via are disposed at respective positions, and the first inner via and the electrode terminal formed on the wiring element are disposed Respectively corresponding to the position.

又,第2本發明的電路元件內藏基板之製造方法係如第1本發明的電路元件內藏基板之製造方法,其中前述安裝電路元件步驟中,形成1或複數個前述貫通孔後,於全 部或一部分之前述貫通孔插入前述電路元件前,於前述第1絕緣基板貼附用以阻塞前述貫通孔之開口的覆膜,並與前述覆膜一同於前述第1絕緣基板之材料的厚度方向上形成1或複數個第2通孔,於前述第2通孔填充第2導電性組成物,形成用以進行電連接之第2內通孔。 Further, a method of manufacturing a circuit element-embedded substrate according to a second aspect of the invention is the method of manufacturing a circuit element-embedded substrate according to the first aspect of the invention, wherein in the step of mounting a circuit element, one or a plurality of the through holes are formed, all Before the through hole of the portion or a part of the through hole is inserted into the circuit component, a film for blocking the opening of the through hole is attached to the first insulating substrate, and the thickness of the material of the first insulating substrate is the same as the film. One or a plurality of second via holes are formed in the second via hole, and the second conductive via is filled in the second via hole to form a second inner via hole for electrical connection.

又,第3本發明的電路元件內藏基板之製造方法係如第2本發明的電路元件內藏基板之製造方法,其中前述第1絕緣基板係以環氧樹脂作為主成分之預浸材料。 In the method of manufacturing a circuit element-embedded substrate according to the second aspect of the invention, the first insulating substrate is a prepreg containing epoxy resin as a main component.

又,第4本發明之電路元件內藏基板之製造方法係如第1本發明之電路元件內藏基板之製造方法,其中於前述安裝電路元件步驟中,形成1或複數個前述貫通孔後,於前述貫通孔插入前述電路元件,並於前述貫通孔之一部分插入具一定形狀的導電性元件。 Further, in the method of manufacturing a circuit element-embedded substrate according to the first aspect of the invention, the method of manufacturing the circuit element-embedded substrate according to the first aspect of the invention, wherein the step of mounting the circuit element forms one or a plurality of the through holes, The circuit element is inserted into the through hole, and a conductive element having a predetermined shape is inserted into one of the through holes.

又,第5本發明之電路元件內藏基板之製造方法係如第1本發明之電路元件內藏基板之製造方法,其中前述第1絕緣基板之材料的厚度係內藏之前述電路元件的長度之-0.2mm以上、+0.08mm以下。 Further, in the method of manufacturing a circuit element-embedded substrate according to the first aspect of the invention, the method of manufacturing the circuit element-embedded substrate according to the first aspect of the invention, wherein a thickness of a material of the first insulating substrate is a length of the circuit element included in the circuit element -0.2mm or more and +0.08mm or less.

又,第6本發明之電路元件內藏基板之製造方法係如第1本發明之電路元件內藏基板之製造方法,其中前述第2絕緣基板之材料的厚度係0.03mm以上、0.2mm以下。 In the method of manufacturing a circuit element-embedded substrate according to the first aspect of the invention, the material of the second insulating substrate is 0.03 mm or more and 0.2 mm or less.

又,第7本發明之電路元件內藏基板之製造方法,係如第1本發明之電路元件內藏基板之製造方法,其中前述電路元件之電極端子係矩形,形成於前述第2絕緣基板之材料的前述第1通孔之直徑係0.03mm以上、0.3mm以下, 且前述電路元件之電極端子的對角線尺寸以下。 In the method of manufacturing a circuit element-embedded substrate according to the first aspect of the invention, the electrode terminal of the circuit element is rectangular and formed on the second insulating substrate. The diameter of the first through hole of the material is 0.03 mm or more and 0.3 mm or less. Further, the diagonal length of the electrode terminal of the circuit element is equal to or less.

又,第8本發明之電路元件內藏基板之製造方法,係如第1本發明之電路元件內藏基板之製造方法,其中前述配線元件係多層印刷基板。 In the method of manufacturing a circuit element-embedded substrate according to the first aspect of the invention, the wiring device is a multilayer printed circuit board.

藉由本發明,可提供一種使用以熱硬化性之環氧樹脂作為主成分的預浸材料等,更加提升電連接信賴性之電路元件內藏基板之製造方法。 According to the present invention, it is possible to provide a method for producing a circuit element-embedded substrate which is improved in electrical connection reliability by using a prepreg or the like which is a thermosetting epoxy resin as a main component.

101a,101b,111,201‧‧‧覆膜 101a, 101b, 111, 201‧‧ ‧ film

102,112,302‧‧‧預浸材料 102,112,302‧‧‧Prepreg

202,221‧‧‧複合板 202,221‧‧‧Composite board

103,203‧‧‧貫通孔 103,203‧‧‧through holes

104,113,204‧‧‧通孔 104,113,204‧‧‧through hole

105a,115a,205a‧‧‧導電性組成物 105a, 115a, 205a‧‧‧ Conductive composition

105b,115b,205b‧‧‧內通孔 105b, 115b, 205b‧‧‧ through hole

106,206‧‧‧電路元件 106,206‧‧‧ circuit components

107‧‧‧導電性元件 107‧‧‧Electrical components

131‧‧‧配線元件 131‧‧‧Wiring components

132‧‧‧電極端子 132‧‧‧electrode terminal

141,142,241‧‧‧電路元件內藏基板 141,142,241‧‧‧ Built-in substrate for circuit components

231‧‧‧印刷基板 231‧‧‧Printed substrate

232‧‧‧通孔區域 232‧‧‧through hole area

A1,A2,B1,B2‧‧‧凸出量 A1, A2, B1, B2‧‧‧ bulging

121,123‧‧‧絕緣基板A 121,123‧‧‧Insert substrate A

122‧‧‧絕緣基板B 122‧‧‧Insert substrate B

C1,C2‧‧‧厚度 C1, C2‧‧‧ thickness

L1,L2,L3‧‧‧直徑 L1, L2, L3‧‧‧ diameter

圖1(1)係顯示用以說明(製造絕緣基板A步驟)(a)~(f)(貼附覆膜步驟、形成貫通孔步驟、重貼覆膜步驟、形成通孔步驟、填充.加熱處理導電性組成物步驟、剝離覆膜.插入元件步驟)之本發明實施形態1的電路元件內藏之製造方法的各步驟之絕緣基板A之製造步驟的截面構造圖。 Fig. 1 (1) shows the steps (the steps of manufacturing the insulating substrate A) (a) to (f) (the step of attaching the film, the step of forming the through hole, the step of reattaching the film, the step of forming the through hole, the filling, heating) A cross-sectional structural view of a manufacturing step of the insulating substrate A in each step of the manufacturing method of the circuit element according to the first embodiment of the present invention, in which the conductive composition is processed, and the film is removed.

圖1(2)係顯示用以說明(製造絕緣基板B步驟)(g)~(j)(貼附覆膜步驟、形成通孔步驟、填充.加熱處理導電性組成物步驟、剝離覆膜步驟)之本發明實施形態1的電路元件內藏之製造方法的各步驟之絕緣基板B之製造步驟的截面構造圖。 Fig. 1 (2) shows the steps of (manufacturing the insulating substrate B) (g) to (j) (the step of attaching the film, forming the through hole, filling, heating the conductive composition, and peeling the film) A cross-sectional structural view of a manufacturing step of the insulating substrate B in each step of the manufacturing method of the circuit element according to the first embodiment of the present invention.

圖1(3)係顯示用以說明(積層一體化步驟)(k)、(m)(積層步驟、加壓加熱處理步驟)之本發明實施形態1的電路元件內藏之製造方法的各步驟之積層一體化絕緣基板A、絕緣基板B及配線元件之製造步驟的截面構造圖。 Fig. 1 (3) shows the steps of the manufacturing method of the circuit element according to the first embodiment of the present invention for explaining (layering integration step) (k), (m) (layering step, pressure heating treatment step) A cross-sectional structural view of a manufacturing step of laminating the integrated insulating substrate A, the insulating substrate B, and the wiring member.

圖2(a)係本發明實施形態1之電路元件內藏基板之製造方法的積層步驟中,電路元件自預浸材料凸出之構造的部分截面構造圖。 Fig. 2 (a) is a partial cross-sectional structural view showing a structure in which a circuit element protrudes from a prepreg in a lamination step of a method of manufacturing a circuit element-embedded substrate according to Embodiment 1 of the present invention.

圖2(b)係本發明實施形態1之電路元件內藏基板之製造方法的積層步驟中,電路元件較預浸材料凹陷之構造的部分截面構造圖。 Fig. 2 (b) is a partial cross-sectional structural view showing a structure in which a circuit element is recessed from a prepreg material in a lamination step of a method of manufacturing a circuit element-embedded substrate according to Embodiment 1 of the present invention.

圖3(a)係本發明實施形態1之電路元件內藏基板之製造方法中,電路元件自預浸材料凸出之積層狀態下經加壓加熱處理後之電路元件內藏基板的部分截面構造圖。 Fig. 3 (a) is a partial cross-sectional structure of a circuit element-embedded substrate after being subjected to pressure heat treatment in a laminated state in which a prepreg material is protruded in a method of manufacturing a circuit element-embedded substrate according to a first embodiment of the present invention; Figure.

圖3(b)係本發明實施形態1之電路元件內藏基板之製造方法中,電路元件較預浸材料凹陷之積層狀態下經加壓加熱處理後之電路元件內藏基板的部分截面構造圖。 Fig. 3 (b) is a partial cross-sectional structural view of a circuit element-embedded substrate in a state in which a circuit element is laminated in a state in which a prepreg material is recessed in a laminated state in a method of manufacturing a circuit element-embedded substrate according to a first embodiment of the present invention; .

圖4(a)~圖4(c)係本發明實施形態1之電路元件內藏基板之製造方法中,形成於絕緣基板B的通孔直徑互異時之剝離覆膜前及剝離後之絕緣基板B的部分截面構造圖。 4(a) to 4(c) are the insulation before and after peeling off the film when the diameters of the through holes of the insulating substrate B are different from each other in the method of manufacturing the circuit element-embedded substrate according to the first embodiment of the present invention. A partial cross-sectional structural view of the substrate B.

圖5(a)係本發明實施形態1之電路元件內藏基板之製造方法中,將形成於絕緣基板B之內通孔的直徑作成較配線元件之電極端子的直徑小之構造之電路元件內藏基板的截面構造圖。 In the method of manufacturing a circuit element-embedded substrate according to the first embodiment of the present invention, the diameter of the through hole formed in the insulating substrate B is set to be smaller than the diameter of the electrode terminal of the wiring member. A cross-sectional structural view of the substrate.

圖5(b)係本發明實施形態1之電路元件內藏基板之製造方法中,將形成於絕緣基板B之內通孔的直徑作成較配線元件之電極端子的直徑大之構造之電路元件內藏基板的截面構造圖。 In the method of manufacturing a circuit element-embedded substrate according to the first embodiment of the present invention, the diameter of the through hole formed in the insulating substrate B is set to be larger than the diameter of the electrode terminal of the wiring member. A cross-sectional structural view of the substrate.

圖6(1)係顯示用以說明(製造絕緣基板A步 驟)(a)~(c)(形成貫通孔步驟、插入電路元件步驟、插入導電性元件步驟)之本發明實施形態2的電路元件內藏之製造方法的各步驟之絕緣基板A之製造步驟的截面構造圖。 Figure 6 (1) is shown to illustrate (manufacture of insulating substrate A step (a) to (c) (steps of forming a through hole, inserting a circuit element, and inserting a conductive element), manufacturing steps of the insulating substrate A in each step of the manufacturing method of the circuit element according to the second embodiment of the present invention Sectional construction diagram.

圖6(2)係顯示用以說明(製造絕緣基板B步驟)(d)~(g)(貼附覆膜步驟、通孔形成步驟、導電性組成物填充.加熱處理步驟、覆膜剝離步驟)之本發明實施形態2的電路元件內藏之製造方法的各步驟之絕緣基板B之製造步驟的截面構造圖。 Fig. 6 (2) shows the steps (the steps of manufacturing the insulating substrate B) (d) to (g) (the film coating step, the through hole forming step, the conductive composition filling, the heat treatment step, and the film peeling step) A cross-sectional structural view of a manufacturing step of the insulating substrate B in each step of the manufacturing method of the circuit element according to the second embodiment of the present invention.

圖6(3)係顯示用以說明(積層一體化步驟)(h)、(i)(積層步驟、加壓加熱處理步驟)之本發明實施形態2的電路元件內藏之製造方法的各步驟之積層一體化絕緣基板A、絕緣基板B及配線元件之製造步驟的截面構造圖。 Fig. 6 (3) shows the steps of the manufacturing method of the circuit element according to the second embodiment of the present invention for explaining (layering integration step) (h), (i) (layering step, pressure heating treatment step) A cross-sectional structural view of a manufacturing step of laminating the integrated insulating substrate A, the insulating substrate B, and the wiring member.

圖7係使用本發明實施形態1或2之製造方法製作的電路元件內藏基板之部分截面照片。 Fig. 7 is a partial cross-sectional photograph of a substrate in which a circuit element is fabricated by using the manufacturing method of the first or second embodiment of the present invention.

圖8(a)~圖8(i)係用以說明(貼附覆膜步驟、形成貫通孔.通孔步驟、插入電路元件步驟、加熱處理1步驟、填充導電性組成物步驟、填充導電性組成物(裡面)步驟、加熱處理2.剝離覆膜步驟、積層步驟、加壓加熱處理步驟)習知電路元件內藏基板之製造方法之各步驟的截面構造圖。 8(a) to 8(i) are for explaining (attach film coating step, forming through hole, through hole step, inserting circuit element step, heat treatment 1 step, filling conductive composition step, filling conductivity) Composition (inside) step, heat treatment 2. Stripping coating step, laminating step, and pressure heating treatment step) A cross-sectional structural view of each step of a conventional method for manufacturing a circuit element-embedded substrate.

圖9(a)~圖9(c)係習知電路元件內藏基板之製造方法各步驟的部分平面圖及截面構造圖。 9(a) to 9(c) are a partial plan view and a cross-sectional structural view showing respective steps of a method of manufacturing a conventional circuit element-embedded substrate.

圖10(a)~圖10(c)係習知電路元件內藏基板之製造方法中,使用以熱硬化性之環氧樹脂作為主成分的預浸材料作為複合板時,各步驟的部分平面圖及截面構造圖。 10(a) to 10(c) show a partial plan view of each step in a method of manufacturing a substrate in which a circuit element is embedded, using a prepreg containing a thermosetting epoxy resin as a main component as a composite sheet. And sectional structure diagram.

用以實施發明之形態 Form for implementing the invention

以下,一面參照圖式一面說明本發明之實施形態。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(實施形態1) (Embodiment 1)

圖1(1)((a)~(f))、圖1(2)((g)~(j))、圖1(3)((k)及(m))係用以說明本發明實施形態1的電路元件內藏基板之製造方法之各步驟的截面構造圖。 1(1)((a)~(f)), Fig. 1(2)((g)~(j)), Fig. 1(3)((k) and (m)) are used to illustrate the present invention A cross-sectional structural view of each step of the method of manufacturing the circuit element-embedded substrate of the first embodiment.

圖1(1)((a)~(f))係顯示內藏電路元件之絕緣基板A的製造步驟、圖1(2)((g)~(j))係顯示形成用以連接電路元件之電極端子與配線元件之電極端子的內通孔之絕緣基板B的製造步驟、圖1(3)((k)及(m))係顯示積層一體化絕緣基板A、絕緣基板B及配線元件的製造步驟。 Fig. 1 (1) ((a) to (f)) show the manufacturing steps of the insulating substrate A showing the built-in circuit components, and Fig. 1 (2) ((g) to (j)) are shown to form circuit components. The manufacturing process of the insulating substrate B of the electrode terminal and the inner via hole of the electrode terminal of the wiring element, and FIG. 1 (3) ((k) and (m)) show the laminated integrated insulating substrate A, the insulating substrate B, and the wiring component Manufacturing steps.

首先,說明圖1(1)((a)~(f))所示之絕緣基板A的製造步驟。 First, the manufacturing steps of the insulating substrate A shown in Fig. 1 (1) ((a) to (f)) will be described.

於絕緣基板A之製造步驟的圖1(1)(a)中,可使用例如通用之印刷材料,即預浸材料作為電絕緣性基板材料。以下,以預浸材料102作為絕緣性基板材料為例進行說明。 In Fig. 1 (1) (a) of the manufacturing step of the insulating substrate A, for example, a general-purpose printing material, that is, a prepreg material can be used as the electrically insulating substrate material. Hereinafter, the prepreg 102 will be described as an insulating substrate material as an example.

一般而言,預浸材料係以玻璃布材料與樹脂成分之熱硬化性樹脂作為主成分,藉由硬化劑、或視需要加工含有無機填料之混合物,形成片材狀。預浸材料可視所需特性藉於經選擇直徑與網目粗度之玻璃布材料塗布熱硬化性樹脂,成形為一定厚度地形成。 In general, the prepreg is formed into a sheet form by using a glass cloth material and a thermosetting resin of a resin component as a main component, and by processing a mixture containing an inorganic filler as needed. The prepreg can be formed into a certain thickness by applying a thermosetting resin to a glass cloth material having a selected diameter and a mesh thickness depending on desired characteristics.

本實施形態1中,藉由積層1片於玻璃布(型號2116)塗布環氧樹脂(重量比55%),成形為厚度約0.14mm之預浸材料、及4片於玻璃布(型號1080)塗布環氧樹脂(重量比70%),成形為厚度約0.1mm之預浸材料,作成總厚度0.54mm之預浸材料102。 In the first embodiment, an epoxy resin (weight ratio: 55%) is applied to a glass cloth (model 2116), and a prepreg having a thickness of about 0.14 mm and four sheets of glass cloth (model number 1080) are formed. An epoxy resin (70% by weight) was applied and formed into a prepreg having a thickness of about 0.1 mm to prepare a prepreg 102 having a total thickness of 0.54 mm.

本實施形態1中,係推定內藏之電路元件尺寸0.6×0.3mm的晶片電阻,設定預浸材料102之厚度,但可對應於內藏之元件種類改變預浸材料102的厚度。例如,為尺寸0.4×0.2mm之晶片元件時,可設定預浸材料102之總厚度係0.34mm(積層1片前述厚度0.14mm之預浸材料與2片厚度0.1mm之預浸材料)。 In the first embodiment, the wafer resistance of the built-in circuit element size of 0.6 × 0.3 mm is estimated, and the thickness of the prepreg 102 is set. However, the thickness of the prepreg 102 can be changed in accordance with the type of the built-in component. For example, in the case of a wafer element having a size of 0.4 × 0.2 mm, the total thickness of the prepreg material 102 can be set to 0.34 mm (one prepreg having a thickness of 0.14 mm and two prepreg having a thickness of 0.1 mm).

本實施形態1中,圖1(1)(a)之貼附覆膜步驟中,對應於所期之厚度,重疊複數片預浸材料,並於其外側面配置厚度0.02mm之覆膜101a,以溫度80℃、壓力0.5MPa、時間1分鐘之條件藉由真空層疊貼合呈一體化。 藉由施加80℃之溫度,軟化預浸材料之環氧樹脂成分,可接著預浸材料群及覆膜101a並一體化。覆膜101a可使用例如,聚對苯二甲酸乙二酯或聚苯硫之薄膜。 In the first embodiment, in the step of attaching the film of Fig. 1 (1) (a), a plurality of prepreg materials are stacked in accordance with the desired thickness, and a film 101a having a thickness of 0.02 mm is disposed on the outer surface thereof. The laminate was integrated by vacuum lamination at a temperature of 80 ° C, a pressure of 0.5 MPa, and a time of 1 minute. By applying a temperature of 80 ° C to soften the epoxy resin component of the prepreg, the prepreg material group and the film 101a can be subsequently integrated. As the film 101a, for example, a film of polyethylene terephthalate or polyphenylene sulfide can be used.

另,為抑制熱膨脹率為小,亦可於前述環氧樹脂添加二氧化矽粒子等無機填料。又,環氧樹脂以外,亦可使用耐熱性高之酚醛樹脂或異氰酸樹脂。又,藉由使用介電損耗正切低之氟樹脂,例如,聚四氟乙烯(PTFE樹脂)、PPO(聚苯醚)樹脂、包含液晶聚合物抑或使該等樹脂改質的樹脂,可提升電絕緣層之高頻特性。又,亦可係未 含玻璃布的構造。 Further, in order to suppress a small thermal expansion coefficient, an inorganic filler such as cerium oxide particles may be added to the epoxy resin. Further, in addition to the epoxy resin, a phenol resin or an isocyanate resin having high heat resistance can also be used. Further, by using a fluororesin having a dielectric loss tangent low, for example, a polytetrafluoroethylene (PTFE resin), a PPO (polyphenylene ether) resin, or a resin containing a liquid crystal polymer or modifying the resin, the electricity can be increased. High frequency characteristics of the insulating layer. Also, you can The structure containing glass cloth.

之後,如圖1(1)(b)所示,於期望配置電路元件106之位置形成直徑0.37mm的貫通孔103。貫通孔103可藉由例如,鑽孔加工、雷射加工、或利用衝孔機之模具加工形成。於具有厚度且玻璃布為芯材之預浸材料102形成貫通孔103的加工法,以鑽孔加工較佳。另,貫通孔103之直徑係設定為相當於內藏之電路元件106之電極端子部的對角線長度尺寸。 Thereafter, as shown in Fig. 1 (1) and (b), a through hole 103 having a diameter of 0.37 mm is formed at a position where the circuit component 106 is desired to be disposed. The through hole 103 can be formed by, for example, drilling processing, laser processing, or mold processing using a punching machine. The method of forming the through-holes 103 in the prepreg 102 having a thickness and a glass cloth as a core material is preferably performed by drilling. Further, the diameter of the through hole 103 is set to correspond to the diagonal length dimension of the electrode terminal portion of the built-in circuit component 106.

之後,如圖1(1)(c)所示,進行阻塞貫通孔103上部之處理,使之後的步驟中導電性組成物105a不會進入貫通孔103中。 Thereafter, as shown in Fig. 1 (1) and (c), the upper portion of the through hole 103 is blocked, so that the conductive composition 105a does not enter the through hole 103 in the subsequent step.

本實施形態1中,剝離去除覆膜101a後,與圖1(1)(a)之貼附覆膜步驟同樣地,以真空層疊重新貼上覆膜101b。 In the first embodiment, after the film 101a is peeled off, the film 101b is re-applied by vacuum lamination in the same manner as the step of attaching the film of Fig. 1 (1) and (a).

又,重新貼上之覆膜101b係阻塞本發明貫通孔之開口的覆膜之一例。 Further, the film 101b to be reattached is an example of a film which blocks the opening of the through hole of the present invention.

另,亦可不剝離覆膜101a,而重疊貼上單面具接著性之覆膜來阻塞貫通孔103。此時,因重疊2片上側之覆膜,故可使用厚度薄者作為覆膜。 Further, the through film 103 may be blocked by laminating the film 101a without being peeled off. At this time, since the film on the upper side of the two sheets is superposed, a thin film can be used as the film.

之後,如圖1(1)(d)所示,於期望形成內通孔105b之位置形成通孔104。加工法係與貫通孔103之加工法相同,通孔104之直徑係0.2mm。 Thereafter, as shown in Fig. 1 (1) and (d), the through hole 104 is formed at a position where the inner through hole 105b is desired to be formed. The processing method is the same as that of the through hole 103, and the diameter of the through hole 104 is 0.2 mm.

之後,如圖1(1)(e)所示,於通孔104填充導電性組成物105a。 Thereafter, as shown in FIG. 1 (1) and (e), the conductive composition 105a is filled in the via hole 104.

導電性組成物105a可使用例如,混合有金屬粒子與熱硬化性樹脂的導電性樹脂組成物。金屬粒子可使用金、銀、銅或鎳等。金、銀、銅或鎳因導電性高而為佳,銅因導電性遷移亦少,故特佳。使用經銀被覆銅之金屬粒子,亦可滿足遷移少且導電性高的兩種特性。熱硬化性樹脂可使用例如,環氧樹脂、酚醛樹脂或異氰酸樹脂。環氧樹脂因耐熱性高而特佳。 As the conductive composition 105a, for example, a conductive resin composition in which metal particles and a thermosetting resin are mixed can be used. As the metal particles, gold, silver, copper, nickel, or the like can be used. Gold, silver, copper or nickel is preferred because of its high conductivity, and copper is less conductive due to its conductivity. The use of silver-coated copper metal particles also satisfies two characteristics of less migration and high conductivity. As the thermosetting resin, for example, an epoxy resin, a phenol resin or an isocyanate resin can be used. Epoxy resins are particularly excellent in heat resistance.

又,導電性組成物105a,亦可使用包含焊料之材料進行金屬接合。 Further, the conductive composition 105a may be metal-bonded using a material containing solder.

導電性組成物105a之填充係將具有通孔104之預浸材料102設置於印刷機(未圖示)的台上,直接自覆膜101b上藉由印刷填充導電性組成物105a。此時,上面之覆膜101b發揮印刷遮罩之功用與防止汙染預浸材料102表面的功用。 In the filling of the conductive composition 105a, the prepreg 102 having the through holes 104 is placed on a stage of a printing machine (not shown), and the conductive composition 105a is directly filled from the film 101b by printing. At this time, the upper film 101b functions as a printing mask and prevents the surface of the prepreg 102 from being contaminated.

圖1(1)(e)之步驟中,於填充導電性組成物105a後,進行80℃ 30分鐘左右的加熱處理,使導電性組成物105a乾燥並柱化,形成內通孔105b。 In the step of (1) and (e), after the conductive composition 105a is filled, heat treatment is performed at 80 ° C for about 30 minutes, and the conductive composition 105a is dried and pillared to form the inner via hole 105b.

另,通孔104係本發明第2通孔之一例,導電性組成物105a係本發明第2導電性組成物之一例。又,內通孔105b係本發明第2內通孔之一例。 Further, the through hole 104 is an example of the second through hole of the present invention, and the conductive composition 105a is an example of the second conductive composition of the present invention. Further, the inner through hole 105b is an example of the second inner through hole of the present invention.

之後,如圖1(1)(f)所示,剝離覆膜101a及101b後,將電路元件106縱向地插入貫通孔103。此時,因內通孔105b藉由加熱處理柱化,故自預浸材料102表面凸出亦無問題。另,插入電路元件106後亦可剝離覆膜101a及101b。 Thereafter, as shown in FIGS. 1 (1) and (f), after the films 101a and 101b are peeled off, the circuit component 106 is inserted into the through hole 103 in the longitudinal direction. At this time, since the inner through hole 105b is pillared by heat treatment, there is no problem in protruding from the surface of the prepreg material 102. Further, after the circuit component 106 is inserted, the films 101a and 101b can be peeled off.

藉由以上步驟,可製造相對於厚度方向縱向地配置電路元件106,並形成有內通孔105b之絕緣基板A121。 By the above steps, the insulating substrate A121 in which the circuit component 106 is disposed longitudinally with respect to the thickness direction and the inner via hole 105b is formed can be manufactured.

另,絕緣基板A121係本發明第1絕緣基板之一例,預浸材料102係本發明第1絕緣基板材料之一例。 Further, the insulating substrate A121 is an example of the first insulating substrate of the present invention, and the prepreg 102 is an example of the first insulating substrate material of the present invention.

又,圖1(1)(b)~圖1(1)(f)中所示之步驟係安裝本發明電路元件步驟之一例。 Further, the steps shown in Figs. 1(1)(b) to 1(1)(f) are examples of the steps of mounting the circuit elements of the present invention.

接著,說明圖1(2)((g)~(j))所示之絕緣基板B的製造步驟。絕緣基板B係以與絕緣基板A相同之製造方法製造。 Next, a manufacturing procedure of the insulating substrate B shown in Fig. 1 (2) ((g) to (j)) will be described. The insulating substrate B is manufactured by the same manufacturing method as the insulating substrate A.

圖1(2)(g)係貼附覆膜之步驟。預浸材料112之厚度係0.14mm,係使用1片於玻璃布(型號2116)塗布環氧樹脂(重量比55%),成形為厚度約0.14mm者。於預浸材料112之兩主面以真空層疊貼附厚度0.02mm的覆膜111。 Fig. 1 (2) (g) is a step of attaching a film. The thickness of the prepreg 112 was 0.14 mm, and one piece of epoxy resin (weight ratio: 55%) was applied to a glass cloth (model 2116) to form a thickness of about 0.14 mm. A film 111 having a thickness of 0.02 mm was attached to the two main faces of the prepreg 112 by vacuum lamination.

圖1(2)(h)係形成通孔步驟。於期望形成內通孔115b之位置藉由鑽孔加工或雷射加工等,加工直徑0.15mm的通孔113。 Fig. 1 (2) (h) is a step of forming a through hole. A through hole 113 having a diameter of 0.15 mm is processed by drilling, laser processing or the like at a position where it is desired to form the inner through hole 115b.

圖1(2)(i)係填充導電性組成物步驟及加熱處理步驟。藉由印刷於通孔113填充導電性組成物115a。之後,藉由加熱處理將導電性組成物115a柱化,形成內通孔115b。 Fig. 1 (2) (i) is a step of filling a conductive composition and a heat treatment step. The conductive composition 115a is filled by printing on the through hole 113. Thereafter, the conductive composition 115a is pillared by heat treatment to form an inner via hole 115b.

圖1(2)(j)係剝離覆膜步驟。藉由剝離去除覆膜111,可製造形成有內通孔115b之絕緣基板B122。 Fig. 1 (2) (j) is a step of peeling off the film. By removing the film 111 by peeling, the insulating substrate B122 in which the inner via hole 115b is formed can be manufactured.

另,絕緣基板B122係本發明第2絕緣基板之一 例,預浸材料112係本發明第2絕緣基板的材料之一例。又,通孔113係本發明第1通孔之一例。又,導電性組成物115a係本發明第1導電性組成物之一例,內通孔115b係本發明第1內通孔之一例。 In addition, the insulating substrate B122 is one of the second insulating substrates of the present invention. For example, the prepreg 112 is an example of a material of the second insulating substrate of the present invention. Further, the through hole 113 is an example of the first through hole of the present invention. Further, the conductive composition 115a is an example of the first conductive composition of the present invention, and the inner through hole 115b is an example of the first inner through hole of the present invention.

又,圖1(2)(h)~圖1(2)(j)所示之步驟係本發明形成內通孔步驟之一例。 Further, the steps shown in Figs. 1(2)(h) to 1(2)(j) are examples of the steps of forming the inner through hole in the present invention.

接著,說明圖1(3)((k)及(m))所示之積層一體化步驟。 Next, the step of integrating the layers shown in Fig. 1 (3) ((k) and (m)) will be described.

如圖1(3)(k)所示,於絕緣基板A121之兩主面配置並積層絕緣基板B122,更於絕緣基板B122之外側面配置配線元件131進行積層。此時,於積層時將形成於絕緣基板A121之電路元件106之電極端子與內通孔105b、形成於絕緣基板B122之內通孔115b、及配線元件131之電極端子132(例如,直徑0.3mm之通孔區域),於積層時進行對準,配置於同一座標上。積層對準之方法,可藉於各基材開出基準孔(未圖示),於加壓加熱治具上以定位銷進行積層,即可輕易地對準。 As shown in Fig. 1 (3) and (k), the insulating substrate B122 is placed on both main surfaces of the insulating substrate A121, and the wiring member 131 is placed on the outer surface of the insulating substrate B122 to be laminated. At this time, at the time of lamination, the electrode terminal and the inner via hole 105b of the circuit element 106 formed on the insulating substrate A121, the via hole 115b formed in the insulating substrate B122, and the electrode terminal 132 of the wiring member 131 (for example, a diameter of 0.3 mm) The through hole area is aligned at the time of lamination and placed on the same coordinate. The method of laminating the layers can be easily aligned by opening a reference hole (not shown) on each substrate and laminating the pin on the pressure heating jig.

圖1(3)(k)之步驟中積層時,因未賦與預浸材料102及112壓力,故未產生樹脂流動,又未加熱至樹脂硬化之溫度,故預浸材料102及112係未硬化的狀態。 In the step of laminating the steps of Fig. 1 (3) and (k), since the pressure of the prepreg materials 102 and 112 is not applied, the resin does not flow and is not heated to the temperature at which the resin is hardened, so the prepreg materials 102 and 112 are not Hardened state.

之後,如圖1(3)(m)所示,利用加壓加熱絕緣基板A121、絕緣基板B122及配線元件131之積層體使其一體化,可製造電路元件內藏基板141。 Then, as shown in Fig. 1 (3) and (m), the laminated body of the insulating substrate A121, the insulating substrate B122, and the wiring member 131 is heated and integrated to form the circuit component-embedded substrate 141.

另,藉於配線元件131使用多層印刷基板,僅以 圖1(3)((k)及(m))所示之步驟,即可製造配線密度高的多層電路元件內藏基板。 In addition, by using the multilayer printed substrate by the wiring member 131, only In the steps shown in Fig. 1 (3) ((k) and (m)), a multilayer circuit element-embedded substrate having a high wiring density can be manufactured.

另,圖1(3)(k)及圖1(3)(m)中所示之步驟係本發明的積層加壓加熱步驟之一例。 Further, the steps shown in Fig. 1 (3) (k) and Fig. 1 (3) (m) are examples of the laminating pressurization heating step of the present invention.

又,圖1(3)(m)之加壓加熱處理步驟的加熱係以預浸材料102、112及內通孔105b、115b中之熱硬化性樹脂硬化的溫度以上(例如150℃~260℃)進行。藉由該加熱,可機械性地堅固接著絕緣基板A121之預浸材料102、絕緣基板B122之預浸材料112、電路元件106及配線元件131。又,藉由內通孔115b,可電連接電路元件106之電極端子與形成於配線元件131之電極端子132。 Further, the heating in the pressure heating treatment step of Fig. 1 (3) (m) is performed at a temperature higher than the temperature at which the thermosetting resin in the prepreg materials 102 and 112 and the inner through holes 105b and 115b is cured (for example, 150 ° C to 260 ° C). )get on. By this heating, the prepreg 102 of the insulating substrate A121, the prepreg 112 of the insulating substrate B122, the circuit component 106, and the wiring member 131 can be mechanically strengthened. Further, the electrode terminal of the circuit component 106 and the electrode terminal 132 formed on the wiring component 131 can be electrically connected via the inner via hole 115b.

又,於圖1(3)(m)之加壓加熱處理步驟中,藉由加熱使預浸材料102、112及內通孔105b、115b中的熱硬化性樹脂時,利用一面加熱一面以壓力1MPa~20MPa加壓,可提升電路元件內藏基板141之機械強度。又,藉於貫通孔103與電路元件106之間隙填充經熔融之樹脂、或充分地壓縮內通孔105b、115b,可得到良好狀態的電連接。於以下實施形態中亦相同。 Further, in the step of the heat treatment of Fig. 1 (3) (m), when the thermosetting resin in the prepreg materials 102 and 112 and the inner through holes 105b and 115b is heated by heating, the pressure is applied by one side while being heated. Pressurization from 1 MPa to 20 MPa can improve the mechanical strength of the built-in substrate 141 of the circuit component. Further, by filling the gap between the through hole 103 and the circuit element 106 with the molten resin or sufficiently compressing the inner through holes 105b and 115b, electrical connection in a good state can be obtained. The same applies to the following embodiments.

又,圖1(3)(m)之加壓加熱步驟中,因於150℃~260℃之高溫真空狀態下施加高壓,呈半硬化狀態的預浸材料102中之樹脂的黏度將暫時下降,因施加壓力而產生流動。因此,藉由預浸材料102填入內通孔105b與通孔104之壁面間的間隙,之後,預浸材料102之樹脂將完全硬化。因此,圖1(3)(m)之加壓加熱步驟後,內通孔105b與預 浸材料102之間將成為無間隙之密著狀態。 Further, in the pressure heating step of Fig. 1 (3) (m), the viscosity of the resin in the semi-hardened prepreg 102 is temporarily lowered by applying a high pressure in a high-temperature vacuum state of 150 ° C to 260 ° C. Flow occurs due to the application of pressure. Therefore, the gap between the inner through hole 105b and the wall surface of the through hole 104 is filled by the prepreg 102, and then the resin of the prepreg 102 is completely hardened. Therefore, after the pressure heating step of Fig. 1 (3) (m), the inner through hole 105b and the pre The immersion material 102 will be in a closed state without gaps.

前述本實施形態1之電路元件內藏基板141之製造方法中,因無於電路元件106之電極端子直接印刷填充導電性組成物105a的步驟,故即使預浸材料102與電路元件106中產生間隙,電路元件106之電極端子間仍未產生短路。又,如圖1(1)(e)所示,因可自單面對絕緣基板A121印刷填充導電性組成物105a,故容易於步驟中處理。 In the method of manufacturing the circuit element-embedded substrate 141 of the first embodiment, since the step of directly filling the electrode assembly 105a with the electrode terminal of the circuit element 106 is performed, even a gap is formed in the prepreg 102 and the circuit element 106. There is still no short circuit between the electrode terminals of the circuit component 106. Further, as shown in Fig. 1 (1) and (e), since the conductive composition 105a is printed and printed on the insulating substrate A121, it is easy to handle in the step.

本實施形態1之構造中,相對於電路元件106之長度0.6mm,設定預浸材料102之厚度為0.54mm,故電路元件106相對於預浸材料102將自凸出單側0.03mm。又,藉由設定覆膜厚度為0.02mm,如圖1(1)(f)所示,於插入電路元件106時,可大致配置於預浸材料102之厚度方向的中央附近。 In the structure of the first embodiment, the thickness of the prepreg 102 is set to 0.54 mm with respect to the length of the circuit component 106 of 0.6 mm, so that the circuit component 106 is 0.03 mm from the one side of the prepreg 102. Moreover, by setting the film thickness to 0.02 mm, as shown in Fig. 1 (1) and (f), when the circuit component 106 is inserted, it can be arranged substantially in the vicinity of the center of the thickness direction of the prepreg 102.

又,因將內通孔115b(直徑0.15mm)之直徑設定成較內通孔105b(直徑0.2mm)、或電路元件106之電極端子尺寸(對角0.37mm)及配線元件131之電極端子132之尺寸(直徑0.3mm)小,可吸收積層差異,故高密度地內藏元件仍可成為鄰接元件間之絕緣性無問題的電路元件內藏基板141。 Further, the diameter of the inner through hole 115b (diameter 0.15 mm) is set to be smaller than the inner through hole 105b (diameter: 0.2 mm), or the electrode terminal size of the circuit element 106 (diagonal angle: 0.37 mm), and the electrode terminal 132 of the wiring member 131. Since the size (diameter: 0.3 mm) is small and the difference in buildup can be absorbed, the high-density built-in element can still be a circuit element built-in substrate 141 having no problem of insulation between adjacent elements.

又,加壓加熱步驟後電路元件內藏基板141內之內通孔105b係如圖1(3)(m)所示之圓柱狀,該圓柱狀之側面於高度方向上係秉直。另一方面,如圖8(i)所示,習知電路元件內藏基板241中,加壓加熱步驟後的內通孔205b於高度方向上側面係呈曲線狀,與藉由本實施形態1之製造 方法製造的內通孔105b係相異之形狀。 Further, after the pressure heating step, the inner through hole 105b in the circuit board built-in substrate 141 is a columnar shape as shown in Fig. 1 (3) and (m), and the cylindrical side surface is straight in the height direction. On the other hand, as shown in FIG. 8(i), in the conventional circuit element-embedded substrate 241, the inner through hole 205b after the pressure heating step has a curved shape in the height direction, and the first embodiment is curved. Manufacturing The inner through holes 105b produced by the method are in a different shape.

圖2(a)及圖2(b)係說明本實施形態1之電路元件內藏基板141之製造方法的圖1(3)(k)所示之積層步驟中材料構造之組合例的部分截面構造圖。 2(a) and 2(b) are partial cross-sectional views showing a combination of material structures in the laminating step shown in Fig. 1 (3) and (k) of the method for manufacturing the circuit element-embedded substrate 141 of the first embodiment. structure map.

預浸材料102之厚度的適當範圍以相對於內藏之電路元件106的長度-0.2~+0.08mm(單側:-0.1~+0.04mm)為佳。換言之,於以預浸材料102之厚度作為基準時,以將單面側之電路元件106的凸出量設為-0.04~+0.1mm之範圍為佳。 The appropriate range of the thickness of the prepreg material 102 is preferably -0.2 to +0.08 mm (one side: -0.1 to +0.04 mm) with respect to the length of the built-in circuit component 106. In other words, when the thickness of the prepreg material 102 is used as a reference, it is preferable to set the amount of protrusion of the circuit element 106 on one side to a range of -0.04 to +0.1 mm.

以下說明該理由。 The reason will be explained below.

絕緣基板B122之內通孔115b的凸出量係與覆膜111之厚度有關。由處理性或剝離性之問題、及與絕緣基板B122之厚度的關係來看,覆膜111係使用0.005~0.05mm之厚度者。 The amount of protrusion of the through hole 115b in the insulating substrate B122 is related to the thickness of the film 111. The film 111 is used in a thickness of 0.005 to 0.05 mm in view of the relationship between the handleability and the peelability and the thickness of the insulating substrate B122.

圖2(a)係電路元件106自預浸材料102凸出狀態之例,係例如,電路元件106之凸出量A1的尺寸係+0.1mm(適當範圍之上限)且內通孔115b之凸出量B1係0.005mm之構造的部分截面構造圖。 Figure 2 (a) is a circuit component 106 protruding from the prepreg material 102 An example of the state is, for example, a partial cross-sectional structural view of a structure in which the size A1 of the circuit element 106 is +0.1 mm (the upper limit of the appropriate range) and the amount of protrusion B1 of the inner through hole 115b is 0.005 mm.

如圖2(a)所示之積層狀態時,內通孔115b於抵接電路元件106之電極端子的狀態下具有壓縮量(A1+B1),故於之後步驟的圖1(3)(m)所示之加壓加熱步驟中,壓力將傳至內通孔115b,可得到良好之連接。於將電路元件106之凸出量A1增大至所需以上時,因需增厚用以吸收電路元件106之凸出的絕緣基板B122之厚度,故加壓時電路元件 106將不易停留在內藏層之中央,上下之內通孔115b的壓縮量容易產生差異,連接信賴性變差。又,不易將插入至貫通孔103之電路元件106配置於預浸材料102之厚度方向的中央。 In the laminated state shown in Fig. 2(a), the inner through hole 115b has a compression amount (A1 + B1) in a state of abutting against the electrode terminal of the circuit component 106, so that Fig. 1 (3) (m) of the subsequent step In the pressurized heating step shown, the pressure will be transmitted to the inner through hole 115b, and a good connection can be obtained. When the amount of protrusion A1 of the circuit component 106 is increased to more than necessary, the thickness of the insulating substrate B122 for absorbing the protruding of the circuit component 106 is increased, so that the circuit component is pressurized. It is difficult for the 106 to stay in the center of the inner layer, and the amount of compression of the through hole 115b in the upper and lower sides is likely to be different, and the connection reliability is deteriorated. Moreover, it is difficult to arrange the circuit component 106 inserted into the through hole 103 in the center of the thickness direction of the prepreg 102.

圖2(b)係電路元件106較預浸材料102凹陷之狀態之例,係例如,電路元件106之凸出量A2的尺寸係-0.04mm(適當範圍之下限)且內通孔115b之凸出量B2係0.05mm之構造的部分截面構造圖。 2(b) shows an example in which the circuit component 106 is recessed from the prepreg material 102, for example, the projection amount A2 of the circuit component 106 is -0.04 mm (the lower limit of the appropriate range) and the inner through hole 115b is convex. A partial cross-sectional structural view of a structure in which B2 is 0.05 mm.

如圖2(b)所示之積層狀態時,壓縮量(B2+A2)之尺寸將成為+0.01mm,故於之後步驟的圖1(3)(m)所示之加壓加熱步驟中可對內通孔115b施加壓力。相對於預浸材料102之電路元件106的凹陷量係0.04mm以上(即,A2<-0.04mm時)時,因無法自覆膜111之厚度設定限制中再增加內通孔115b的凸出量B2,之後步驟的圖1(3)(m)所示之加壓加熱步驟中將無法對內通孔115b施加壓力。 When the laminated state is as shown in Fig. 2(b), the size of the compression amount (B2 + A2) will be +0.01 mm, so that it can be in the pressure heating step shown in Fig. 1 (3) (m) of the subsequent step. Pressure is applied to the inner through hole 115b. When the amount of recess of the circuit component 106 of the prepreg 102 is 0.04 mm or more (that is, when A2 < -0.04 mm), the amount of protrusion of the inner via 115b cannot be increased from the thickness setting limit of the film 111. B2, in the pressurization heating step shown in Fig. 1 (3) (m) of the subsequent step, it is impossible to apply pressure to the inner through hole 115b.

以設定預浸材料102之厚度使電路元件106之凸出量係單側+0.03~+0.08mm較佳,但於厚度之種類受到限制的通用材料時,絕緣基板A121之厚度超出理想值時,如前述,藉由調整內通孔115b的凸出量,即使電路元件106較預浸材料102之表面凹陷,仍可無問題地連接。 It is preferable to set the thickness of the prepreg material 102 so that the protruding amount of the circuit component 106 is one side +0.03 to +0.08 mm, but when the thickness of the insulating substrate A121 exceeds an ideal value when the thickness of the insulating material is limited. As described above, by adjusting the amount of protrusion of the inner through hole 115b, even if the circuit component 106 is recessed from the surface of the prepreg material 102, it can be connected without problems.

圖3(a)及圖3(b)係說明本實施形態1之電路元件內藏基板141之製造方法的圖1(3)(m)所示之加壓加熱步驟後的材料構造之組合例的部分截面構造圖。 3(a) and 3(b) are diagrams showing a combination of material structures after the pressure heating step shown in Fig. 1 (3) and (m) of the method for manufacturing the circuit element-embedded substrate 141 of the first embodiment. Partial section construction diagram.

圖3(a)係顯示圖2(a)所示之構造中加壓加熱處理 後的部分截面構造圖、圖3(b)係顯示圖2(b)所示之構造中加壓加熱處理後的部分截面構造圖。 Figure 3 (a) shows the pressurized heat treatment in the configuration shown in Figure 2 (a) The partial cross-sectional structural view after FIG. 3(b) shows a partial cross-sectional structural view of the structure shown in FIG. 2(b) after the pressure heat treatment.

預浸材料112之厚度的適當範圍以0.03mm以上、0.2mm以下為佳。以下說明該理由。 A suitable range of the thickness of the prepreg 112 is preferably 0.03 mm or more and 0.2 mm or less. The reason will be explained below.

配線元件131電極端子132之厚度一般係0.005~0.05mm左右。 Wiring element 131 The thickness of the electrode terminal 132 is generally about 0.005 to 0.05 mm.

如圖3(a)所示,電路元件106自預浸材料102凸出時,預浸材料112需係吸收電路元件106之凸出量(最大0.1mm)與配線元件131之電極端子132之厚度(最大0.05mm)的厚度。內通孔115b之壓縮後的厚度係最小0.05mm時,預浸材料112之厚度(C1)需為0.2mm左右。但,厚度C1為0.2mm以上時,因預浸材料112係2片構造,將成為成本上升之要因,並有電路元件內藏基板141之厚度變厚的問題。 As shown in FIG. 3(a), the circuit component 106 protrudes from the prepreg material 102. At this time, the prepreg 112 is required to have a thickness of the absorption circuit element 106 (maximum 0.1 mm) and the thickness of the electrode terminal 132 of the wiring member 131 (maximum 0.05 mm). When the thickness of the inner through hole 115b after compression is at least 0.05 mm, the thickness (C1) of the prepreg 112 is required to be about 0.2 mm. However, when the thickness C1 is 0.2 mm or more, the prepreg 112 has a two-piece structure, which causes a cost increase, and the thickness of the circuit board built-in substrate 141 becomes thick.

如圖3(b)所示,藉不使電路元件106自預浸材料102凸出,預浸材料112之厚度(C2)只要係可吸收電極端子132之厚度(最小0.005mm)即可。但,考量到預浸材料112本身之處理性與確保覆膜111之剝離性及穩定之內通孔115b的凸出量之觀點、或可取得作為材料之厚度,需為0.03mm以上之厚度。 As shown in FIG. 3(b), the thickness (C2) of the prepreg 112 is such that the thickness (minimum 0.005 mm) of the electrode terminal 132 can be absorbed without causing the circuit component 106 to protrude from the prepreg material 102. However, the thickness of the prepreg 112 itself and the viewpoint of ensuring the peeling property of the film 111 and the amount of protrusion of the through hole 115b in the stable state or the thickness of the material to be obtained may be 0.03 mm or more.

另,於圖2(a)及圖2(b)中,電路元件106之電極端子上下的面之未與內通孔115b接觸的部分與絕緣基板B122間雖有間隙,但於圖1(3)(m)之加壓加熱步驟中,預浸材料102及112中的樹脂軟化流動,而填入該間隙。因 此,如圖3(a)及圖3(b)所示,圖1(3)(m)之加壓加熱步驟後電路元件106之電極端子與絕緣基板B122間係成為無間隙的狀態。 2(a) and 2(b), there is a gap between the upper and lower surfaces of the electrode terminals of the circuit element 106 that are not in contact with the inner via 115b and the insulating substrate B122, but in FIG. 1 (3) In the pressure heating step of (m), the resin in the prepregs 102 and 112 softens and flows, and fills the gap. because As shown in Fig. 3 (a) and Fig. 3 (b), after the pressure heating step of Fig. 1 (3) (m), the electrode terminal of the circuit element 106 and the insulating substrate B 122 are in a state of no gap.

另一方面,內通孔115b因藉圖1(2)(i)之加熱處理柱化,於圖1(3)(m)之加壓加熱步驟中即使加壓加熱仍不易流動。因此,圖1(3)(m)之加壓加熱步驟時,內通孔115b之部分將不會流入電路元件106與預浸材料102間的間隙、或電路元件106與絕緣基板B122間之間隙,預浸材料102或112之樹脂將軟化而流入並填入該等間隙中。 On the other hand, the inner through hole 115b is columnized by the heat treatment of Fig. 1 (2) (i), and it is difficult to flow even under pressure heating in the pressure heating step of Fig. 1 (3) (m). Therefore, in the pressure heating step of Fig. 1 (3) (m), the portion of the inner through hole 115b will not flow into the gap between the circuit component 106 and the prepreg 102, or the gap between the circuit component 106 and the insulating substrate B122. The resin of the prepreg material 102 or 112 will soften and flow into and fill the gaps.

形成於絕緣基板B122之內通孔115b的直徑L以0.03mm以上、0.3mm以下,且內藏之電路元件106之電極端子的對角線尺寸以下為佳。以下說明該理由。 The diameter L of the through hole 115b formed in the insulating substrate B122 is 0.03 mm or more and 0.3 mm or less, and the diagonal dimension of the electrode terminal of the built-in circuit component 106 is preferably equal to or less. The reason will be explained below.

圖4(a)~圖4(c)中,顯示絕緣基板B122之製造步驟的剝離覆膜111前及剝離後的截面構造圖。圖4(a)~圖4(c)係顯示通孔113之直徑相異的構造之絕緣基板B122的各截面構造圖。 4(a) to 4(c), a cross-sectional structural view before and after peeling off the peeling film 111 in the manufacturing process of the insulating substrate B122 is shown. 4(a) to 4(c) are cross-sectional structural views showing an insulating substrate B122 having a structure in which the diameters of the through holes 113 are different.

圖1(2)(i)之填充導電性組成物步驟中,於形成於絕緣基板B122之通孔113印刷填充導電性組成物115a時,因導電性組成物115a之黏性而經刮漿板擷取些微,成為凹陷狀態。此於通孔徑越大影響越大、凹量越深。 In the step of filling the conductive composition in FIG. 1 (2) (i), when the conductive composition 115a is filled and filled in the through hole 113 formed in the insulating substrate B122, the squeegee is passed through the squeegee of the conductive composition 115a. Take a little bit and become a recessed state. Therefore, the larger the through hole diameter, the greater the influence and the deeper the concave amount.

例如,覆膜111之厚度為0.02mm時,如圖4(a)所示,若通孔113之直徑L1係0.15mm,導電性組成物115a填充後之凹量係0.01mm左右,如圖4(a)之右圖所示,剝離覆膜111後,內通孔115b係較預浸材料112表面凸出的狀態, 之後步驟的圖1(3)(m)所示之加壓加熱步驟中,因內通孔115b得到充分之壓縮,故可得良好之連接信賴性之狀態。 For example, when the thickness of the coating film 111 is 0.02 mm, as shown in FIG. 4(a), if the diameter L1 of the through hole 113 is 0.15 mm, the concave amount after filling the conductive composition 115a is about 0.01 mm, as shown in FIG. As shown in the right figure of (a), after the film 111 is peeled off, the inner through hole 115b is in a state of being protruded from the surface of the prepreg 112. In the pressure heating step shown in Fig. 1 (3) and (m) of the subsequent steps, since the inner through hole 115b is sufficiently compressed, a good connection reliability state can be obtained.

內通孔115b之直徑L小於0.03mm時,電路元件106之電極端子及與配線元件131之電極端子132的連接面積變小,而使連接信賴性惡化。 When the diameter L of the inner through hole 115b is less than 0.03 mm, the connection area between the electrode terminal of the circuit element 106 and the electrode terminal 132 of the wiring element 131 is small, and the connection reliability is deteriorated.

如圖4(b)所示,若通孔113之直徑L2為0.25mm,導電性組成物115a填充後之凹量係0.02mm左右,如圖4(b)之右圖所示,剝離覆膜111後,內通孔115b係成為與預浸材料112表面相同的高度。 As shown in Fig. 4(b), if the diameter L2 of the through hole 113 is 0.25 mm, the concave amount after the filling of the conductive composition 115a is about 0.02 mm, as shown in the right figure of Fig. 4(b), the film is peeled off. After 111, the inner through hole 115b has the same height as the surface of the prepreg 112.

如圖4(c)所示,若通孔113之直徑L3係0.3mm,導電性組成物115a填充後之凹量係0.03mm左右,如圖4(c)之右圖所示,剝離覆膜111後,內通孔115b成為較預浸材料112表面凹陷,之後步驟的圖1(3)(m)所示之加壓加熱步驟中將不易對內通孔115b施加壓力,因與配線元件131之電極端子132間產生間隙,使電連接信賴性惡化。但,即使通孔113之直徑L3為0.3mm,藉由增厚覆膜111為0.05mm,於剝離覆膜111後,可將內通孔115b作成較預浸材料112表面凸出的狀態。 As shown in Fig. 4(c), if the diameter L3 of the through hole 113 is 0.3 mm, the concave amount after filling the conductive composition 115a is about 0.03 mm, as shown in the right figure of Fig. 4(c), the film is peeled off. After the 111, the inner through hole 115b is recessed toward the surface of the prepreg 112, and the pressure heating step shown in Fig. 1 (3) (m) of the subsequent step will not easily apply pressure to the inner through hole 115b, and the wiring member 131 A gap is formed between the electrode terminals 132 to deteriorate the electrical connection reliability. However, even if the diameter L3 of the through hole 113 is 0.3 mm and the thickness of the thick film 111 is 0.05 mm, the inner through hole 115b can be made to protrude from the surface of the prepreg 112 after the film 111 is peeled off.

圖5(a)及圖5(b)係顯示本實施形態1之圖1(3)(m)所示的加壓加熱步驟後之電路元件內藏基板141的截面構造圖。 (a) and (b) of FIG. 5 are cross-sectional structural views showing the circuit element-containing substrate 141 after the pressure heating step shown in Fig. 1 (3) and (m) of the first embodiment.

圖5(a)係顯示將形成於絕緣基板B122之內通孔115b的直徑作成較配線元件131之電極端子132的直徑小的構造之電路元件內藏基板141的截面構造圖、圖5(b)係顯示 將內通孔115b之直徑作成較電極端子132之直徑大的構造之電路元件內藏基板141的截面構造圖。 5(a) is a cross-sectional structural view showing a circuit element-embedded substrate 141 having a structure in which the diameter of the through hole 115b formed in the insulating substrate B122 is smaller than the diameter of the electrode terminal 132 of the wiring member 131, and FIG. 5(b) ) display A cross-sectional structural view of the circuit element-accommodating substrate 141 having a structure in which the diameter of the inner through hole 115b is larger than the diameter of the electrode terminal 132.

因相對於基板之厚度方向縱向地內藏電路元件106的目的係高密度安裝,如圖5(a)及圖5(b)所示,係密集地配置內藏之電路元件106。因此,如圖5(b)所示,將內通孔115b之直徑設成大於配線元件131之電極端子132的直徑0.3mm時,有對相鄰元件之絕緣性變差的問題。因各種構造元件之加工精度或積層精度造成的位移、及之後步驟之加壓加熱步驟中內通孔115b受到壓縮造成內通孔115b變大產生等係為要因。 Since the purpose of the built-in circuit element 106 in the longitudinal direction of the thickness direction of the substrate is high-density mounting, as shown in FIGS. 5(a) and 5(b), the built-in circuit element 106 is densely arranged. Therefore, as shown in FIG. 5(b), when the diameter of the inner through hole 115b is set larger than the diameter of the electrode terminal 132 of the wiring member 131 by 0.3 mm, there is a problem that insulation properties of adjacent elements are deteriorated. The displacement due to the processing accuracy or the lamination accuracy of the various structural elements, and the internal through-hole 115b being compressed during the pressurization heating step in the subsequent step are caused to cause the inner through-hole 115b to become large.

又,內藏之電路元件106為小時,以高密度地內藏電路元件106為目的,有配合電路元件106之電極端子的對角線尺寸,縮短配線元件131之電極端子132的直徑的情形。此時,內通孔115b直徑之最大尺寸係設為電路元件106之電極端子的對角線尺寸以下。 Further, the built-in circuit component 106 is small, and the purpose of incorporating the circuit component 106 at a high density is to reduce the diameter of the electrode terminal 132 of the wiring component 131 by matching the diagonal dimension of the electrode terminal of the circuit component 106. At this time, the maximum size of the diameter of the inner through hole 115b is set to be equal to or less than the diagonal dimension of the electrode terminal of the circuit component 106.

另,本實施形態1中,以電連接上下配線元件131之間為目的,以於預浸材料102設有內通孔105b之構造說明,但於可僅以內藏之電路元件106進行上下配線元件131間的電連接,而作成電路設計時,不需內通孔105b。此時,可省略圖1(1)(c)~圖1(1)(e)之步驟省略,只要於途中步驟不會汙染預浸材料102的表面,亦可未貼附覆膜101a。 In the first embodiment, for the purpose of electrically connecting the upper and lower wiring elements 131, the structure in which the prepreg 102 is provided with the inner via hole 105b is described. However, the upper and lower wiring elements can be connected only by the built-in circuit element 106. There are 131 electrical connections, and when the circuit is designed, the inner through hole 105b is not required. At this point, the steps of Figure 1 (1) (c) ~ Figure 1 (1) (e) can be omitted Omitted, as long as the step does not contaminate the surface of the prepreg 102, the film 101a may not be attached.

(實施形態2) (Embodiment 2)

圖6(1)((a)~(c))、圖6(2)((d)~(g))、圖6(3)((h)及(i))係用以說明本發明實施形態2之電路元件內藏基板之製造方法 之各步驟的截面構造圖。另,與實施形態1相同之構造係使用相同符號並省略其說明。 6(1)((a)~(c)), Fig. 6(2)((d)~(g)), Fig. 6(3)((h) and (i)) are used to illustrate the present invention Method for manufacturing circuit element built-in substrate according to second embodiment A cross-sectional structural diagram of each step. The same components as those in the first embodiment are denoted by the same reference numerals, and their description will be omitted.

圖6(1)((a)~(c))係顯示內藏電路元件及導電性元件之絕緣基板A之製造步驟,圖6(2)((d)~(g))係顯示形成用以連接電路元件之電極端子與導電性元件、配線元件之電極端子的內通孔之絕緣基板B的製造步驟、圖6(3)((h)及(i))係顯示積層一體化絕緣基板A、絕緣基板B及配線元件之製造步驟。 Fig. 6 (1) ((a) to (c)) show the manufacturing steps of the insulating substrate A in which the circuit element and the conductive element are built, and Fig. 6 (2) ((d) to (g)) are used for display formation. A manufacturing step of connecting the electrode terminal of the circuit element to the insulating substrate B of the conductive element and the inner via hole of the electrode terminal of the wiring element, and FIG. 6 (3) ((h) and (i)) showing the laminated integrated insulating substrate A. Manufacturing steps of the insulating substrate B and the wiring member.

首先,說明圖6(1)((a)~(c))所示之絕緣基板A的製造步驟。 First, the manufacturing steps of the insulating substrate A shown in Fig. 6 (1) ((a) to (c)) will be described.

於絕緣基板A123之製造步驟,即圖6(1)(a)中,電絕緣性基板材料,係例如於積層複數片通用之印刷基板材料即預浸材料後,藉由真空層疊等方法一體化之厚度0.54mm的預浸材料102,藉由鑽孔加工或雷射加工等形成直徑0.37mm之貫通孔103。 In the manufacturing step of the insulating substrate A123, that is, in FIG. 6(1)(a), the electrically insulating substrate material is integrated, for example, by laminating a plurality of sheets of a common printed circuit board material, which is a prepreg material. The prepreg 102 having a thickness of 0.54 mm is formed into a through hole 103 having a diameter of 0.37 mm by drilling, laser processing or the like.

之後,如圖6(1)(b)所示,於貫通孔103之期望位置插入電路元件106。之後,如圖6(1)(c)所示,於貫通孔103之期望位置插入導電性元件107。導電性元件107可使用金屬之棒材。使用於銅之棒材經鍍金或鍍錫等抗氧化的處理者時,導電率低且可得與導電性組成物為良好之連接狀態。 Thereafter, as shown in FIGS. 6(1) and (b), the circuit component 106 is inserted at a desired position of the through hole 103. Thereafter, as shown in FIGS. 6(1) and (c), the conductive element 107 is inserted at a desired position of the through hole 103. As the conductive member 107, a metal bar can be used. When the copper bar is subjected to oxidation resistance such as gold plating or tin plating, the conductivity is low and the conductive composition is in a good connection state.

另,導電性元件107係本發明之具一定形狀的導電性元件之一例。 Further, the conductive element 107 is an example of a conductive element having a shape of the present invention.

本實施形態2中,相對於預浸材料102之貫通孔 103,係於插入電路元件106後再插入導電性元件107,但即使改變插入該等之順序,甚至是隨機地插入均無問題。又,任一貫通孔103均形成相同尺寸,但亦可配合導電性元件107之尺寸,個別地設定貫通孔103之尺寸。 In the second embodiment, the through hole with respect to the prepreg 102 103, the conductive element 107 is inserted after the circuit element 106 is inserted, but even if the order of insertion is changed, there is no problem even if it is randomly inserted. Further, any of the through holes 103 is formed to have the same size. However, the size of the through hole 103 may be individually set in accordance with the size of the conductive element 107.

本實施之形態2絕緣基板A123中,因不需利用導電性組成物形成內通孔,故未於預浸材料102表面貼附覆膜,但亦可貼附覆膜用以保護預浸材料102表面。 In the insulating substrate A123 of the second embodiment, since the inner through hole is not formed by the conductive composition, the film is not attached to the surface of the prepreg 102, but the film may be attached to protect the prepreg 102. surface.

接著,說明圖6(2)((d)~(g))所示之絕緣基板B之製造步驟。絕緣基板B係與實施形態1中使用圖1(2)((g)~(j))說明的製造步驟相同。 Next, a manufacturing procedure of the insulating substrate B shown in Fig. 6 (2) ((d) to (g)) will be described. The insulating substrate B is the same as the manufacturing steps described in the first embodiment using FIG. 1 (2) ((g) to (j)).

圖6(2)(d)係於貼附覆膜步驟中,於厚度0.14mm之預浸材料112的兩主面真空層疊有厚度0.02mm之覆膜111。 6(2) and (d) show a film 111 having a thickness of 0.02 mm laminated on both main surfaces of a prepreg 112 having a thickness of 0.14 mm in the step of attaching a film.

圖6(e)係於通孔形成步驟中於期望形成內通孔115b之位置藉由鑽孔加工,加工直徑0.15mm的通孔113。 Fig. 6(e) is a through hole 113 having a diameter of 0.15 mm which is processed by drilling at a position where the inner through hole 115b is desired to be formed in the through hole forming step.

圖6(f)係填充導電性組成物步驟及加熱處理步驟中,藉由印刷於通孔113填充導電性組成物115a。之後,藉由加熱處理將導電性組成物115a柱化,形成內通孔115b。 In FIG. 6(f), in the step of filling the conductive composition and the heat treatment step, the conductive composition 115a is filled by printing on the through hole 113. Thereafter, the conductive composition 115a is pillared by heat treatment to form an inner via hole 115b.

圖6(g)係覆膜剝離步驟中藉由剝離去除覆膜111,可製造形成有內通孔115b之絕緣基板B122。 In Fig. 6(g), in the film peeling step, the film 111 is removed by peeling, whereby the insulating substrate B122 having the inner through holes 115b formed therein can be manufactured.

然後,說明圖6(3)((h)及(i))所示之積層一體化步驟。 Next, the step of integrating the layers shown in Fig. 6 (3) ((h) and (i)) will be described.

如圖6(3)(h)所示,於絕緣基板A123之兩主面配 置並積層絕緣基板B122,更進行於絕緣基板B122之外側面配置並積層配線元件131。此時,形成於絕緣基板A123之電路元件106的電極端子與導電性元件107、形成於絕緣基板B之內通孔115b、及配線元件131之電極端子132(例如,直徑0.3mm之通孔區域),於積層時進行對準,配置於同一座標上。 As shown in Figure 6 (3) (h), on the two main faces of the insulating substrate A123 The insulating substrate B122 is laminated and placed on the outer surface of the insulating substrate B122 to laminate the wiring elements 131. At this time, the electrode terminal of the circuit element 106 formed on the insulating substrate A123 and the conductive element 107, the through hole 115b formed in the insulating substrate B, and the electrode terminal 132 of the wiring member 131 (for example, a through hole region having a diameter of 0.3 mm) ), aligning at the time of lamination, and arranging on the same coordinate.

之後,如圖6(3)(i)所示,藉由加壓加熱絕緣基板A123、絕緣基板B122及配線元件131之積層體使其一體化,可製造電路元件內藏基板142。 Then, as shown in Fig. 6 (3) and (i), the laminated body of the insulating substrate A123, the insulating substrate B122, and the wiring member 131 is heated and integrated to form the circuit element-embedded substrate 142.

如以上,本實施形態2中,係使用作為金屬棒材之導電性元件107取代利用實施形態1中使用之利用導電性組成物105a的內通孔105b,得到電氣導通的構造。藉此,因不需於絕緣基板A123印刷填充導電性組成物,可大幅地削減步驟。又,使用0Ω之晶片電阻(跳線電阻)作為導電性元件107亦可得到相同之效果。 As described above, in the second embodiment, the conductive element 107 as the metal bar is used instead of the inner through hole 105b using the conductive composition 105a used in the first embodiment, and the structure is electrically connected. Thereby, the step of filling the conductive composition without printing the insulating substrate A123 can be greatly reduced. Further, the same effect can be obtained by using the 0 Ω chip resistor (jumper resistance) as the conductive element 107.

另,各實施形態中使用之預浸材料102及112,加壓加熱後亦未產生厚度變化,但於使用加壓加熱後於厚度方向收縮之絕緣基板材料時,可預先設想收縮量再設定絕緣性基板的材料厚度。 Further, the prepreg materials 102 and 112 used in the respective embodiments do not have a thickness change after the pressure heating. However, when the insulating substrate material which is shrunk in the thickness direction after pressurization heating is used, it is possible to preliminarily assume the shrinkage amount and set the insulation. The material thickness of the substrate.

圖7係使用本實施形態1或2之製造方法製作的電路元件內藏基板的部分截面照片,係內藏有作為電路元件106之尺寸0.6×0.3mm的晶片電阻之電路元件內藏基板的部分放大照片。 Fig. 7 is a partial cross-sectional photograph of a circuit element-embedded substrate produced by the manufacturing method of the first or second embodiment, and is a portion in which a circuit element-embedded substrate having a chip resistance of 0.6 × 0.3 mm as a circuit element 106 is housed. Zoom in on the photo.

如以上說明,依據本發明,用以進行相對於基 板之厚度方向縱向地內藏的電路元件之電極端子、及配線元件之電極端子的電連接之內通孔的形成,係未直接於電路元件之電極端子部形成,藉由另外準備之於薄的絕緣性材料形成內通孔並柱化後積層再一體化,則不需限定絕緣性材料,無論使用任何材料均可防止電路元件之電極端子間短路。 As explained above, in accordance with the present invention, for performing relative to the base The formation of the through-holes in the electrical connection between the electrode terminals of the circuit elements and the electrode terminals of the wiring elements in the thickness direction of the board is not formed directly on the electrode terminal portions of the circuit elements, and is additionally prepared for thin Since the insulating material forms the inner through hole and is pillared and then laminated and integrated, it is not necessary to define an insulating material, and any short circuit between the electrode terminals of the circuit element can be prevented regardless of the use of any material.

因此,藉由本發明,可提供一種即使使用通用材料,即低成本之預浸材料等作為內藏電路元件之絕緣材料,仍可高密度地內藏電路元件,未產生電路元件端子間之短路,並更加提升有電連接信賴性的電路元件內藏基板之製造方法。 Therefore, according to the present invention, it is possible to provide a high-density built-in circuit component even if a general-purpose material, that is, a low-cost prepreg or the like is used as an insulating material for a built-in circuit component, and a short circuit between terminals of the circuit component is not generated. Further, a method of manufacturing a built-in substrate of a circuit component having electrical connection reliability is further improved.

產業上之可利用性 Industrial availability

本發明之電路元件內藏基板之製造方法係使用以熱硬化性環氧樹脂作為主成分的預浸材料等,具有提升電連接信賴性的效果,可作為電路元件內藏基板及電路元件內藏模組等使用。 In the method for producing a circuit element-embedded substrate of the present invention, a prepreg containing a thermosetting epoxy resin as a main component is used, and the effect of improving the reliability of electrical connection is obtained, and the substrate can be built in a circuit element and the circuit element is built in. Modules, etc. are used.

101a,101b,111‧‧‧覆膜 101a, 101b, 111‧‧ ‧ film

102,112‧‧‧預浸材料 102,112‧‧‧Prepreg

103‧‧‧貫通孔 103‧‧‧through holes

104,113‧‧‧通孔 104,113‧‧‧through hole

105a,115a‧‧‧導電性組成物 105a, 115a‧‧‧ Conductive composition

105b,115b‧‧‧內通孔 105b, 115b‧‧‧through hole

106‧‧‧電路元件 106‧‧‧ Circuit components

131‧‧‧配線元件 131‧‧‧Wiring components

132‧‧‧電極端子 132‧‧‧electrode terminal

121,122‧‧‧絕緣基板 121,122‧‧‧Insert substrate

141‧‧‧電路元件內藏基板 141‧‧‧ Built-in substrate for circuit components

Claims (8)

一種電路元件內藏基板之製造方法,具有:電路元件安裝步驟,於第1絕緣基板之材料的厚度方向上形成1或複數個貫通孔,並於全部或一部分之前述貫通孔插入電路元件,使其上下之電極端子朝向前述厚度方向;內通孔形成步驟,於第2絕緣基板之材料的厚度方向上形成1或複數個第1通孔,並於前述第1通孔填充第1導電性組成物,形成用以進行電連接之第1內通孔;及積層加壓加熱步驟,於插入有前述電路元件之前述第1絕緣基板的材料兩面,配置分別形成有前述第1內通孔之前述第2絕緣基板的材料,更於前述第2絕緣基板之材料的外側面分別配置並積層配線元件,進行加壓及加熱,前述積層加壓加熱步驟中,前述電路元件之電極端子與前述第1內通孔配置於分別對應之位置,且前述第1內通孔與形成於前述配線元件之電極端子配置於分別對應之位置。 A method of manufacturing a circuit board built-in substrate, comprising: a circuit element mounting step of forming one or a plurality of through holes in a thickness direction of a material of the first insulating substrate, and inserting the circuit elements into all or a part of the through holes; The upper and lower electrode terminals face the thickness direction; the inner via hole forming step forms one or a plurality of first via holes in the thickness direction of the material of the second insulating substrate, and fills the first conductive layer with the first conductive layer And forming a first inner through hole for electrical connection; and a laminated pressure heating step of arranging the first inner through hole on each of the surfaces of the first insulating substrate on which the circuit element is inserted The material of the second insulating substrate is disposed on the outer surface of the material of the second insulating substrate, and the wiring member is laminated and pressurized, and the electrode terminal of the circuit element and the first electrode are laminated and heated. The inner through holes are disposed at respective positions, and the first inner through holes and the electrode terminals formed on the wiring elements are disposed at respective positions. 如申請專利範圍第1項之電路元件內藏基板之製造方法,其中前述安裝電路元件步驟中,形成1或複數個前述貫通孔後,於全部或一部分之前述貫通孔插入前述電路元件前,於前述第1絕緣基板貼附用以阻塞前述貫通孔之開口的覆膜,並與前述覆膜一同於前述第1絕緣基 板之材料的厚度方向上形成1或複數個第2通孔,於前述第2通孔填充第2導電性組成物,形成用以進行電連接之第2內通孔。 The method of manufacturing a circuit board built-in substrate according to the first aspect of the invention, wherein the step of mounting the circuit element forms one or a plurality of the through holes, and before inserting the circuit elements into all or a part of the through holes, a film for blocking an opening of the through hole is attached to the first insulating substrate, and is coupled to the first insulating base together with the coating film One or a plurality of second through holes are formed in the thickness direction of the material of the plate, and the second conductive holes are filled in the second through holes to form a second inner through hole for electrical connection. 如申請專利範圍第2項之電路元件內藏基板之製造方法,其中前述第1絕緣基板係以環氧樹脂作為主成分之預浸材料。 A method of producing a circuit element-embedded substrate according to the second aspect of the invention, wherein the first insulating substrate is a prepreg containing epoxy resin as a main component. 如申請專利範圍第1項之電路元件內藏基板之製造方法,其中於前述安裝電路元件步驟中,形成1或複數個前述貫通孔後,於前述貫通孔插入前述電路元件,並於前述貫通孔之一部分插入具一定形狀的導電性元件。 The method of manufacturing a circuit board built-in substrate according to the first aspect of the invention, wherein, in the step of mounting the circuit element, one or a plurality of the through holes are formed, and the circuit element is inserted into the through hole and the through hole A part of the conductive element is inserted into the shape. 如申請專利範圍第1項之電路元件內藏基板之製造方法,其中前述第1絕緣基板之材料的厚度係內藏之前述電路元件的長度之-0.2mm以上、+0.08mm以下。 The method of manufacturing a circuit element-embedded substrate according to the first aspect of the invention, wherein the thickness of the material of the first insulating substrate is -0.2 mm or more and +0.08 mm or less in length of the circuit element incorporated in the first insulating substrate. 如申請專利範圍第1項之電路元件內藏基板之製造方法,其中前述第2絕緣基板之材料的厚度係0.03mm以上、0.2mm以下。 The method of manufacturing a circuit element-embedded substrate according to the first aspect of the invention, wherein the material of the second insulating substrate has a thickness of 0.03 mm or more and 0.2 mm or less. 如申請專利範圍第1項之電路元件內藏基板之製造方法,其中前述電路元件之電極端子係矩形,形成於前述第2絕緣基板之材料的前述第1通孔之直徑係0.03mm以上、0.3mm以下,且為前述電路元件之電極端子的對角線尺寸以下。 The method of manufacturing a circuit board built-in substrate according to the first aspect of the invention, wherein the electrode terminal of the circuit element is rectangular, and a diameter of the first through hole formed in the material of the second insulating substrate is 0.03 mm or more and 0.3. It is less than mm and is equal to or less than the diagonal dimension of the electrode terminal of the above-mentioned circuit component. 如申請專利範圍第1項之電路元件內藏基板之製造方法,其中前述配線元件係多層印刷基板。 The method of manufacturing a circuit board built-in substrate according to the first aspect of the invention, wherein the wiring element is a multilayer printed board.
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