TW201413873A - Method for manufacturing semiconductor device and semiconductor device - Google Patents

Method for manufacturing semiconductor device and semiconductor device Download PDF

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Publication number
TW201413873A
TW201413873A TW102134419A TW102134419A TW201413873A TW 201413873 A TW201413873 A TW 201413873A TW 102134419 A TW102134419 A TW 102134419A TW 102134419 A TW102134419 A TW 102134419A TW 201413873 A TW201413873 A TW 201413873A
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Taiwan
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layer
columnar
semiconductor device
film
type diffusion
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TW102134419A
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Chinese (zh)
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Fujio Masuoka
Nozomu Harada
Hiroki Nakamura
Navab Singh
Zhixian Chen
Aashit Ramachandra KAMATH
xin-peng Wang
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Unisantis Elect Singapore Pte
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate

Abstract

A method for manufacturing a semiconductor device is provided, which includes: a first step of forming a planar silicon layer on a silicon substrate, and forming a first columnar silicon layer and a second columnar silicon layer on the planar silicon layer; a second step of forming an oxide film hard mask on the first columnar silicon layer and the second columnar silicon layer, and forming a second oxide film which is thicker than a gate insulating film on the planar silicon layer; and a third step of forming the gate insulating film around the first columnar silicon layer and the second columnar silicon layer, forming a polysilicon layer and a metal layer around the gate insulating film, wherein a thickness of the polysilicon layer is less than half of an interval between the first columnar silicon layer and the second columnar silicon layer, forming a third resist for forming a gate wiring, and conducting an anisotropic etching, thereby forming the gate wiring.

Description

半導體裝置的製造方法以及半導體裝置 Semiconductor device manufacturing method and semiconductor device

本發明是有關於一種半導體裝置的製造方法以及半導體裝置。 The present invention relates to a method of fabricating a semiconductor device and a semiconductor device.

半導體積體電路、尤其是使用了金屬氧化物半導體(Metal Oxide Semiconductor，MOS)電晶體(transistor)的積體電路正趨向高積體化。伴隨著該高積體化，其中所用的MOS電晶體已微細化至奈米(nano)領域。此種MOS電晶體的微細化發展時，存在下述問題，即：漏電流(leak current)的抑制變得困難，從而會因確保必要的電流量的要求而無法輕易減小電路的佔有面積。為了解決此種問題，提出有環繞閘極電晶體(Surrounding Gate Transistor，以下稱作「SGT」)，其採用下述結構，即：相對於基板而沿垂直方向配置有源極(source)、閘極(gate)、汲極(drain)，且閘極電極圍繞柱狀半導體層(例如參照專利文獻1、專利文獻2、專利文獻3)。 A semiconductor integrated circuit, in particular, an integrated circuit using a metal oxide semiconductor (MOS) transistor is tending to be highly integrated. Along with this high integration, the MOS transistor used therein has been miniaturized to the field of nano. When the miniaturization of such a MOS transistor progresses, there is a problem in that leakage of a leakage current becomes difficult, and the area occupied by the circuit cannot be easily reduced by securing a required amount of current. In order to solve such a problem, a Surrounding Gate Transistor (hereinafter referred to as "SGT") has been proposed which has a structure in which a source, a gate are arranged in a vertical direction with respect to a substrate. A gate and a drain are arranged, and the gate electrode surrounds the columnar semiconductor layer (see, for example, Patent Document 1, Patent Document 2, and Patent Document 3).

先前的SGT的製造方法中，形成呈柱狀地形成有氮化膜硬式罩幕(hard mask)的矽(silicon)柱，並形成矽柱下部的擴 散層之後，堆積閘極材料，隨後對閘極材料進行平坦化並進行回蝕刻(etching back)，而於矽柱與氮化膜硬式罩幕的側壁形成絕緣膜側牆(side wall)。隨後，形成用於閘極配線的抗蝕劑圖案(resist pattern)，對閘極材料進行了蝕刻(etching)之後，去除氮化膜硬式罩幕，於矽柱上部形成擴散層(例如參照專利文獻4)。 In the prior SGT manufacturing method, a silicon pillar having a hard mask of a nitride film formed in a columnar shape is formed, and a lower portion of the mast is formed. After the dispersion, the gate material is deposited, and then the gate material is planarized and etched back, and an insulating film side wall is formed on the sidewalls of the pillar and the nitride film hard mask. Subsequently, a resist pattern for the gate wiring is formed, and after the gate material is etched, the nitride film hard mask is removed, and a diffusion layer is formed on the upper portion of the mast (for example, refer to the patent document 4).

此種方法中，當矽柱間隔變窄時，必須將厚的閘極材料堆積於矽柱間，而有時會於矽柱間形成被稱作空隙(void)的孔。當形成空隙時，在回蝕刻後於閘極材料中會出現孔。隨後為了形成絕緣膜側牆而堆積絕緣膜時，絕緣膜會堆積於空隙內。因而，閘極材料加工困難。 In this method, when the column spacing is narrowed, a thick gate material must be deposited between the columns, and a hole called a void is sometimes formed between the columns. When a void is formed, a hole may be formed in the gate material after etch back. Subsequently, when an insulating film is deposited in order to form the insulating film spacer, the insulating film is deposited in the gap. Therefore, the gate material processing is difficult.

因此，提出有一種方法：於矽柱形成後，形成閘極氧化膜，堆積薄的多晶矽後，形成覆蓋矽柱上部並用於形成閘極配線的抗蝕劑，對閘極配線進行蝕刻，隨後，堆積厚的氧化膜，使矽柱上部露出，將矽柱上部的薄的多晶矽去除，並藉由濕式蝕刻(wet etching)來去除厚的氧化膜(例如參照非專利文獻1)。 Therefore, there is proposed a method of forming a gate oxide film after depositing a pillar, and depositing a thin polysilicon, forming a resist covering the upper portion of the pillar and used to form a gate wiring, and etching the gate wiring, and then, A thick oxide film is deposited to expose the upper portion of the column, and the thin polycrystalline silicon on the upper portion of the column is removed, and a thick oxide film is removed by wet etching (see, for example, Non-Patent Document 1).

然而，並未提出用於將金屬使用在閘極電極的方法。而且，必須形成覆蓋矽柱上部並用於形成閘極配線的抗蝕劑，因而，必須覆蓋矽柱上部而非自對準製程(self-aligned process)。 However, a method for using a metal at a gate electrode has not been proposed. Moreover, it is necessary to form a resist covering the upper portion of the mast and for forming the gate wiring, and therefore, it is necessary to cover the upper portion of the mast instead of the self-aligned process.

現有技術文獻 Prior art literature 專利文獻 Patent literature

專利文獻1：日本專利特開平2-71556號公報 Patent Document 1: Japanese Patent Laid-Open No. 2-71556

專利文獻2：日本專利特開平2-188966號公報 Patent Document 2: Japanese Patent Laid-Open No. Hei 2-188966

專利文獻3：日本專利特開平3-145761號公報 Patent Document 3: Japanese Patent Laid-Open No. Hei 3-145761

專利文獻4：日本專利特開2009-182317號公報 Patent Document 4: Japanese Patent Laid-Open Publication No. 2009-182317

非專利文獻 Non-patent literature

非專利文獻1：B.Yang, K.D.Buddharaju, S.H.G.Teo, N.Singh, G.D.Lo以及D.L.Kwong,“垂直矽奈米線結構以及環繞閘極MOSFET (Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFET)”,IEEE電子元件快報(IEEE Electron Device Letters),VOL.29,NO.7,2008年7月，pp791-794. Non-Patent Document 1: B.Yang, KDBuddharaju, SHGTeo, N.Singh, GDLo, and DLKwong, "Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFETs" ), IEEE Electron Device Letters, VOL. 29, No. 7, July 2008, pp 791-794.

因此，本發明的目的在於提供一種使用薄的閘極材、為金屬閘極且為自對準製程的SGT的製造方法與其結果所獲得的SGT的結構。 SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a structure of an SGT obtained by using a thin gate material, a metal gate, and a self-aligned SGT manufacturing method and the result thereof.

本發明的半導體裝置的製造方法的特徵在於包括：第1步驟，於矽基板上形成平面狀矽層，並於上述平面狀矽層上形成第1柱狀矽層與第2柱狀矽層；第2步驟，於上述第1步驟之後，於上述第1柱狀矽層與上述第2柱狀矽層上形成氧化膜硬式罩幕，於上述平面狀矽層上形成比閘極絕緣膜厚的第2氧化膜；以及第3步驟，於上述第2步驟之後，於上述第1柱狀矽層與上述第2柱狀矽層的周圍形成閘極絕緣膜，於上述閘極絕緣膜的周圍使金屬膜以及多晶矽膜成膜，上述多晶矽膜的膜厚比上述第1柱狀矽層與上述第2柱狀矽層之間的間隔的一半薄，且形成用於形成閘極配線的第3抗蝕劑，進行異向性蝕刻，藉此形成上述閘極 配線。 A method of manufacturing a semiconductor device according to the present invention includes the first step of forming a planar germanium layer on a germanium substrate, and forming a first columnar layer and a second columnar layer on the planar layer; In the second step, after the first step, an oxide film hard mask is formed on the first columnar layer and the second columnar layer, and a thickness of the gate insulating layer is formed on the planar layer a second oxide film; and a third step, after the second step, forming a gate insulating film around the first columnar layer and the second columnar layer, and surrounding the gate insulating film The metal film and the polysilicon film are formed, and the film thickness of the polysilicon film is thinner than a half of the interval between the first columnar layer and the second columnar layer, and a third electrode for forming a gate wiring is formed. An etchant, performing an anisotropic etch to form the gate Wiring.

本發明的半導體裝置的製造方法包括：第4步驟，於上述第3步驟之後，堆積第4抗蝕劑，使上述第1柱狀矽層與上述第2柱狀矽層上部側壁的上述多晶矽膜露出，藉由蝕刻來去除露出的上述多晶矽膜，剝離上述第4抗蝕劑，藉由蝕刻來去除上述金屬膜，形成連接於上述閘極配線的第1閘極電極與第2閘極電極。 A method of manufacturing a semiconductor device according to the present invention includes the fourth step of depositing a fourth resist after the third step to form the polycrystalline germanium film on the first columnar layer and the upper side wall of the second columnar layer Exposed, the exposed polysilicon film is removed by etching, the fourth resist is peeled off, and the metal film is removed by etching to form a first gate electrode and a second gate electrode connected to the gate wiring.

而且，本發明的半導體裝置的製造方法中，於上述第1柱狀矽層、上述第2柱狀矽層與上述平面狀矽層上堆積厚的氧化膜，於上述第1柱狀矽層與上述第2柱狀矽層的側壁上堆積薄的氧化膜，藉由等向性蝕刻來去除氧化膜，藉此，於上述第1柱狀矽層與上述第2柱狀矽層上形成氧化膜硬式罩幕，於上述平面狀矽層上形成比閘極絕緣膜厚的第2氧化膜。 Further, in the method of manufacturing a semiconductor device of the present invention, a thick oxide film is deposited on the first columnar layer, the second columnar layer, and the planar layer, and the first columnar layer is A thin oxide film is deposited on the sidewall of the second columnar layer, and an oxide film is removed by isotropic etching, thereby forming an oxide film on the first columnar layer and the second columnar layer. In the hard mask, a second oxide film thicker than the gate insulating film is formed on the planar germanium layer.

而且，本發明的半導體裝置的製造方法更包括：第5步驟，於上述第1柱狀矽層的上部形成第1 n型擴散層，於上述第1柱狀矽層的下部與上述平面狀矽層的上部形成第2 n型擴散層，於上述第2柱狀矽層的上部形成第1 p型擴散層，於上述第2柱狀矽層的下部與上述平面狀矽層的上部形成第2 p型擴散層。 Further, the method of manufacturing a semiconductor device of the present invention further includes a fifth step of forming a first n-type diffusion layer on an upper portion of the first columnar layer, and a lower portion of the first columnar layer and the planar germanium a second n-type diffusion layer is formed on the upper portion of the layer, and a first p-type diffusion layer is formed on the upper portion of the second columnar layer, and a second portion is formed on the lower portion of the second columnar layer and the upper portion of the planar layer. P-type diffusion layer.

本發明的半導體裝置的製造方法更包括：第6步驟，於上述第1 n型擴散層上、上述第2 n型擴散層上、上述第1 p型擴散層、上述第2 p型擴散層上與上述閘極配線上，形成矽化物(silicide)。 Further, the method of manufacturing a semiconductor device according to the present invention includes the sixth step of: forming, on the first n-type diffusion layer, the second n-type diffusion layer, the first p-type diffusion layer, and the second p-type diffusion layer A silicide is formed on the gate wiring.

而且，本發明的半導體裝置的特徵在於包括：平面狀矽層，形成於矽基板上；第1柱狀矽層及第2柱狀矽層，形成於上述平面狀矽層上；閘極絕緣膜，形成於上述第1柱狀矽層的周圍；第1閘極電極，形成於上述閘極絕緣膜的周圍，且包含金屬膜及多晶矽膜的積層結構；閘極絕緣膜，形成於上述第2柱狀矽層的周圍；第2閘極電極，形成於上述閘極絕緣膜的周圍，且包含金屬膜及多晶矽膜的積層結構，且上述多晶矽膜的膜厚比上述第1柱狀矽層與上述第2柱狀矽層之間的間隔的一半薄；閘極配線，連接於上述第1閘極電極及上述第2閘極電極，且上述閘極配線的上表面的高度比上述第1閘極電極及第2閘極電極的上表面的高度低；第2氧化膜，形成於上述閘極配線與上述平面狀矽層之間，且比上述閘極絕緣膜厚；第1 n型擴散層，形成於上述第1柱狀矽層的上部；第2 n型擴散層，形成於上述第1柱狀矽層的下部與上述平面狀矽層的上部；第1 p型擴散層，形成於上述第2柱狀矽層的上部；以及第2 p型擴散層，形成於上述第2柱狀矽層的下部與上述平面狀矽層的上部。 Further, a semiconductor device according to the present invention includes: a planar germanium layer formed on a germanium substrate; a first columnar tantalum layer and a second columnar tantalum layer formed on the planar tantalum layer; and a gate insulating film The first gate electrode is formed around the gate insulating film, and includes a laminated structure of a metal film and a polysilicon film. The gate insulating film is formed in the second layer. a second gate electrode is formed around the gate insulating film and includes a laminated structure of a metal film and a polysilicon film, and the film thickness of the polysilicon film is larger than that of the first columnar layer One half of the interval between the second columnar tantalum layers is thin; the gate wiring is connected to the first gate electrode and the second gate electrode, and the height of the upper surface of the gate wiring is higher than the first gate The height of the upper surface of the pole electrode and the second gate electrode is low; the second oxide film is formed between the gate wiring and the planar germanium layer and is thicker than the gate insulating film; and the first n-type diffusion layer Formed on the upper portion of the first columnar layer; 2 n a diffusion layer formed on a lower portion of the first columnar layer and an upper portion of the planar layer; a first p-type diffusion layer formed on an upper portion of the second columnar layer; and a second p-type diffusion layer The lower portion of the second columnar layer and the upper portion of the planar layer are formed.

本發明的半導體裝置中，上述閘極配線包含上述金屬膜與矽化物的積層結構。 In the semiconductor device of the present invention, the gate wiring includes a laminated structure of the metal film and a germanide.

本發明的半導體裝置中，上述閘極配線的中心線相對於連結上述第1柱狀矽層的中心點與上述第2柱狀矽層的中心點的線而偏移第1規定量。 In the semiconductor device of the present invention, the center line of the gate wiring is shifted by a first predetermined amount with respect to a line connecting a center point of the first columnar layer and a center point of the second columnar layer.

本發明的半導體裝置包括：矽化物，形成於上述第1 n 型擴散層及上述第2 n型擴散層上與上述第1 p型擴散層及上述第2 p型擴散層上。 The semiconductor device of the present invention includes: a telluride formed on the first n The type of diffusion layer and the second n-type diffusion layer are on the first p-type diffusion layer and the second p-type diffusion layer.

根據本發明，可提供使用薄的閘極材、為金屬閘極且為自對準製程的SGT的製造方法與其結果所獲得的SGT的結構。 According to the present invention, it is possible to provide a structure of a SGT obtained by using a thin gate material, a method of manufacturing a SGT which is a metal gate and a self-aligned process, and a result thereof.

藉由第3步驟及第4步驟而實現自對準製程，上述第3步驟是於上述第1步驟之後，於上述第1柱狀矽層與上述第2柱狀矽層上形成氧化膜硬式罩幕，於上述第1柱狀矽層與上述第2柱狀矽層的周圍形成閘極絕緣膜，於上述閘極絕緣膜的周圍使金屬膜以及多晶矽膜成膜，上述多晶矽膜的膜厚比上述第1柱狀矽層與上述第2柱狀矽層之間的間隔的一半薄，且形成用於形成閘極配線的第3抗蝕劑，進行異向性蝕刻，藉此形成上述閘極配線；上述第4步驟是於上述第3步驟之後，堆積第4抗蝕劑，使上述第1柱狀矽層與上述第2柱狀矽層上部側壁的上述多晶矽膜露出，藉由蝕刻來去除露出的上述多晶矽膜，剝離上述第4抗蝕劑，藉由蝕刻來去除上述金屬膜，形成連接於上述閘極配線的第1閘極電極與第2閘極電極。由於為自對準製程，因此高積體化成為可能。 The self-alignment process is performed by the third step and the fourth step, and after the first step, the oxide film hard mask is formed on the first columnar layer and the second columnar layer. a gate insulating film is formed around the first columnar layer and the second columnar layer, and a metal film and a polysilicon film are formed around the gate insulating film, and a film thickness ratio of the polysilicon film is formed. The first columnar tantalum layer and the second columnar tantalum layer are thinner than half, and a third resist for forming a gate wiring is formed, and anisotropic etching is performed to form the gate. In the fourth step, after the third step, the fourth resist is deposited, and the polycrystalline germanium film on the first columnar layer and the upper side wall of the second columnar layer is exposed, and is removed by etching. The exposed polysilicon film is peeled off, the fourth resist is removed, and the metal film is removed by etching to form a first gate electrode and a second gate electrode connected to the gate wiring. Due to the self-aligned process, high integration is possible.

尤其，藉由氧化膜硬式罩幕，於閘極配線形成中保護矽柱上部，藉此實現自對準製程。 In particular, the upper portion of the mast is protected in the formation of the gate wiring by the oxide film hard mask, thereby realizing the self-alignment process.

而且，藉由形成第2氧化膜，從而可降低閘極配線與基板間的電容，上述第2氧化膜是形成於上述閘極配線與上述平面 狀矽層之間，且比上述閘極絕緣膜厚。而且，可使閘極配線與基板間的絕緣更為確實。 Further, by forming the second oxide film, the capacitance between the gate wiring and the substrate can be reduced, and the second oxide film is formed on the gate wiring and the plane Between the ruthenium layers, and thicker than the gate insulating film. Moreover, the insulation between the gate wiring and the substrate can be made more reliable.

而且，上述閘極配線包含上述金屬膜與矽化物的積層結構。由於矽化物與金屬膜為直接接觸，因此可實現低電阻化。 Further, the gate wiring includes a laminated structure of the metal film and the germanide. Since the telluride is in direct contact with the metal film, low resistance can be achieved.

上述閘極配線的中心線相對於連結上述第1柱狀矽層的中心點與上述第2柱狀矽層的中心點的線而偏移第1規定量。容易形成連接第2 n型擴散層與第2 p型擴散層的矽化物。因而，可進行高積體化。 The center line of the gate wiring is shifted by a first predetermined amount with respect to a line connecting a center point of the first columnar layer and a center point of the second columnar layer. It is easy to form a telluride that connects the second n-type diffusion layer and the second p-type diffusion layer. Therefore, high integration can be performed.

101‧‧‧矽基板 101‧‧‧矽 substrate

102、103‧‧‧第1抗蝕劑 102, 103‧‧‧1st resist

104、105‧‧‧第1柱狀矽層 104, 105‧‧‧1st columnar layer

106‧‧‧第2抗蝕劑 106‧‧‧2nd resist

107‧‧‧平面狀矽層 107‧‧‧planar layer

108‧‧‧元件分離膜 108‧‧‧Component separation membrane

109‧‧‧氧化膜 109‧‧‧Oxide film

110‧‧‧第2氧化膜 110‧‧‧2nd oxide film

111、112‧‧‧氧化膜硬式罩幕 111, 112‧‧‧ oxide film hard mask

113、114‧‧‧閘極絕緣膜 113, 114‧‧‧ gate insulating film

115‧‧‧金屬膜 115‧‧‧Metal film

116‧‧‧多晶矽膜 116‧‧‧Polysilicon film

117‧‧‧第3抗蝕劑 117‧‧‧3rd resist

118a、118b‧‧‧閘極電極 118a, 118b‧‧‧ gate electrode

118c‧‧‧閘極配線 118c‧‧‧gate wiring

119‧‧‧第4抗蝕劑 119‧‧‧4th resist

120‧‧‧第6抗蝕劑 120‧‧‧6th resist

121第1 n型擴散層 121 first n-type diffusion layer

122‧‧‧第2 n型擴散層 122‧‧‧2nd n-type diffusion layer

123‧‧‧第7抗蝕劑 123‧‧‧7th resist

124‧‧‧第1 p型擴散層 124‧‧‧1st p-type diffusion layer

125‧‧‧第2 p型擴散層 125‧‧‧2nd p-type diffusion layer

126‧‧‧氮化膜 126‧‧‧ nitride film

127、128、129、130、131、132、133、134‧‧‧矽化物 127, 128, 129, 130, 131, 132, 133, 134‧‧‧ Telluride

137‧‧‧接觸阻擋層 137‧‧‧Contact barrier

138‧‧‧層間絕緣膜 138‧‧‧Interlayer insulating film

139‧‧‧第8抗蝕劑 139‧‧‧8th resist

140、141、143、144‧‧‧接觸孔 140, 141, 143, 144‧‧ contact holes

142‧‧‧第9抗蝕劑 142‧‧‧9th resist

145、146、147、148‧‧‧接觸部 145, 146, 147, 148‧ ‧ contact

149‧‧‧金屬 149‧‧‧Metal

150、151、152、153‧‧‧第10抗蝕劑 150, 151, 152, 153 ‧ ‧ 10th resist

154、155、156、157‧‧‧金屬配線 154, 155, 156, 157‧‧‧ metal wiring

160‧‧‧氧化膜 160‧‧‧Oxide film

161‧‧‧第5抗蝕劑 161‧‧‧5th resist

圖1(A)是本發明的實施方式的半導體裝置的平面圖。圖1(B)是圖1(A)的X-X'線上的剖面圖。圖1(C)是圖1(A)的Y-Y'線上的剖面圖。 Fig. 1(A) is a plan view showing a semiconductor device according to an embodiment of the present invention. Fig. 1(B) is a cross-sectional view taken along line XX' of Fig. 1(A). Fig. 1(C) is a cross-sectional view taken along line YY' of Fig. 1(A).

圖2(A)是表示本實施方式的半導體裝置的製造方法的平面圖。圖2(B)是圖2(A)的X-X'線上的剖面圖。圖2(C)是圖2(A)的Y-Y'線上的剖面圖。 2(A) is a plan view showing a method of manufacturing the semiconductor device of the embodiment. Fig. 2(B) is a cross-sectional view taken along line XX' of Fig. 2(A). Fig. 2(C) is a cross-sectional view taken along line YY' of Fig. 2(A).

圖3(A)是表示本實施方式的半導體裝置的製造方法的平面圖。圖3(B)是圖3(A)的X-X'線上的剖面圖。圖3(C)是圖3(A)的Y-Y'線上的剖面圖。 3(A) is a plan view showing a method of manufacturing the semiconductor device of the embodiment. Fig. 3(B) is a cross-sectional view taken along line XX' of Fig. 3(A). Fig. 3(C) is a cross-sectional view taken along line YY' of Fig. 3(A).

圖4(A)是表示本實施方式的半導體裝置的製造方法的平面圖。圖4(B)是圖4(A)的X-X'線上的剖面圖。圖4(C)是圖4(A)的Y-Y'線上的剖面圖。 4(A) is a plan view showing a method of manufacturing the semiconductor device of the embodiment. Fig. 4(B) is a cross-sectional view taken along line XX' of Fig. 4(A). Fig. 4(C) is a cross-sectional view taken along line YY' of Fig. 4(A).

圖5(A)是表示本實施方式的半導體裝置的製造方法的平面圖。圖5(B)是圖5(A)的X-X'線上的剖面圖。圖5(C)是圖5(A)的Y-Y'線上的剖面圖。 FIG. 5(A) is a plan view showing a method of manufacturing the semiconductor device of the embodiment. Fig. 5(B) is a cross-sectional view taken along line XX' of Fig. 5(A). Fig. 5(C) is a cross-sectional view taken along line YY' of Fig. 5(A).

圖6(A)是表示本實施方式的半導體裝置的製造方法的平面圖。圖6(B)是圖6(A)的X-X'線上的剖面圖。圖6(C)是圖6(A)的Y-Y'線上的剖面圖。 Fig. 6(A) is a plan view showing a method of manufacturing the semiconductor device of the embodiment. Fig. 6(B) is a cross-sectional view taken along line XX' of Fig. 6(A). Fig. 6(C) is a cross-sectional view taken along line YY' of Fig. 6(A).

圖7(A)是表示本實施方式的半導體裝置的製造方法的平面圖。圖7(B)是圖7(A)的X-X'線上的剖面圖。圖7(C)是圖7(A)的Y-Y'線上的剖面圖。 Fig. 7(A) is a plan view showing a method of manufacturing the semiconductor device of the embodiment. Fig. 7(B) is a cross-sectional view taken along line XX' of Fig. 7(A). Fig. 7(C) is a cross-sectional view taken along line YY' of Fig. 7(A).

圖8(A)是表示本實施方式的半導體裝置的製造方法的平面圖。圖8(B)是圖8(A)的X-X'線上的剖面圖。圖8(C)是圖8(A)的Y-Y'線上的剖面圖。 FIG. 8(A) is a plan view showing a method of manufacturing the semiconductor device of the embodiment. Fig. 8(B) is a cross-sectional view taken along line XX' of Fig. 8(A). Fig. 8(C) is a cross-sectional view taken along line YY' of Fig. 8(A).

圖9(A)是表示本實施方式的半導體裝置的製造方法的平面圖。圖9(B)是圖9(A)的X-X'線上的剖面圖。圖9(C)是圖9(A)的Y-Y'線上的剖面圖。 FIG. 9(A) is a plan view showing a method of manufacturing the semiconductor device of the embodiment. Fig. 9(B) is a cross-sectional view taken along line XX' of Fig. 9(A). Fig. 9(C) is a cross-sectional view taken along line YY' of Fig. 9(A).

圖10(A)是表示本實施方式的半導體裝置的製造方法的平面圖。圖10(B)是圖10(A)的X-X'線上的剖面圖。圖10(C)是圖10(A)的Y-Y'線上的剖面圖。 FIG. 10(A) is a plan view showing a method of manufacturing the semiconductor device of the embodiment. Fig. 10(B) is a cross-sectional view taken along line XX' of Fig. 10(A). Fig. 10(C) is a cross-sectional view taken along line YY' of Fig. 10(A).

圖11(A)是表示本實施方式的半導體裝置的製造方法的平面圖。圖11(B)是圖11(A)的X-X'線上的剖面圖。圖11(C)是圖11(A)的Y-Y'線上的剖面圖。 FIG. 11(A) is a plan view showing a method of manufacturing the semiconductor device of the embodiment. Fig. 11(B) is a cross-sectional view taken along line XX' of Fig. 11(A). Fig. 11(C) is a cross-sectional view taken along line YY' of Fig. 11(A).

圖12(A)是表示本實施方式的半導體裝置的製造方法的平 面圖。圖12(B)是圖12(A)的X-X'線上的剖面圖。圖12(C)是圖12(A)的Y-Y'線上的剖面圖。 FIG. 12(A) shows the flat method of manufacturing the semiconductor device of the present embodiment. Surface map. Fig. 12 (B) is a cross-sectional view taken along line XX' of Fig. 12 (A). Fig. 12(C) is a cross-sectional view taken along line YY' of Fig. 12(A).

圖13(A)是表示本實施方式的半導體裝置的製造方法的平面圖。圖13(B)是圖13(A)的X-X'線上的剖面圖。圖13(C)是圖13(A)的Y-Y'線上的剖面圖。 FIG. 13(A) is a plan view showing a method of manufacturing the semiconductor device of the embodiment. Fig. 13 (B) is a cross-sectional view taken along line XX' of Fig. 13 (A). Fig. 13(C) is a cross-sectional view taken along line YY' of Fig. 13(A).

圖14(A)是表示本實施方式的半導體裝置的製造方法的平面圖。圖14(B)是圖14(A)的X-X'線上的剖面圖。圖14(C)是圖14(A)的Y-Y'線上的剖面圖。 FIG. 14(A) is a plan view showing a method of manufacturing the semiconductor device of the embodiment. Fig. 14 (B) is a cross-sectional view taken along line XX' of Fig. 14 (A). Fig. 14 (C) is a cross-sectional view taken along line YY' of Fig. 14 (A).

圖15(A)是表示本實施方式的半導體裝置的製造方法的平面圖。圖15(B)是圖15(A)的X-X'線上的剖面圖。圖15(C)是圖15(A)的Y-Y'線上的剖面圖。 Fig. 15(A) is a plan view showing a method of manufacturing the semiconductor device of the embodiment. Fig. 15 (B) is a cross-sectional view taken along line XX' of Fig. 15 (A). Fig. 15(C) is a cross-sectional view taken along line YY' of Fig. 15(A).

圖16(A)是表示本實施方式的半導體裝置的製造方法的平面圖。圖16(B)是圖16(A)的X-X'線上的剖面圖。圖16(C)是圖16(A)的Y-Y'線上的剖面圖。 Fig. 16(A) is a plan view showing a method of manufacturing the semiconductor device of the embodiment. Fig. 16 (B) is a cross-sectional view taken along line XX' of Fig. 16 (A). Fig. 16 (C) is a cross-sectional view taken along line YY' of Fig. 16 (A).

圖17(A)是表示本實施方式的半導體裝置的製造方法的平面圖。圖17(B)是圖17(A)的X-X'線上的剖面圖。圖17(C)是圖17(A)的Y-Y'線上的剖面圖。 17(A) is a plan view showing a method of manufacturing the semiconductor device of the embodiment. Fig. 17 (B) is a cross-sectional view taken along line XX' of Fig. 17 (A). Fig. 17 (C) is a cross-sectional view taken along line YY' of Fig. 17 (A).

圖18(A)是表示本實施方式的半導體裝置的製造方法的平面圖。圖18(B)是圖18(A)的X-X'線上的剖面圖。圖18(C)是圖18(A)的Y-Y'線上的剖面圖。 FIG. 18(A) is a plan view showing a method of manufacturing the semiconductor device of the embodiment. Fig. 18 (B) is a cross-sectional view taken along line XX' of Fig. 18 (A). Fig. 18(C) is a cross-sectional view taken along line YY' of Fig. 18(A).

圖19(A)是表示本實施方式的半導體裝置的製造方法的平面圖。圖19(B)是圖19(A)的X-X'線上的剖面圖。圖19(C) 是圖19(A)的Y-Y'線上的剖面圖。 19(A) is a plan view showing a method of manufacturing the semiconductor device of the embodiment. Fig. 19 (B) is a cross-sectional view taken along line XX' of Fig. 19 (A). Figure 19 (C) It is a cross-sectional view on the Y-Y' line of Fig. 19(A).

圖20(A)是表示本實施方式的半導體裝置的製造方法的平面圖。圖20(B)是圖20(A)的X-X'線上的剖面圖。圖20(C)是圖20(A)的Y-Y'線上的剖面圖。 FIG. 20(A) is a plan view showing a method of manufacturing the semiconductor device of the embodiment. Fig. 20 (B) is a cross-sectional view taken along line XX' of Fig. 20 (A). Fig. 20(C) is a cross-sectional view taken along line YY' of Fig. 20(A).

圖21(A)是表示本實施方式的半導體裝置的製造方法的平面圖。圖21(B)是圖21(A)的X-X'線上的剖面圖。圖21(C)是圖21(A)的Y-Y'線上的剖面圖。 21(A) is a plan view showing a method of manufacturing the semiconductor device of the embodiment. Fig. 21 (B) is a cross-sectional view taken along line XX' of Fig. 21 (A). Fig. 21 (C) is a cross-sectional view taken along line YY' of Fig. 21 (A).

圖22(A)是表示本實施方式的半導體裝置的製造方法的平面圖。圖22(B)是圖22(A)的X-X'線上的剖面圖。圖22(C)是圖22(A)的Y-Y'線上的剖面圖。 Fig. 22 (A) is a plan view showing a method of manufacturing the semiconductor device of the embodiment. Fig. 22 (B) is a cross-sectional view taken along line XX' of Fig. 22 (A). Fig. 22 (C) is a cross-sectional view taken along line YY' of Fig. 22 (A).

圖23(A)是表示本實施方式的半導體裝置的製造方法的平面圖。圖23(B)是圖23(A)的X-X'線上的剖面圖。圖23(C)是圖23(A)的Y-Y'線上的剖面圖。 Fig. 23(A) is a plan view showing a method of manufacturing the semiconductor device of the embodiment. Fig. 23 (B) is a cross-sectional view taken along line XX' of Fig. 23 (A). Fig. 23(C) is a cross-sectional view taken along line YY' of Fig. 23(A).

圖24(A)是表示本實施方式的半導體裝置的製造方法的平面圖。圖24(B)是圖24(A)的X-X'線上的剖面圖。圖24(C)是圖24(A)的Y-Y'線上的剖面圖。 Fig. 24(A) is a plan view showing a method of manufacturing the semiconductor device of the embodiment. Fig. 24 (B) is a cross-sectional view taken along line XX' of Fig. 24 (A). Fig. 24(C) is a cross-sectional view taken along line YY' of Fig. 24(A).

圖25(A)是表示本實施方式的半導體裝置的製造方法的平面圖。圖25(B)是圖25(A)的X-X'線上的剖面圖。圖25(C)是圖25(A)的Y-Y'線上的剖面圖。 Fig. 25(A) is a plan view showing a method of manufacturing the semiconductor device of the embodiment. Fig. 25(B) is a cross-sectional view taken along line XX' of Fig. 25(A). Fig. 25(C) is a cross-sectional view taken along line YY' of Fig. 25(A).

圖26(A)是表示本實施方式的半導體裝置的製造方法的平面圖。圖26(B)是圖26(A)的X-X'線上的剖面圖。圖26(C)是圖26(A)的Y-Y'線上的剖面圖。 FIG. 26(A) is a plan view showing a method of manufacturing the semiconductor device of the embodiment. Fig. 26 (B) is a cross-sectional view taken along line XX' of Fig. 26 (A). Fig. 26(C) is a cross-sectional view taken along line YY' of Fig. 26(A).

圖27(A)是表示本實施方式的半導體裝置的製造方法的平面圖。圖27(B)是圖27(A)的X-X'線上的剖面圖。圖27(C)是圖27(A)的Y-Y'線上的剖面圖。 FIG. 27(A) is a plan view showing a method of manufacturing the semiconductor device of the embodiment. Fig. 27 (B) is a cross-sectional view taken along line XX' of Fig. 27 (A). Fig. 27(C) is a cross-sectional view taken along line YY' of Fig. 27(A).

圖28(A)是表示本實施方式的半導體裝置的製造方法的平面圖。圖28(B)是圖28(A)的X-X'線上的剖面圖。圖28(C)是圖28(A)的Y-Y'線上的剖面圖。 FIG. 28(A) is a plan view showing a method of manufacturing the semiconductor device of the embodiment. Fig. 28(B) is a cross-sectional view taken along line XX' of Fig. 28(A). Fig. 28(C) is a cross-sectional view taken along line YY' of Fig. 28(A).

圖29(A)是表示本實施方式的半導體裝置的製造方法的平面圖。圖29(B)是29圖(A)的X-X'線上的剖面圖。圖29(C)是圖29(A)的Y-Y'線上的剖面圖。 FIG. 29(A) is a plan view showing a method of manufacturing the semiconductor device of the embodiment. Fig. 29 (B) is a cross-sectional view taken along line XX' of Fig. 29 (A). Fig. 29 (C) is a cross-sectional view taken along line YY' of Fig. 29 (A).

圖30(A)是表示本實施方式的半導體裝置的製造方法的平面圖。圖30(B)是圖30(A)的X-X'線上的剖面圖。圖30(C)是圖30(A)的Y-Y'線上的剖面圖。 FIG. 30(A) is a plan view showing a method of manufacturing the semiconductor device of the embodiment. Fig. 30 (B) is a cross-sectional view taken along line XX' of Fig. 30 (A). Fig. 30 (C) is a cross-sectional view taken along line YY' of Fig. 30 (A).

圖31(A)是表示本實施方式的半導體裝置的製造方法的平面圖。圖31(B)是圖31(A)的X-X'線上的剖面圖。圖31(C)是圖31(A)的Y-Y'線上的剖面圖。 FIG. 31(A) is a plan view showing a method of manufacturing the semiconductor device of the embodiment. Fig. 31 (B) is a cross-sectional view taken along line XX' of Fig. 31 (A). Fig. 31 (C) is a cross-sectional view taken along line YY' of Fig. 31 (A).

圖32(A)是表示本實施方式的半導體裝置的製造方法的平面圖。圖32(B)是圖32(A)的X-X'線上的剖面圖。圖32(C)是圖32(A)的Y-Y'線上的剖面圖。 32(A) is a plan view showing a method of manufacturing the semiconductor device of the embodiment. Fig. 32 (B) is a cross-sectional view taken along line XX' of Fig. 32 (A). Fig. 32(C) is a cross-sectional view taken along line YY' of Fig. 32(A).

圖33(A)是表示本實施方式的半導體裝置的製造方法的平面圖。圖33(B)是圖33(A)的X-X'線上的剖面圖。圖33(C)是圖33(A)的Y-Y'線上的剖面圖。 Fig. 33(A) is a plan view showing a method of manufacturing the semiconductor device of the embodiment. Fig. 33 (B) is a cross-sectional view taken along line XX' of Fig. 33 (A). Fig. 33(C) is a cross-sectional view taken along line YY' of Fig. 33(A).

圖34(A)是表示本實施方式的半導體裝置的製造方法的平 面圖。圖34(B)是圖34(A)的X-X'線上的剖面圖。圖34(C)是圖34(A)的Y-Y'線上的剖面圖。 FIG. 34(A) shows the flattening method of the semiconductor device of the present embodiment. Surface map. Fig. 34 (B) is a cross-sectional view taken along line XX' of Fig. 34 (A). Fig. 34(C) is a cross-sectional view taken along line YY' of Fig. 34(A).

圖35(A)是表示本實施方式的半導體裝置的製造方法的平面圖。圖35(B)是圖35(A)的X-X'線上的剖面圖。圖35(C)是圖35(A)的Y-Y'線上的剖面圖。 35(A) is a plan view showing a method of manufacturing the semiconductor device of the embodiment. Fig. 35 (B) is a cross-sectional view taken along line XX' of Fig. 35 (A). Fig. 35(C) is a cross-sectional view taken along line YY' of Fig. 35(A).

圖36(A)是表示本實施方式的半導體裝置的製造方法的平面圖。圖36(B)是圖36(A)的X-X'線上的剖面圖。圖36(C)是圖36(A)的Y-Y'線上的剖面圖。 36(A) is a plan view showing a method of manufacturing the semiconductor device of the embodiment. Fig. 36 (B) is a cross-sectional view taken along line XX' of Fig. 36 (A). Fig. 36 (C) is a cross-sectional view taken along line YY' of Fig. 36 (A).

圖37(A)是表示本實施方式的半導體裝置的製造方法的平面圖。圖37(B)是圖37(A)的X-X'線上的剖面圖。圖37(C)是圖37(A)的Y-Y'線上的剖面圖。 37(A) is a plan view showing a method of manufacturing the semiconductor device of the embodiment. Fig. 37 (B) is a cross-sectional view taken along line XX' of Fig. 37 (A). Fig. 37(C) is a cross-sectional view taken along line YY' of Fig. 37(A).

圖38(A)是表示本實施方式的半導體裝置的製造方法的平面圖。圖38(B)是圖38(A)的X-X'線上的剖面圖。圖38(C)是圖38(A)的Y-Y'線上的剖面圖。 38(A) is a plan view showing a method of manufacturing the semiconductor device of the embodiment. Fig. 38 (B) is a cross-sectional view taken along line XX' of Fig. 38 (A). Fig. 38 (C) is a cross-sectional view taken along line YY' of Fig. 38 (A).

圖39(A)是表示本實施方式的半導體裝置的製造方法的平面圖。圖39(B)是圖39(A)的X-X'線上的剖面圖。圖39(C)是圖39(A)的Y-Y'線上的剖面圖。 FIG. 39(A) is a plan view showing a method of manufacturing the semiconductor device of the embodiment. Fig. 39 (B) is a cross-sectional view taken along line XX' of Fig. 39 (A). Fig. 39 (C) is a cross-sectional view taken along line YY' of Fig. 39 (A).

圖40(A)是表示本實施方式的半導體裝置的製造方法的平面圖。圖40(B)是圖40(A)的X-X'線上的剖面圖。圖40(C)是圖40(A)的Y-Y'線上的剖面圖。 40(A) is a plan view showing a method of manufacturing the semiconductor device of the embodiment. Fig. 40 (B) is a cross-sectional view taken along line XX' of Fig. 40 (A). Fig. 40 (C) is a cross-sectional view taken along line YY' of Fig. 40 (A).

圖41(A)是表示本實施方式的半導體裝置的製造方法的平面圖。圖41(B)是圖41(A)的X-X'線上的剖面圖。圖41(C) 是圖41(A)的Y-Y'線上的剖面圖。 41(A) is a plan view showing a method of manufacturing the semiconductor device of the embodiment. Fig. 41 (B) is a cross-sectional view taken along line XX' of Fig. 41 (A). Figure 41 (C) It is a sectional view on the Y-Y' line of Fig. 41 (A).

圖42(A)是表示本實施方式的半導體裝置的製造方法的平面圖。圖42(B)是圖42(A)的X-X'線上的剖面圖。圖42(C)是圖42(A)的Y-Y'線上的剖面圖。 42(A) is a plan view showing a method of manufacturing the semiconductor device of the embodiment. Fig. 42 (B) is a cross-sectional view taken along line XX' of Fig. 42 (A). Fig. 42 (C) is a cross-sectional view taken along line YY' of Fig. 42 (A).

圖43(A)是表示本實施方式的半導體裝置的製造方法的平面圖。圖43(B)是圖43(A)的X-X'線上的剖面圖。圖43(C)是圖43(A)的Y-Y'線上的剖面圖。 Fig. 43(A) is a plan view showing a method of manufacturing the semiconductor device of the embodiment. Fig. 43 (B) is a cross-sectional view taken along line XX' of Fig. 43 (A). Fig. 43(C) is a cross-sectional view taken along line YY' of Fig. 43(A).

以下，參照圖2(A)、圖2(B)、圖2(C)~圖43(A)、圖43(B)、圖43(C)，對本發明的實施方式的具有SGT結構的半導體裝置的製造步驟進行說明。 Hereinafter, a semiconductor having an SGT structure according to an embodiment of the present invention will be described with reference to FIGS. 2(A), 2(B), 2(C) to 43(A), 43(B), and 43(C). The manufacturing steps of the device will be described.

以下，表示第1步驟，即：於矽基板上形成平面狀矽層，並於平面狀矽層上形成第1柱狀矽層與第2柱狀矽層。 Hereinafter, a first step of forming a planar tantalum layer on the tantalum substrate and forming a first columnar tantalum layer and a second columnar tantalum layer on the planar tantalum layer will be described.

如圖2(A)、圖2(B)、圖2(C)所示，於矽基板101上形成第1抗蝕劑102、103，該第1抗蝕劑102、103用於形成第1柱狀矽層104與第2柱狀矽層105。 As shown in FIG. 2(A), FIG. 2(B), and FIG. 2(C), the first resists 102 and 103 are formed on the germanium substrate 101, and the first resists 102 and 103 are used to form the first one. The columnar layer 104 and the second columnar layer 105.

如圖3(A)、圖3(B)、圖3(C)所示，對矽基板101進行蝕刻，形成第1柱狀矽層104與第2柱狀矽層105。由於是使用抗蝕劑來形成柱狀矽，因此與使用硬式罩幕的步驟相比，能夠減少步驟數。 As shown in FIG. 3(A), FIG. 3(B), and FIG. 3(C), the ruthenium substrate 101 is etched to form the first columnar layer 104 and the second columnar layer 105. Since the resist is used to form the columnar crucible, the number of steps can be reduced as compared with the step of using the hard mask.

如圖4(A)、圖4(B)、圖4(C)所示，剝離第1抗蝕劑102、103。 As shown in FIG. 4(A), FIG. 4(B), and FIG. 4(C), the first resists 102 and 103 are peeled off.

如圖5(A)、圖5(B)、圖5(C)所示，形成用於形成平面狀矽層107的第2抗蝕劑106。 As shown in FIG. 5(A), FIG. 5(B), and FIG. 5(C), the second resist 106 for forming the planar germanium layer 107 is formed.

如圖6(A)、圖6(B)、圖6(C)所示，對矽基板101進行蝕刻，以形成平面狀矽層107。 As shown in FIG. 6(A), FIG. 6(B), and FIG. 6(C), the ruthenium substrate 101 is etched to form a planar ruthenium layer 107.

如圖7(A)、圖7(B)、圖7(C)所示，剝離第2抗蝕劑106。 As shown in FIG. 7(A), FIG. 7(B), and FIG. 7(C), the second resist 106 is peeled off.

如圖8(A)、圖8(B)、圖8(C)所示，於平面狀矽層107的周圍形成元件分離膜108。 As shown in FIG. 8(A), FIG. 8(B), and FIG. 8(C), the element isolation film 108 is formed around the planar ruthenium layer 107.

藉由以上內容而示出第1步驟，即：於矽基板101上形成平面狀矽層107，並於平面狀矽層107上形成第1柱狀矽層104與第2柱狀矽層105。 The first step is the above, that is, the planar ruthenium layer 107 is formed on the ruthenium substrate 101, and the first columnar ruthenium layer 104 and the second columnar ruthenium layer 105 are formed on the planar ruthenium layer 107.

繼而，表示第2步驟，即：於第1柱狀矽層與第2柱狀矽層上形成氧化膜硬式罩幕，於平面狀矽層上，形成比閘極絕緣膜厚的第2氧化膜。 Then, the second step is to form an oxide film hard mask on the first columnar layer and the second columnar layer, and form a second oxide film thicker than the gate insulating film on the planar layer. .

如圖9(A)、圖9(B)、圖9(C)所示，以覆蓋第1柱狀矽層104、第2柱狀矽層105與平面狀矽層107的方式，堆積氧化膜109。較佳為藉由常壓化學氣相沈積(Chemical Vapor Deposition，CVD)來進行堆積。若使用由常壓CVD造成的堆積，則可於第1柱狀矽層104、第2柱狀矽層105與平面狀矽層107上堆積厚的氧化膜，而於第1柱狀矽層104與第2柱狀矽層105的側壁堆積薄的氧化膜。進而，可使堆積於第1柱狀矽層104與第2柱狀矽層105上的氧化膜厚比堆積於平面狀矽層107上的氧 化膜厚更厚。 As shown in FIG. 9(A), FIG. 9(B), and FIG. 9(C), an oxide film is deposited so as to cover the first columnar layer 104, the second columnar layer 105, and the planar layer 107. 109. Preferably, the deposition is carried out by atmospheric Vapor Deposition (CVD). When the deposition by atmospheric pressure CVD is used, a thick oxide film can be deposited on the first columnar layer 104, the second columnar layer 105, and the planar layer 107, and the first columnar layer 104 can be deposited on the first columnar layer 104. A thin oxide film is deposited on the sidewall of the second columnar layer 105. Further, the oxide film deposited on the first columnar layer 104 and the second columnar layer 105 can be made thicker than the oxygen deposited on the planar layer 107. The film thickness is thicker.

如圖10(A)、圖10(B)、圖10(C)所示，藉由等向性蝕刻來去除氧化膜109，藉此，於第1柱狀矽層104與第2柱狀矽層105上形成氧化膜硬式罩幕111、112，而於平面狀矽層107上形成比閘極絕緣膜厚的第2氧化膜110。 As shown in FIG. 10(A), FIG. 10(B), and FIG. 10(C), the oxide film 109 is removed by isotropic etching, whereby the first columnar layer 104 and the second columnar layer are formed. The oxide film hard masks 111 and 112 are formed on the layer 105, and the second oxide film 110 thicker than the gate insulating film is formed on the planar germanium layer 107.

藉由以上內容，示出了第2步驟，即：於第1柱狀矽層與第2柱狀矽層上形成氧化膜硬式罩幕，而於平面狀矽層上形成比閘極絕緣膜厚的第2氧化膜。 From the above, a second step is shown in which an oxide film hard mask is formed on the first columnar layer and the second columnar layer, and a thicker gate insulating film is formed on the planar layer. The second oxide film.

繼而，表示第3步驟，即：於第1柱狀矽層與第2柱狀矽層的周圍形成閘極絕緣膜，於閘極絕緣膜的周圍使金屬膜以及多晶矽膜成膜，多晶矽膜的膜厚比第1柱狀矽層與第2柱狀矽層之間的間隔的一半薄，且形成用於形成閘極配線的第3抗蝕劑，進行異向性蝕刻，藉此形成閘極配線。 Next, a third step is shown in which a gate insulating film is formed around the first columnar layer and the second columnar layer, and a metal film and a polysilicon film are formed around the gate insulating film, and the polycrystalline film is formed. The film thickness is thinner than a half of the interval between the first columnar layer and the second columnar layer, and a third resist for forming a gate wiring is formed, and anisotropic etching is performed to form a gate. Wiring.

如圖11(A)、圖11(B)、圖11(C)所示，於第1柱狀矽層104與第2柱狀矽層105的周圍，形成閘極絕緣膜113、114，於閘極絕緣膜113、114的周圍，使金屬膜115及多晶矽膜116成膜。因而，可防止於多晶矽膜116中形成空隙。金屬膜115只要是氮化鈦等被用於半導體製程且是設定電晶體的臨限值電壓的金屬即可。閘極絕緣膜113、114只要是氧化膜、氮氧化膜、高介電質膜等被用於半導體製程的膜即可。 As shown in FIG. 11(A), FIG. 11(B), and FIG. 11(C), gate insulating films 113 and 114 are formed around the first columnar layer 104 and the second columnar layer 105. The metal film 115 and the polysilicon film 116 are formed around the gate insulating films 113 and 114. Thus, voids can be prevented from being formed in the polysilicon film 116. The metal film 115 may be a metal that is used in a semiconductor process such as titanium nitride and that sets a threshold voltage of the transistor. The gate insulating films 113 and 114 may be used for a semiconductor process such as an oxide film, an oxynitride film, or a high dielectric film.

如圖12(A)、圖12(B)、圖12(C)所示，形成用於形成閘極配線的第3抗蝕劑117。於本實施例中，是以抗蝕劑高度 比柱狀矽層低的方式而記載。這是因為考慮到：當柱狀矽層的高度高時，柱狀矽層上部的抗蝕劑厚度變薄，或者，柱狀矽層上部的多晶矽會露出。隨著閘極配線寬度變細，柱狀矽層上部的多晶矽變得容易露出。抗蝕劑高度亦可高於柱狀矽層。 As shown in FIG. 12(A), FIG. 12(B), and FIG. 12(C), the third resist 117 for forming a gate wiring is formed. In this embodiment, the resist height is It is described in a manner lower than the columnar layer. This is because it is considered that when the height of the columnar layer is high, the thickness of the resist on the upper portion of the columnar layer is thinned, or the polysilicon in the upper portion of the columnar layer is exposed. As the width of the gate wiring becomes thinner, the polysilicon in the upper portion of the columnar layer is easily exposed. The resist height can also be higher than the columnar layer.

而且，此時，較佳的是，以用於閘極配線的第3抗蝕劑117的中心線相對於連結第1柱狀矽層104的中心點與第2柱狀矽層105的中心點的線而偏移的方式，來形成第3抗蝕劑117。這是為了容易形成連接第2 n型擴散層與第2 p型擴散層的矽化物。 Further, in this case, it is preferable that the center line of the third resist 117 for the gate wiring is opposite to the center point of the first columnar layer 104 and the center point of the second columnar layer 105. The third resist 117 is formed by a line offset manner. This is to facilitate formation of a telluride that connects the second n-type diffusion layer and the second p-type diffusion layer.

如圖13(A)、圖13(B)、圖13(C)所示，對多晶矽膜116與金屬膜115進行蝕刻。形成閘極電極118a、118b、閘極配線118c。此時，即使柱狀矽層上部的抗蝕劑厚度薄，或者柱狀矽層上部的多晶矽露出，亦可藉由氧化膜硬式罩幕111、112來保護柱狀矽層上部。 As shown in FIG. 13(A), FIG. 13(B), and FIG. 13(C), the polysilicon film 116 and the metal film 115 are etched. Gate electrodes 118a and 118b and gate wiring 118c are formed. At this time, even if the thickness of the resist on the upper portion of the columnar layer is thin, or the polysilicon in the upper portion of the columnar layer is exposed, the upper portion of the columnar layer can be protected by the oxide film hard masks 111 and 112.

如圖14(A)、圖14(B)、圖14(C)所示，對第2氧化膜110進行蝕刻。此時，氧化膜硬式罩幕111、112亦受到蝕刻，但由於堆積於第1柱狀矽層104與第2柱狀矽層105上的氧化膜厚比堆積於平面狀矽層107上的氧化膜厚更厚，因此氧化膜硬式罩幕111、112仍有殘留。若無殘留，則在隨後的步驟中，於多晶矽膜去除中，矽柱會受到蝕刻。此時，只要使露出的多晶矽膜的高度增加受到蝕刻的矽柱的高度部份即可。而且，第2氧化膜110亦可於第4步驟之後進行蝕刻。 As shown in FIG. 14(A), FIG. 14(B), and FIG. 14(C), the second oxide film 110 is etched. At this time, the oxide film hard masks 111 and 112 are also etched, but the oxide film deposited on the first columnar layer 104 and the second columnar layer 105 is thicker than the oxide layer deposited on the planar layer 107. Since the film thickness is thicker, the oxide film hard masks 111 and 112 remain. If there is no residue, in the subsequent step, the pillar is etched in the polysilicon film removal. In this case, the height of the exposed polysilicon film may be increased by the height of the etched mast. Further, the second oxide film 110 may be etched after the fourth step.

如圖15(A)、圖15(B)、圖15(C)所示，剝離第3 抗蝕劑117。 As shown in Fig. 15 (A), Fig. 15 (B), and Fig. 15 (C), peeling off the third Resist 117.

藉由以上內容，示出第3步驟，即：於第1柱狀矽層與第2柱狀矽層的周圍形成閘極絕緣膜，於閘極絕緣膜的周圍使金屬膜以及多晶矽膜成膜，多晶矽膜的膜厚比第1柱狀矽層與第2柱狀矽層之間的間隔的一半薄，且形成用於形成閘極配線的第3抗蝕劑，進行異向性蝕刻，藉此形成閘極配線。 According to the above, a third step is shown in which a gate insulating film is formed around the first columnar layer and the second columnar layer, and a metal film and a polycrystalline film are formed around the gate insulating film. The film thickness of the polycrystalline germanium film is thinner than a half of the interval between the first columnar layer and the second columnar layer, and a third resist for forming a gate wiring is formed, and anisotropic etching is performed. This forms a gate wiring.

繼而，表示第4步驟，即：堆積第4抗蝕劑，使第1柱狀矽層與第2柱狀矽層上部側壁的多晶矽膜露出，藉由蝕刻來去除露出的多晶矽膜，剝離第4抗蝕劑，藉由蝕刻來去除金屬膜，從而形成連接於閘極配線的第1閘極電極與第2閘極電極。 Next, the fourth step is shown in which the fourth resist is deposited, and the polycrystalline germanium film on the upper side wall of the first columnar layer and the second columnar layer is exposed, and the exposed polysilicon film is removed by etching, and the fourth layer is peeled off. The resist is removed by etching to form a first gate electrode and a second gate electrode connected to the gate wiring.

如圖16(A)、圖16(B)、圖16(C)所示，堆積第4抗蝕劑119，使第1柱狀矽層104與第2柱狀矽層105上部側壁的多晶矽膜116露出。較佳為使用抗蝕劑回蝕刻。而且，亦可使用旋塗玻璃(spin-on-glass)等的塗佈膜。 As shown in FIG. 16(A), FIG. 16(B), and FIG. 16(C), the fourth resist 119 is deposited to form a polycrystalline germanium film on the upper side walls of the first columnar layer 104 and the second columnar layer 105. 116 exposed. It is preferred to use resist etch back. Further, a coating film of spin-on-glass or the like can also be used.

如圖17(A)、圖17(B)、圖17(C)所示，藉由蝕刻來去除露出的多晶矽膜116。較佳的是等向性乾式蝕刻(dry etching)。 As shown in FIGS. 17(A), 17(B), and 17(C), the exposed polysilicon film 116 is removed by etching. Preferred is an isotropic dry etching.

如圖18(A)、圖18(B)、圖18(C)所示，剝離第4抗蝕劑119。 As shown in FIG. 18(A), FIG. 18(B), and FIG. 18(C), the fourth resist 119 is peeled off.

如圖19(A)、圖19(B)、圖19(C)所示，堆積氧化膜160。 As shown in FIG. 19(A), FIG. 19(B), and FIG. 19(C), the oxide film 160 is deposited.

如圖20(A)、圖20(B)、圖20(C)所示，堆積第5 抗蝕劑161，使第1柱狀矽層104與第2柱狀矽層105上部側壁的氧化膜160露出。較佳為使用抗蝕劑回蝕刻。而且，亦可使用旋塗玻璃(spin-on-glass)等的塗佈膜。 As shown in Fig. 20 (A), Fig. 20 (B), and Fig. 20 (C), the fifth stack is stacked. The resist 161 exposes the oxide film 160 on the upper side wall of the first columnar layer 104 and the second columnar layer 105. It is preferred to use resist etch back. Further, a coating film of spin-on-glass or the like can also be used.

如圖21(A)、圖21(B)、圖21(C)所示，藉由蝕刻來去除露出的氧化膜160。較佳為等向性蝕刻。 As shown in FIG. 21(A), FIG. 21(B), and FIG. 21(C), the exposed oxide film 160 is removed by etching. Isotropic etching is preferred.

如圖22(A)、圖22(B)、圖22(C)所示，剝離第5抗蝕劑161。 As shown in FIG. 22 (A), FIG. 22 (B), and FIG. 22 (C), the fifth resist 161 is peeled off.

如圖23(A)、圖23(B)、圖23(C)所示，藉由蝕刻來去除金屬膜115，形成連接於閘極配線118c的第1閘極電極118b與第2閘極電極118a。因而，成為自對準製程。 As shown in FIG. 23(A), FIG. 23(B), and FIG. 23(C), the metal film 115 is removed by etching, and the first gate electrode 118b and the second gate electrode connected to the gate wiring 118c are formed. 118a. Thus, it becomes a self-aligned process.

如圖24(A)、圖24(B)、圖24(C)所示，藉由蝕刻來去除氧化膜硬式罩幕111、112與氧化膜160。 As shown in FIGS. 24(A), 24(B), and 24(C), the oxide film hard masks 111 and 112 and the oxide film 160 are removed by etching.

藉由以上內容，示出了第4步驟，即：堆積第4抗蝕劑，使第1柱狀矽層與第2柱狀矽層上部側壁的多晶矽膜露出，藉由蝕刻來去除露出的多晶矽膜，剝離第4抗蝕劑，藉由蝕刻來去除金屬膜，從而形成連接於閘極配線的第1閘極電極與第2閘極電極。 According to the above, the fourth step is shown in which the fourth resist is deposited, and the polycrystalline germanium film on the upper side wall of the first columnar layer and the second columnar layer is exposed, and the exposed polysilicon is removed by etching. The film is peeled off from the fourth resist, and the metal film is removed by etching to form a first gate electrode and a second gate electrode connected to the gate wiring.

繼而，表示第5步驟，即：於第1柱狀矽層的上部形成第1 n型擴散層，於第1柱狀矽層的下部與平面狀矽層的上部形成第2 n型擴散層，於第2柱狀矽層的上部形成第1 p型擴散層，於第2柱狀矽層的下部與平面狀矽層的上部形成第2 p型擴散層。 Then, the fifth step is to form a first n-type diffusion layer on the upper portion of the first columnar layer and a second n-type diffusion layer on the lower portion of the first columnar layer and the upper portion of the planar layer. A first p-type diffusion layer is formed on the upper portion of the second columnar layer, and a second p-type diffusion layer is formed on the lower portion of the second columnar layer and the upper portion of the planar layer.

如圖25(A)、圖25(B)、圖25(C)所示，為了形成 第1 n型擴散層與第2 n型擴散層，形成第6抗蝕劑120。亦可於形成第6抗蝕劑120之前，堆積薄的氧化膜。 As shown in Fig. 25 (A), Fig. 25 (B), and Fig. 25 (C), in order to form The first n-type diffusion layer and the second n-type diffusion layer form the sixth resist 120. A thin oxide film may be deposited before the formation of the sixth resist 120.

如圖26(A)、圖26(B)、圖26(C)所示，注入砷，形成第1 n型擴散層121與第2 n型擴散層122。 As shown in FIG. 26(A), FIG. 26(B), and FIG. 26(C), arsenic is implanted to form the first n-type diffusion layer 121 and the second n-type diffusion layer 122.

如圖27(A)、圖27(B)、圖27(C)所示，剝離第6抗蝕劑120。 As shown in FIG. 27(A), FIG. 27(B), and FIG. 27(C), the sixth resist 120 is peeled off.

如圖28(A)、圖28(B)、圖28(C)所示，形成用於形成第1 p型擴散層與第2 p型擴散層的第7抗蝕劑123。 As shown in FIG. 28(A), FIG. 28(B), and FIG. 28(C), the seventh resist 123 for forming the first p-type diffusion layer and the second p-type diffusion layer is formed.

如圖29(A)、圖29(B)、圖29(C)所示，注入硼或氟化硼，形成第1 p型擴散層124與第2 p型擴散層125。 As shown in FIG. 29(A), FIG. 29(B), and FIG. 29(C), boron or boron fluoride is implanted to form the first p-type diffusion layer 124 and the second p-type diffusion layer 125.

如圖30(A)、圖30(B)、圖30(C)所示，剝離第7抗蝕劑123，堆積氮化膜126，並進行熱處理。 As shown in FIG. 30(A), FIG. 30(B), and FIG. 30(C), the seventh resist 123 is peeled off, the nitride film 126 is deposited, and heat treatment is performed.

藉由以上內容，示出了第5步驟，即：於第1柱狀矽層的上部形成第1 n型擴散層，於第1柱狀矽層的下部與平面狀矽層的上部形成第2 n型擴散層，於第2柱狀矽層的上部形成第1 p型擴散層，於第2柱狀矽層的下部與平面狀矽層的上部形成第2 p型擴散層。 According to the above, the fifth step is the step of forming the first n-type diffusion layer on the upper portion of the first columnar layer and forming the second portion on the lower portion of the first columnar layer and the upper portion of the planar layer. In the n-type diffusion layer, a first p-type diffusion layer is formed on the upper portion of the second columnar layer, and a second p-type diffusion layer is formed on the lower portion of the second columnar layer and the upper portion of the planar layer.

繼而，表示第6步驟，即：於第1 n型擴散層上、第2 n型擴散層上、第1 p型擴散層、第2 p型擴散層上與閘極配線上，形成矽化物。 Next, a sixth step is shown in which a telluride is formed on the first n-type diffusion layer, on the second n-type diffusion layer, on the first p-type diffusion layer, and on the second p-type diffusion layer, and on the gate wiring.

如圖31(A)、圖31(B)、圖31(C)所示，對氮化膜126進行蝕刻，形成氮化膜側牆，並堆積金屬，進行熱處理，而去 除未反應的金屬，藉此，於第1 n型擴散層121上、第2 n型擴散層122上、第1 p型擴散層124、第2 p型擴散層125上、閘極配線118c、第1閘極電極118b與第2閘極電極118a上，形成矽化物128、130、132、134、127、131、129、133。氮化膜側牆亦可設為氧化膜與氮化膜的積層結構。 As shown in FIG. 31(A), FIG. 31(B), and FIG. 31(C), the nitride film 126 is etched to form a nitride film spacer, and a metal is deposited and heat-treated. In addition to the unreacted metal, the first n-type diffusion layer 121, the second n-type diffusion layer 122, the first p-type diffusion layer 124, the second p-type diffusion layer 125, the gate wiring 118c, Tellurides 128, 130, 132, 134, 127, 131, 129, and 133 are formed on the first gate electrode 118b and the second gate electrode 118a. The side wall of the nitride film may also be a laminated structure of an oxide film and a nitride film.

第2 n型擴散層122與第2 p型擴散層125將藉由矽化物130而連接。閘極配線118c的中心線相對於連結第1柱狀矽層104的中心點與第2柱狀矽層105的中心點的線而偏移，因此容易形成矽化物130。因而，可進行高積體化。 The second n-type diffusion layer 122 and the second p-type diffusion layer 125 are connected by a telluride 130. The center line of the gate wiring 118c is shifted with respect to the line connecting the center point of the first columnar layer 104 and the center point of the second columnar layer 105, and thus the germanide 130 is easily formed. Therefore, high integration can be performed.

而且，由於多晶矽膜116薄，因此閘極配線118c容易成為金屬膜115與矽化物127的積層結構。由於矽化物127與金屬膜115為直接接觸，因此可實現低電阻化。 Further, since the polysilicon film 116 is thin, the gate wiring 118c easily becomes a laminated structure of the metal film 115 and the germanide 127. Since the telluride 127 is in direct contact with the metal film 115, it is possible to achieve low resistance.

藉由以上內容，示出了第6步驟，即：於第1 n型擴散層上、第2 n型擴散層上、第1 p型擴散層、第2 p型擴散層上與閘極配線上，形成矽化物。 From the above, the sixth step is shown on the first n-type diffusion layer, on the second n-type diffusion layer, on the first p-type diffusion layer, and on the second p-type diffusion layer, and on the gate wiring. Forming a telluride.

如圖32(A)、圖32(B)、圖32(C)所示，使氮化膜等接觸阻擋層(contact stopper)137成膜，形成層間絕緣膜138。 As shown in FIG. 32(A), FIG. 32(B), and FIG. 32(C), a contact stopper 137 such as a nitride film is formed into a film to form an interlayer insulating film 138.

如圖33(A)、圖33(B)、圖33(C)所示，形成用於形成接觸孔的第8抗蝕劑139。 As shown in FIG. 33(A), FIG. 33(B), and FIG. 33(C), the eighth resist 139 for forming a contact hole is formed.

如圖34(A)、圖34(B)、圖34(C)所示，對層間絕緣膜138進行蝕刻，形成接觸孔140、141。 As shown in FIGS. 34(A), 34(B), and 34(C), the interlayer insulating film 138 is etched to form contact holes 140 and 141.

如圖35(A)、圖35(B)、圖35(C)所示，剝離第8 抗蝕劑139。 As shown in Fig. 35 (A), Fig. 35 (B), and Fig. 35 (C), peeling off the eighth Resist 139.

如圖36(A)、圖36(B)、圖36(C)所示，形成用於形成接觸孔的第9抗蝕劑142，對層間絕緣膜138進行蝕刻，形成接觸孔143、144。 As shown in FIGS. 36(A), 36(B), and 36(C), a ninth resist 142 for forming a contact hole is formed, and the interlayer insulating film 138 is etched to form contact holes 143 and 144.

如圖37(A)、圖37(B)、圖37(C)所示，剝離第9抗蝕劑142。 As shown in FIG. 37(A), FIG. 37(B), and FIG. 37(C), the ninth resist 142 is peeled off.

如圖38(A)、圖38(B)、圖38(C)所示，對接觸阻擋層137進行蝕刻，去除接觸孔140、141、接觸孔143、144下的接觸阻擋層137。 As shown in FIGS. 38(A), 38(B), and 38(C), the contact barrier layer 137 is etched to remove the contact barrier layers 137 under the contact holes 140 and 141 and the contact holes 143 and 144.

如圖39(A)、圖39(B)、圖39(C)所示，堆積金屬，形成接觸部145、146、147、148。 As shown in Fig. 39 (A), Fig. 39 (B), and Fig. 39 (C), metal is deposited to form contact portions 145, 146, 147, and 148.

如圖40(A)、圖40(B)、圖40(C)所示，堆積用於金屬配線的金屬149。 As shown in FIG. 40 (A), FIG. 40 (B), and FIG. 40 (C), the metal 149 for metal wiring is deposited.

如圖41(A)、圖41(B)、圖41(C)所示，形成用於形成金屬配線的第10抗蝕劑150、151、152、153。 As shown in FIGS. 41(A), 41(B), and 41(C), the tenth resists 150, 151, 152, and 153 for forming metal wirings are formed.

如圖42(A)、圖42(B)、圖42(C)所示，對金屬149進行蝕刻，形成金屬配線154、155、156、157。 As shown in FIGS. 42(A), 42(B), and 42(C), the metal 149 is etched to form metal wirings 154, 155, 156, and 157.

繼而，如圖43(A)、圖43(B)、圖43(C)所示，剝離第10抗蝕劑150、151、152、153。藉由以上內容，示出使用薄的閘極材、為金屬閘極且為自對準製程的SGT的製造方法。 Then, as shown in FIGS. 43(A), 43(B), and 43(C), the tenth resists 150, 151, 152, and 153 are peeled off. From the above, a method of manufacturing an SGT using a thin gate material, a metal gate, and a self-aligned process is shown.

圖1(A)、圖1(B)、圖1(C)表示藉由上述製造方法而獲得的半導體裝置的結構。如圖1(A)、圖1(B)、圖1(C) 所示，半導體裝置包括：平面狀矽層107，形成於矽基板101上；第1柱狀矽層104及第2柱狀矽層105，形成於上述平面狀矽層107上；閘極絕緣膜113，形成於上述第1柱狀矽層104的周圍；第1閘極電極118b，形成於上述閘極絕緣膜113的周圍，且包含金屬膜115及多晶矽膜116的積層結構；閘極絕緣膜114，形成於上述第2柱狀矽層105的周圍；第2閘極電極118a，形成於上述閘極絕緣膜114的周圍，且包含金屬膜115及多晶矽膜116的積層結構，上述多晶矽膜116的膜厚比上述第1柱狀矽層104與上述第2柱狀矽層105之間的間隔的一半薄；閘極配線118c，連接於上述第1閘極電極及上述第2閘極電極118b、118a，上述閘極配線118c的上表面的高度比上述第1閘極電極及第2閘極電極118b、118a的上表面的高度低；第2氧化膜110，形成於上述閘極配線118c與上述平面狀矽層107之間，且比上述閘極絕緣膜113、114厚；第1 n型擴散層121，形成於上述第1柱狀矽層104的上部；第2 n型擴散層112，形成於上述第1柱狀矽層104的下部與上述平面狀矽層107的上部；第1 p型擴散層124，形成於上述第2柱狀矽層105的上部；以及第2 p型擴散層125，形成於上述第2柱狀矽層105的下部與上述平面狀矽層107的上部。 1(A), 1(B), and 1(C) show the structure of a semiconductor device obtained by the above-described manufacturing method. Figure 1 (A), Figure 1 (B), Figure 1 (C) As shown, the semiconductor device includes a planar germanium layer 107 formed on the germanium substrate 101; a first columnar germanium layer 104 and a second pillarar germanium layer 105 formed on the planar germanium layer 107; a gate insulating film 113 is formed around the first columnar layer 104; the first gate electrode 118b is formed around the gate insulating film 113, and includes a laminated structure of the metal film 115 and the polysilicon film 116; and a gate insulating film 114 is formed around the second columnar layer 105; the second gate electrode 118a is formed around the gate insulating film 114, and includes a laminated structure of the metal film 115 and the polysilicon film 116, and the polysilicon film 116 is formed. The film thickness is thinner than a half of the interval between the first columnar layer 104 and the second columnar layer 105; the gate line 118c is connected to the first gate electrode and the second gate electrode 118b 118a, the height of the upper surface of the gate wiring 118c is lower than the height of the upper surfaces of the first gate electrode and the second gate electrodes 118b and 118a, and the second oxide film 110 is formed on the gate wiring 118c and Between the planar germanium layers 107 and the gate insulating films 113 and 114 The first n-type diffusion layer 121 is formed on the upper portion of the first columnar layer 104, and the second n-type diffusion layer 112 is formed on the lower portion of the first columnar layer 104 and the planar layer 107. An upper portion; a first p-type diffusion layer 124 formed on an upper portion of the second columnar layer 105; and a second p-type diffusion layer 125 formed on a lower portion of the second columnar layer 105 and the planar germanium The upper portion of layer 107.

由於具有形成在上述閘極配線118c與上述平面狀矽層107之間且比上述閘極絕緣膜113、114厚的第2氧化膜110，因此可降低閘極配線與基板間的電容，可使閘極配線與基板間的絕緣變得確實。 Since the second oxide film 110 is formed between the gate wiring 118c and the planar germanium layer 107 and is thicker than the gate insulating films 113 and 114, the capacitance between the gate wiring and the substrate can be reduced. The insulation between the gate wiring and the substrate becomes practical.

而且，上述閘極配線118c包含上述金屬膜115與矽化物127的積層結構。由於矽化物127與金屬膜115為直接接觸，因此可實現低電阻化。 Further, the gate wiring 118c includes a laminated structure of the metal film 115 and the germanide 127. Since the telluride 127 is in direct contact with the metal film 115, it is possible to achieve low resistance.

上述閘極配線118c的中心線相對於連結上述第1柱狀矽層104的中心點與上述第2柱狀矽層105的中心點的線而偏移第1規定量。容易形成連接第2 n型擴散層122與第2 p型擴散層125的矽化物130。因而，可進行高積體化。 The center line of the gate line 118c is shifted by a first predetermined amount with respect to a line connecting the center point of the first columnar layer 104 and the center point of the second columnar layer 105. The telluride 130 connecting the second n-type diffusion layer 122 and the second p-type diffusion layer 125 is easily formed. Therefore, high integration can be performed.

再者，本發明在不脫離其廣義的精神與範圍之條件下，可採用各種實施方式以及變形。而且，上述實施方式是用於說明本發明的一實施例，並不限定本發明的範圍。 Further, various embodiments and modifications may be employed without departing from the spirit and scope of the invention. Further, the above embodiment is for explaining an embodiment of the present invention, and does not limit the scope of the present invention.

例如，於上述實施例中，將p型(包括p+型)與n型(包括n+型)分別設為相反的導電型的半導體裝置的製造方法、以及藉由該方法獲得的半導體裝置當然亦包含於本發明的技術範圍內。 For example, in the above embodiments, a method of manufacturing a semiconductor device in which a p-type (including a p + type) and an n-type (including an n + type) are respectively opposite conductivity types, and a semiconductor device obtained by the method are of course It is also included in the technical scope of the present invention.

101‧‧‧矽基板 101‧‧‧矽 substrate

104、105‧‧‧第1柱狀矽層 104, 105‧‧‧1st columnar layer

107‧‧‧平面狀矽層 107‧‧‧planar layer

108‧‧‧元件分離膜 108‧‧‧Component separation membrane

110‧‧‧第2氧化膜 110‧‧‧2nd oxide film

113、114‧‧‧閘極絕緣膜 113, 114‧‧‧ gate insulating film

115‧‧‧金屬膜 115‧‧‧Metal film

116‧‧‧多晶矽膜 116‧‧‧Polysilicon film

118a、118b‧‧‧閘極電極 118a, 118b‧‧‧ gate electrode

118c‧‧‧閘極配線 118c‧‧‧gate wiring

121‧‧‧第1 n型擴散層 121‧‧‧1 n-type diffusion layer

122‧‧‧第2 n型擴散層 122‧‧‧2nd n-type diffusion layer

124‧‧‧第1 p型擴散層 124‧‧‧1st p-type diffusion layer

125‧‧‧第2 p型擴散層 125‧‧‧2nd p-type diffusion layer

126‧‧‧氮化膜 126‧‧‧ nitride film

127、128、129、131、132、133、134‧‧‧矽化物 127, 128, 129, 131, 132, 133, 134‧‧‧ Telluride

137‧‧‧接觸阻擋層 137‧‧‧Contact barrier

138‧‧‧層間絕緣膜 138‧‧‧Interlayer insulating film

145、146、147、148‧‧‧接觸部 145, 146, 147, 148‧ ‧ contact

154、155、156、157‧‧‧金屬配線 154, 155, 156, 157‧‧‧ metal wiring

Claims (9)

一種半導體裝置的製造方法，上述半導體裝置為相對於矽基板而沿垂直方向呈柱狀地配置有源極、閘極、汲極，且閘極電極包圍柱狀半導體層的結構，上述半導體裝置的製造方法的特徵在於包括：第1步驟，於上述矽基板上形成平面狀矽層，並於上述平面狀矽層上形成第1柱狀矽層與第2柱狀矽層；第2步驟，於上述第1步驟之後，於上述第1柱狀矽層與上述第2柱狀矽層上形成氧化膜硬式罩幕，於上述平面狀矽層上形成比閘極絕緣膜厚的第2氧化膜；以及第3步驟，於上述第2步驟之後，於上述第1柱狀矽層與上述第2柱狀矽層的周圍形成閘極絕緣膜，於上述閘極絕緣膜的周圍使金屬膜以及多晶矽膜成膜，並形成用於形成閘極配線的第3抗蝕劑，進行異向性蝕刻，藉此形成上述閘極配線；此處，上述多晶矽膜的膜厚比上述第1柱狀矽層與上述第2柱狀矽層之間的間隔的一半薄。 In a method of manufacturing a semiconductor device, the semiconductor device is configured such that a source electrode, a gate electrode, and a drain electrode are arranged in a columnar shape in a vertical direction with respect to the germanium substrate, and the gate electrode surrounds the columnar semiconductor layer, and the semiconductor device is The manufacturing method is characterized in that, in the first step, a planar tantalum layer is formed on the tantalum substrate, and a first columnar tantalum layer and a second columnar tantalum layer are formed on the planar tantalum layer; and the second step is After the first step, an oxide film hard mask is formed on the first columnar layer and the second columnar layer, and a second oxide film thicker than the gate insulating film is formed on the planar layer; And a third step, after the second step, forming a gate insulating film around the first columnar layer and the second columnar layer, and forming a metal film and a polysilicon film around the gate insulating film Forming a film and forming a third resist for forming a gate wiring, and performing anisotropic etching to form the gate wiring; wherein the thickness of the polysilicon film is larger than that of the first columnar layer The interval between the second columnar layer Half thin. 如申請專利範圍第1項所述的半導體裝置的製造方法，其包括：第4步驟，於上述第3步驟之後，堆積第4抗蝕劑，使上述第1柱狀矽層與上述第2柱狀矽層上部側壁的上述多晶矽膜露出，藉由蝕刻來去除露出的上述多晶矽膜，剝離上述第4抗蝕劑，藉由蝕刻來去除上述金屬膜，形成連接於上述閘極配線的第1閘極電極與第2閘極電極。 The method of manufacturing a semiconductor device according to claim 1, comprising the fourth step of depositing a fourth resist after the third step to cause the first columnar layer and the second column The polysilicon film on the upper sidewall of the layer is exposed, the exposed polysilicon film is removed by etching, the fourth resist is peeled off, and the metal film is removed by etching to form a first gate connected to the gate wiring. a pole electrode and a second gate electrode. 如申請專利範圍第1項所述的半導體裝置的製造方法，其中於上述第1柱狀矽層、上述第2柱狀矽層與上述平面狀矽層上堆積厚的氧化膜，於上述第1柱狀矽層與上述第2柱狀矽層的側壁上堆積薄的氧化膜，藉由等向性蝕刻來去除氧化膜，藉此，於上述第1柱狀矽層與上述第2柱狀矽層上形成氧化膜硬式罩幕，於上述平面狀矽層上形成比閘極絕緣膜厚的第2氧化膜。 The method of manufacturing a semiconductor device according to the first aspect of the invention, wherein the first columnar layer, the second columnar layer, and the planar layer are deposited with a thick oxide film on the first A thin oxide film is deposited on the columnar ruthenium layer and the sidewall of the second columnar ruthenium layer, and the oxide film is removed by isotropic etching, thereby forming the first columnar ruthenium layer and the second columnar ruthenium An oxide film hard mask is formed on the layer, and a second oxide film thicker than the gate insulating film is formed on the planar germanium layer. 如申請專利範圍第2項所述的半導體裝置的製造方法，更包括：第5步驟，於上述第1柱狀矽層的上部形成第1 n型擴散層，於上述第1柱狀矽層的下部與上述平面狀矽層的上部形成第2 n型擴散層，於上述第2柱狀矽層的上部形成第1 p型擴散層，於上述第2柱狀矽層的下部與上述平面狀矽層的上部形成第2 p型擴散層。 The method of manufacturing a semiconductor device according to claim 2, further comprising the fifth step of forming a first n-type diffusion layer on an upper portion of the first columnar layer and on the first columnar layer a second n-type diffusion layer is formed on an upper portion of the planar ruthenium layer, and a first p-type diffusion layer is formed on an upper portion of the second columnar ruthenium layer, and the planar ruthenium is formed on a lower portion of the second columnar ruthenium layer. A second p-type diffusion layer is formed on the upper portion of the layer. 如申請專利範圍第4項所述的半導體裝置的製造方法，更包括：第6步驟，於上述第1 n型擴散層上、上述第2 n型擴散層上、上述第1 p型擴散層上、上述第2 p型擴散層上與上述閘極配線上，形成矽化物。 The method of manufacturing a semiconductor device according to claim 4, further comprising: a sixth step, on the first n-type diffusion layer, the second n-type diffusion layer, and the first p-type diffusion layer A telluride is formed on the second p-type diffusion layer and on the gate wiring. 一種半導體裝置，為相對於矽基板而沿垂直方向呈柱狀地配置有源極、閘極、汲極，且閘極電極包圍柱狀半導體層的結構，上述半導體裝置的特徵在於包括：平面狀矽層，形成於矽基板上； 第1柱狀矽層及第2柱狀矽層，形成於上述平面狀矽層上；閘極絕緣膜，形成於上述第1柱狀矽層的周圍；第1閘極電極，形成於上述閘極絕緣膜的周圍，且包含金屬膜及多晶矽膜的積層結構；閘極絕緣膜，形成於上述第2柱狀矽層的周圍；第2閘極電極，形成於上述閘極絕緣膜的周圍，且包含金屬膜及多晶矽膜的積層結構，此處，上述多晶矽膜的膜厚比上述第1柱狀矽層與上述第2柱狀矽層之間的間隔的一半薄；閘極配線，連接於上述第1閘極電極及上述第2閘極電極，此處，上述閘極配線的上表面的高度比上述第1閘極電極及第2閘極電極的上表面的高度低；第2氧化膜，形成於上述閘極配線與上述平面狀矽層之間，且比上述閘極絕緣膜厚；第1 n型擴散層，形成於上述第1柱狀矽層的上部；第2 n型擴散層，形成於上述第1柱狀矽層的下部與上述平面狀矽層的上部；第1 p型擴散層，形成於上述第2柱狀矽層的上部；以及第2 p型擴散層，形成於上述第2柱狀矽層的下部與上述平面狀矽層的上部。 A semiconductor device is characterized in that a source electrode, a gate electrode, and a drain electrode are arranged in a columnar shape in a vertical direction with respect to a germanium substrate, and a gate electrode surrounds the columnar semiconductor layer. The semiconductor device is characterized in that it includes a planar shape. a layer of germanium formed on the germanium substrate; The first columnar layer and the second columnar layer are formed on the planar layer; the gate insulating film is formed around the first columnar layer; and the first gate electrode is formed on the gate a layered structure of a metal film and a polysilicon film is included around the pole insulating film; a gate insulating film is formed around the second columnar layer; and a second gate electrode is formed around the gate insulating film. Further, the laminated structure including the metal film and the polycrystalline germanium film is thinner than the half of the interval between the first columnar layer and the second columnar layer; the gate wiring is connected to In the first gate electrode and the second gate electrode, the height of the upper surface of the gate wiring is lower than the height of the upper surfaces of the first gate electrode and the second gate electrode; and the second oxide film And formed between the gate wiring and the planar germanium layer and thicker than the gate insulating film; the first n-type diffusion layer is formed on an upper portion of the first columnar layer; and the second n-type diffusion layer And formed on a lower portion of the first columnar layer and an upper portion of the planar layer; 1 p-type diffusion layer formed in an upper portion of the first columnar silicon layer; and a second P-type diffusion layer formed on a lower portion of the upper portion of the first columnar silicon layer and the planar silicon layer. 如申請專利範圍第6項所述的半導體裝置，其中上述閘極配線包含上述金屬膜與矽化物的積層結構。 The semiconductor device according to claim 6, wherein the gate wiring includes a laminated structure of the metal film and a germanide. 如申請專利範圍第6項所述的半導體裝置，其中 上述閘極配線的中心線相對於連結上述第1柱狀矽層的中心點與上述第2柱狀矽層的中心點的線而偏移第1規定量。 The semiconductor device according to claim 6, wherein The center line of the gate wiring is shifted by a first predetermined amount with respect to a line connecting a center point of the first columnar layer and a center point of the second columnar layer. 如申請專利範圍第8項所述的半導體裝置，其包括：矽化物，形成於上述第1 n型擴散層及上述第2 n型擴散層上與上述第1 p型擴散層及上述第2 p型擴散層上。 The semiconductor device according to claim 8, comprising: a telluride formed on the first n-type diffusion layer and the second n-type diffusion layer, and the first p-type diffusion layer and the second p On the diffusion layer.
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