TW201411639A - Control circuit, memory device and voltage control method thereof - Google Patents

Abstract

A memory device and a voltage control method thereof are provided. The memory device includes a memory cell, a voltage regulator circuit and the control circuit. The control circuit receives a clock signal, and to determine a clock frequency of the clock signal so as to produce a control signal. An operation voltage is converted into an internal supply voltage for supplying the control circuit by the voltage regulator circuit according to the control signal.

Description

Memory device and voltage control method thereof

The present invention relates to a voltage control technique for a memory device, and more particularly to a control circuit, a memory device, and a voltage control method thereof.

In the prior art, the processing speed of the central processing unit chip is often increased by increasing the operating voltage or by overclocking, but the speed of the lifting method is limited to the central processing unit. With the existing memory device, the internal supply voltage of the memory device is kept constant regardless of the applied operating voltage, that is, the processing speed of the memory device is fixed. Therefore, the internal supply voltage cannot be adjusted by the external signal of the memory device, and thus the processing speed of the memory device cannot be improved.

In view of this, the present invention provides a control circuit, a memory device, and a voltage control method thereof, thereby solving the problems described in the prior art.

The invention provides a memory device comprising a memory unit, a voltage regulating circuit and a control circuit. The voltage regulating circuit is coupled to the memory unit. The control circuit is coupled to the memory unit and the voltage regulating circuit. The control circuit receives the clock signal and determines the clock frequency of the clock signal to generate a control signal. Voltage adjustment The node circuit converts the operating voltage into an internal supply voltage according to the control signal for supply to the control circuit.

In an embodiment of the invention, the control circuit determines whether the frequency is down according to the clock frequency, if the control signal causes the voltage adjustment circuit to lower the internal supply voltage when the frequency is down, and if the clock frequency is the up frequency control signal The voltage regulating circuit is raised to the internal supply voltage.

The invention further provides a control circuit in a memory device. The control circuit is coupled to the voltage regulating circuit. The control circuit receives the clock signal and determines the clock frequency of the clock signal to generate a control signal, wherein the voltage regulating circuit converts the operating voltage into an internal supply voltage according to the control signal for supply to the control circuit for use.

The present invention further provides a voltage control method for a memory device, which includes the following steps. Receive clock signal. And converting the operating voltage to a corresponding internal supply voltage for use by the internal circuitry of the memory device based on the clock frequency of the clock signal.

In an embodiment of the invention, the step of converting the operating voltage to the corresponding internal supply voltage for use by the internal circuit of the memory device according to the clock frequency of the clock signal includes: determining according to the clock frequency Whether it is frequency down, if the internal supply voltage is lowered during down-conversion, and the internal supply voltage is raised if the clock frequency is up-converted.

Based on the above, the present invention automatically adjusts the internal supply voltage level by detecting the clock frequency or frequency change of the clock signal. When the external clock frequency is detected to be increased, the internal supply voltage can be automatically increased to achieve better. Performance, but also automatically detects when the external clock frequency is reduced Reduce the internal supply voltage to a potential that can operate normally.

The above described features and advantages of the invention will be apparent from the following description.

1 is a schematic diagram of a memory device 100 in accordance with an embodiment of the present invention. 2 is a schematic diagram of the clock signal SCLK of FIG. 1. Please refer to Figure 1 and Figure 2. The control circuit 130 is coupled to the voltage regulation circuit 120. The control circuit 130 periodically receives a clock signal SCLK and determines the clock frequency FR of the clock signal SLCK to generate a control signal Sref to the voltage regulation circuit 120. The voltage regulation circuit 120 is coupled to the memory unit 110. The voltage regulating circuit 120 can convert the operating voltage VDD into an adjustable internal supply voltage VINT according to the control signal Sref for use by the control circuit 130. Moreover, the voltage regulating circuit 120 can further convert the operating voltage VDD into a plurality of fixed operating voltages, such as 3V, -0.5V, 1.5V, and 0.65V, for supplying the memory unit 110 for use.

In an embodiment, the control circuit 130 can infer the clock frequency FR by determining the number of pulse waves of the clock signal SCLK. Referring to FIG. 2, the control circuit 130 generates a signal DET of a fixed width, and counts the pulse number SP of the clock signal SCLK covered during the period when the signal DET is at a logic high level (preset period t), in order to estimate The clock frequency FR of the pulse signal SCLK. As shown in FIG. 2, the signal DET covers a total of three pulse signals of the clock signal SCLK during the preset period t, and can infer that the frequency FR is 3/t.

Next, the control circuit 130 is based on the clock frequency FR (or the number of pulse waves) SP) sends a control signal Sref to control the operation of the voltage regulating circuit 120 and adjust the internal supply voltage VINT for use by the control circuit 130. Among them, the adjustment method can be referred to a lookup table.

Table 1 is a look-up table that records a table of the relationship between the pulse wave number SP, the clock frequency FR, and the corresponding internal supply voltage for a predetermined period. When the control circuit 130 controls the operation of the voltage regulating circuit 120 in accordance with Table 1, there are the following cases.

(1) If the clock frequency FR is lower than 2/t, the internal supply voltage VINT is lowered to 1.2V.

(2) If the clock frequency FR is between 2/t and 10/t, the internal supply voltage VINT is adjusted to 1.5V.

(3) If the clock frequency FR is between 11/t and 15/t, the internal supply voltage VINT is adjusted to 1.8V.

(4) If the clock frequency FR is higher than 15/t, it means that the internal supply voltage VINT should be adjusted to the highest potential, such as 2V.

Please note that the lookup table used in the present invention is not limited to the contents of Table 1. Any feature value that can indirectly estimate the clock frequency FR, such as the pulse number SP, can be used for searching.

In another embodiment, the control circuit 130 can more determine the change in the clock frequency FR and extend the application of the lookup table. When the pulse signal SCLK is down-converted, the control circuit 130 sends a control signal Sref to cause the voltage regulating circuit 120 to lower the internal supply voltage VINT. When the pulse signal SCLK is up-converted, the control signal Sref from the control circuit 130 adjusts the voltage. The circuit 120 raises the internal supply voltage VINT.

Please refer to FIG. 3. FIG. 3 is a schematic diagram of a memory system 300 in accordance with an embodiment of the present invention. In this embodiment, the control circuit can further turn on or off the components in the memory system according to the clock frequency FR (or frequency change). For example, when the clock frequency FR (or system frequency) is lower than the first frequency or is down-converted, the control circuit 130 provides a disable signal S1 for completely turning off unnecessary components to save power consumption. When the frequency FR is higher than the second frequency or is up-converted, the control circuit 130 provides a consistent energy signal S2 for turning on the components to be operated to improve system performance. Similarly, when the pulse frequency FR is lower than the first frequency or is down-converted, the control circuit 130 can also enable the component to be turned on, and when the pulse frequency FR is higher than the second frequency or is up-converted, the control circuit 130 can also be disabled. Can close the part. For example, the component 200 of the switch is a heat sink. For another example, when the component 140 is an input receiver, the enable signal S2 causes the component 140 to automatically change from an inverter type to a differential type to improve the response speed of the memory device 100 itself to a high frequency. . And the disable signal S1 causes the component 140 Reverse action. It should be noted that the present invention does not limit the location of the components, and components that are internal or external to the memory device 100 can be switched by the control circuit 130.

Please refer to FIG. 4. FIG. 4 is a schematic diagram of a memory device 400 in accordance with an embodiment of the present invention. The control circuit 130 includes a clock receiving and detecting unit 132, a control unit 134, and a storage unit 136. The clock receiving and detecting unit 132 receives the clock signal SCLK and determines the clock frequency FR of the clock signal SCLK. The storage unit 136 stores a set of lookup tables 138 corresponding to the feature values of the internal supply voltage VINT. The control unit 134 is coupled to the clock receiving and detecting unit 132, the storage unit 136, and the voltage regulating circuit 120. The control unit 134 finds the internal supply voltage VINT corresponding to the feature value from the lookup table 138, and issues a control signal Sref to cause the control voltage adjustment circuit 120 to adjust the internal supply voltage VINT to the set value.

Please refer to FIG. 5. FIG. 5 is a control flow chart of a memory system according to an embodiment of the invention. First, it is judged whether or not the memory device is operating (step S501). If not, it means that the memory device stops operating and ends. If so, the clock frequency of the system clock signal is periodically determined (step S503). For example, the clock frequency can be estimated by counting the number of pulse waves corresponding to the clock signal during the preset period. Next, it is determined that the clock frequency is in the set value corresponding to the lookup table (step S505). Then, the internal supply voltage is adjusted to a set value (step S507) to achieve better operational efficiency. Thereafter, the process returns to step S503, and the flow of steps S503 to S507 is performed again.

Going back to step S505, the next step may be followed by step S509 or S513 in addition to step S507. In step S509, determining the clock frequency and The magnitude of the first frequency or the change of the clock frequency, if the clock frequency is lower than the first frequency (or is down-converted), provides a disable signal for turning off unnecessary components (step S511). In step S513, determining a change in the clock frequency and the magnitude of the second frequency or the clock frequency, and if the system frequency is higher than the second frequency (or ascending frequency), providing a consistent energy signal for opening the component to be operated ( Step S515). If the result of step S509 or S513 is NO, the process returns to step S501. It should be noted that the present invention does not limit the conditions of the switch components. For example, step 511 can enable the components to be turned on, and step S515 can also disable the components.

Please refer to FIG. 6. FIG. 6 is a flow chart showing a voltage control method of the memory device according to an embodiment of the present invention.

The memory device receives a clock signal (step S601), and then converts an operating voltage into a corresponding internal supply voltage for use by the internal circuit of the memory device based on the clock frequency of the clock signal (step S603). This step can be used in conjunction with a lookup table to set the value of the internal supply voltage, wherein the lookup table stores a set of eigenvalues corresponding to the internal supply voltage. The characteristic value is the clock frequency or the number of pulse waves of the clock signal. In an embodiment, it is further determined whether the clock signal is up-converted or down-converted. When the pulse signal is up-converted, the internal supply voltage is raised, and when the pulse signal is down-converted, the internal supply voltage is lowered. .

In another exemplary embodiment, the present invention can further turn on or off components in the memory system according to a clock frequency or frequency change of the clock signal, wherein the memory system includes components inside the memory device and other external components. (Step S605), for example, the clock frequency of the current pulse signal is lower than the first When the frequency (or down frequency), a disable signal is provided to turn off the parts that do not need to be operated; and when the clock frequency of the current pulse signal is higher than the second frequency (or is up frequency), a consistent energy signal is provided, Used to open the part to be operated.

In summary, the present invention automatically adjusts the level of the internal supply voltage by detecting the clock frequency or frequency change of the clock signal. When the external clock frequency is detected to increase, the internal supply voltage can be automatically increased to achieve better performance. When the external clock frequency is detected to decrease, the internal supply voltage can be automatically adjusted to operate normally. The potential that does not malfunction. On the other hand, if the external clock frequency is detected to be higher than a certain frequency (or is up-converted), the uniform energy signal can be simultaneously supplied to other components, so that the memory device itself can be improved for the high frequency. The speed of the reaction. Similarly, if the clock frequency is below a certain frequency (or is down-converted), an disable signal can also be provided to completely turn off unnecessary components to save power.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and those skilled in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧ memory device

110‧‧‧ memory unit

120‧‧‧Voltage adjustment circuit

130‧‧‧Control circuit

132‧‧‧clock receiving and detecting unit

134‧‧‧Control unit

136‧‧‧ storage unit

138‧‧‧ lookup table

140, 150, 200‧‧‧ parts

400‧‧‧ memory device

DET‧‧ signal

FR‧‧‧ clock frequency

SCLK‧‧‧ clock signal

SP‧‧‧ pulse wave times

Sref‧‧‧ control signal

S1‧‧‧ disable signal

S2‧‧‧Enable signal

t‧‧‧Predetermined period

VDD‧‧‧ working voltage

VINT‧‧‧ internal supply voltage

S501~S515, S601~S605‧‧‧ steps

1 is a schematic diagram of a memory device in accordance with an embodiment of the present invention.

2 is a schematic diagram of a clock signal in accordance with an embodiment of the present invention.

3 is a schematic diagram of a memory system in accordance with an embodiment of the present invention.

4 is a schematic diagram of a memory device in accordance with an embodiment of the present invention.

FIG. 5 is a flow chart of control of a memory system according to an embodiment of the invention Figure.

6 is a flow chart of a voltage control method of a memory device in accordance with an embodiment of the present invention.

100‧‧‧ memory device

110‧‧‧ memory unit

120‧‧‧Voltage adjustment circuit

130‧‧‧Control circuit

SCLK‧‧‧ clock signal

Sref‧‧‧ control signal

VDD‧‧‧ working voltage

VINT‧‧‧ internal supply voltage

Claims (15)

A memory device includes: a memory unit; a voltage regulating circuit coupled to the memory unit; and a control circuit coupled to the memory unit and the voltage regulating circuit, the control circuit receiving a clock signal and determining the clock A clock frequency of the signal is used to generate a control signal, wherein the voltage regulating circuit converts an operating voltage into an internal supply voltage according to the control signal for supply to the control circuit for use. The memory device of claim 1, wherein the control circuit determines whether the frequency is down-converted according to the clock frequency, and if the control signal causes the voltage regulating circuit to lower the internal supply voltage when the frequency is down, And if the clock frequency is up-converted, the control signal causes the voltage regulating circuit to raise the internal supply voltage. The memory device of claim 1, wherein the control circuit counts a pulse number of the clock signal covered by the clock signal during a predetermined period to estimate the clock of the clock signal. frequency. The memory device of claim 1, wherein when the frequency of the clock signal is lower than a first frequency, the control circuit provides a disable signal for turning off the component that does not need to be operated. The memory device of claim 1, wherein when the frequency of the clock signal is higher than a second frequency, the control circuit provides a consistent energy signal for turning on the component to be operated. The memory device of claim 1, wherein the The control circuit includes: a clock receiving and detecting unit that receives the clock signal and determines the clock frequency of the clock signal; and a storage unit stores a set of lookup tables corresponding to a characteristic value of the internal supply voltage And a control unit coupled to the clock receiving and detecting unit, the storage unit and the voltage regulating circuit, the control unit is configured to find the characteristic value corresponding to the internal supply voltage from the lookup table to issue the control signal, so that The control voltage regulating circuit adjusts the internal supply voltage to a set value. The memory device of claim 6, wherein the characteristic value corresponding to the internal supply voltage is the clock frequency or a pulse number of the clock signal. A voltage control method for a memory device, the method of the voltage control method comprising: receiving a clock signal; and converting an operating voltage to a corresponding internal supply voltage according to a clock frequency of the clock signal for the memory The internal circuit of the body device is used. The voltage control method of the memory device of claim 8, wherein the step of: according to the clock frequency of the clock signal comprises: counting the clock signal covered by the clock signal during a preset period The number of pulses is used to estimate the clock frequency of the clock signal. The voltage control method for a memory device according to claim 8, wherein the operating voltage is converted into a corresponding internal power supply. The step of pressing includes setting a value of the internal supply voltage in conjunction with a lookup table, wherein the lookup table stores a set of eigenvalues corresponding to the internal supply voltage. The voltage control method of the memory device according to claim 8, wherein the characteristic value corresponding to the internal supply voltage is the clock frequency or a pulse number of the clock signal. The voltage control method of the memory device of claim 8, wherein the operating voltage is converted into a corresponding internal supply voltage according to the clock frequency of the clock signal, for the memory device The step of using the internal circuit includes: determining whether the frequency is down-converted according to the clock frequency, if the internal supply voltage is lowered when the frequency is down, and the internal supply voltage is raised if the clock frequency is the up-conversion. The voltage control method of the memory device according to claim 8, wherein the step of the voltage control method further comprises: turning on or off a component in a memory system according to the clock frequency or frequency change, wherein the memory The body system includes components within the memory device and other external components. The voltage control method of the memory device according to claim 13, wherein the step of turning on or off the components in the memory device according to the clock frequency or frequency change comprises: when the clock frequency is lower than one At the first frequency, a disable signal is provided to turn off the components that do not need to be operated. The power of the memory device as described in claim 13 a pressure control method, wherein the step of turning on or off a component in the memory device according to the clock frequency or frequency change comprises: providing a uniform energy signal when the clock frequency is higher than a second frequency, Operating parts.