CN101114190A - Speed regulation system and executing method thereof - Google Patents
Speed regulation system and executing method thereof Download PDFInfo
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- CN101114190A CN101114190A CNA2006101081942A CN200610108194A CN101114190A CN 101114190 A CN101114190 A CN 101114190A CN A2006101081942 A CNA2006101081942 A CN A2006101081942A CN 200610108194 A CN200610108194 A CN 200610108194A CN 101114190 A CN101114190 A CN 101114190A
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Abstract
The invention discloses a speed regulating system and the implementing method, which can provide different adaptive power saving models for different appliances (such as a portable device or an ordinary device) and/or different corner chips. The speed regulating system comprises a reference speed generator used for prestoring a plurality of reference speed values, an operating speed generator used for prestoring a plurality of operating speed values, a comparative cell used for judging whether the operating speed value and the reference speed value satisfy a preset logical operation relation, a voltage controller used for deciding the change of an operating voltage potential according to the comparison result, and a speed detector used for sensing the operating speed value.
Description
[technical field]
The present invention is relevant for a kind of velocity-controlled system and manner of execution thereof, be meant a kind of chip speed regulating system and manner of execution thereof especially, it can determine its exclusive adaptability battery saving mode (Adaptive power saving behavior) according to the different application of chip.
[background technology]
Generally speaking, power consumption is one of usefulness pointer that often is regarded as various electronic systems, as for 3C (being communication class, computer and consumer electronics class) electronic product.Because too high power consumption is unfavorable for heat radiation, fiduciary level and the life of product of electronic system, so for the goods producer, how setting up a kind of electricity saver will be a very important problem.
As everyone knows, how much power consumption often can be by system operation speed (as the operating frequency) change of a power supply supplies management and electronic system (as the IC chip).For an oscillator that maintains this electronic system synchronous operation, one of this oscillator output operating frequency size can be considered power supply (or core) voltage that is proportional to this oscillator of supply.This has brought up a kind of feasible mode, and promptly according to the difference between aforementioned output frequency and the fixed reference frequency, the increase of adjustment property or reduce this output frequency can improve or reduce the current potential of this supply voltage.
As known to, same type electronic system (as the IC chip) can be applied on the different device respectively, even under the system frequency speed of the actual use of those different devices is different situation, still may have the same power mode of using.For example, when a standardization chip application on general device (as a personal computer), and supply following time at a specific supply voltage 1.2V, the system frequency maximum of its execution can reach more than the 500MHz; If other has the standardization chip of a homotype selected when a portable apparatus (as a mobile phone) is gone up, its chip frequency may only need be carried out the stable operation that 400MHz just is enough to keep this portable apparatus, and need not to reach the speed of 500MHz.Cause is that can produce maximum frequency is the frequency of the energy consumption of 500MHz at execution 400MHz, the waste (as all using supply voltage 1.2V) on the energy beyond doubt.In addition, the battery saving mode with cake core adopted that is applied to different device is similar each other.Therefore, traditional electronic system can't provide optionally adaptability battery saving mode for different devices.
Secondly, as known to, under different processing procedure speed, produce the execution usefulness that can influence these chips with cake core significantly.In with a collection of silicon wafer process, the chip of different yield grades can be depicted as each corner (Corner) that is distributed in a statistics chart and go up as presenting a Gaussian distribution (GaussianDistributions).Under different simulated environment tests, most chips one of is concentrated in this chart in the corner (Corner) or simulated environment of Typical-N and Typical-P (TT), has only the minority chip one of can be distributed in this chart in Fast-N and Fast-P (FF) corner or in the corner of a Slow-N and Slow-P (SS).Generally speaking, under same power supplies voltage (1.2V) supply, test the operating speed of the chip of (ascending the throne) via the SS environmental simulation and want slow compared with the operating speed that is distributed in other chip outside the SS corner under the same processing procedure in the SS corner.Operating speed via the chip of FF environmental simulation (ascending the throne in the FF corner) is faster than the speed that is distributed in other chip outside the FF corner under the same processing procedure.These chips under different corners all should meet the yield requirement, and chip structure is all identical.Yet the chip under these different simulated environment still uses identical battery saving mode, rather than uses each adaptive battery saving mode, can form the waste on the energy.
[summary of the invention]
A fundamental purpose of the present invention is to provide a kind of velocity-controlled system, it can determine its adaptive battery saving mode according to the different application (for example being applied in mobile phone, screen, desktop PC or laptop computer) of an electronic system (as an integrated circuit (IC) chip).
Another order of the present invention is to provide a kind of velocity-controlled system, and it can determine its adaptive battery saving mode respectively according to the different processing procedure speed (so-called " varying environment simulation ") of chip.
A further object of the present invention is to provide a kind of velocity-controlled system, and it can be according to different conditions, as a chip temperature difference, a power modes or manual command, for determine its adaptive battery saving mode with cake core.
The present invention also aims to provide the manner of execution of above-mentioned velocity-controlled system.
First embodiment according to the present invention, a velocity-controlled system that is installed on the electronic system (for example, independently chip) can have other different optionally application, for example is applied to a wheeled apparatus and computer installation.This velocity-controlled system comprises a reference velocity generator, is provided with a buffer that can prestore a plurality of reference speed value; One operating speed generator is provided with a buffer that can prestore a plurality of operating speed values; One comparing unit, this comparing unit are used to judge whether aforementioned operation speed and reference velocity satisfy a predetermined logical operation relation, and wherein this logical operation contextual definition is that operating speed should be less than or equal to reference velocity; One voltage controller, based on the comparative result of aforementioned comparing unit, the logic current potential of decision operating voltage is to offer a Speed Sensor; One pressure-sensitive oscillating unit is supplied with the operating voltage of electronic system based on this, produces the operating frequency of making a plurality of operating speed values; And a Speed Sensor, be used for detecting the aforementioned operation velocity amplitude and with its aforementioned operation speed generator that temporarily prestores.
Compared to the first embodiment of the present invention, in a second embodiment, this velocity-controlled system further comprises: a speed proportional arithmetical unit is used to calculate the speed proportional value of this operating speed with respect to reference velocity; And a speed proportional scope generator, a plurality of speed proportional scopes are used to prestore.By this, this comparing unit can judge whether a predetermined logical operation relation is satisfied, and wherein the aforementioned speed proportional value that is defined as of this logical operation relation is therein in the speed proportional scope of presetting.By the operating speed and the supply voltage of this work chip of continuation adjustment (improve or reduce), till this predetermined logical operation relation is satisfied, so can choose a required battery saving mode.
In addition, the present invention also provides a kind of method of regulating the operating speed of electronic system, and it may further comprise the steps:
A plurality of reference speed value prestore;
Detect a plurality of operating speed values respectively, wherein those operating speed value systems produce according to an operating voltage of supplying with electronic system;
Aforementioned a plurality of operating speed value prestores;
Judge whether aforementioned operation velocity amplitude and reference speed value satisfy a predetermined logical operation relation; And
If logical operation relation that should be predetermined is to be satisfied, then keep the logic current potential of this operating voltage constant; Otherwise, adjust the logic current potential of this operating voltage, till this predetermined logical operation relation is satisfied.
[description of drawings]
With reference to a plurality of accompanying drawings, introduce the present invention in detail by means of non-limiting example of the present invention:
Fig. 1 is the structural representation according to the velocity-controlled system of first embodiment of the invention.
Fig. 2 is the structural representation according to the velocity-controlled system of second embodiment of the invention.
Fig. 3 A is the structural representation that is applied to the voltage controller in the velocity-controlled system of the present invention.
Fig. 3 B is the structural representation that is applied to another voltage controller of velocity-controlled system of the present invention.
Fig. 4 is the structural representation that is applied to the reference velocity generator of velocity-controlled system of the present invention.
Fig. 5 A is the process flow diagram of chip operation speed adjusting method according to an embodiment of the invention.
Fig. 5 B is the process flow diagram of operating speed control method according to another embodiment of the present invention.
Fig. 6 is the structural representation according to a Speed Sensor of the present invention.
Fig. 7 is according to a method flow diagram of the present invention, its corresponding operating frequency of detecting from each selected ring oscillator group.
[embodiment]
See also Fig. 1, be the structural representation of a kind of velocity-controlled system 10 of foundation first embodiment of the invention.This velocity-controlled system 10 can be applicable to an electronic system that is structured in standard chips or the integrated circuit (IC) system.This electronic system can be applied on the different devices, for example one movably installs (as mobile phone or PDA) or a computerized device (as personal computer) etc.The main composition of this velocity-controlled system 10 is a reference velocity generator 102, a comparing unit 104, a voltage controller 106, one pressure-sensitive oscillating unit (Voltage-Dependent Oscillators Unit) 108, one Speed Sensor 110 and an operating speed generator 112.
See also Fig. 4, above-mentioned reference speed generator 102 comprises a reference velocity setup unit 1024 and a reference velocity buffer (Reference Speed Register) 1026.This reference velocity setup unit 1024 can receive a voltage setting signal 1000 that is provided with by artificial input or initialization, with default a plurality of different reference speed value in this reference velocity buffer 1026.These a plurality of different reference speed value can be respectively at the chip under different application and/or the different simulated environment (Different Corner) and pre-set.For being applied to same apparatus but the same cake core that belongs to the test of different simulated environments carry out processing procedure driving voltage control (Process-driven Voltage Control) and be example, one represents first reference speed value default of jogging speed, be under particular power source voltage (for example minimum) or reference power supply voltage (for example 1.2V), according to via SS (Slow-N﹠amp; Slow-P) operation frequency value (for example 380MHz) that adopted of the SS-Corner chip of environmental simulation test.One represents second reference speed value of midrange speed default, is under same power supplies voltage, takes (the Typical-N﹠amp via TT; Typical-P) operation frequency value (for example 400MHz) of the TT-Corner chip employing of environmental simulation test.One represents the 3rd reference speed value of prestissimo default, is under same power supplies voltage, via FF (Fast-N﹠amp; Fast-P) operation frequency value (for example 420MHz) of the FF-Corner chip employing of environmental simulation test.
Carrying out a frequency drives Control of Voltage (Frequency-driven Voltage Control) with the same cake core that is applied to different device in addition is example, wherein first reference speed value default of representing jogging speed is to be taken under particular power source voltage (for example minimum) or the reference power supply voltage (for example 1.2V) to be enough to make this cake core to keep an operation frequency value of a portable apparatus stable operation (for example 350MHz).One represents second reference speed value default of fast speed, is to be taken under the same power supplies voltage, to be applied in the general device (for example personal computer) operation frequency value (for example 400MHz) with cake core.
In addition carry out one and be controlled to be example in conjunction with frequency drives and processing procedure driving voltage with the same cake core that is applied to different device and belongs to varying environment simulation test (Different-Corner), wherein one represent first reference speed value of jogging speed default, be to be taken under particular power source voltage (for example minimum) or the reference power supply voltage (for example 1.2V), be applied to portable apparatus and via SS (Slow-N﹠amp; Slow-P) operating frequency (for example 350MHz) of the SS-Corner chip of environmental simulation test.It should be noted that following be under same processing procedure and have identical structure of varying environment simulation test (Different-Corner) that the illustrated electronic system of the present invention adopts with cake core.
Because at SS (Slow-N﹠amp; Slow-P) the SS-Corner chip under the environmental simulation test is slower than the same cake core under other environmental simulation on the operating speed, so the first embodiment of the present invention promptly adopts an operating frequency at SS simulated environment or corner (SS-Corner) chip as a reference speed value, but does not therefore limit the scope of the invention.As everyone knows, between the operating frequency of chip and its operating speed corresponding relation of existence is arranged.Therefore will be understood that, if can consume the higher energy than the chip under the SS simulated environment (SS-Corner) with the chip of other simulated environment of identical operations speed applications in same apparatus.Therefore, the electronic system of illustration of the present invention can reduce the operating speed of this electronic system according to the operating frequency of adopted chip under the SS simulated environment, thereby further reduces the supply voltage of this system, to realize battery saving mode.
In another embodiment, the particular power source voltage (Ivdd) of this adopted chip can determine with following expression formula:
Ivdd＝1.2V-Delta.....................(1)
Wherein magnitude of voltage 1.2V is a normal voltage only for reference, and it supplies adopted chip under this SS simulated environment, but the scope that its value does not limit the present invention to be advocated." Delta " value representative is applied to required one first minimum and in one first device (for example generally using) and is applied to a minimum voltage difference between second required in one second device (for example portable application) minimum.The quantity of the required use ring oscillator of the chip that this minimum voltage difference can determine this SS environmental simulation (RingOscillator) is poor, this normal voltage deducts after the minimum voltage difference, thereby can obtain a final reference speed value, and this final reference velocity amplitude can be lower than the normal speed value of chip under normal voltage (1.2V) of this SS environmental simulation.
See also Fig. 1 and Fig. 4,102 outputs of this reference velocity generator wherein a reference speed value 1020 (for example under particular power source voltage, adopt a operating frequency) once the chip of SS simulated environment test (SS-Corner), this reference speed value 1020 can be sent to this comparing unit 104 via this reference velocity buffer 1026, is used for mating with an operating speed value 1120 of this operating speed generator 112 outputs.
In addition, this operating speed generator 112 has an operating speed buffer (Operating SpeedRegister) and is used for storing a plurality of different operating speed values 1120, and wherein these operating speed values 1120 are to produce according to the friction speed situation that Speed Sensor 110 is detected.Afterwards, 112 outputs of this operating speed generator wherein an optimal operating speed value 1120 give this comparing unit 104.
This comparing unit 104 judges whether this operating speed value 1120 and reference speed value 1020 satisfy a predetermined logical operation relation.In the present embodiment, this predetermined logical operation relation may be defined as this operating speed value 1120 and is less than or equals reference speed value 1020; That is represent the operating speed of this work chip will be synchronized with or lag behind this reference velocity.If predetermined logical operation relation is satisfied, then this comparing unit 104 can keep the logic current potential of a built-in function voltage 1070 constant by this voltage controller 106 of order, and will give this pressure-sensitive oscillating unit 108 from power supply unit 107 output voltages; Otherwise, comparing unit 104 will order this voltage controller 106 according to the difference between aforementioned comparative result and the predetermined logical operation relation, regulates the logic current potential that this power supply unit 107 is sent to a built-in function voltage 1070 of this pressure-sensitive oscillating unit 108.
This pressure-sensitive oscillating unit 108 comprises many group ring oscillator groups (Ring Oscillator Sets), and the Different Logic current potential of the operating voltage 1070 that this unit 108 can produce according to this power supply unit 107, the ring oscillator group of selecting right quantity wherein for use is to simulate the operating frequency that several can be detected by Speed Sensor 110 respectively.This can be reflected an accurate system operation frequency of the required employing of this electrical system (as an IC chip) fully by the operating frequency of emulation, so can hold preferable adaptability battery saving mode.Note that in the ring oscillator group that each group is selected and to comprise one or more ring oscillators.
Based on aforementioned, a closed circuit (Loop) as shown in Figure 1 can be established, and promptly carries out: continue to adjust this supply voltage to upgrade this operating speed value 1120, then relatively this two velocity amplitude 1020 and 1120 to determine supply voltage.This closed circuit can continue to carry out, till this comparing unit 104 judges that this reference speed value 1020 and operating speed value 1120 satisfy this default logical operation relation.Note that no matter this Speed Sensor 110 and pressure-sensitive oscillating unit 108 be independence or be combined into one separately, all belongs to the scope that the present invention advocates.
To be applied to same apparatus but the same cake core that belongs to varying environment simulation test (Different Corner) carry out a processing procedure driving voltage and be controlled to be example, as to be stored in a reference speed value 1020 in this reference velocity generator 102 be to adopt an operating frequency 380MHz via the chip of SS environmental simulation test (SS-Corner) in advance, and it operates in particular power source voltage 1.2V.Yet, when an actual operational speed value 1120 (being provided by operating speed generator 112) via the same cake core of TT environmental simulation test (TT-Corner) is when recording 400MHz, two speed know promptly that through after comparing this 380Mhz than above-mentioned reference velocity amplitude 1020 is high.In this case, voltage controller 106 can be braked and regulate variable resistor 1060a or 1060b to reduce the logic current potential of an operating voltage 1070 that is produced by power supply unit 107.According to the current potential of aforementioned reformed operating voltage 1070, can effectively reduce this operating speed value 1120, and compare again with reference speed value 1020, form a closed circuit by this.In each circulation in this loop, continue to regulate operating voltage 1070, this operating speed value 1120 can be adjusted to 380MHz constantly from 400MHz, till this operating speed is worth this reference speed value 1020 of 1120 convergences.By this, for for the same cake core of different simulated environment tests (Different Corner), can optionally obtain its required adaptability battery saving mode.
Carry out the example that is controlled to be of a frequency drives voltage in addition with a same cake core that is applied to different device.Reference speed value as this chip is to adopt the chip operation frequency of 350MHz in advance, and this frequency values promptly is enough to keep a mobile phone stable operation under specific voltage 1.2V.But when being applied on the personal computer because of same cake core, its operating speed maximum can reach 400MHz, so when this homotype chip application during in mobile phone, its actual operational speed value 1120 may record 390MHz, this is more much higher than above-mentioned reference velocity amplitude (350MHz) 1020.Utilize above-mentioned identical inventive concept, this operating speed value 1120 can be adjusted to 350MHz from 390MHz constantly, till near reference speed value 1020.Because needed reference speed value is variant between the control of frequency drives Control of Voltage and aforesaid processing procedure driving voltage, therefore for be applied in different device for cake core, can optionally obtain another kind of adaptability battery saving mode.
The same cake core that is applied to different device with one again but belongs to the test of different simulated environment is carried out one and is controlled to be example in conjunction with frequency drives voltage and processing procedure driving voltage.Reference speed value as a chip is when adopting the operating frequency of 340MHz in advance, and this frequency values promptly is enough to keep a same cake core via SS environmental simulation test (SS Corner) and stably operates on the mobile phone under supply voltage 1.2V.But because should be when the homotype chip application of SS environmental simulation test be on personal computer, its speed operation maximum can reach 400MHz, so when a homotype chip application that belongs to varying environment simulation test (as TT Corner) in action during phone, its actual operational speed value 1120 may can measure 390MHz, and this is more high than above-mentioned reference velocity amplitude (being 340MHz) 1020.Utilize above-mentioned identical inventive concept, can make this operating speed value 1120 be adjusted to 340MHz constantly, till it is near reference speed value 1020 from 390MHz.By this, be applied in different device but belong to for the same cake core of varying environment emulation for one, can optionally obtain another kind of adaptability battery saving mode.
Please further consult Fig. 2, it shows a kind of velocity-controlled system according to second embodiment of the invention.With the first embodiment difference be in: this velocity-controlled system 20 of second embodiment mainly comprises a reference velocity generator 202, a speed proportional arithmetical unit 204, a speed proportional scope generator 206, a comparing unit 208, a voltage controller 210, one pressure-sensitive oscillating unit 212, a Speed Sensor 214 and an operating speed generator 216.
This reference velocity generator 202 has and is same as configuration shown in Figure 4, and it comprises a reference velocity setup unit 2024 and a reference velocity buffer 2026.Wherein the reference velocity setup unit 2024 of this reference velocity generator 202 receives a voltage setting signal 2000, in advance a plurality of different reference speed value are stored in this reference velocity buffer 2026.Afterwards, be the operating speed value of correspondence from these operating speed generator 216 outputs, reference velocity buffer 2026 is optionally exported a reference speed value 2020 to this speed proportional arithmetical unit 204.
According to the friction speed situation that Speed Sensor 214 detects, the operating speed generator 216 with an operating speed buffer can be used to store a plurality of different operating speed values.These operating speed values be by the ring oscillator group (ROSC) that is selected in this electronic system produce respectively.Then, according to a selected reference speed value 2020 that outputs to this speed proportional device 204, these operating speed generator 216 outputs are an only operating speed value 2160 wherein.
Utilize operating speed value 2160 divided by this reference speed value 2020, this speed proportional arithmetical unit 204 can calculate a velocity ratio 2040 and provide and give this comparing unit 208.One " 110% " velocity ratio for example, the operating speed of promptly representing this work chip are faster than a predetermined reference speed (similarly being an operating frequency that adopts a SS environmental simulation chip).
This speed proportional scope generator 206 can utilize software or hardware (as can be a buffer) to reach, and this speed proportional scope generator 206 can will be preset within it a plurality of friction speed proportional range parameters 2060 only one and offers this comparing unit 208.Should can comprise different ratio states by default speed proportional range parameter 2060, a ratio 85% for example, proportional range 80%～100%, or below 95%, to be applied to the chip of different device and/or different simulated environment respectively.By this, these different ratios will provide different adaptability battery saving modes to give the work chip that each is applied to the different simulated environment on the different device.Default speed proportional scope can being preset based on a controlling signal 2030, with the kind of the needs that respond the environment (high temperature) of some special functions (for example a, battery saving mode) in detecting, user, electronic system or influence the other factors of power consumption.
This comparing unit 208 is used to judge whether a predetermined logical operation relation is satisfied.As this speed proportional value 2040 are " 95% ", promptly are included in the default speed proportional scope 80%～100%, also represent the power supply supply of this work chip to reach an adaptability battery saving mode that is suitable for this system.Afterwards, 210 pairs of this comparing unit 208 these voltage controllers of braking remain unchanged from the logic current potential that power supply unit 211 one of outputs to the pressure-sensitive oscillating unit 212 operating voltage 2110.In another case, if speed proportional value 2040 is " 120% ", promptly exceeded a default speed proportional scope 80%～100%, also represent the power supply supply of this work chip to exceed the needs of this system, and cause the waste of the energy.Afterwards, this comparing unit 208 is just braked 210 pairs of this voltage controllers and is downgraded from the logic current potential that power supply unit 211 outputs to an operating voltage 2110 of pressure-sensitive oscillating unit 212.Aforesaid voltage controller 210 can have and is same as the configuration shown in Fig. 3 A or the 3B.
Be similar to first embodiment shown in Figure 1, the different operating voltage potential that this pressure-sensitive oscillating unit 212 produces according to this power supply unit 211, to export several operating frequencies, these operating frequencies are produced by the ring oscillator group of choosing in this pressure-sensitive oscillating unit 212 (ROSC).Please further consult the 6th figure, this Speed Sensor 214 receives a calibration frequency signal 2138 with standard operation frequency, to detect the operating frequency of the ring oscillator group of selecting in the pressure-sensitive oscillating unit 212 respectively, obtain a plurality of operating speed values 2160 by this to be pre-stored in this operating speed generator 216.Reaching in the lasting circulation of supply voltage correction step via comprising velocity ratio, this predetermined logical operation relation finally can be satisfied.Cause is optionally to provide one to be suitable for battery saving mode at the required situation of change of work chip.
With reference to figure 5A, under a normal manipulation mode, the speed adjusting method of electronic system as shown in Figure 2 (as a work chip) comprises following steps:
Step S500a according to an operating voltage or the core voltage of this work chip, selects and starts the ring oscillator group (ROSC) of an amount of quantity;
Step S502a, based on an operating voltage, the operating frequency that detecting is generated from each selecteed ring oscillator group (ROSC), and with operating frequency as the operating speed value of a correspondence to be pre-stored in the operating speed buffer (as shown in Figure 7).Wherein the step of this detecting operating frequency further comprises: at the periodicity that calculates this operating frequency of a period of time inside counting;
Step S504a, but the default multinomial reference speed value of program is in the reference velocity buffer of this operating speed generator;
Step S506a calculates the speed proportional value of this operating speed corresponding to this reference velocity;
Step S508a, but the default multinomial speed proportional range parameter of program is to this speed proportional scope generator;
Step S510a judges whether a default logical operation relation is satisfied, and wherein the definition of this logical operation relation is meant that aforementioned speed proportional value position is therein among the corresponding speed proportional range parameter; And
Step S516a is satisfied if be somebody's turn to do default logical operation relation, then keeps the logic current potential of this operating voltage constant, and gets back to step S500a, whether change to continue this operating speed value of detecting, thus the power consumption situation of lasting this work chip of monitoring; Otherwise implementation step S512a and step S514a promptly based on an aforementioned velocity ratio difference down, regulate a variable resistor of this voltage controller, thereby the logic current potential that changes this operating voltage just; Get back to step S500a afterwards, promptly utilize, reduce the operating frequency and the power consumption of this work chip constantly, till this predetermined logical operation relation has been satisfied through associating step S500a in the circulation of setting up between the step S516a each time.By this, can obtain an adaptability battery saving mode that is suitable for this work chip.
Please further consult Fig. 5 B, under a power on mode, a method of regulating the operating speed of electronic system may further comprise the steps:
Step S500b, this work chip of initialization is to load some required settings and setting (Configuration);
Step S502b, default complex item reference frequency value to the reference frequency buffer of this reference frequency generator as prestoring;
Step S504b according to supply voltage, selects and starts the ring oscillator group of right quantity;
Step S506b, the corresponding operating frequency that produces of ring oscillator group that detecting is chosen by each group, and it is pre-stored in this operating speed buffer (as shown in Figure 7) as an operating speed value, the step of wherein detecting this operating frequency further comprises, as the periodicity at one section this operating frequency of special time inside counting;
Step S508b, an output more suitable operating speed value wherein from this operating speed buffer;
Step S510b judges whether this operating speed value is lower than the corresponding reference velocity amplitude.In another kind of situation, the position is in a default speed proportional scope with respect to the speed proportional value of reference velocity can to judge an operating speed value, and this judgement can be realized by step 506a shown in Fig. 5 A and step 510a; And
Step S512b if this operating speed value (as 299MHz) is lower than reference speed value (as 300MHz), then keeps the logic current potential of this operating voltage constant and finish this flow process; Otherwise, if this operating speed (as 350MHz) causes energy dissipation faster than reference velocity (as 300MHz), then according to this speed comparative result, execution in step S516b and S514b, change the logic current potential of this operating voltage with a variable resistor of regulation voltage controller, jump to step S504b then, utilize each circuit cycle of setting up from step S504b to step S510b, continue to reduce this operating frequency, till this operating speed value is lower than reference speed value fully.Can obtain required battery saving mode by this.
Step S502b among step S502a among Fig. 5 A or Fig. 5 B has been described in detail the method for each operating frequency of detecting from each selected ring oscillator group of electronic system.The flow process of this method comprises following steps as shown in Figure 7:
Step S710 receives a position signal with standard operation frequency, and wherein this standard operation frequency is provided by an external device or other assembly;
Step S720 in a special time period, utilizes the periodicity of one second this standard operation frequency of rolling counters forward;
Step S712, reception one has the operation clock signal of an operating frequency, and wherein this operating frequency is produced by each selected ring oscillator group;
Step S722, be synchronized with step S720 in second counter begin counting, and in same period, with the periodicity of one first this operating frequency of rolling counters forward;
Step S730, this cycle numerical value of representing operating frequency that prestores is as an operating speed value; And
Step S740 judges whether all selected ring oscillator groups were all detected; If go to the step S508b shown in the step S506a shown in Fig. 5 A or Fig. 5 B; Otherwise, go to the step S504b shown in the step S500a shown in Fig. 5 A or Fig. 5 B.
By being the default various speed proportional scope of above-mentioned different situation, the present invention can be used to regulate the adaptability power supply supply of (improve or a reduce) electronic system, with in response to different states, for example, one when standby battery saving mode, read a small amount of in the process word processing or user with power mode or for supporting the effective power mode of 3D drawing engine.In addition, so-called reference speed value and operating speed value are not limited in frequency values, in some cases, can realize with other parameter, as the operating temperature value of the chip of working and default reference temperature value, or the startup signal of some specific functions, as in a large number/or a small amount of graphic processing data.This speed proportional value range can be a particular range or numerical value (for example, being lower than the temperature value or a temperature percent value of an appointment), and these numerical value can reset according to its demand for the user in the chip manufacturing process or in advance.
In sum; though the present invention discloses as above with some preferred embodiments; but it is not in order to limit the present invention; those of ordinary skill in the art; without departing from the spirit and scope of the present invention; when the present invention being made various modifications and change, protection scope of the present invention is when being as the criterion with the scope that accompanying Claim was defined.
Claims (29)
1. manner of execution is used to regulate the operating speed of an electronic system, it is characterized in that comprising:
(1a) at least one operating speed value of detecting, this operating speed value are according to the operating voltage of this electronic system of supply and corresponding the generation;
(1b) judge whether this an operating speed value and a reference speed value satisfy a predetermined logical operation relation;
If logical operation relation that (1c) should be predetermined is satisfied, then keep the logic current potential of aforementioned operation voltage constant; And
If (1d) predetermined logical operation relation is not satisfied, then regulate the logic current potential of this operating voltage, till this predetermined logical operation relation was satisfied, wherein this reference speed value was by prestoring in advance.
2. the method for claim 1, it is characterized in that: this electronic system is an integrated circuit (IC) chip.
3. the method for claim 1 is characterized in that: detect after the operating speed value, store this operating speed value.
4. the method for claim 1, it is characterized in that: in implementation step (1a) before, further comprise a step, a plurality of different reference speed value promptly prestore in a reference velocity buffer.
5. the method for claim 1 is characterized in that: the step that this detects this operating speed value, be based on aforementioned operation voltage, and make a pressure-sensitive oscillating unit of this electronic system produce an operating frequency.
6. method as claimed in claim 5 is characterized in that: this pressure-sensitive oscillating unit has a plurality of ring oscillator groups, wherein comprises at least one ring oscillator in each oscillator group.
7. method as claimed in claim 6 is characterized in that may further comprise the steps:
(1e) select several ring oscillator groups;
(1f), from this selected ring oscillator group, detect a plurality of operating speed values according to this operating voltage of supplying with electronic system; And
(1g) prestore these a plurality of operating speed values in an operating speed buffer.
8. method as claimed in claim 7 is characterized in that further comprising following steps:
Reception has a position signal of a standard operation frequency;
In one section special time, count out the periodicity of this standard operation frequency;
Reception has an operation clock signal of an operating frequency, and wherein this operating frequency is produced by each ring oscillator group that is selected;
In aforementioned identical special time and be synchronized with the aforesaid standards frequency of operation periodicity begin counting, count out the periodicity of this operating frequency;
The cycle numerical value that makes this representative operating frequency as this operating speed value to be pre-stored in this operating speed buffer;
Judge whether that each ring oscillator group that is selected was all detected; And
If the ring oscillator group that is selected was all detected, then forward step (1b) to; Otherwise forward step (1e) to.
9. the method for claim 1 is characterized in that: this predetermined logical operation relation is defined as this operating speed value and is less than or equal to this reference speed value.
10. the method for claim 1 is characterized in that further may further comprise the steps:
At least one speed proportional scope that prestores is in a speed proportional scope buffer.
11. method as claimed in claim 10 is characterized in that further may further comprise the steps: before this predetermined logical operation relation of decision, produce a speed proportional value with respect to this reference speed value with this operating speed value.
12. method as claimed in claim 11 is characterized in that: it is that the position is in the speed proportional scope that this prestores that this predetermined logical operation relation is defined as this operation ratio value.
13. the method for claim 1 is characterized in that further may further comprise the steps:
If logical operation relation that should be predetermined is not satisfied, then change a variable-resistance resistance value to regulate the logic current potential of this operating voltage, get back to step (1a) then.
14. the method for claim 1 is characterized in that further may further comprise the steps:
If logical operation relation that should be predetermined is satisfied, then keep the logic current potential of this operating voltage constant, get back to step (1a) then.
15. a velocity-controlled system is used to regulate the operating speed of an electronic system, it is characterized in that comprising:
One reference velocity generator, at least one reference speed value is used for prestoring;
One Speed Sensor is used for detecting at least one operating speed value, and wherein this operating speed value is to supply with the operating voltage of this electronic system and corresponding the generation according to one;
One operating speed generator, this operating speed value is used for prestoring;
One comparing unit is used for judging whether aforementioned operation velocity amplitude and reference speed value satisfy a predetermined logical operation relation; And
One voltage controller according to the comparative result in the above-mentioned steps, determines the logic current potential of this operating voltage.
16. system as claimed in claim 15 is characterized in that: this electronic system is an integrated circuit (IC) chip.
17. system as claimed in claim 15 is characterized in that: this reference velocity generator has a reference velocity buffer with a plurality of reference speed value that prestore.
18. system as claimed in claim 15 is characterized in that: this system comprises that further a pressure-sensitive oscillating unit has a plurality of ring oscillator groups, can produce a plurality of operating frequencies respectively according to the logic current potential of this operating voltage.
19. system as claimed in claim 18 is characterized in that: this Speed Sensor is used for detecting a plurality of operation frequency value with as the operating speed value, and it is pre-stored in this operating speed generator.
20. system as claimed in claim 19, it is characterized in that: this Speed Sensor has one first counter and one second counter, this second counter adopts has a position signal of a standard operation frequency to count one section periodicity in the special time, and this first counter adopts by the corresponding operation clock signal with an operating frequency that produces of each selected ring oscillator group of this pressure-sensitive oscillating unit, in same section special time and be synchronized with the counting that begins of second counter, count the periodicity of this operating frequency.
21. system as claimed in claim 20 is characterized in that: this Speed Sensor is used for judging whether the ring oscillator group was detected.
22. system as claimed in claim 19 is characterized in that: this operating speed generator has an operating speed buffer with several operating speed values that prestore.
23. system as claimed in claim 15 is characterized in that: this system further comprises a speed proportional scope generator, and a plurality of friction speed proportional range values are used for prestoring.
24. system as claimed in claim 15, it is characterized in that: this system further comprises a speed proportional arithmetical unit, before judging whether this predetermined logical operation relation is satisfied, calculate the speed proportional value of this operating speed value with respect to this reference speed value.
25. system as claimed in claim 24 is characterized in that: this comparing unit is used to judge whether this logical operation relation is satisfied, and wherein this speed proportional value is in this default speed proportional scope.
26. system as claimed in claim 15 is characterized in that: this comparing unit is used to judge whether this predetermined logical operation relation is satisfied, and wherein this logical operation concerns that being defined as this operating speed value is less than or equal to this reference speed value.
27. system as claimed in claim 15 is characterized in that: if logical operation relation that should be predetermined is to be satisfied, then this voltage controller remains unchanged the logic current potential of the operating voltage of feed speed detector.
28. system as claimed in claim 15, it is characterized in that: if logical operation relation that should be predetermined is not satisfied, then this voltage controller is regulated the logic current potential of the operating voltage of this feed speed detector, till this predetermined logical operation relation is satisfied.
29. system as claimed in claim 15 is characterized in that: this voltage controller comprises a variable resistor, is used to determine the logic current potential of this operating voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006101081942A CN101114190A (en) | 2006-07-25 | 2006-07-25 | Speed regulation system and executing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006101081942A CN101114190A (en) | 2006-07-25 | 2006-07-25 | Speed regulation system and executing method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN101114190A true CN101114190A (en) | 2008-01-30 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2006101081942A Pending CN101114190A (en) | 2006-07-25 | 2006-07-25 | Speed regulation system and executing method thereof |
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| Country | Link |
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| CN (1) | CN101114190A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9269406B2 (en) | 2012-10-24 | 2016-02-23 | Winbond Electronics Corp. | Semiconductor memory device for controlling an internal supply voltage based on a clock frequency of an external clock signal and a look-up table |
| TWI562162B (en) * | 2012-09-14 | 2016-12-11 | Winbond Electronics Corp | Memory device and voltage control method thereof |
-
2006
- 2006-07-25 CN CNA2006101081942A patent/CN101114190A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI562162B (en) * | 2012-09-14 | 2016-12-11 | Winbond Electronics Corp | Memory device and voltage control method thereof |
| US9269406B2 (en) | 2012-10-24 | 2016-02-23 | Winbond Electronics Corp. | Semiconductor memory device for controlling an internal supply voltage based on a clock frequency of an external clock signal and a look-up table |
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