TW201409691A - Semiconductor device and fabricating method thereof - Google Patents

Abstract

A semiconductor device is provided. The device includes a semiconductor substrate and a gate structure thereon. A well region is formed in the semiconductor substrate. Source and drain regions are formed inside and outside of the well region of the semiconductor substrate, respectively. At least one set of first and second heavily doped regions is formed in the well region between the source and drain regions, wherein the first and second heavily doped regions are vertically stacked from bottom to top and have a doping concentration greater than that of the well region. The semiconductor substrate and the first heavily doped region have a first type conductivity and the well region and the second heavily doped region have a second type conductivity. A method for fabricating a semiconductor device is also disclosed.

Description

Semiconductor device and method of manufacturing same

The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a super junction structure and a method of fabricating the same.

Semiconductor devices, such as high voltage components, are generally classified into vertical diffused double-diffused MOSFETs (VDMOSFETs) and horizontally diffused MOSFETs (LDMOSFETs). For the above-mentioned high voltage component withstand voltage, it usually reduces the doping concentration of the deep well region (or called the drift region), increases the depth of the drift region, or increases the isolation structure under the gate (or It is the length of the field oxide.

FIG. 1 is a schematic cross-sectional view showing a conventional N-type horizontal diffusion gold-oxygen half field effect transistor (LDMOSFET). The N-type horizontal diffusion gold-oxygen field effect transistor 10 includes a P-type semiconductor substrate 100 and a P-type epitaxial layer 102 thereon. The P-type epitaxial layer 102 has a gate structure 116 and a field oxide layer 114 thereon. Furthermore, the P-type epitaxial layer 102 on both sides of the gate structure 116 is a P-type body region 106 and an N-type drift region 104, wherein the drift region 104 further extends to the underlying P-type semiconductor substrate 100. Inside. The base region 106 has a P-type contact region 108 and an adjacent N-type contact region 110 (both referred to as a source region), and the drift region 104 has an N-type contact region 112 (also referred to as a drain region). Furthermore, a source electrode 117 is electrically connected to the P-type contact region 108 and the N-type contact region 110; a drain electrode 119 is electrically connected. Connected to the N-type contact region 112; and a gate electrode 121 is electrically connected to the gate structure 116.

As described above, in order to increase the withstand voltage of the above-described transistor 10, it is necessary to reduce the doping concentration of the drift region 104 and/or increase the length of the field oxide layer 114 under the gate structure 116. However, when the withstand voltage is raised in the above manner, the on-resistance (Ron) of the above-described transistor 10 is also increased or the size of the transistor 10 is increased.

Therefore, it is necessary to find a semiconductor device capable of increasing withstand voltage while avoiding an increase in on-resistance of the above device.

An embodiment of the present invention provides a semiconductor device including: a semiconductor substrate having a first conductivity type; a well region having a second conductivity type formed in the semiconductor substrate; a drain region and a source region; Formed in the well region of the semiconductor substrate and outside the well region; at least one set of the first and second heavily doped regions are formed in the well region between the drain region and the source region, wherein the first and second weights The doped regions are vertically stacked from bottom to top, respectively having a first conductivity type and a second conductivity type, and a doping concentration greater than a doping concentration of the well region; and a gate structure disposed on the semiconductor substrate.

Another embodiment of the present invention provides a method of fabricating a semiconductor device, comprising: providing a semiconductor substrate having a first conductivity type; forming a well region in the semiconductor substrate, wherein the well region has a second conductivity type; Forming at least one set of first and second heavily doped regions, wherein the first and second heavily doped regions are vertically stacked from bottom to top, respectively having a first conductivity type and a second conductivity type, and the doping concentration is greater than Doping concentration of the well region; at the semiconductor substrate a drain region and a source region are respectively formed in the well region and the outside of the well region, so that the first and second heavily doped regions of the group are located in the well region between the drain region and the source region; and in the semiconductor A gate structure is formed on the substrate.

Hereinafter, a semiconductor device and a method of manufacturing the same according to embodiments of the present invention will be described. However, the present invention is to be understood as being limited to the details of the present invention.

Referring to FIG. 2D, a cross-sectional view of a semiconductor device 20 in accordance with an embodiment of the present invention is shown. In the present embodiment, the semiconductor device 20 may be a horizontal diffusion metal oxide half field effect transistor (LDMOSFET) having a super junction structure. Furthermore, the semiconductor device 20 includes a semiconductor substrate 200, such as a germanium or silicon on insulator (SOI) substrate or other suitable semiconductor substrate, having a first conductivity type.

A well region 204, a source region 218, a drain region 220, and a substrate region 212 are formed in the semiconductor substrate 200. For example, well region 204 has a second conductivity type opposite to the first conductivity type and extends into the semiconductor substrate 200 from the upper surface of semiconductor substrate 200. Moreover, the well region 204 corresponds to an active region A of the semiconductor substrate 200 (defined by a portion of the isolation structure (eg, field oxide layer 214)) as a drift region of the LDMOSFET.

The source region 218 is composed of a doped region 218a having a second conductivity type and a doped region 218b having a first conductivity type. The source region 218 is formed outside the well region 204 of the semiconductor substrate 200 and corresponds to the active region A. Again, base The body region 212 has a first conductivity type and is formed outside the well region 204 of the semiconductor substrate 200 such that the source region 218 is located within the body region 212. The drain region 220 is composed only of a doped region having a second conductivity type. The drain region 220 is formed within the well region 204 and corresponds to the active region A.

At least one first heavily doped region 201 and a second heavily doped region 203 are formed in the well region 204 between the drain region 220 and the source region 218, wherein the first heavily doped region 201 and the second heavily doped region The miscellaneous regions 203 are vertically stacked from bottom to top, and the first heavily doped regions 201 are electrically floating. The first and second heavily doped regions 201 and 203 have a first conductivity type and a second conductivity type, respectively, and the doping concentration is greater than the doping concentration of the well region 204 to form an ultra in the well region 204 of the semiconductor substrate 200. Joint structure. In this embodiment, the first conductivity type is a P type, and the second conductivity type is an N type. However, in other embodiments, the first conductivity type may also be N-type and the second conductivity type is P-type.

In other embodiments, the semiconductor device 20 can include a plurality of first and second heavily doped regions 201 and 203 stacked vertically within the well region 204 of the semiconductor substrate 200 to form a plurality of super junctions within the semiconductor substrate 200. structure.

The gate structure 216 is disposed on the semiconductor substrate 200 and between the source region 218 and the drain region 220. Gate structure 216 typically includes a gate (e.g., comprised of a germanium), a gate dielectric layer located below, and a field oxide layer 214 underlying the gate dielectric layer.

The semiconductor device 20 further includes an inner dielectric layer (ILD) 226 and a plurality of interconnect structures 221, 223 and 225 located therein. In this embodiment, the interconnect structure 221 is electrically connected to the source region 218 as a source electrode; the interconnect structure 223 is electrically connected to the gate junction. The structure 216 is used as a gate electrode; and the interconnect structure 225 is electrically connected to the drain region 220 to serve as a drain electrode.

In the above embodiment, the heavily doped region having the first conductivity type and electrically floating in the super junction structure helps to form a depletion region in the well region 204 (ie, the drift region), thereby enhancing the semiconductor device 20 The withstand voltage of the LDMOSFET. Furthermore, the heavily doped region having the second conductivity type in the super junction structure provides an additional current path in the well region 204 (ie, the drift region) to reduce the on-resistance between the source region and the drain region. .

2A through 2D are cross-sectional views showing a method of fabricating a semiconductor device 20 in accordance with an embodiment of the present invention. Referring to FIG. 2A, a semiconductor substrate 200 is provided, such as a germanium substrate or a silicon on insulator (SOI) substrate or other suitable semiconductor substrate having a first conductivity type. Then, a well region 204 may be formed in a predetermined region (ie, active region A) of the semiconductor substrate 200 by a doping process (eg, ion cloth value) and thermal diffusion processes, wherein the well region 204 has A second conductivity type different from the first conductivity type serves as a drift region of the subsequently formed LDMOSFET.

In the present embodiment, a set of first and second heavily doped regions 201 and 203 may be formed in the well region 204, wherein the first and second heavily doped regions 201 and 203 are vertically stacked from bottom to top. The first and second heavily doped regions 201 and 203 have a first conductivity type and a second conductivity type, respectively, and the doping concentration is greater than the doping concentration of the well region 204 to form an ultra in the well region 204 of the semiconductor substrate 200. Joint structure.

In other embodiments, a plurality of first and second heavily doped regions 201 and 203 may be formed in well region 204 of semiconductor substrate 200. The above complex array The first and second heavily doped regions 201 and 203 are generally vertically aligned with each other to form a plurality of super junction structures within the well region 204 of the semiconductor substrate 200.

In the above embodiment, the first and second heavily doped regions 201 and 203 are located between the subsequently formed drain region 220 and the source region 218 (indicated in FIG. 2C), wherein the first heavily doped region 211 is an electrical floating connection. In this embodiment, the first conductivity type is a P type, and the second conductivity type is an N type. However, in other embodiments, the first conductivity type may also be N-type and the second conductivity type is P-type.

Referring to FIGS. 2B and 2C, a plurality of isolation structures (eg, field oxide layer 214) may be formed on the semiconductor substrate 200 by a conventional MOS process, in which a portion of the field oxide layer 214 defines the active region A, and other portions. The field oxide layer 214 defines a drain region D to be formed in the well region 204. Thereafter, a gate structure 216 is formed over the semiconductor substrate 200 to define a source region S to be formed outside the well region 204 in the active region A, as shown in FIG. 2B.

Then, a substrate region 212 having a first conductivity type is selectively formed on the outside of the well region 204 of the semiconductor substrate 200 by a process such as a doping process (for example, ion cloth value) and thermal diffusion, so as to be subsequently formed. Source region 218 is located within substrate region 212. Then, a doping region 218a having a second conductivity type is formed in the source region S to be formed (indicated in FIG. 2B) by a doping process (for example, an ion cloth value), and the drain region D to be formed is formed. (labeled in Figure 2B) forms a doped region having a second conductivity type (i.e., drain region 220). Thereafter, a doped region 218b having a first conductivity type is formed adjacent to the doped region 218a and a source region 218 is formed with the doped region 218a in the source region S to be formed (indicated in FIG. 2B). As shown in Figure 2C.

In other embodiments, doped regions 218b may be formed prior to forming doped regions 218a and drain regions 220. In the present embodiment, the source region 218, the gate structure 216, the drain region 220, and the well region 204 having the super junction structure constitute an LDFETMOS.

Referring to FIG. 2D, an inner dielectric layer (ILD) 226 and a plurality of interconnect structures 221, 223 and 225 located therein may be formed on the semiconductor substrate 200 by a conventional metallization process. The interconnect structure 221 is electrically connected to the source region 218 as a source electrode; the interconnect structure 223 is electrically connected to the gate structure 216 as a gate electrode; and the interconnect structure 225 is electrically connected to the gate electrode 225. The pole region 220 serves as a drain electrode. In this way, the fabrication of the semiconductor device 20 is completed.

According to the above embodiment, since the heavily doped region having the first conductivity type and electrically floating in the super junction structure can form a depletion region in the drift region, the withstand voltage of the LDMOSFET in the semiconductor device can be improved. Furthermore, since the heavily doped region having the second conductivity type in the super junction structure provides an additional current path in the drift region, the on-resistance of the LDMOSFET can be lowered. In addition, according to the above embodiment, the withstand voltage of the LDMOSFET can be further improved by controlling the number of super junction structures vertically stacked in the drift region while avoiding an increase in the on-resistance of the LDMOSFET.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can be modified and retouched without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

Conventional knowledge

10‧‧‧N type horizontal diffusion gold oxide half field effect transistor

100‧‧‧P type semiconductor substrate

102‧‧‧P type epitaxial layer

104‧‧‧N type drift zone

106‧‧‧P type base area

108‧‧‧P type contact area

110, 112‧‧‧N type contact area

114‧‧‧Field oxide layer

116‧‧‧ gate structure

117‧‧‧ source electrode

119‧‧‧汲electrode

121‧‧‧gate electrode

Example

20‧‧‧Semiconductor device

200‧‧‧Semiconductor substrate

201‧‧‧First doped area

203‧‧‧Second doped area

204‧‧‧ Well Area

212‧‧‧basal area

214‧‧ ‧ field oxide layer

216‧‧‧ gate structure

218‧‧‧ source area

218a, 218b‧‧‧ doped area

220‧‧‧Bungee Area

221, 223, 225‧‧‧ interconnected structure

226‧‧‧ Inner dielectric layer

A‧‧‧active area

D‧‧‧To be formed into the bungee area

S‧‧‧The source area to be formed

Fig. 1 is a schematic cross-sectional view showing a conventional N-type horizontal diffusion gold-oxygen half field effect transistor.

2A to 2D are cross-sectional views showing a method of fabricating a semiconductor device in accordance with an embodiment of the present invention.

20‧‧‧Semiconductor device

200‧‧‧Semiconductor substrate

201‧‧‧First doped area

203‧‧‧Second doped area

204‧‧‧ Well Area

212‧‧‧basal area

214‧‧ ‧ field oxide layer

216‧‧‧ gate structure

218‧‧‧ source area

218a, 218b‧‧‧ doped area

220‧‧‧Bungee Area

221, 223, 225‧‧‧ interconnected structure

226‧‧‧ Inner dielectric layer

A‧‧‧active area

Claims (12)

A semiconductor device comprising: a semiconductor substrate having a first conductivity type; a well region having a second conductivity type formed in the semiconductor substrate; a drain region and a source region respectively formed on the semiconductor The well region of the substrate and the outside of the well region; at least one set of first and second heavily doped regions formed in the well region between the drain region and the source region, wherein the first and the The second heavily doped regions are vertically stacked from bottom to top, respectively having the first conductivity type and the second conductivity type, and the doping concentration is greater than the doping concentration of the well region; and a gate structure is disposed on the semiconductor On the substrate. The semiconductor device of claim 1, wherein the first heavily doped region is electrically floating. The semiconductor device of claim 1, further comprising a plurality of first and second heavily doped regions stacked vertically in the well region. The semiconductor device of claim 1, wherein the first conductivity type is a P type, and the second conductivity type is an N type. The semiconductor device of claim 1, wherein the first conductivity type is N-type and the second conductivity type is P-type. The semiconductor device of claim 1, further comprising a substrate region having the first conductivity type and formed outside the well region of the semiconductor substrate such that the source region is located in the substrate region. A method of fabricating a semiconductor device, comprising: providing a semiconductor substrate having a first conductivity type; forming a well region in the semiconductor substrate, wherein the well region has a first a second conductivity type; forming at least one set of first and second heavily doped regions in the well region, wherein the first and the second heavily doped regions are vertically stacked from bottom to top, respectively having the first conductivity type and The second conductivity type, and the doping concentration is greater than the doping concentration of the well region; forming a drain region and a source region respectively in the well region of the semiconductor substrate and the outside of the well region, so that the group is first And the second heavily doped region is located in the well region between the drain region and the source region; and a gate structure is formed on the semiconductor substrate. The method of fabricating a semiconductor device according to claim 7, wherein the first heavily doped region is electrically floating. The method for fabricating a semiconductor device according to claim 7, further comprising forming a plurality of first and second heavily doped regions in the well region, wherein the first and second heavily doped regions of the complex array are vertical Stacked in the well area. The method of manufacturing a semiconductor device according to claim 7, wherein the first conductivity type is a P type, and the second conductivity type is an N type. The method of fabricating a semiconductor device according to claim 7, wherein the first conductivity type is N-type and the second conductivity type is P-type. The method for manufacturing a semiconductor device according to claim 7, further comprising forming a base region outside the well region of the semiconductor substrate, wherein the source region is located in the base region, wherein the base region has the first A conductive type.