TWI508263B - Integrated circuit device - Google Patents

Description

Integrated circuit device

The present invention is an integrated circuit device, especially an integrated circuit device having a transistor having two different operating voltages.

Integrating a plurality of circuit modules having different functions into the same semiconductor wafer is a trend in the integrated circuit industry, and the operating voltage is completed on the same semiconductor wafer because the operating voltage ranges of the different functional circuit modules are different. A plurality of circuit modules having different ranges are tasks that are often encountered in the process of manufacturing integrated circuits. However, circuit components used in circuit modules with different operating voltage ranges are quite different. Therefore, the integration of such common process steps is not easy, resulting in complicated processes and high product cost and low yield. How to improve the lack of such means of practice is the main purpose of the development of this case.

An object of the present invention is to provide an integrated circuit device including a semiconductor substrate and a first operating voltage transistor and a second operating voltage transistor completed on the semiconductor substrate, wherein the first operating voltage is greater than the second operating voltage The first working voltage transistor comprises: a first drain structure formed in the semiconductor substrate; a first source structure formed in the semiconductor substrate, comprising the following structure: a high voltage first electrical well region a first electrical matrix region, a high concentration first electrical doping region, a second electrical gradation region, and a high concentration second electrical doping region, wherein the second electrical gradation region Surrounding a high concentration of the second electrically conductive doped region, and the second electrically electrically grading region is surrounded by the first electrically conductive substrate region; an isolation structure formed in the semiconductor substrate and located in the first drain structure and Between a source structure and a first gate structure, between the first source structure and the first drain structure and a portion above the isolation structure; and the second working voltage transistor includes: Bipolar junction Formed in the semiconductor substrate; a second source structure formed in the semiconductor substrate; a second gate structure formed in the semiconductor substrate between the source structure and the drain structure; and a first electrical property The drift region is formed in the semiconductor substrate to surround at least the second drain structure, and the dopant concentration of the first electrical drift region is equal to the first electrical base region.

In a preferred embodiment of the present invention, the semiconductor substrate is a germanium substrate, and the first working voltage electro-crystal system is a lateral insulating gate bipolar transistor, and the working voltage is up to 800 volts.

In a preferred embodiment of the present invention, the high voltage first electrical well region, the first electrical base region, the high concentration first electrical doping region, the second electrical gradation region, and the above The dopant concentrations of the second electro-doped region of high concentration are respectively of the order of magnitude 10 ¹³ cm ^-2 , 10 ¹³ cm ^-2 , 10 ¹⁵ cm ^-2 , 10 ¹³ cm ^-2 , 10 ¹⁵ cm ^-2 .

In a preferred embodiment of the present invention, the isolation structure is formed by a field oxide layer plus a ruthenium oxide layer having a thickness of about 5000 angstroms, and the ruthenium oxide layer is made of tetraethoxy decane. Low pressure chemical vapor deposition is done.

In a preferred embodiment of the present invention, the first gate structure includes: a gate dielectric layer between the first source structure and the first drain structure; and a segmented gate conductor The structure is formed on the surface of the gate dielectric layer.

In a preferred embodiment of the present invention, a P-type top region is further included, most of which are located below the isolation structure and extend only partially toward the first source structure.

In a preferred embodiment of the present invention, the second operating voltage transistor is an N-type MOS transistor having an operating voltage of 5 volts, wherein the first electrical drift region is a P-type drift region formed in The semiconductor substrate is configured to surround the second drain structure and the second source structure.

In a preferred embodiment of the present invention, the second operating voltage transistor is a P-type MOS transistor having an operating voltage of 30 volts, wherein the first electrical drift region is a P-type drift region formed in The semiconductor substrate is configured to surround the second drain structure.

Another object of the present invention is to provide an integrated circuit device including a semiconductor substrate and a first operating voltage transistor and a second operating voltage transistor completed on the semiconductor substrate, wherein the first operating voltage is greater than the second The working voltage, the first working voltage transistor comprises: a first drain structure formed in the semiconductor substrate; a first source structure formed in the semiconductor substrate, comprising the following structure: a high voltage first electrical property a well region, a first electrical matrix region, a high concentration first electrical doping region, a second electrical gradation region, and a high concentration second electrical doping region, wherein the second electrical The layer region surrounds the high concentration second electrical doping region, and the second electrical gradation region is surrounded by the first electrical matrix region; an isolation structure is formed in the semiconductor substrate and located in the first drain structure And a first gate structure, and a first gate structure between the first source structure and the first drain structure and a portion above the isolation structure; and the second working voltage transistor comprises: a second a structure formed in the semiconductor substrate; a second source structure formed in the semiconductor substrate; a second gate structure formed in the semiconductor substrate between the source structure and the drain structure; and a second The sexual drift region is formed in the semiconductor substrate to surround at least the second drain structure, and the dopant concentration of the second electrical drift region is equal to the second electrical gradient region.

In a preferred embodiment of the present invention, the semiconductor substrate is a germanium substrate, and the first working voltage electro-crystal system is a lateral insulating gate bipolar transistor, and the working voltage is up to 800 volts.

In a preferred embodiment of the present invention, the high voltage first electrical well region, the first electrical base region, the high concentration first electrical doping region, the second electrical gradation region, and the above The dopant concentrations of the second electro-doped region of high concentration are respectively of the order of magnitude 10 ¹³ cm ^-2 , 10 ¹³ cm ^-2 , 10 ¹⁵ cm ^-2 , 10 ¹³ cm ^-2 , 10 ¹⁵ cm ^-2 .

In a preferred embodiment of the present invention, the isolation structure is formed by a field oxide layer plus a ruthenium oxide layer having a thickness of about 5000 angstroms, and the ruthenium oxide layer is made of tetraethoxy decane. Low pressure chemical vapor deposition is done.

In a preferred embodiment of the present invention, the first gate structure includes: a gate dielectric layer between the first source structure and the first drain structure; and a segmented gate conductor The structure is formed on the surface of the gate dielectric layer.

In a preferred embodiment of the present invention, a P-type top region is further included, most of which are located below the isolation structure and extend only partially toward the first source structure.

In a preferred embodiment of the present invention, the second operating voltage transistor is a P-type MOS transistor having an operating voltage of 5 volts, wherein the second electrical drift region is an N-type drift region formed in The semiconductor substrate is configured to surround the second drain structure and the second source structure.

In a preferred embodiment of the present invention, the second operating voltage transistor is an N-type MOS transistor having an operating voltage of 30 volts, wherein the second electrical drift region is an N-type drift region formed in The semiconductor substrate is configured to surround the second drain structure.

Please refer to FIG. 1A to FIG. 1F , which are schematic cross-sectional structures of various MOS transistors which are to be completed on the same wafer, wherein FIG. 1A is a P-type MOS transistor having a working voltage of 5 volts. Schematic diagram of the cross-sectional structure, which is mainly completed on the P-type substrate 1, the P-type substrate 1 has a deep N-type well region (Deep Well, referred to as DNW) 10, and then completes the N-type drift region in the deep N-type well region 10. (N-Drift, ND for short) 11, and finally complete a high-concentration P-type doping region (abbreviated as P+) 110, a high-concentration N-doped region 111 (abbreviated as N+) in and above the N-type drift region 11 and Structure of gate structure 112 and the like. The high-concentration P-doped region 110 is used to complete the source/drain region, and the high-concentration N-doped region 111 is used to complete the substrate contact region, wherein the dopant concentration of the high-concentration N-doped region 111 is greater than N-type drift region 11. The high concentration of the P-doped region 110 and the high concentration of the N-doped region 111 are separated by the isolation structure 119.

1B is a schematic cross-sectional structural view of an N-type MOS transistor having an operating voltage of 5 volts, which is mainly completed on a P-type substrate 1 having a deep N-type well region (Deep Well, referred to as DNW). 10), then a P-type drift region (P-Drift, PD for short) 14 is completed in the deep N-type well region 10, and finally a high-concentration P-type doping region is completed in the upper and upper portions of the P-type drift region 14 (abbreviation) P+) 110, a high concentration N-doped region 111 (abbreviated as N+), and a gate structure 112. The high concentration P-doped region 110 is used to complete the substrate contact region, and the high concentration N-doped region 111 is used to complete the source/drain region, wherein the high concentration P-doped region (P+) 110 is doped. The mass concentration is greater than the P-type drift region (PD) 14. The high concentration of the P-doped region 110 and the high concentration of the N-doped region 111 are separated by the isolation structure 119.

1C is a schematic cross-sectional structural view of an N-type MOS transistor having an operating voltage of up to 30 volts, which is completed on a P-type substrate 1 having a deep N-type well region (DNW) 10 in the P-type substrate 1, and then deep A high voltage P Well (HVPW) 12 is completed in the N-type well region 10. In the high voltage P-type well region 12, an N-type drift region (ND) 11, a high-concentration N-type doping region (N+) 111, and a high-concentration P-type doping region 110 are also completed to complete the source/ The drain region and the substrate contact region are separated by a high-concentration P-type doped region 110 and a high-concentration N-type doped region 111 through the isolation structure 119. The isolation structure 119 is further completed with a gate structure 112 on the surface of the channel 118 completed by the high voltage P-type well region 12.

1D is a schematic cross-sectional view of a P-type MOS transistor having an operating voltage of up to 30 volts, which can also be completed on a P-type substrate 1 having a deep N-type well region (DNW) 10 in the P-type substrate 1, and then A high voltage N Well (HVNW) 13 is completed in the deep N-type well region 10. In the high voltage N-type well region (HVNW) 13, a P-type drift region (P-Drift, PD for short) 14, a high-concentration N-type doped region (N+) 111, and a high-concentration P-type doped region are completed. (P+) 110 for completing the source/drain region and the substrate contact region. As for the high concentration of the P-type doped region 110 and the high concentration of the N-type doped region 111, the isolation structure 119 is used to complete the isolation. The isolation structure 119 is also completed with the gate structure 112 on the surface of the channel 118 completed by the high voltage N-type well region 13.

Figure 1C and Figure 1D are symmetrical components of N-type MOS and P-type MOS transistors, respectively, with operating voltages up to 30 volts. For Figure 1E and Figure 1F, the operating voltage is up to 30. The asymmetric type elements of the N-type gold oxide semi-transistor of the volt and the P-type gold-oxygen semi-transistor can be completed on the P-type substrate 1, but the basic structure is not greatly different, and therefore will not be described again.

Looking at the various types of MOS transistors shown in FIG. 1A to FIG. 1F, the structure is applied to a P-type substrate 1, a deep N-type well region 10, an N-type drift region 11, and a high-concentration P-type doping. A region 110, a high concentration N-doped region 111, a gate structure 112, a P-type drift region 14, a high voltage P-type well region 12, an isolation structure 119, and a high voltage N-type well region 13. The gate structure 112 has a multi-layer structure, at least a gate dielectric layer and a gate conductor layer, but is not shown in the figure for the sake of simplicity.

Referring to FIG. 2, it is a cross-sectional structural diagram of a Lateral Insulated-Gate Bipolar Transistor (LIGBT) developed in this case, which is a gold-oxygen semi-transistor with an operating voltage of up to 800 volts. The schematic diagram of the cross-sectional structure is such that three kinds of transistor structures having operating voltages of 5 volts, 30 volts, and 800 volts can be completed on the same substrate without excessively increasing the number of masks and the doping process. In this case, the N-type gradient region (N GRADE, NG for short) and the P-type matrix (P-BODY), which are commonly used in the conventional insulated gate bipolar transistor, are omitted, and the N-type drift region 11 and the P-type drift region 14 are utilized. To replace it. As shown in the figure, the lateral insulating gate bipolar transistor (LIGBT) can also be completed on the P-type substrate 1. The P-type substrate 1 is provided with an isolation structure 119 and an isolation structure 200, wherein the isolation structure 119 is used to isolate the source. The pole structure 201 is in contact with the substrate contact region 209, and the isolation structure 200 is disposed between the source structure 201 and the gate structure 202. The isolation structure 119 and the isolation structure 119 of FIGS. 1A to 1F can be completed by a field oxide layer, and the isolation structure 200 is completed by the field oxide layer plus a cerium oxide layer having a thickness of about 5000 angstroms, and the thickness is about 5000. The ruthenium oxide layer of angstrom can be completed by low pressure chemical vapor deposition (LP-TEOS) using tetraethoxy decane as a raw material. The segmented gate conductor structure 2031 and the continuous gate dielectric layer 2030 are located between the source structure 201 and the gate structure 202 and straddle the isolation structure 200, and can be processed by the same process as shown in FIG. 1A. The gate structure 112 in Figure 1F is completed together.

The P-type substrate 1 also has a deep N-type well region (DNW) 10, and then a P-type top region (P_TOP) 21 is completed in the deep N-type well region 10, and most of the P-type top region 21 is located in the isolation structure. Below 200, only a portion extends in the direction of the source structure 201. The drain structure 202 is mainly composed of an N-type drift region (N-Drift) 11 and a high-concentration P-type doping region 110. The base contact region 209 is also completed by the high concentration P-type doping region 110, but the high concentration P-type doping region 110 is surrounded by the High Voltage P Well (HVPW) 12 .

In addition, the source structure 201 includes the following structures: a high voltage P-well (HVPW) 12, a P-Drift (PD) 14, and a high-concentration P-type doping region. 110, an N-type drift region (N-Drift) 11 and a high concentration N-type doped region (N+) 111. The N-Drift 11 is used to replace the conventional N-type gradient region (N GRADE, NG for short) to surround the high-concentration N-doped region (N+) 111, while the P-type The drift zone (PD) 14 is used to replace the conventional P-type matrix (P-BODY).

The doping concentrations of the above structures are respectively of the following order of magnitude: N-type dopant: N+(1015 cm ^-2 )>ND(10 ¹³ cm ^-2 )>DNW(10 ¹² cm ^-2 ), P-type dopant: P+ (10 ¹⁵ cm ^-2 ) > PD (10 ¹³ cm ^-2 ) and HVPW (10 ¹³ cm ^-2 ) > P_TOP (10 ¹² cm ^-2 ).

In summary, after the technology of the present invention is improved, the problem of the conventional means can be effectively improved. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

1. . . P-type substrate

10. . . Deep N type well area

11. . . N-type drift zone

12. . . High voltage P type well area

13. . . High voltage N-type well area

14. . . P-type drift zone

110. . . High concentration P-doped region

111. . . High concentration N-doped region

112. . . Gate structure

118. . . aisle

119. . . Isolation structure

200. . . Isolation structure

201. . . Isolated source structure

202. . . Bungee structure

2030. . . Gate dielectric layer

2031. . . Segmented gate structure

209. . . Matrix contact area

twenty one. . . P type top area

1A to FIG. 1F are schematic cross-sectional views of various types of MOS transistors to be completed on the same wafer.

Figure 2: Schematic diagram of the cross-sectional structure of the transverse insulated gate bipolar transistor developed in this case

1. . . P-type substrate

10. . . Deep N type well area

11. . . N-type drift zone

12. . . High voltage P type well area

14. . . P-type drift zone

twenty one. . . P type top area

110. . . High concentration P-doped region

111. . . High concentration N-doped region

119. . . Isolation structure

200. . . Isolation structure

201. . . Isolated source structure

202. . . Bungee structure

2030. . . Gate dielectric layer

2031. . . Segmented gate structure

209. . . Matrix contact area

Claims (16)

An integrated circuit device comprising a semiconductor substrate and a first operating voltage transistor and a second operating voltage transistor completed on the semiconductor substrate, wherein the first operating voltage is greater than the second operating voltage, the first An operating voltage transistor includes: a first drain structure formed in the semiconductor substrate; a first source structure formed in the semiconductor substrate, comprising the following structure: a high voltage first electrical well region a first electrical matrix region, a high concentration first electrical doping region, a second electrical gradation region, and a high concentration second electrical doping region, wherein the second electrical gradation layer The region surrounds the high concentration second electrical doping region, and the second electrical gradation region is surrounded by the first electrical substrate region; an isolation structure is formed in the semiconductor substrate and located at the a drain structure and the first source structure, and a first gate structure between the first source structure and the first drain structure and a portion above the isolation structure; The second working voltage transistor comprises a second drain structure formed in the semiconductor substrate; a second source structure formed in the semiconductor substrate; a second gate structure formed in the semiconductor substrate and located in the source structure and the germanium And a first electrical drift region formed in the semiconductor substrate to at least surround the second drain structure, and a dopant concentration of the first electrical drift region is equal to the first Sexual matrix area. The integrated circuit device of claim 1, wherein the semiconductor substrate is a germanium substrate, and the first working voltage electro-crystal system is a lateral insulating gate bipolar transistor, and the working voltage is up to 800. volt. The integrated circuit device of claim 1, wherein the high voltage first electrical well region, the first electrical substrate region, the high concentration first electrical doping region, the second power The doping concentration of the gradation zone and the second electrically doped zone of the high concentration are respectively of the order of magnitude 10 ¹³ cm ^-2 , 10 ¹³ cm ^-2 , 10 ¹⁵ cm ^-2 , 10 ¹³ cm ^-2 , 10 ¹⁵ Cm ^-2 . The integrated circuit device of claim 1, wherein the isolation structure is formed by a field oxide layer plus a ruthenium oxide layer having a thickness of about 5000 angstroms, and the ruthenium oxide layer is made of tetraethoxy The low pressure chemical vapor deposition of the decane as a raw material is carried out. The integrated circuit device of claim 1, wherein the first gate structure comprises: a gate dielectric layer between the first source structure and the first drain structure; and a A segmented gate conductor structure is formed on a surface of the gate dielectric layer. The integrated circuit device of claim 1, further comprising a P-type top region, the majority of which is located below the isolation structure and extends only partially toward the first source structure. The integrated circuit device of claim 1, wherein the second operating voltage transistor is an N-type MOS transistor having an operating voltage of 5 volts, wherein the first electrical drift region is a P A type drift region is formed in the semiconductor substrate to surround the second drain structure and the second source structure. The integrated circuit device of claim 1, wherein the second operating voltage transistor is a P-type MOS transistor having an operating voltage of 30 volts, wherein the first electrical drift region is a P A drift region is formed in the semiconductor substrate to surround the second drain structure. An integrated circuit device comprising a semiconductor substrate and a first operating voltage transistor and a second operating voltage transistor completed on the semiconductor substrate, wherein the first operating voltage is greater than the second operating voltage, the first An operating voltage transistor includes: a first drain structure formed in the semiconductor substrate; a first source structure formed in the semiconductor substrate, comprising the following structure: a high voltage first electrical well region a first electrical matrix region, a high concentration first electrical doping region, a second electrical gradation region, and a high concentration second electrical doping region, wherein the second electrical gradation layer The region surrounds the high concentration second electrical doping region, and the second electrical gradation region is surrounded by the first electrical substrate region; an isolation structure is formed in the semiconductor substrate and located at the a drain structure and the first source structure, and a first gate structure between the first source structure and the first drain structure and a portion above the isolation structure; The second working voltage transistor comprises a second drain structure is formed in the semiconductor substrate; a second source structure is formed in the semiconductor substrate; a second gate structure is formed in the semiconductor substrate and located in the second source structure Between the second drain structures; and a second electrical drift region formed in the semiconductor substrate to at least surround the second drain structure, and the dopant concentration of the second electrical drift region is equal to The second electrical gradation zone. The integrated circuit device of claim 9, wherein the semiconductor substrate is a germanium substrate, and the first working voltage electro-crystal system is a lateral insulating gate bipolar transistor, and the working voltage is up to 800. volt. The integrated circuit device of claim 9, wherein the high voltage first electrical well region, the first electrical substrate region, the high concentration first electrical doping region, the second electricity The doping concentration of the gradation zone and the second electrically doped zone of the high concentration are respectively of the order of magnitude 10 ¹³ cm ^-2 , 10 ¹³ cm ^-2 , 10 ¹⁵ cm ^-2 , 10 ¹³ cm ^-2 , 10 ¹⁵ Cm ^-2 . The integrated circuit device of claim 9, wherein the isolation structure is formed by a field oxide layer plus a ruthenium oxide layer having a thickness of about 5000 angstroms, and the ruthenium oxide layer is made of tetraethoxy The low pressure chemical vapor deposition of the decane as a raw material is carried out. The integrated circuit device of claim 9, wherein the first gate structure comprises: a gate dielectric layer between the first source structure and the first drain structure; and a A segmented gate conductor structure is formed on a surface of the gate dielectric layer. The integrated circuit device of claim 9, further comprising a P-type top region, the majority of which is located below the isolation structure and extends only partially toward the first source structure. The integrated circuit device of claim 9, wherein the second operating voltage transistor is a P-type MOS transistor having an operating voltage of 5 volts, wherein the second electrical drift region is a N A type drift region is formed in the semiconductor substrate to surround the second drain structure and the second source structure. The integrated circuit device of claim 9, wherein the second operating voltage transistor is an N-type MOS transistor having an operating voltage of 30 volts, wherein the second electrical drift region is a N A drift region is formed in the semiconductor substrate to surround the second drain structure.