TW201409542A - 一種化合物半導體元件及其製備方法 - Google Patents

一種化合物半導體元件及其製備方法 Download PDF

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TW201409542A
TW201409542A TW102130581A TW102130581A TW201409542A TW 201409542 A TW201409542 A TW 201409542A TW 102130581 A TW102130581 A TW 102130581A TW 102130581 A TW102130581 A TW 102130581A TW 201409542 A TW201409542 A TW 201409542A
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doping
compound semiconductor
semiconductor device
doped region
layer
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TWI518749B (zh
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Chun-Ju Tun
yi-chao Lin
Chen-Fu Chiang
Cheng-Huang Kuo
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Formosa Epitaxy Inc
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Abstract

本發明係關於一種化合物半導體元件及其製備方法，包括使用選擇性摻雜技術在基板形成一摻雜區，使半導體於基板上不同區域的成長速率不同，進而形成具有高低差結構的半導體層，並在之後繼續成長化合物半導體元件結構以製作化合物半導體元件。

Description

一種化合物半導體元件及其製備方法
    本發明係一種化合物半導體元件及其製備方法，尤指一種具有不同摻雜情形的基板的化合物半導體元件與其製備方法。
    在成長氮化鎵系發光二極體(LED)時，目前產業上主要使用的基板材料為藍寶石(Al2O3)或碳化矽(SiC)，由於與用於成長的半導體材料如氮化鎵(GaN)之晶體結構或晶格常數不同，因此在基板上成長氮化鎵半導體層時，半導體層內會產生晶格缺陷(lattice defect)或差排(dislocation)。這種缺陷可能由半導體層底部延伸至發光二極體結構表面，而劣化發光二極體的發光層結構，減損發光二極體的發光效率。
    由於缺陷或差排的多寡直接影響發光二極體發光效率，故減少缺陷或差排之密度即能提昇發光二極體發光效率。習知減少缺陷或差排之密度的方法之一，為先在基板上形成氮化鎵柱狀結構，再於柱狀結構上繼續成長氮化鎵半導體層，此時由於氮化鎵半導體層係於氮化鎵柱狀結構上形成，故大幅減少氮化鎵半導體層內缺陷或差排的產生。在基板上形成氮化鎵柱狀結構的先前技術，美國專利號7521274揭示了一種成長奈米柱體之方法，如第一A~C圖所示，其係於一基板7上設置一圖案化遮罩13，此遮罩13具有複數個孔洞而使基板7的部份表面暴露出，接著以非脈衝式成長半導體材料81於孔洞中，與遮罩13形成一平面，最後再以脈衝式接續成長半導體奈米柱82於半導體材料81之上，以形成柱狀結構。然而，在此案所揭示的方式中，在奈米等級的孔洞中成長半導體材料的難度很高，且透過脈衝式成長奈米柱不易逐片(wafer to wafer)控制均勻性，因此成品之間的差異相當大；此外，脈衝式成長奈米柱的機台維護週期較短，造成成本增加，而二次成長的製程本身也因有較多道工序，因此良率也較低。
    另外，於美國專利號7981714一案中，揭示了在矽基板上成長氮化鎵奈米柱之步驟，其係先成長複數個奈米柱於基板上，並且垂直於矽基板；接著以非晶材料填滿奈米柱之間的空隙，並且露出奈米柱的上部，此階段的製程難度相當高，而最後則是以部分奈米柱的上部為晶種，成長氮化鎵於非晶材料上。故此案的方式也是一種二次成長，對良率也有不好的影響。
    因此，基於半導體元件中的柱狀結構在製備時的技術門檻過高以及良率無法達到水準的問題，本發明提出一種半導體元件之製備方法及其結構，以克服此重要課題。
    本發明之主要目的，係提供一種化合物半導體元件，其藉由包括離子擴散或離子佈植等技術，對基板或基板上之緩衝層先做選擇性摻雜處理，之後只要經過一次成長即可獲得具有奈米級或微米級高低差的半導體結構，以克服晶格差異造成的差排等缺陷問題，並且可以架構出柱狀形式之磊晶層，同時製作方式較為簡單，有助於維持良率。
    本發明之次要目的，係提供一種半導體元件之製備方法，其透過調整摻雜過程中所使用的離子源，形成不同的摻雜區域，進而透過半導體之成長速率差異，在不同區域形成不同高度的半導體結構，具有靈活性。
    故本發明揭示了一種化合物半導體元件及其製備方法，其步驟係包含：對一基板進行摻雜，使該基板具有至少一第一摻雜區以及至少一第二摻雜區；於該基板上成長半導體層，其中成長於該第一摻雜區及第二摻雜區上之半導體高度不同而形成一高低差結構。如此方法操作之下，即可獲得具高低差結構之半導體層，之後續行其他膜層之成長而製備諸如發光二極體、電晶體、光偵測器等半導體元件。
1．．．基板
11．．．第一摻雜區
12．．．第二摻雜區
13．．．遮罩
14．．．緩衝層
2．．．半導體層
21．．．柱狀結構
3．．．磊晶層/功能層
31．．．N型氮化物層
32．．．多重量子井層
33．．．P型氮化物層
34．．．透明導電層
4．．．延伸層
5．．．空間
6．．．延伸體
7．．．基板
81．．．半導體材料
82．．．半導體奈米柱
第一A~C圖：其係為先前技術之奈米柱製備流程圖；
第二A~D圖：其係為本發明之一較佳實施例之摻雜製程與半導體層成長之流程與結構變化示意圖；
第二E~F圖：其係為本發明之一較佳實施例之結構示意圖；
第三圖：其係為本發明之一較佳實施例之製作流程與結構變化示意圖；
第四圖：其係為本發明之一較佳實施例之另一製作流程與結構變化示意圖；
第五圖：其係為本發明之一較佳實施例之摻雜離子種類或數量不同之結構示意圖；
第六圖：其係為本發明之一較佳實施例之一發光二極體結構示意圖；
第七A~B圖：其係為本發明之另一較佳實施例之結構示意圖；以及
第八A~B圖：其係為本發明之再一較佳實施例之結構示意圖。
    由於過往的柱狀結構在製備的過程中都需要經過兩次成長而影響良率的水準，故為了克服該些技術缺陷，提出本發明以改善及解決相關課題。
    首先，請參考第二A~D圖，此些圖是本發明製備高低差半導體結構時，各個步驟階段之剖面結構變化，該些步驟係包含：
步驟S1：如第二A圖至第二B圖所示，摻雜一基板，使該基板具有至少一第一摻雜區以及至少一第二摻雜區；其中該第一摻雜區和第二摻雜區的摻雜情不同，例如可具有不同的摻雜元素、摻雜深度或摻雜濃度；其中該基板材料可以是藍寶石、碳化矽、矽、砷化鎵、氧化鎵、氮化鎵、鋁酸鋰、鎵酸鋰或氮化鋁；以及
步驟S2：如第二C圖至第二D圖所示，成長一半導體層於該基板之上，該半導體層在該第一摻雜區與該第二摻雜區的高度不同，而使該半導體層具有至少一高低差結構。
    本發明可以離子佈植或離子擴散的摻雜方式進行，以離子佈植為例，於步驟S1中，首先如第二A圖所示，本實施例係於藍寶石基板1上形成遮罩13來做屏障、分隔，而後進行離子佈植得到如第二B圖所示之至少一第一摻雜區11以及至少一第二摻雜區12；其中第一摻雜區11與第二摻雜區12係可為週期性排列或為不規則排列；其中該第一摻雜區11因未受遮罩13覆蓋，故於離子佈植製程時較該第二摻雜區12摻雜了更多的雜質；其中於本實施例該摻雜元素組成可包括選自鋁(Al)、氮(N)、鎵(Ga)、鎂(Mg)、鋅(Zn)、銦(In)、鉻(Cr)、鈦(Ti)、矽(Si)、氬(Ar)等元素之任一或組合，且該第一摻雜區11之摻雜濃度範圍為1×1014至1×1021 (1/cm3)，而該第二摻雜區12的摻雜濃度係不小於零，並小於該第一摻雜區11之摻雜濃度。本發明之另一實施例則是該第一摻雜區11之摻雜元素組成與該第二摻雜區12的摻雜元素組成不同。另外，此步驟亦可以相似之離子佈植或離子擴散方法改於基板上的緩衝層或任意半導體層進行摻雜，並無限定。
    接著於步驟S2中，如第二C圖及第二D圖所示，先移除摻雜後之基板1上的遮罩13，然後在基板1上成長III-V族化合物如Alx1Gay1In(1-x1-y1)N, 1≧x1≧0, 1≧y1≧0之半導體層2，且半導體層2的晶體結構或晶格常數與基板1未摻雜部分的晶體結構或晶格常數有差異。由於基板1在第一摻雜區11與第二摻雜區12有不同摻雜濃度或不同摻雜元素組成的情形，使得半導體層2在第一摻雜區11上的成長速率與在第二摻雜區12上不同，故在一定成長時間下，半導體層2在第一摻雜區11上與在第二摻雜區12上的成長高度會有差異。如第二D圖所示，本實施例中之半導體層2在第一摻雜區11上的成長速率快於在第二摻雜區12，故半導體層2在第一摻雜區11上的成長高度比在第二摻雜區12高，而使半導體層2具有至少一高低差結構；其中此高低差結構係可為週期性排列或為不規則排列。
    與前述實施例相較，本發明之另一實施例相反地是使半導體層2在第一摻雜區11上的成長高度比在第二摻雜區12低，如第二E圖與第二F圖所示。此一實施例係藉離子佈植製程，在第一摻雜區11注入不利於成長半導體材料的雜質，或破壞第一摻雜區11的晶體結構，或改變該區的晶格常數，以降低半導體層2在第一摻雜區11的成長速率，例如在第二E圖所示之成長狀況即是半導體層2在第一摻雜區11的成長速率降低，而在第二F圖所示之成長狀況即是半導體層2在第一摻雜區11的成長速率為零。此時，半導體層2在第二摻雜區12的成長高度比在第一摻雜區11高，而形成與第二D圖所示相反的高低差結構。另外，本發明之另一實施例是用離子佈植或離子擴散方法改於緩衝層或其他任意半導體層進行摻雜，而在基板上的緩衝層或其他任意半導體層形成第一摻雜區11，並破壞第一摻雜區11表面晶體結構，使半導體成長製程中第一摻雜區11表面形成粗糙面，在光學效果上有增加散射效果，而使得本實施例在後續製成發光二極體時，發光二極體的出光效率可以更提昇。
    本發明之一實施例如第三圖所示，與上述實施例相較，其係在對基板1以離子佈植方式進行摻雜而區分出第一摻雜區11以及第二摻雜區12後，再於基板1上形成一緩衝層14，緩衝層之材料可包括選自Alx2Gay2In(1-x2-y2)N, 1≧x2≧0, 1≧y2≧0，或ZnO、MgO、SiC等之任一。其中，此緩衝層14覆蓋第一摻雜區11以及第二摻雜區12，且於緩衝層14上成長半導體層2時，半導體層2仍可受第一摻雜區11以及第二摻雜區12的差異影響，而於對應第一摻雜區11以及第二摻雜區12的位置產生高低差結構。
    本發明之另一實施例如第四圖所示，與上述各實施例相較，主要差異係遮罩13的至少兩個區域具有不同厚度，使得基板1在進行離子佈植或擴散的摻雜製程時，在基板1上會根據遮罩13的不同區域厚度有不同的摻雜情形，而在基板1上對應形成至少一第一摻雜區11與一第二摻雜區12，其中第一摻雜區11與第二摻雜區12的摻雜深度與濃度不同。如第四圖所示，基板1在對應遮罩13厚度較薄的區域形成第一摻雜區11，在對應遮罩13厚度較厚的區域形成第二摻雜區12，且在第一摻雜區11的摻雜深度比在第二摻雜區12深，濃度也較第二摻雜區高，當後續於此第一摻雜區11及第二摻雜區12上直接成長或間接於緩衝層14上成長半導體層2時，因為在對應第一摻雜區11的半導體成長速率比在第二摻雜區12慢，故半導體層2在對應第一摻雜區11位置的高度比在對應第二摻雜區12位置的高度矮，而在半導體層2形成高低差結構。
    本發明之另一實施例如第五圖所示，與上述各實施例相較，其係將基板1上的部分離子摻雜區以多重佈植方式進行額外的佈植程序，使得第一摻雜區11之佈植離子數量不同於第二摻雜區12。另外，也可在各次的離子佈植中植入不同的離子，使得第一摻雜區11以及第二摻雜區12具有不同的佈植離子或摻雜元素組成，讓成長於其上的半導體層2因而產生高低差結構。
    另外，本發明中上述各實施例之半導體層2的高低差結構外形可以是線狀、柱狀、溝槽狀、階梯狀或是任何有起伏外形的凹陷/凸起狀結構。
    而利用上述之製程方法，可形成本發明之一較佳應用實施例結構，如第六圖所示，其中半導體層2在第二摻雜區12形成一柱狀結構21後，在於此柱狀結構21周圍形成一功能層或磊晶層3，此磊晶層3可依序堆疊包含如N型氮化物層31、主動層或多重量子井(MQW)層32、P型氮化物層33以及透明導電層34等。
    於此實施例中，第二摻雜區12的寬度範圍為5nm至100μm，而相鄰之第一摻雜區11的寬度範圍則為100nm至100μm，也就是為使半導體層2形成一柱體較細、柱體間距較寬之結構，以適合前述磊晶層3包覆柱狀結構21。
    本發明的另一較佳應用實施例，係於形成具有高低差結構的半導體層2後，繼續成長形成延伸層4，此延伸層4的材料為III-V族化合物半導體如Alx3Gay3In(1-x3-y3)N, 1≧x3≧0, 1≧y3≧0，並可與半導體層2相同或相異。如第七A圖所示，延伸層4係覆蓋並填滿具有高低差結構的半導體層2，其中在基板1的至少一第一摻雜區11與一第二摻雜區12的寬度範圍為5nm至50μm。另外，本發明還有一較佳應用實施例如第七B圖所示，相較於前述第七A圖所示之較佳實施例，此實施中之延伸層4在至少一第一摻雜區11上並未完全填滿，而形成至少一空間5，其中此空間5的高度係不大於10μm，使得此實施例可增加光線散射效果而在製成發光二極體時可提升發光二極體的出光效率。
    如第八A圖所示，本發明之又一較佳應用實施例係於摻雜後之基板1上一次性成長形成具有高低差結構之半導體層2後，進一步於半導體層2之高度較高的部位（如柱狀結構或凸起結構）上形成二個以上的延伸體6，其中延伸體6為Alx4Gay4In(1-x4-y4)N, 1≧x4≧0, 1≧y4≧0的晶種，且可與半導體層2相同或相異；然後繼續進行半導體成長製程，使半導體從延伸體6橫向成長並接合形成一覆蓋半導體層2的延伸層4，如第八B圖所示，其中此延伸層4為Alx4Gay4In(1-x4-y4)N, 1≧x4≧0, 1≧y4≧0並具至少一連續表面，此表面可為一平面或為具起伏的面，另外此延伸層4可為單層或多層結構；其中半導體層2於延伸層4與基板1之間具有至少一空間5，而當此空間5有三個以上時，空間5之間可具有相同距離間隔或不同距離間隔。
    在前述本發明各應用實施例的延伸層4上繼續成長功能層或磊晶層結構，可形成本發明之化合物半導體元件，如發光二極體、光偵測器、太陽能電池或功率電晶體等等。以本發明之發光二極體為例，其係於延伸層4上陸續形成一N型或P型半導體層、一主動層與一P型或N型半導體層等磊晶層結構而形成本發明之發光二極體，並具有高發光效率、製程簡化、良率及元件壽命可大幅提昇之優點。本發明所揭示的方法不但快速簡易，同時也降低了二次成長時所會面臨的難度和缺陷。在具有實際功效之下，提供了一極具經濟和實用價值的半導體元件及其製備方法。
    惟以上所述者，僅為本發明之較佳實施例而已，並非用來限定本發明實施之範圍，舉凡依本發明申請專利範圍所述之形狀、構造、特徵及精神所為之均等變化與修飾，均應包括於本發明之申請專利範圍內。
1．．．基板
11．．．第一摻雜區
12．．．第二摻雜區
2．．．半導體層

Claims (32)

  1. 一種化合物半導體元件，其係包含：
    一基板，其具有至少一第一摻雜區以及至少一第二摻雜區；以及
    一半導體層，設置於該基板上；
    其中該第一摻雜區與該第二摻雜區分別有不同摻雜情形。
  2. 如申請專利範圍第1項所述之化合物半導體元件，其中該第一摻雜區或該第二摻雜區之摻雜元素組成係包括選自於鋁(Al)、氮(N)、鎵(Ga)、鎂(Mg)、鋅(Zn)、銦(In)、鉻(Cr)、鈦(Ti)、矽(Si)以及氬(Ar)所組成之群組其中至少之一者。
  3. 如申請專利範圍第2項所述之化合物半導體元件，其中該第一摻雜區之摻雜濃度範圍為1×1014至1×1021(1/cm3)，且其中所述不同摻雜情形係指該第二摻雜區的摻雜濃度係不小於零，並小於該第一摻雜區之摻雜濃度。
  4. 如申請專利範圍第2項所述之化合物半導體元件，其中所述不同摻雜情形係指該第一摻雜區之摻雜元素組成與該第二摻雜區的摻雜元素組成不同。
  5. 如申請專利範圍第1項所述之化合物半導體元件，其中所述不同摻雜情形係指該第一摻雜區與該第二摻雜區的摻雜深度不同。
  6. 如申請專利範圍第1項所述之化合物半導體元件，其中該半導體層材料為III-V族化合物。
  7. 如申請專利範圍第1項所述之化合物半導體元件，其中該半導體層材料包括Alx1Gay1In(1-x1-y1)N, 1≧x1≧0, 1≧y1≧0。
  8. 如申請專利範圍第1項所述之化合物半導體元件，其中該第一摻雜區與該第二摻雜區可為週期性排列或不規則排列。
  9. 如申請專利範圍第1項所述之化合物半導體元件，更包含一緩衝層位於該基板與該半導體層之間。
  10. 如申請專利範圍第1項所述之化合物半導體元件，其中該半導體層在該第一摻雜區的成長速率快於在該第二摻雜區的成長速率。
  11. 如申請專利範圍第1項所述之化合物半導體元件，其中該半導體層分別在對應該第一摻雜區與該第二摻雜區的位置有不同高度的高低差結構。
  12. 如申請專利範圍第11項所述之化合物半導體元件，其中該高低差結構外形可以為線狀、柱狀、溝槽狀、階梯狀、凹陷結構或凸起結構。
  13. 如申請專利範圍第1項所述之化合物半導體元件，其中該第一摻雜區與該第二摻雜區上的寬度範圍為5nm至50μm。
  14. 如申請專利範圍第1項所述之化合物半導體元件，其中該第一摻雜區與該第二摻雜區上的寬度範圍不同。
  15. 如申請專利範圍第14項所述之化合物半導體元件，其中該第一摻雜區的寬度範圍為100nm至100μm，該第二摻雜區的寬度範圍為5nm至100μm。
  16. 如申請專利範圍第11項所述之化合物半導體元件，更包含一磊晶層，其中該磊晶層包括一N型氮化物層、一主動層及一P型氮化物層，且該磊晶層係形成於該半導體層的柱狀之該高低差結構的周圍。
  17. 如申請專利範圍第1項所述之化合物半導體元件，更包含一延伸層，其中該延伸層覆蓋該半導體層。
  18. 如申請專利範圍第17項所述之化合物半導體元件，其中該延伸層填滿該半導體層。
  19. 如申請專利範圍第17項所述之化合物半導體元件，其中該延伸層與該半導體層之間形成有至少一空間。
  20. 如申請專利範圍第19項所述之化合物半導體元件，其中該空間的高度係不大於10um。
  21. 如申請專利範圍第17項所述之化合物半導體元件，其中該延伸層係於該半導體層之高度較高的部位上成長接合形成，並具有一連續表面。
  22. 如申請專利範圍第17項所述之化合物半導體元件，更包含二個以上的延伸體位於該半導體層之高度較高的部位上，該延伸層係於該延伸體上成長接合形成，並具有一連續表面。
  23. 如申請專利範圍第19項所述之化合物半導體元件，其中該空間有三個以上，且該空間彼此之間可具有相同距離間隔或不同距離間隔。
  24. 如申請專利範圍第17項所述之化合物半導體元件，更包含一N型半導體層、一主動層與一P型半導體層形成於該延伸層上。
  25. 如申請專利範圍第1項所述之化合物半導體元件，其中該元件的製備步驟係包含：
    形成至少一遮罩於該基板上；
    摻雜該基板使其具有該第一摻雜區以及該第二摻雜區；以及
    形成一半導體層於該基板上。
  26. 如申請專利範圍第25項所述之化合物半導體元件，其中該摻雜步驟係用離子佈植方法完成。
  27. 如申請專利範圍第25項所述之化合物半導體元件，其中該摻雜步驟係用離子擴散方法完成。
  28. 如申請專利範圍第25項所述之化合物半導體元件，其中該遮罩在至少兩個區域具有不同厚度，而使基板上於摻雜步驟時對應形成該第一摻雜區與該第二摻雜區。
  29. 如申請專利範圍第25項所述之化合物半導體元件，其中該摻雜步驟於摻雜該第一摻雜區使用的摻雜元素與摻雜該第二摻雜區使用的摻雜元素不同。
  30. 一種化合物半導體元件，其係包含：
    一基板；
    一緩衝層，其具有至少一第一摻雜區以及至少一第二摻雜區；以及
    一半導體層，設置於該緩衝層上；
    其中該第一摻雜區與該第二摻雜區分別有不同摻雜情形。
  31. 一種化合物半導體元件，其係包含：
    一基板，其具有至少一第一摻雜區；以及
    一半導體層，設置於該基板上；
    其中，該半導體層在該第一摻雜區上的成長速率，較在該基板之非該第一摻雜區的位置上為快。
  32. 一種化合物半導體元件，其係包含：
    一基板；以及
    一緩衝層，設置於該基板上，具有至少一第一摻雜區，且該第一摻雜區表面係為粗糙面。
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