TW201409505A - Laminated ceramic electronic component - Google Patents

Abstract

Provided is a laminated ceramic electronic component that does not invite a reduction in performance due to breakage in an internal electrode layer, has favorable thermal shock resistance, and is highly reliable. A laminated section (10) has the following: a thermal shock mitigating section (11) which corresponds to a region near an external layer (20) including a region in contact with the external layer and which is provided with a curved ceramic layer (1, (1a)) and an internal electrode layer (2, (2a)) the thickness of which changes smoothly according to a position; and a normal laminated section (12) which corresponds to a region inside from the thermal shock mitigating section and which is provided with a ceramic layer (1, (1b)) the degree of curvature of which is smaller than the ceramic layer (1, (1a)) of the thermal shock mitigating section (11), and an internal electrode layer (2, (2b)) in which the degree of thickness change according to a position in a direction following the main surface of the external layer (20) is smaller than the internal electrode layer (2, (2a)) of the thermal shock mitigating section (11). With regard to the thermal shock mitigating section, the CV value of the thickness of the ceramic layer is no more than 15%, the CV value of the thickness of at least one layer of the internal electrode layers is at least 40%, and the CV value of the distance between mid-points is at least 40% in a case of one set of adjacent ceramic layers.

Description

Laminated ceramic electronic parts

The present invention relates to a laminated ceramic electronic component comprising: a laminated portion having a plurality of laminated ceramic layers and an internal electrode layer between the ceramic layers; and an outer layer portion sandwiching the laminated portion from both main faces It is provided with a ceramic layer that does not include an internal electrode layer.

As one of the representative laminated ceramic electronic parts, there is a wafer type multilayer ceramic capacitor. Further, with the recent miniaturization and high performance of electronic equipment, it is desirable for the ceramic capacitor to have a larger electrostatic capacitance per unit volume than before, and to obtain a larger capacity.

In order to achieve such miniaturization and increase in capacity, it is generally necessary to reduce the thickness of the ceramic layer and the internal electrode layer and increase the number of layers of the ceramic layer and the internal electrode layer in the laminated portion, that is, to increase the number of layers.

However, in the case of multi-layering, the internal electrode layer ratio per unit volume of the multilayer ceramic capacitor is degenerated. As a result, there is a problem that delamination easily occurs due to the difference in sintering shrinkage temperature between the ceramic layer and the internal electrode layer.

Further, in the ceramic constituting the ceramic layer and the metal constituting the internal electrode layer portion, the respective thermal expansion coefficients are different. Therefore, in the multilayer ceramic capacitor obtained by the firing step, there is an internal stress due to the difference in thermal expansion coefficient. Further, since the ratio of the internal electrode layer is increased by the multilayering, the internal stress is increased, and there is a problem that cracks are generated when a thermal shock is applied.

In this regard, as a solution to such problems, a laminated ceramic electronic component is disclosed, as shown in FIGS. 8 and 9, a laminated body 103 having a ceramic layer 107 and internal electrode layers 105 and 106 alternately laminated, and a laminated body 103 disposed thereon. The ends are respectively connected to the external electrodes 102, 102 of the internal electrode layers 105, 106; and the first ceramics having the same average particle diameter or smaller average particle diameter than the conductor particles are present in the internal electrode layers 105, 106. The particles (not shown) have the second ceramic particles 108 having an average particle diameter larger than that of the internal electrode layers 105 and 106 (FIG. 9) (refer to Patent Document 1).

Further, according to the invention of Patent Document 1, since the difference in thermal expansion coefficient between the ceramic layers 107 is small, and the bonding force between the ceramic layers 107 is increased, the laminated ceramic electronic component is mounted on the circuit board and the external electrode 102 is soldered. In the case of 102, the laminated body 103 which is caused by heat shock or the like has a high heat-resistance stress, and a laminated ceramic electronic component which is less likely to cause cracks or delamination in the inside of the laminated body 103 can be obtained (Patent Document 1,0045) ).

However, in the case of Patent Document 1, since the second ceramic particles having the average particle diameter larger than the thickness of the internal electrode layers 105 and 106 present in the internal electrode layers 105 and 106 cause the internal electrode layer to be interrupted, When the laminated ceramic electronic component is a laminated ceramic capacitor, there is a phenomenon that the electrostatic capacitance is lowered, which is contrary to the requirement of increasing the capacity.

Moreover, the same problem exists in laminated ceramic electronic parts other than laminated ceramic capacitors.

[Previous Technical Literature] [Patent Literature]

[Patent Document 1] Japanese Patent Laid-Open Publication No. 2000-277369

The present invention has been made in view of the above problems, and it is an object of the invention to provide a reduction in performance due to discontinuity of internal electrode layers, and also excellent thermal shock resistance and high reliability. Laminated ceramic electronic parts.

In order to solve the above problems, the laminated ceramic electronic component of the present invention is characterized in that it comprises: a laminate portion having a plurality of laminated ceramic layers and an internal electrode layer between the ceramic layers; and an outer layer portion having One or more ceramic layers disposed so as to sandwich the laminated portion in the direction of the lamination direction; in the laminated ceramic electronic component, the laminated portion includes a region near the outer layer portion adjacent to the region of the outer layer portion The thermal shock absorbing portion includes: the curved ceramic layer and the inner electrode layer whose thickness is smoothly changed according to a position along a main surface of the outer layer portion; and the thermal shock The region of the inner side of the mitigation portion is a normal laminated portion, and the normal laminated portion includes: the ceramic layer having a degree of bending smaller than the ceramic layer of the thermal shock absorbing portion; and the inner electrode layer according to the outer layer portion The degree of change in thickness caused by the position in the direction of the main surface is smaller than the above-mentioned internal electrode layer of the thermal shock absorbing portion In the thermal shock absorbing portion, the CV value of the thickness of the ceramic layer is 15% or less, and the CV value of the thickness of the internal electrode layer of at least one layer is 40% or more, and the ceramic layers adjacent to each other are observed. The length of the straight line connecting the points in the thickness direction of one ceramic layer and the other ceramic layer in the stacking direction of the laminated portion, that is, the CV value of the distance between the midpoints is 40% or more.

Further, in the above-mentioned general laminated portion, it is preferable that the CV value of the thickness of the ceramic layer is 15% or less, and the CV value of the thickness of the internal electrode layer is 20% or less, and when one ceramic layer adjacent to each other is observed, Located in a ceramic layer and another ceramic The length of the straight line connecting the points in the thickness direction of the layer along the lamination direction of the laminated portion, that is, the CV value of the distance between the midpoints is 20% or less.

By having the above-described basic structure (the structure of the thermal shock absorbing portion) excellent in thermal shock resistance, the normal laminated portion is formed as described above, and the internal electrode layer and the ceramic layer are reliably deformed without being deformed in the usual laminated portion. Based on this, it is possible to obtain a laminated ceramic electronic component having excellent electrical characteristics, and the present invention can be further effective.

Further, the laminated ceramic electronic component of the present invention is preferably a surface mount type multilayer ceramic capacitor.

In particular, in order to achieve miniaturization and high performance (large capacity), the surface mount type multilayer ceramic capacitor has been continuously developed into a multilayer. As a result, there is a problem that delamination tends to occur due to the difference in sintering shrinkage temperature between the ceramic layer and the internal electrode layer. However, by applying the present invention, it is possible to provide a thermal shock resistance which is small, but can be obtained. A multilayer ceramic capacitor with a large electrostatic capacitance and high reliability is particularly meaningful.

In the laminated ceramic electronic component of the present invention, as described above, in the laminated portion, a region near the outer layer portion including the region adjacent to the outer layer portion is formed as a thermal shock absorbing portion including a curved ceramic layer and a thickness. The inner electrode layer smoothly changes according to the position in the direction of the main surface of the outer layer portion; the region on the inner side of the thermal shock mitigation portion is formed as a normal laminated portion, the normal laminated portion including the degree of bending less than the thermal shock mitigation The ceramic layer of the ceramic layer and the thickness of the ceramic layer according to the position along the main surface of the outer layer portion are smaller than the inner electrode layer of the inner electrode layer of the thermal shock absorbing portion; and the thermal shock absorbing portion satisfies the following Necessary conditions: the CV value of the thickness of the ceramic layer is 15% or less, and the CV value of the thickness of the internal electrode layer of at least one layer is 40% or more, and the CV value of the distance between the midpoints when one ceramic layer adjacent to each other is observed 40% or more; therefore, it can provide high resistance to thermal shock, for example, in the case of a laminated ceramic capacitor, it is small but can obtain a large electrostatic capacitance and is highly reliable and small. High performance laminated ceramic electronic parts.

That is, in the laminated ceramic electronic component of the present invention, (a) the ceramic layer is curved; and (b) the thickness is smoothly changed according to the position in the direction of the main surface of the outer layer portion in the inner electrode layer of the first layer (having a thickness) The distribution) can efficiently disperse the thermal shock, thereby improving the thermal shock resistance.

Further, since the continuity of the thermal shock absorbing portion and the normal laminated portion of the internal electrode layer is high and uninterrupted, for example, in the case of a laminated ceramic capacitor, it is possible to obtain a small size but to obtain a large static electricity. Multilayer ceramic electronic parts with high capacitance.

1 (1a, 1b) ‧ ‧ ceramic layer

2 (2a, 2b) ‧ ‧ internal electrode layer

10‧‧‧Ministry Department

11‧‧‧ Impact mitigation department

12‧‧‧ Usually the Ministry of Construction

20 (20a, 20b) ‧ ‧ outer layer

30‧‧‧Layered body

31 (31a, 31b) ‧ ‧ end face of laminated body

33 (33a, 33b) ‧ ‧ external electrodes

102‧‧‧External electrode

103‧‧‧Layered body

105‧‧‧Internal electrode layer

106‧‧‧Internal electrode layer

107‧‧‧Ceramic layer

108‧‧‧Second ceramic particles

Lp ₁ ‧‧‧ is perpendicular to the tangent to the tangent Lt ₁

Lp ₂ ‧‧‧ perpendicular to the reference line Lr ₁

Lp ₃ ‧‧‧ perpendicular to the reference line Lr ₂

Lt ₁ ‧‧‧ tangent to the ceramic layer

Lt ₂ ‧‧‧ parallel to the tangent Lt ₁

Lr ₁ , Lr ₂ ‧‧‧ reference line

P ₁ ‧‧‧ Appropriate points of the interface between the ceramic layer and the internal electrode layer

P ₂ ‧‧‧ the intersection of the opposite side of the ceramic layer and the interface of the internal electrode layer

P ₃ ‧‧‧Intersection of one of the main faces of the internal electrode layer and the perpendicular line Lp ₂

P ₄ ‧‧‧ the intersection of the other main surface of the internal electrode layer and the perpendicular line Lp ₂

Pc ₁ , Pc ₂ ‧‧‧ midpoint

Fig. 1 is a cross-sectional view showing a laminated ceramic electronic component (multilayer ceramic capacitor) according to an embodiment of the present invention.

Fig. 2 is a view showing an enlarged main portion of a multilayer ceramic capacitor according to an embodiment of the present invention.

Fig. 3 is a view for explaining a method of measuring the thickness of a ceramic layer of a multilayer ceramic capacitor according to an embodiment of the present invention.

Fig. 4 is a view for explaining a method of measuring the thickness of the internal electrode layer of the multilayer ceramic capacitor according to the embodiment of the present invention.

Fig. 5 is a view for explaining a method of measuring the distance between points of mutually adjacent ceramic layers of the multilayer ceramic capacitor according to the embodiment of the present invention.

Fig. 6 is a view showing a metal microscope photograph of a cross section (LT cross section) in which a multilayer ceramic capacitor (sample of the example) produced under the condition 1 produced in the example of the present invention is subjected to resin fixation polishing.

Fig. 7 is a view showing a metal microscope photograph of a cross section (LT cross section) in which a multilayer ceramic capacitor (a sample of a comparative example) under the condition 5 produced in the example of the present invention is subjected to resin fixation polishing.

Fig. 8 is a partially broken perspective view showing an example of a prior art laminated ceramic capacitor.

Fig. 9 is an enlarged cross-sectional view showing a main portion of a portion A of the multilayer ceramic capacitor of Fig. 7.

The embodiments of the present invention are disclosed below, and the features of the present invention will be described in more detail.

1 is a cross-sectional view showing a configuration of a multilayer ceramic electronic component (a wafer type multilayer ceramic capacitor) according to an embodiment of the present invention; and FIG. 2 is an enlarged view of a main part thereof.

As shown in FIGS. 1 and 2, the multilayer ceramic capacitor includes a laminate portion 10 having a laminated plurality of ceramic layers 1 and an internal electrode layer 2 between the ceramic layers 1, and an outer layer portion 20 (20a, 20b). It has one or more ceramic layers which are disposed so as to sandwich the laminated portion 10 from the lamination direction and do not include internal electrodes.

Further, in the pair of end faces 31 (31a, 31b) including the laminated body 30 of the laminated portion 10 and the outer layer portion 20 as described above, the respective end portions of the plurality of internal electrodes 2 are exposed, and the internal electrodes 2 are turned on. A pair of external electrodes 33 (33a, 33b) are formed in this manner.

Further, as shown in FIG. 2, the region of the laminated portion 10 including the region adjacent to the region of the outer layer portion 20 constitutes a thermal shock absorbing portion 11 including a curved ceramic layer 1 (1a). And the internal electrode layer 2 (2a) whose thickness is smoothly changed according to the position in the direction along the principal surface of the outer layer portion 20.

Further, as shown in FIG. 2, in the laminated portion 10, a region further inside than the thermal shock relaxing portion 11 constitutes a normal laminated portion 12 including a ceramic layer 1 (1b) which is curved. The degree of change of the thickness of the ceramic layer 1 (1a) and the internal electrode layer 2 (2b) which are less than the thermal shock mitigation portion 11 in accordance with the position in the direction of the main surface of the outer layer portion 20 is smaller than the thermal shock mitigation. Internal electrode layer 2 (2a) of portion 11 (Fig. 2).

Further, the CV value of the thickness of the ceramic layer 1 (1a) existing in the thermal shock absorbing portion 11 is set to be 15% or less.

Further, at least one of the internal electrode layers 2 (2a) existing in the thermal shock absorbing portion 11 is configured such that the CV value of the thickness is 40% or more.

Further, it is configured to be located in the center of the thickness direction of one ceramic layer and the other ceramic layer 2 (2a) when the ceramic layer 2 (2a) adjacent to each other existing in the thermal shock absorbing portion 11 is observed. The CV value of the length of the straight line which is connected along the lamination direction of the laminated portion 10, that is, the distance between the midpoints is 40% or more.

Further, the CV value of the thickness of the ceramic layer 1 (1b) existing in the laminated portion 12 is usually 15% or less.

Further, the CV value of the thickness of the internal electrode layer 2 (2b) existing in the laminated portion 12 is usually 20% or less.

Further, when the ceramic layer 1 (1b) is adjacent to each other in the normal laminated portion 12, the point in the center of the thickness direction of one ceramic layer and the other ceramic layer 1 is along the lamination direction of the laminated portion 10. The length of the connected straight line, that is, the distance between the midpoints, has a CV value of 20% or less.

In the multilayer ceramic capacitor according to the embodiment of the present invention, the ceramic layer 1 (1a) is bent and (2) the thickness is based on the internal electrode layer 2 (2a) along the first layer. Since the position of the inner surface of the inner layer portion 20 is smoothly changed (having a thickness distribution), the thermal shock can be efficiently dispersed, and the thermal shock resistance can be improved.

In particular, when the state of the bending of the ceramic layer 1 (1a) and the change in the thickness of the internal electrode are irregular (random), the thermal shock can be more efficiently dispersed, which is preferable.

In addition, since the internal electrode layer 2 (2b) in the laminated portion 12 and the internal electrode 2 in the internal electrode layer 2 (2a) in the thermal shock absorbing portion 11 are not interrupted, continuity is ensured, so that it can be small and obtained. Larger electrostatic capacitance.

Further, since the ceramic layer 1 (1b), the internal electrode layer 2 (2b), and the intermediate point distance in the normal laminated portion 12 are adjusted as described above, the laminated ceramic having the desired characteristics can be surely provided. Electronic parts.

Further, the CV value of the thickness of the (a) ceramic layer 1 (1a) in the thermal shock absorbing portion 11; (b) the CV value of the thickness of the internal electrode layer 2 (2a); and (c) the CV value of the distance between the points of the ceramic layer 1 (1a) adjacent to each other

It is obtained by the method described below.

Further, generally, the CV value of the thickness of the (a') ceramic layer 1 (1b) in the laminated portion 12; and (C') the CV value of the thickness of the internal electrode layer 2 (2b); and (c') are adjacent to each other. CV value of the distance between points in a pair of ceramic layers 1 (1b)

It is also obtained by the method described below.

<1> Pretreatment of a sample for measuring the thickness of the ceramic layer and the internal electrode layer

By laminating and polishing the laminated ceramic capacitor as a sample (hereinafter also referred to as "resin fixed polishing"), the surface of the laminated ceramic capacitor is parallel to the height (layer) direction and the longitudinal direction (LT surface). ) and expose the obtained polished end face.

However, the thickness can also be measured on a surface (WT surface) in which the elements of the multilayer ceramic capacitor are parallel to the height (layer) direction and the width direction.

On the other hand, 0.5 mol% of an aqueous FeCl ₃ solution (iron chloride solution) was prepared.

Then, the multilayer ceramic capacitor fixed by the resin was immersed in the ferric chloride solution for 30 seconds, and the internal electrode layer (Ni electrode layer) exposed on the polished end surface was eluted (chemical etching).

At this time, since the concave portion is formed on the polishing end surface in accordance with the amount of elution of the internal electrode layer, the interface between the internal electrode layer and the ceramic layer becomes clear.

Further, the polished end face of the multilayer ceramic capacitor subjected to the chemical etching treatment was observed by a SEM (Scanning Electron Microscope), and an SEM image of 3,000 to 5,000 times was obtained.

Next, the measurement described below was carried out using the obtained SEM image.

<2> Determination of the thickness of the ceramic layer

Hereinafter, a method of measuring the thickness of the ceramic layer will be described with reference to Fig. 3 .

A point P _{1 is} appropriately taken at the interface between the ceramic layer 1 (1a, 1b) and the internal electrode layer 2 (2a, 2b), at which point a tangent Lt _{1 is} drawn with respect to the ceramic layer. Lt of _a tangent line with respect to the perpendicular line Lp ₁ make for extended as to face the opposite side of the ceramic layer 1 (interface), the interface of the determined intersection point P _2. By this intersection point P ₂ and tangential to the initial Lt ₁ of parallel lead Lt _2. The distance between the two parallel straight lines Lt ₁ and Lt ₂ was measured, and the thickness of the ceramic layer was determined.

Further, the measurement is performed on the ceramic layer 1 (1a) which is bent by the thermal shock absorbing portion 11, and the layered portion 12 is usually bent to a degree smaller than the ceramic layer 1 (1b) of the ceramic layer 1 (1a) of the thermal shock absorbing portion 11. Each of the ceramic layers was measured at 20 points.

Further, the average value, the standard deviation, and the CV value ((standard deviation/average value) × 100 (%))) of the thickness of the ceramic layer were determined from the measurement data.

Further, in each of the ceramic layer 1 (1a) in which the thermal shock absorbing portion 11 is bent and the ceramic layer 1 (1b) in the laminated portion 12, the three ceramic layers are each measured to determine the maximum. CV value.

<3> Determination of Thickness of Internal Electrode Layer

Hereinafter, a method of measuring the thickness of the internal electrode layer will be described with reference to FIG.

The reference electrode is drawn in such a manner that the inner electrode layer 2, which is a small degree of change in thickness according to the position in the direction of the main surface of the outer layer portion, is substantially parallel to the inner electrode layer 2 (2a) of the laminated portion 12 Lr ₁ (position is arbitrary). In FIG. 4, 20 in the outer portion (20a) drawn reference line Lr _1, but the field of view of SEM image may not include one outer layer portion 20, it may also lead to a build-up portion 10.

Thereafter, a perpendicular line Lp _{2 is} formed with respect to the reference line Lr ₁ . Determination located on the perpendicular line Lp internal _electrode layers 2 (2a, 2b) with a main surface perpendicular Lp those of the other main surface 2 of the intersection point of the perpendicular line Lp by one of ₂ P ₃ and the internal electrode layer ₂ of the point of intersection P The length of the straight line connecting ₄ (i.e., the distance between P ₃ and P ₄ ) is the thickness of the internal electrode layer 2 (2a, 2b).

The internal electrode layer 2 (2a) whose thickness of the thermal shock absorbing portion 11 is smoothly changed, and the degree of thickness change is smaller than the normal laminated portion 12 of the internal electrode layer 2 (2a) of the thermal shock absorbing portion 11. The internal electrode layer 2 (2b) was measured at 20 points for each of the internal electrode layers 2 (2a, 2b).

The average value, standard deviation, and CV value ((standard deviation/average value) × 100 (%)) of the internal electrode layers 2 (2a, 2b) were obtained from this data.

Further, in the internal electrode layer 2 (2a) of the thermal shock absorbing portion 11, and the internal electrode layer 2 (2b) of the laminated portion 12, respectively, three internal electrode layers 2 (2a, 2b) are also formed. The measurement was carried out.

Further, in the internal electrode layer 2 (2a) of the thermal shock absorbing portion 11, the maximum CV value among the three groups is the maximum CV value of the thickness of the internal electrode layer 2 (2a) of the thermal shock absorbing portion 11.

In addition, in the internal electrode layer 2 (2b) of the laminated portion 12, the maximum CV value among the three groups is the maximum CV value of the thickness of the internal electrode layer 2 (2b) of the normal laminated portion 12.

<4> Determination of the distance between the midpoints of ceramic layers adjacent to each other

Hereinafter, a method of measuring the distance between dots in two ceramic layers adjacent to each other will be described with reference to FIG.

The reference line Lr ₂ (arbitrary position) is drawn so as to be substantially parallel to the ceramic layer 1 (1b) of the normal laminated portion 12. In FIG. 5, the reference line Lr _{2 is} drawn from the outer layer portion 20 (20a). However, since the outer layer portion 20 is not included in the field of view of the SEM image, it may be taken out at the layered portion 10.

Thereafter, a perpendicular line Lp _{3 is} formed with respect to the reference line Lr2.

Next, the midpoints Pc ₁ and Pc ₂ of one and the other two ceramic layers 1 (1a, 1b) adjacent to each other are designated. The midpoints Pc ₁ and Pc ₂ are located at the center of the thickness direction of the two ceramic layers 11 (1a, 1b) and are located on the above-mentioned perpendicular line Lp ₃ .

Then, the distance between the designated two midpoints Pc ₁ and Pc ₂ (distance between the midpoints) is measured.

When the distance between the midpoints is measured, the ceramic layer 1 (1a) which is bent by the thermal shock absorbing portion 11 and the ceramic which is bent to a degree smaller than the normal laminated portion 12 of the ceramic layer 1 (1a) of the thermal shock mitigation portion 11 are smaller. For layer 1 (1b), a point of 20 points is adjacent to one of the adjacent ceramic layers. Determination of the distance between the two.

Further, the average value, the standard deviation, and the CV value ((standard deviation/average value) × 100 (%))) of the intermediate point distance were obtained from the measurement data.

Further, in the ceramic layer 1 (1a) which is bent by the thermal shock absorbing portion 11, and the ceramic layer 1 (1b) which is usually the laminated portion 12, the interlayer distance is determined for the ceramic layers of the three groups. Determination. Further, regarding the inter-point distance in the thermal shock mitigation unit 11, the CV value of the maximum midpoint distance among the three groups is obtained, and the normal mid-layer layer 12 is also obtained among the largest midpoints among the three groups. The CV value of the distance.

<5> Method and sequence for grasping the state of the thermal shock absorbing portion and the normal laminated portion in the laminated ceramic electronic component of the present invention

(1) The thickness of the curved ceramic layer and the thickness of the internal electrode layer whose thickness is smoothly changed are measured by the thermal shock absorbing portion by the above method, and the average value, standard deviation, and CV value are obtained ((standard deviation/average value) ) × 100 (%)).

(2) Next, by using the above method, the thickness of the internal electrode layer having a small thickness of the ceramic layer having a small degree of bending of the laminated portion and a small change in thickness depending on the position is measured, and an average value and a standard are obtained. Deviation, CV value ((standard deviation / average) × 100 (%)).

(3) Since the thickness of the ceramic layer and the thickness of the internal electrode layer can be arbitrarily selected, the thickness of the ceramic layer and the thickness of the internal electrode can be defined by the CV value for the thermal shock absorbing portion and the usual laminated portion, respectively.

(4) When the thickness of the ceramic layer is measured, the midpoint of the thickness can be obtained. Therefore, by the above method, the distance between the points of the adjacent ceramic layers is measured for the thermal shock absorbing portion and the normal laminated portion, and the average value and the standard deviation are obtained from the obtained measurement data, and the CV value is calculated from the standard deviation. .

(5) Further, the CV value of the distance between the points of the thickness of the ceramic layer is different between the normal laminated portion and the thermal shock absorbing portion, and it is understood that the ceramic layer of the thermal shock absorbing portion is curved and The difference in CV value indicates the degree of bending (condition).

Further, the CV value of the thickness of the internal electrode layer of the thermal shock relaxation portion exceeds 20%, and it is understood that the position of the thickness of the internal electrode layer varies depending on the position in the direction of the main surface of the outer layer portion; depending on the thickness of the internal electrode layer When the CV value is 40% or more, it is known that it has a sufficient thickness distribution.

Hereinafter, the present invention will be more specifically described by showing an embodiment.

[Examples]

In this embodiment, a wafer type multilayer ceramic capacitor is produced as a laminated ceramic electronic component, and the relationship between the firing rate of the baking in the baking step and the structure of the laminated portion, the crack generation rate in the thermal shock test, and the electrostatic capacitance are examined.

(A) Fabrication of ceramic raw material powder for ceramic layer (dielectric layer)

First, a raw material powder (ceramic raw material powder) for a ceramic layer functioning as a dielectric layer is produced in the following order.

First, BaCO ₃ powder and TiO ₂ powder were weighed so that the ratio of Ba to Ti (Ba/Ti) became 1.001, and wet pulverization and mixing were carried out by using a zirconia ball mill.

Thereafter, the mixture was dried, heated to 900 ° C or higher, and heat-treated (pre-fired) to prepare a calcium-titanium-iodine composite oxide (BaTiO ₃ -based ceramic powder) having an average particle diameter of 0.20 μm.

0.6 mol of Dy ₂ O ₃ , 1.2 mol of MgCO ₃ , 0.2 mol of MnCO ₃ , 1.0 mol of BaCO were added as a powder to 100 parts per million of the BaTiO ₃ -based ceramic powder. _3, in terms of SiO ₂ was further added 0.7 parts by mole of SiO ₂ sol, zirconia balls by using the pulverizing mill and mixed, thereby making the ceramic powder of ceramic raw material layer (dielectric layer) with it.

(B) Production of Ni cream

Ni powder having an average particle diameter of 0.25 μm, an organic vehicle (ethylcellulose/rosinol = 1/9 (weight ratio)), and rosin were mixed, and dispersed and mixed using a three-roll mill to prepare A Ni paste for the formation of an internal electrode layer.

(C) Fabrication of multilayer ceramic capacitors

(C-1) A polybutyraldehyde-based binder and a plasticizer are added to the ceramic raw material powder prepared in the above manner, and toluene and ethanol are added, and the slurry is made by using a zirconia (ZrO ₂ ) ball mill. The sheet was formed into a sheet having a thickness of 1.9 μm by a gravure coater, whereby a ceramic green sheet was obtained.

After (C-2), the Ni paste prepared in the above manner was screen-printed on the ceramic green sheet to form a conductive paste pattern to be an internal electrode (layer).

(C-3) Thereafter, a ceramic green sheet having a conductive paste pattern was formed, and 300 sheets were laminated in such a manner that the sides of the conductive paste pattern were alternately turned to the opposite side. In addition, a ceramic green sheet for a layer portion other than the conductor paste pattern (internal electrode layer) in which a specific sheet is not formed is deposited so as to sandwich the formed laminated structure from both sides, thereby forming a laminated block.

After (C-4), the laminated body was cut into a laminated body (raw layer wafer) having a length L of 2.0 mm and a width W of 1.25 mm after being densified by sintering.

Further, the obtained green laminated wafer was heated to 280 ° C in a stream of N ₂ to burn off the binder. Then, heating is continued in the N ₂ -H ₂ -H ₂ O gas flow until it is 1000 ppm or less in terms of carbon, and the binder is sufficiently burned and removed.

(C-5) Thereafter, calcination was carried out in N ₂ under conditions of an average temperature increase rate of 40 ° C / sec, a maximum temperature of 1220 ° C, and a residence time of 10 seconds, thereby obtaining a laminated body having a sintered end (layered ceramics) Capacitor component).

After (C-6), a conductive paste containing copper as a main component was applied to the end surface of the laminated internal electrode layer of the laminate, and baked at 800 ° C to form an external electrode. Further, a Ni plating film or a Sn plating film was sequentially formed on the surface of the external electrode by wet plating.

As a result, as shown in FIGS. 1 and 2, it is possible to obtain a structure in which a pair of external electrodes 33 (33a, 33b) are disposed such that the inner electrode 2 and the laminated body 30 are electrically connected to the end faces 31 (31a, 31b). In the multilayer ceramic capacitor, the laminated body 30 includes: a laminate portion 10 having a laminated layer The plurality of ceramic layers 1 and the internal electrode layer 2 between the ceramic layers 1 and the outer layer portion 20 (20a, 20b) have a ceramic layer disposed so as to sandwich the laminated portion 10.

Further, the thickness (e.g. thickness) of the ceramic layer (dielectric layer) of the obtained multilayer ceramic capacitor was 1.6 μm.

Further, in this example, as described above, firing was carried out under the conditions of an average temperature increase rate = 40 ° C / sec (Condition 1) to prepare a laminated ceramic capacitor, but it was also baked under the following conditions 2 to 5; And make a multilayer ceramic capacitor.

Average heating rate: 100 ° C / sec (condition 2)

Average heating rate: 270 ° C / sec (condition 3)

Average heating rate: 5 ° C / sec (condition 4)

Average heating rate: 0.17 ° C / sec (condition 5)

In addition, the multilayer ceramic capacitors of the conditions 2 to 5 were produced under the conditions of the above condition 1 except that the average temperature increase rate was different as described above.

(D) Characteristic evaluation

Each of the multilayer ceramic capacitors produced under the conditions of the above conditions 1 to 5 was subjected to resin fixed polishing for 100 samples, and the end faces (LT end faces) of the multilayer ceramic capacitor were exposed as polishing end faces, and were exposed by a metal microscope. The state of the ceramic layer and the internal electrode layer in the region from the outer layer to the center of the buildup portion was confirmed.

Further, regarding each of the multilayer ceramic capacitors, 100 multilayer ceramic capacitors were subjected to a thermal shock test immersed in a solder bath of 325 ° C for 2 seconds, and the presence or absence of cracks was observed by metal microscope observation.

Further, regarding each of the multilayer ceramic capacitors, the electrostatic capacitance was measured for each of 100 samples using an LCR measuring instrument at 120 Hz and 0.5 Vrms.

Further, the multilayer ceramic capacitor produced under the above condition 1 (average temperature increase rate = 40 ° C / sec) was subjected to resin fixed polishing, and the exposed polished end face (LT end face) was exposed. The micrograph photo is shown in Figure 6.

Further, Table 1 shows the following values obtained for the multilayer ceramic capacitor produced under the conditions of the above conditions 1 to 5: (a) CV value of the thickness of the ceramic layer 1 (1a) in the thermal shock absorbing portion 11 ( (b) the CV value (the maximum value) of the thickness of the internal electrode layer 2 (2a) in the thermal shock mitigation portion 11; (c) a ceramic layer adjacent to each other in the thermal shock mitigation portion 11 The CV value (the maximum value) of the distance between the midpoints of 1(1a); (d) the CV value (the maximum value) of the thickness of the ceramic layer 1 (1b) in the laminated portion 12; (e) the usual laminated portion The CV value (the maximum value) of the thickness of the internal electrode layer 2 (2b) in 12; (f) the CV value of the distance between the midpoints of one of the ceramic layers 1 (1b) adjacent to each other in the laminated portion 12 ( (max) (g) the rate of occurrence of cracks in the thermal shock test; (h) the value of the electrostatic capacitance.

The multilayer ceramic capacitor under the condition 1 of Table 1 was a multilayer ceramic capacitor produced by the step of firing at a temperature increase rate of 40 ° C / sec.

Further, as shown in Table 1, the CV value (maximum value) of the thickness of the ceramic layer 1 (1a) of the thermal shock absorbing portion 11 is 15%, and the CV value (maximum value) of the thickness of the internal electrode layer is 45%; The CV value (maximum value) of the inter-point distance when one ceramic layer 1 (1a) adjacent to each other was observed was 46%.

Further, in the laminated portion 12, the CV value (maximum value) of the thickness of the ceramic layer 1 (1b) is 15%; the CV value (maximum value) of the thickness of the internal electrode layer 2 (2b) is 20%; The CV value (maximum value) of the inter-point distance when one ceramic layer 1 (1b) was observed was 20%.

In other words, in the multilayer ceramic capacitor of the first aspect, as shown in FIG. 6 and FIGS. 2 to 5, the vicinity of the layer portion including the region adjacent to the outer layer portion 20 constitutes the thermal shock absorbing portion 11, and the thermal shock absorbing portion 11 includes The curved ceramic layer 1 (1a) and the inner electrode layer 2 (2a) whose thickness is smoothly changed according to the position in the direction of the main surface of the outer layer portion 20; and the region closer to the inner side than the thermal shock absorbing portion 11 The normal laminated portion 12 is configured to include an internal electrode layer having a thickness which is smaller than a position along the main surface of the outer layer portion 20 by a thickness smaller than that of the internal electrode layer 2 (2a) of the thermal shock absorbing portion 11. 2 (2b). Further, the internal electrode layers 2 (2a, 2b) are uninterrupted and have high continuity.

As a result, in the case of the multilayer ceramic capacitor under the condition 1, it was confirmed that the thermal shock resistance was excellent as shown in Table 1, and no crack occurred in the thermal shock test, and a large electrostatic capacitance was obtained.

Further, in the case of the multilayer ceramic capacitor under Condition 1, the state of the bending of the ceramic layer 1 (1a) in the impact relaxing portion 11 and the internal electrode layer 2 can be seen from the metal micrograph of FIG. 6 and FIGS. 2 to 5. The state of the change in the thickness of (2a) is irregular (random), and it is considered that a higher thermal shock resistance is achieved.

Further, in the case of the multilayer ceramic capacitor under the condition 2 in which the average temperature increase rate in the baking step is 100 ° C / sec and the average temperature increase rate is 270 ° C / sec, as shown in Table 1, It is to be noted that the ceramic layer and the internal electrode layer in the thermal shock absorbing portion and the usual laminated portion satisfy the requirements of the present invention, and it is confirmed that the thermal shock resistance is excellent and is in the thermal shock test as in the case of the laminated ceramic capacitor under Condition 1. There is also no crack and a large electrostatic capacitance.

On the other hand, in the case where the average temperature increase rate in the baking step is set to 5 ° C / sec 4 and the average temperature increase rate is set to 0.17 ° C / sec under the condition of the multilayer ceramic capacitor 5, as shown in Table 1, heat The CV value (the maximum value) of the thickness of the ceramic layer in the impact relaxation portion, the CV value (the maximum value) of the thickness of the internal electrode layer, and the CV value of the distance between the points of the ceramic layers adjacent to each other ( Any of the maximum values did not satisfy the requirements of the present invention, and it was confirmed that the obtained electrostatic capacitance was small and cracks were generated in the thermal shock test. Further, the reason why the electrostatic capacitance in the multilayer ceramic capacitors under the conditions 4 and 5 is small is considered to be due to the internal electrode layer discontinuity and the occurrence of cracks.

In addition, FIG. 7 is a metal micrograph showing the polished end face (LT end face) exposed by resin fixation polishing of the multilayer ceramic capacitor produced under the condition 5 (average temperature increase rate = 0.17 ° C / sec).

As can be seen from Fig. 7, the thermal shock absorbing portion 11 formed in the case of the multilayer ceramic capacitor (Fig. 6) produced under the condition 1 is not formed in the case of the multilayer ceramic capacitor fabricated under the condition 4, and is formed in the laminated portion 10 The internal electrode layer is intermittent.

In the above embodiments and examples, the multilayer ceramic capacitor has been described as an example. However, the present invention is not limited to the multilayer ceramic capacitor, and can be applied to a plurality of ceramic layers having a buildup layer and an internal electrode layer between the ceramic layers. Various laminated ceramic electronic parts such as laminated LC composite parts or laminated varistor.

The present invention is not limited to the above-described embodiments and examples, and the material or the number of layers constituting the ceramic layer and the internal electrode layer, the constituent materials or the arrangement of the internal electrodes or the external electrodes, and the like can be Various applications and modifications are possible within the scope of the invention.

1 (1a, 1b) ‧ ‧ ceramic layer

2 (2a, 2b) ‧ ‧ internal electrode layer

10‧‧‧Ministry Department

11‧‧‧ Impact mitigation department

12‧‧‧ Usually the Ministry of Construction

30‧‧‧Layered body

Lp ₁ ‧‧‧ perpendicular to the tangent line Lt ₁

Lp ₂ ‧‧‧ vertical line of reference line Lr ₁

Lt ₁ ‧‧‧ tangent to the ceramic layer

Lt ₂ ‧‧‧ parallel to the tangent Lt ₁

P ₁ ‧‧‧ Appropriate points of the interface between the ceramic layer and the internal electrode layer

P ₂ ‧‧‧ the intersection of the opposite side of the ceramic layer and the interface of the internal electrode layer

Claims (3)

A laminated ceramic electronic component, comprising: a laminated portion having a laminated plurality of ceramic layers and an internal electrode layer between the ceramic layers; and an outer layer portion having a self-clamping direction One or more ceramic layers disposed as described above, wherein the laminated portion includes a thermal shock absorbing portion in a vicinity of an outer layer portion adjacent to the outer layer portion, and the thermal shock absorbing portion The inner ceramic layer that is curved and has a thickness that changes smoothly according to a position along a main surface of the outer layer portion; and a region that is further inside than the thermal shock absorbing portion constitutes a normal laminated portion The normal laminated portion includes: the ceramic layer having a degree of bending smaller than the ceramic layer of the thermal shock absorbing portion; and the internal electrode layer having a thickness according to a position along a direction of a main surface of the outer layer portion The degree of change is smaller than the internal electrode layer of the thermal shock absorbing portion; and the thickness of the ceramic layer in the thermal shock absorbing portion The CV value is 15% or less, and the CV value of the thickness of the inner electrode layer of at least one layer is 40% or more, and is located in the thickness direction of one ceramic layer and the other ceramic layer when viewed from adjacent one ceramic layer. The length of the straight line connecting the points in the center of the layered portion, that is, the distance between the midpoints, is 40% or more. The multilayer ceramic electronic component according to claim 1, wherein in the normal laminated portion, the CV value of the thickness of the ceramic layer is 15% or less, and the CV value of the thickness of the internal electrode layer is 20% or less, which is adjacent to each other. When the ceramic layer is observed, it is located in a ceramic layer and another pottery The length of the straight line connecting the points in the thickness direction of the porcelain layer in the lamination direction of the laminated portion, that is, the CV value of the distance between the midpoints is 20% or less. A multilayer ceramic electronic component according to claim 1 or 2, which is a surface mount type multilayer ceramic capacitor.