TW201407731A - Semiconductor assembly with dual connecting channels between interposer and coreless substrate - Google Patents

Abstract

A semiconductor assembly includes a semiconductor device, a through-via interposer, a coreless substrate and a stiffener. The semiconductor device is flip mounted on the interposer, and the interposer is affixed on the coreless substrate by adhesive and extends into an aperture of a stiffener which provides mechanical support for the coreless substrate. The electrically connection between the interposer and the coreless substrate includes bond wire and conductive micro-via. The coreless substrate can provide fan-out routing for the interposer.

Description

a semiconductor package having a double connection channel between the interposer and the coreless substrate

The present invention relates to a semiconductor assembly, especially to an intermediary The semiconductor package has a semiconductor component flip-chip mounted thereon, wherein the interposer is fixed on a coreless substrate. The interposer has a perforation, and the interposer and the connection between the coreless substrates are flexibly connected via conductive micropores and wire bonding.

High-performance semiconductor wafers typically use a low-k value The electrical layer acts as an intermediate layer material. When a dielectric material having a low k value is porous, fragile, and very sensitive to interface stress, a conventional flip chip package having a laminated substrate faces a thermal expansion coefficient between the low-k wafer and the laminated substrate. Matching leads to various reliability issues as well as yield issues. In order to solve the above problems, attempts have been made to reduce the interface stress by bonding an interposer (e.g., tantalum) matching the thermal expansion coefficient between the wafer and the laminated substrate. In addition, the interposer can provide ultra-fine circuit routing. Therefore, before the wafer is connected to the laminated substrate via the via, a plurality of wafers are first placed on the substrate. On the interposer, a method of preparing a semiconductor body for preparing a high bulk density and improving properties has been attracting attention.

In addition, provide intermediate layer mechanical support and signal routing The laminate substrate typically includes a double-sided circuit board "core layer" having a plurality of "layered" structures on each side of the core layer. The double-sided core layer uses a plurality of coated perforations as internal vertical connections, and a build-up structure having micropores as a layer-to-layer connection. For example, a 4-2-4 substrate refers to a two-layer core layer having four build-up structures attached to each face. In order to reduce the warpage deformation of a package substrate, a thickness of about 0.8-0.4 mm is usually used. The core layer. The use of thick core layers reduces the problem of warpage, but high performance components are almost impossible to achieve for shorter routing lengths. To solve this problem, a long-term research has developed a coreless substrate with a variety of reinforcing supports to minimize warpage and deformation.

Therefore, it has a thermal expansion coefficient similar to that of the tantalum wafer. It is highly desirable to have a perforated interposer to address problems in yield and reliability, and to use a coreless substrate without a core layer to improve the electrical performance of the assembly.

U.S. Patent No. 7,738,258 to Ohno et al., Lee U.S. Patent No. 8, 183, 678, U.S. Patent No. 8,379,400 to Sanuhara, U.S. Patent No. 8,384, 225 to Rahman et al., and U.S. Patent No. 8,310,063, the disclosure of which is incorporated herein by reference. Stacked between the wafer and the laminate substrate to provide a lateral direction and a vertical connection. Although the perforation of the intercalation layer can improve the performance of the system, when the density of the perforations is very high, the phase between the perforations Mutual interference will be a major limiting factor. In addition, through-holes with small diameters and high-density vias will increase production costs, and the price of the product will increase due to low yield.

U.S. Patent No. 6,570,248 to Ahn et al. U.S. Patent No. 7, 750, 452 to Do, et al., and U.S. Patent No. 8,263,434, the disclosure of which is incorporated herein by reference. A plurality of perforations formed through the interposer for micromachining are used to pair a plurality of semiconductor elements on opposite surfaces of the interposer. Such a structure provides excellent electrical performance between the attached components. However, the conventional bonding technique to connect the interposer and the laminated substrate suffers from performance limitations and can only accommodate a lower number of lead modules. In addition, when the crucible and the resin substrate have different coefficients of thermal expansion, and the interposer hardly adheres to the side walls of the surrounding substrate, the fragility caused by insufficient support, and the thermal cycling process due to the excessively thin and brittle nature of the interposer Problems such as cracks are easily generated, making the preparation of such a structure prohibitive and impractical.

U.S. Patent No. 7,902,660 to Lee et al., Lin et al. U.S. Patent No. 7, 754, 598, U.S. Patent No. 8, 227, 703 to Maruyamo et al., U.S. Patent Application Serial No. 2012/0005, the entire disclosure of U.S. Pat. Coreless substrate structure. Some coreless substrates may have acceptable coplanar properties via improvements in reinforcement materials or structures, however warpage is typically repeated when the substrate size reaches a certain size or when the substrate is subjected to high temperature processing during the assembly process. occur. For example, when packaging a semiconductor wafer greater than 10 square millimeters, the coplanar nature of the substrate may increase to more than 30 microns after solder reflow, which is unacceptable for packaging requirements.

Gritti's US Patent No. 7,605,476, Lim's United States No. 7, 663, 245, U.S. Patent No. 8,372, 692 to Liou et al., and U.S. Patent No. 7,309,913 to the disclosure of U.S. Pat. When perforating to provide the shortest path in the vertical direction, the signal integrity of the group components will be adversely affected when the system needs to transmit or receive high frequency signals.

Although multiple uses of active or passive have been reported in the literature With the layered architecture, many performance or reliability issues remain. For example, although a resin material is used to fill its interface to enhance its structure, soldering between the interposer and the package substrate may have reliability problems.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor package in which the semiconductor element is flip-chip mounted on an interposer which is fixed to a coreless substrate which is a mechanical support. A reinforcing layer as the interposer and the further support of the coreless substrate can be used to suppress warpage and bending of the assembly. The reinforcing layer has a through hole, and the interposer extends into the through hole of the reinforcing layer and is electrically connected to the coreless substrate. The electrical connection between the interposer and the coreless substrate is via one or more conductive vias in the interposer and the coreless substrate One or more conductive micropores are flexibly coupled, and are directly connected to the coreless substrate by one or more mechanically formed wires, thereby reducing the number of the conductive vias of the interposer, and It is required to balance the use of wire bonding, thereby improving the productivity of the assembly and obtaining an affordable cost. For example, the power/ground I/Os of the semiconductor components can be connected via conductive vias, and the I/Os of the signals can be connected via wire bonding, and vice versa. Accordingly, the present invention provides a composite circuit board and a semiconductor package including a semiconductor component electrically connected to a composite circuit board, wherein the composite circuit board includes an interposer, a coreless substrate, and a reinforcement layer .

In a preferred embodiment, such as a microprocessor, a controller, Or a semiconductor component of the memory chip, which is flip-chip mounted on the first surface of the interposer via a bump array. However, in most cases, more than one wafer will need to be connected to the interposer. For example, a logic chip may connect four memory chips to process data quickly, or an array of segmented logic chips are connected to each other on an interposer, which reduces the cost compared to fabricating a single large wafer. The bumps can be solder, gold, or solder coated copper posts, and the choice of bumps can depend on their spacing requirements. For example, in an element having a very fine pitch, it is preferable to use a copper pillar coated with solder because the solder is collapsed in a small amount during the solder reflow process to avoid bridging between the solders.

The interposer can be made of tantalum, ceramic, or glass, and The opposite surfaces have a plurality of contact pads. Specifically, in the interposer, one of the first surfaces facing a first vertical direction may include a plurality of first contact pads, and one or more bond fingers, and facing a second drop One of the second surfaces of the straight direction has a plurality of second contact pads. The first contact pad on the first surface can be electrically connected to the second contact pad corresponding to the second surface via a vertical connecting component (such as a conductive via). Alternatively, the first contact pad on the first surface can be electrically connected to the bonding finger on the first surface via a lateral circuit formed in the interposer. The circuitry in the interposer can have one or more wiring layers and can distribute signals to other locations in a lateral direction at one location. Thus, a portion of the first contact pad can be vertically connected to the second contact pad on the second surface via the conductive via, and the other portion of the first contact pad can be electrically coupled to the bond finger of the first surface. According to this, in the flip chip package, after the semiconductor component is connected to the first contact pad of the interposer, the I/O pad of the flip-chip semiconductor component can be connected to the interposer via the conductive via. a second contact pad, which is then connected to the coreless substrate via conductive microvias, or can be connected to the bonding finger, the bonding finger replacing the conductive via in the interposer with a wire to electrically connect to the coreless substrate . More specifically, the first contact pad at the peripheral edge of the flip chip can transmit/receive electronic signals from the circuit, the conductive vias, and the second contact pads, or can transmit/receive from the circuit, the bonding fingers, and The electronic signal of the line. Although the interposer described in this embodiment is an inactive element, it should be understood that the interposer may include a transistor integrated in the interposer, such that the interposer may become an active semiconductor. element.

The wire can be composed of gold, aluminum, copper, or an alloy thereof. The fight a wire system as the interposing layer and a connecting passage between the coreless substrates, and may have one end of the engaging finger contact with one of the interposing layers, and the coreless base One of the plates is connected to the other end of the pad.

The connection pad of the coreless substrate may be composed of metal. Example For the purpose of joining, the connection pad can consist essentially of copper, as well as nickel, palladium, gold coated copper, or alloys thereof. The wire may be exposed from the surface of the coreless substrate in the first vertical direction, and aligned with the through hole of the reinforcing layer and extending to the through hole of the reinforcing layer. More specifically, the connection pad may be laterally aligned laterally in a lateral direction to a peripheral edge of the interposer and a sidewall of the via of the reinforcement layer, and in a lateral direction from a peripheral edge of the interposer and the reinforcement layer The side walls of the through hole extend laterally. The connection pad is electrically connected to the connection pad of the interposer via the wire, or can be electrically connected to the circuit of the coreless substrate via the conductive micro hole in the coreless substrate.

The coreless substrate can cover the intermediary in the second vertical direction And a reinforcement layer and including one or more connection pads, a first dielectric layer, and one or more first wires. For example, the first dielectric layer covers the interposer, the connection pad, and the reinforcement layer in the second vertical direction, and extends to the peripheral edge of the group. The first dielectric layer includes one or more first microvias, and the microvias are disposed adjacent to the connection pads and the second contact pads of the interposer, and are selectively adjacent to the reinforcement layer. One or more first wires are disposed on the first dielectric layer (eg, extending from the first dielectric layer toward the second vertical direction and laterally extending on the first dielectric layer) and The first vertical direction extends into the first microvia to form one or more conductive microvias, and the conductive microvia is electrically connected to the connection pad and the second contact pad, thereby providing the connection pad and the interposer The second contact The signal of the pad is routed and the electrical connection of the reinforcement layer is selectively provided. Specifically, the first wire can directly contact the connection pad and the second contact pad to provide signal routing of the interposer, so that the electrical connection between the interposer and the coreless substrate can be bidirectional Channel and can be solder free. The first wire may also directly contact the reinforcing layer as a ground or be electrically connected as a passive component such as a thin film transistor or a capacitor disposed on the reinforcing layer.

The coreless substrate can include additional dielectric layers, additional microporous layers, and additional wire layers if further signal routing requirements are required. For example, the coreless substrate may further include a second dielectric layer, one or more second micro holes, and one or more second wires. The second dielectric layer having one or more second micro holes disposed therein is disposed on the first dielectric layer and the first conductive line (eg, from the first dielectric layer and the first conductive line The second vertical direction extends and extends to the peripheral edge of the group. The second microvia is disposed adjacent to the first wire. One or more second wires are disposed on the second dielectric layer (eg, extending from the second dielectric layer toward the second vertical direction and laterally extending on the second dielectric layer), and Extending into the second micro-hole in the first vertical direction to provide an electrical connection of the first wire. In addition, the first micro hole and the second micro hole may have the same size, and the first dielectric layer, the first wire, the second dielectric layer, and the second wire may have an elongated and flat shape. a surface facing the second vertical direction.

The coreless substrate may include one or more internal connection pads to provide a lower level assembly (such as a motherboard), and/or another electronic component (such as a semiconductor component), Or an electrical connection of another semiconductor body (such as a BGA semiconductor package). The inner connection pad may extend to the first wire in the second vertical direction or extend beyond the first wire and include a contact surface that is exposed toward the second vertical direction. For example, the inner connection pad can abut and be integrally formed with the second wire. In addition, the first wire and the second wire can provide electrical connection between the inner connection pad, the connection pad, and the second contact pad of the interposer. Therefore, the electrical connection point (for example, the first contact pad of the interposer and the inner connection pad of the coreless substrate) can be electrically connected to each other and located on the opposite surface facing the opposite vertical direction, so that Or a plurality of semiconductor wafers may be flipped onto a semiconductor package.

The reinforcing layer has a through hole and can extend to a peripheral edge of the group to provide mechanical support of the coreless substrate and the interposer, and the reinforcing layer can be a single layer structure or a multilayer structure (for example, a circuit board) , or a multilayer ceramic plate, or a laminate of a substrate and a conductive layer). The reinforcing layer may be made of ceramic, metal, or other inorganic materials such as alumina (Al ₂ O ₃ ), aluminum nitride (AlN), tantalum nitride (SiN), bismuth (Si), copper (Cu), Copper alloy (for example: Cu/Mo/Cu), aluminum (Al), stainless steel, and the like. The reinforcing layer can also be made of an organic material such as a copper foil laminate.

The coreless substrate of the present invention may further include a certain a positioning member is disposed as a guiding guide of the interposing layer, and is laterally aligned with a peripheral edge of the interposer and the connecting pad, and extends at a peripheral edge of the interposer and outside the connecting pad to Prevents unnecessary displacement of the interposer when the interposer is attached. In any case, the interposer and the positioning member can be aligned with the through hole of the reinforcing layer and extend into the adding The through hole of the strong layer. The keeper can be made of a metal such as copper, aluminum, nickel, iron, tin, or alloys thereof.

The coreless substrate of the present invention may further comprise a configuration guide, the addition The arrangement of the strong layer may be adjacent to a peripheral edge of the reinforcing layer, laterally aligned with a peripheral edge of the reinforcing layer, and extending outwardly of a peripheral edge of the reinforcing layer. Like the positioning member, the reinforcing layer can be made of a metal such as copper, aluminum, nickel, iron, tin, or an alloy thereof.

The positioning member, the configuration guide, and the connection pad are in contact The first dielectric layer of the coreless substrate extends from the first dielectric layer of the coreless substrate toward the first vertical direction and can be formed of the same material (such as copper) at the same time. Additionally, the keeper and the arranging guide can have a pattern to avoid unnecessary movement of the interposer and the reinforced layer, respectively. For example, the locating member and the arranging guide can comprise a continuous or discontinuous strip or stud array, the locating member and the arranging guide being simultaneously formed and having the same or different patterns. Specifically, the positioning member can laterally align the four side surfaces of the interposer to stop lateral displacement of the interposer. For example, the positioning member may be aligned along four sides, two diagonals, or four corners of the interposer, and the gap between the interposer and the positioning member is preferably in the range of about 0.001 to 1 mm. The interposer can maintain a distance from the inner wall of the through hole by the positioning member and the connecting pad, and a bonding material can be added between the interposer and the reinforcing layer to increase the rigidity thereof. Similarly, the arrangement guides can be laterally aligned with the four outer side surfaces of the reinforcement layer to stop lateral displacement of the reinforcement layer. For example, the configuration guide can be aligned along four outer sides, two outer diagonals, or four outer corners of the reinforcement layer, and the periphery of the reinforcement layer The gap between the edge and the arrangement guide is preferably in the range of about 0.001 to 1 mm. Further, the positioning member and the arrangement guide preferably have a thickness in the range of 10 to 200 μm.

The interposer and the reinforcement layer can be fixed using an adhesive And mechanically connected to the first dielectric layer of the coreless substrate. The adhesive may contact the interposer, the reinforcement layer, the positioning member, the arrangement guide, and the first dielectric layer, and between the interposer and the coreless substrate, and between the reinforcement layer And between the coreless substrates. In any case, the adhesive may be coplanar with the positioning member, the arrangement guide, and the connecting pad in the second vertical direction, and lower than the positioning member, the configuration guide, And the connection pad. When the interposer and the adhesive under the reinforcement layer are lower than the positioning member and the arrangement guide in the first vertical direction, the positioning member and the arrangement guide can prevent the interposer and the reinforcement layer from being Unwanted displacement caused by curing of the adhesive.

The invention also provides a three-dimensional semiconductor component, wherein The interposer is an active semiconductor component. In such an application, a first semiconductor component, such as a wafer, can be electrically connected to the first contact pad of the interposer (eg, a semiconductor wafer) exposed by the via of the enhancement layer using a variety of connection media. The bonding medium includes gold, solder, or copper stud bumps.

The invention has many advantages in the conductive wear in the interposer The holes improve the stability of the power supply to the attached wafer. In addition to the perforations in the interposer, the wires can provide an alternative interconnect path between the interposer and the coreless substrate, thereby reducing the number of perforations required in the interposer. Therefore, the size of the interposer can be reduced, or due to the lower perforation in the interposer Degree, can increase the yield of the product. Therefore, increasing the wire bonding can significantly reduce the cost of the interposer and the semiconductor package. The positioning member of the coreless substrate can accurately limit the placement position of the interposer to avoid the electrical connection error between the interposer and the coreless substrate due to the lateral displacement of the interposer, thereby greatly improving Product yield. The electrical connection between the interposer and the coreless substrate is directly connected without solder, and thus is advantageous for exhibiting high I/O value, high performance, and high reliability. The reinforcement layer provides a power/ground platform, a heat sink, and the interposer and stable mechanical support of the coreless substrate. The semiconductor package using the same is highly reliable, inexpensive, and very suitable for mass production.

101‧‧‧Composite circuit board

113‧‧‧ Positioning parts

111‧‧‧Connecting mat

131‧‧‧Adhesive

11‧‧‧metal layer

115‧‧‧Configure guides

110, 210‧‧‧ semiconductor group

23‧‧‧Support board

20‧‧‧ Coreless substrate

293‧‧‧ openings

241‧‧‧First wire

24‧‧‧covered layer

21‧‧‧First dielectric layer

281‧‧‧second wire

284‧‧‧Internal connection pad

261‧‧‧Second dielectric layer

213‧‧‧ first micropores

291‧‧‧ solder mask material

243‧‧‧First conductive micropores

263‧‧‧Second micropores

283‧‧‧Second conductive micropores

310‧‧‧Three-dimensional body

311‧‧‧ first surface

313‧‧‧ second surface

31‧‧‧Intermediary

312‧‧‧First contact pad

314‧‧‧Second contact pad

321‧‧‧Line

318‧‧‧Electrical perforation

316‧‧‧ joint finger

320‧‧‧lateral circuit

41‧‧‧ Strengthening layer

411‧‧‧through hole

51, 53‧‧‧ semiconductor wafer

61, 63‧‧‧ solder bumps

71‧‧‧ Sealing material

81‧‧‧ Heat sink

801‧‧‧ Thermal Adhesive

The invention will be more apparent from the following detailed description of the preferred embodiments, wherein: FIG. 1A-1J is an embodiment of the invention including an interposer, a semiconductor wafer, and a reinforcement. A cross-sectional view of a method of fabricating a layer and a semiconductor package electrically connected to one of the interposer coreless substrates.

1K is a cross-sectional view of a three-dimensional assembly including semiconductor elements attached to both sides of a composite circuit board in an embodiment of the present invention.

2 is a cross-sectional view of a three-dimensional assembly of an embodiment of the present invention with an additional internal connection between the reinforcing layer and the coreless substrate, and a heat sink attached to the semiconductor wafer and the reinforcing layer. .

Hereinafter, embodiments will be provided to explain the present invention in detail. The implementation of the situation. Other advantages and utilities of the present invention will be more apparent from the teachings of the present invention. It should be noted that the drawings are simplified in the drawings, and the number, shape, and size of components shown in the drawings may be modified according to actual conditions, and the configuration of components may be more complicated. Other variations and modifications can be made without departing from the spirit and scope of the invention as defined in the invention.

[Example 1]

1A-1J are half of an embodiment of the present invention In the method of manufacturing a conductor assembly, the semiconductor package includes an interposer, a semiconductor wafer, a reinforcement layer, and a coreless substrate electrically connected to the interposer via wire bonding and conductive microvias.

As shown in FIG. 1J, the semiconductor package 110 includes an interposer 31, a reinforcement layer 41, a semiconductor wafer 51, a coreless substrate 20, and a wire 321 . The interposer 31 includes a first surface 311, a second surface 313 opposite the first surface 311, a first contact pad 312 on the first surface 311, and a bonding finger 316, and a second contact pad 314 on the second surface 313. And a conductive via 318 partially connected to the first contact pad 312 and the second contact pad 314, and a lateral circuit 320 electrically connected to the bonding finger 316 and a portion of the first pad 312. The interposer 31 can be an interposer, a glass interposer, or a ceramic interposer, which includes a wire pattern that is fanned out to the second contact pad 314 by the fine pitch of the portion of the first contact pads 312. The coarse pitch, and further includes a pattern of conductors extending laterally from the portion of the first contact pad 312 to the bond fingers 316. The coreless substrate 20 is electrically connected to the interposer 31, And including a connection pad 111, a positioning member 113, a configuration guide 115, a first dielectric layer 21, a first wire 241, a second dielectric layer 261, and a second wire 281. The positioning member 113 extends from the first dielectric layer 21 in the upward direction and is adjacent to the peripheral edge of the interposer 31. The connection pad 111, the positioning member 113, and the interposer 31 are aligned with the through holes 411 of the reinforcing layer 41 and extend into the through holes 411 of the reinforcing layer 41.

1A is a cross-sectional view of a laminated substrate, the laminated substrate package The metal layer 11, the first dielectric layer 21, and the support plate 23 are included. The metal layer 11 shown in the drawing is a copper layer having a thickness of 35 μm. However, the metal layer 11 can also be various metal materials and is not limited to the copper layer. In addition, the metal layer 11 can be deposited on the dielectric layer 21 by various techniques, including lamination, electroplating, electroless plating, evaporation, sputtering, and combinations thereof to deposit a single layer or a plurality of layers, and the thickness thereof is relatively thin. Preferably in the range of 10 to 200 microns.

The first dielectric layer 21 is typically made of epoxy, glass epoxy, polyimide, and the like, and has a thickness of 50 microns. In this embodiment, the first dielectric layer 21 is interposed between the metal layer 11 and the support plate 23. However, the support plate 23 may be omitted in some aspects. The support plate 23 is usually made of copper, but copper alloy and other materials can be used. The thickness of the support plate 23 can be in the range of 25 to 1000 micrometers, and is preferably determined by the process and cost. Up to 100 microns. In this embodiment, the support plate 23 is a copper plate having a thickness of 35 μm.

1B and 1B' are respectively a cross-sectional view and a plan view showing the formation of the connection pad 111, the positioning member 113, and the arrangement of the guide member 115 on the first dielectric layer 21. Connection pad 111, positioning member 113, and configuration guide 115 It can be formed by photolithography and wet etching to remove selected portions of the metal layer 11. In this illustration, as shown in FIG. 1B', the positioning member 113 includes a plurality of metal studs of a rectangular array, and The four sides of the interposer disposed on the dielectric layer 21 then conform. Similarly, the configuration guide 115 includes a plurality of metal studs of a rectangular array and conforms to the four sides of the reinforcing layer 41 that is subsequently disposed on the first dielectric layer 21. However, the form of the positioning member 113 and the arrangement guide 115 is not limited thereto, and may be any pattern that prevents the interposer layer and the reinforcement layer from being unnecessarily displaced. For example, the positioning member 113 and the configuration guide 115 may also be composed of continuous or discontinuous strips and conform to the subsequently disposed interposer and the four sides, the two diagonals, or the four corners of the reinforcing layer. Further, the positioning member 113 and the arrangement guide 115 may be omitted, but it is preferable that the positioning member 113 and the arrangement guide 115 are present in consideration of the accuracy of the components to be subsequently disposed.

FIG. 1C shows that the interposer 31 is placed on the first layer using the adhesive 131. A cross-sectional view of a structure on a dielectric layer 21. The interposer 31 includes a first surface 311, a second surface 313 opposite to the first surface 311, a first contact pad 312 on the first surface 311, and a second contact pad on the second surface 313. 314 , a conductive via 318 electrically connected to the portion of the first contact pad 312 and the second contact pad 314 , and a lateral circuit 320 electrically connected to the bonding finger 316 and a portion of the first contact pad 312 . The interposer 31 can be an interposer, a glass interposer, or a ceramic dielectric layer, which includes a wire pattern that is fanned out to a second contact by the fine pitch of the portion of the first contact pads 312. The pad 314 has a coarse pitch and further includes a wire pattern extending laterally from the portion of the first contact pad 312 to the bonding finger 316.

The positioning member 113 can serve as a configuration guide of the interposer 31, and Thereby, the interposer 31 is accurately placed at a predetermined position, and its second surface 313 faces the first dielectric layer 21. The positioning member 113 extends from the first dielectric layer 21 in the upward direction and extends beyond the second surface 313 of the interposer 31, and is laterally aligned on the four sides of the interposer 31 in the lateral direction, and on the interposer 31. The four sides extend outwardly. When the positioning member 113 is close to the four sides of the interposer 31 and conforms to the four sides of the interposer 31, and the adhesive 131 under the interposer 31 is lower than the positioning member 113, any of the interposer 31 can be prevented from curing the adhesive. Unnecessary displacement. Preferably, the gap between the interposer 31 and the positioning member 113 is in the range of 0.001 to 1 mm.

FIG. 1D shows that the reinforcing layer 41 is placed on the first layer using the adhesive 131. A cross-sectional view of a structure on a dielectric layer 21. The interposer 31, the positioning member 113, and the connection pad 111 are aligned with the through holes 411 of the reinforcing layer 41, and inserted into the through holes 411 of the reinforcing layer 41. The through hole 411 is formed on the reinforcing layer 41 by laser drilling, and can also be formed by other techniques such as stamping and mechanical drilling. The reinforcing layer 41 in the drawings is a ceramic sheet having a thickness of about 0.6 mm, but may be other single layer or multilayer structures such as a multilayer circuit board, a glass plate, or a metal plate.

The intermediate layer 31 and the inner sidewall of the through hole 411 are positioned by The member 113 and the connection pad 111 are kept away from each other. In this figure, the reinforcement layer 41 can be accurately disposed at a predetermined position via the arrangement guide 115, and the arrangement guide 115 is directed from the first dielectric layer 21 toward Extending in the upward direction and extending beyond the attachment surface of the reinforcing layer 41 and extending laterally beyond the reinforcing layer 41 The peripheral edges, and the four peripheral edges of the reinforcing layer 41 are laterally aligned, and in addition, the adhesive 131 under the reinforcing layer 41 is lower than the arrangement guide 115. When the arrangement of the guide members 115 is close to the side direction and conforms to the four outer side surfaces of the reinforcing layer 41, and the adhesive 131 under the reinforcing layer 41 is lower than the arrangement guide, the reinforcing layer 41 can be prevented from being completely cured by the adhesive 131. There are any unnecessary displacements before. Preferably, the gap between the reinforcing layer 41 and the arrangement guide 115 is in the range of 0.001 to 1 mm.

FIG. 1E is formed through the support plate 23, the first dielectric layer 21, And the first micro-hole 213 of the adhesive 131 to expose the structural view of the second contact pad 314 and the connection pad 111. The first microholes 213 can be formed by a variety of techniques including laser drilling, plasma etching, and lithography. Pulsed lasers can be used to improve laser drilling performance, or metal reticle and scanning laser beams can be used. For example, the copper plate can be etched first to create a metal window and then irradiate the laser beam. The first microwell 213 typically has a diameter of 50 microns. Referring to FIG. 1F, the first wire 241 formed on the first dielectric layer 21 is deposited on the support plate 23 via the deposition coating layer 24, and deposited into the first micro hole 213, and then patterned on the support plate 23 and thereon. The coating layer 24 is formed. Alternatively, when the laminate substrate does not have the support plate 23 or some embodiments of the support plate 23 are removed after the step of FIG. 1D, the first dielectric layer 21 may be directly metallized after the first micro holes 213 are formed. A first wire 241 is formed.

The coating layer 24 can be deposited by various techniques to form a single layer or multilayer structure including electroplating, electroless plating, evaporation, sputtering, and combinations thereof. For example, depositing the coating layer 24 first causes the first dielectric layer 21 to react with the electroless copper to cause a catalyst reaction by dipping the structure into the activator solution, and then A thin copper layer is coated as a seed layer by electroless plating, and then a second copper layer of a desired thickness is formed on the seed layer by electroplating. Alternatively, before depositing the electroplated copper layer on the seed layer, the seed layer may be formed by a sputtering method such as a titanium/copper seed layer film, and once the desired thickness is achieved, the support plate may be patterned using various techniques. 23 and the cover layer 24 to form a first wire 241 comprising wet etching, electrochemical etching, laser assisted etching, and combinations thereof with an etch mask (not shown) to define the first wire 241. Therefore, the first wire 241 extends from the first dielectric layer 21 toward the lower direction, extends laterally on the first dielectric layer 21, and extends in the upward direction into the first micro hole 213 to form an electrical connection to the second contact. Pad 314 and first conductive microvia 243 of connection pad 111.

For convenience of explanation, the support plate 23 and the cover thereon The layer 24 is represented by a single layer. Since the copper is a homogeneous coating, the boundary between the metal layers (both shown by dashed lines) may be difficult to detect or even undetectable, but the boundary between the coating layer 24 and the first dielectric layer 21 is clearly visible. .

1G is a second dielectric layer 261 disposed on the first wire 241 And a cross-sectional view of the structure on the first dielectric layer 21. The second dielectric layer 261 can be made of epoxy resin, glass epoxy resin, polyimide, and the like, and is formed by various techniques including film pressing, roller coating, spin coating And spray deposition, and usually have a thickness of 50 microns. Preferably, the first dielectric layer 21 and the second dielectric layer 261 are the same material.

FIG. 1H is a second microvia formed through the second dielectric layer 261. 263, to reveal a structural cross-sectional view of selected portions of the first wire 241. Like the first microhole 213, the second microhole 263 can be formed by various techniques including Laser drilling, plasma etching and lithography, and typically 50 microns in diameter. Preferably, the first microhole 213 and the second microhole 263 have the same size.

Referring to FIG. 1I, a second wire 281 is formed on the second dielectric layer 261 to complete the composite circuit board 101. The composite circuit board 101 includes an interposer 31, a reinforcement layer 41, and a coreless substrate 20. In this figure, the coreless substrate 20 includes a positioning member 113, a connection pad 111, a configuration guide 115, and a first dielectric layer 21, a first wire 241, a second dielectric layer 261, and a second wire 281. Layer-added circuit. The second wire 281 extends from the second dielectric layer 261 in a downward direction and extends laterally on the second dielectric layer 261 and extends into the second micro hole 263 in an upward direction to form an electrical connection with the first wire 241. The second conductive microhole 283.

The second wire 281 can be deposited as a conductive layer via various techniques, including electroplating, electroless plating, sputtering, and combinations thereof, followed by patterning the conductive layer by various means including wet etching, electrochemical etching, laser assisted etching. It is combined with an etch mask (not shown) to define a second wire 281. Preferably, the first wire 241 and the second wire 281 are made of the same material and have the same thickness.

The interposer 31 and the reinforcement layer 41 are attached to the first dielectric layer 21 via the adhesive 131, and the adhesive 131 contacts the interposer 31 and the first dielectric layer 21, and interposed between the interposer 31 and the first dielectric layer. 21, and between the reinforcing layer 41 and the first dielectric layer 21, the interposer 31 and the reinforcing layer 41 are formed by the positioning member 113 interposed between the interposer 31 and the reinforcing layer 41 and the connection pad 111 of the coreless substrate 20. Keep a distance from each other. The positioning member 113, the connection pad 111, and the arrangement guide 115 extend upward from the first dielectric layer 21, The positioning member 113 is adjacent to the peripheral edge of the interposer 31, the connection pad 111 is located between the peripheral edge of the positioning member 113 and the inner side wall of the reinforcing layer 41, and the arrangement guiding member 115 is adjacent to the peripheral edge of the outer side wall of the reinforcing layer 41. The adhesive 131 contacts the positioning member 113, the connection pad 111, and the arrangement guide 115, and is coplanar with the positioning member 113, the connection pad 111, and the arrangement guide 115 in the downward direction, and is lower than the positioning member 113 in the upward direction. The pad 111 is connected, and the guide 115 is disposed.

As shown in FIG. 1J, the coreless base is electrically connected by the wire 321 The bonding pads 111 of the board 21 and the bonding fingers 316 of the interposer 31, and the semiconductor wafer 51 are flipped over the first surface 311 of the interposer 31 via the solder bumps 61 on the first contact pads 312 of the interposer 31. The first wire 241 of the coreless substrate 20 is in direct contact with the second contact pad 314 of the interposer 31. The first wire 241 is also in direct contact with the connection pad 111 , and the connection pad 111 of the coreless substrate 21 is electrically connected to the bonding finger 316 of the interposer 31 via the wire 321 . Therefore, the electrical connection between the interposer 31 and the coreless substrate 20 is flexibly connected via a combination of the bonding wires 321 and the first conductive microvias 243, and the interposer 31 and the coreless substrate 20 are free of solder. Accordingly, after flip-chip assembly, the connection between the semiconductor wafer 51 and the coreless substrate 20 can be via the first contact pad 312 of the interposer 31, the conductive vias 318, and the second contact pads 314 of the interposer 31, followed by The coreless substrate 20 is connected via microvias while being bonded to the coreless substrate 20 by bonding fingers 316 of the interposer 31.

FIG. 1K has another semiconductor wafer 53 attached to a coreless base. A cross-sectional view of the semiconductor body 210 on the board 20. The semiconductor wafer 53 is aligned with the arrangement position of the interposer 31 and via the solder bumps on the inner connection pads 284 63 is electrically connected to the coreless substrate 20, and the inner connection pad 284 is exposed from the opening 293 of the solder resist material 291. Accordingly, the semiconductor wafers 51, 53 can be electrically connected to each other via the interposer 31, the coreless substrate 20, and the solder bumps 61, 63.

In addition, the opening 293 of the solder resist material 291 is exposed The remaining inner connection pads 284 can house a conductive joint, such as solder bumps, solder balls, pins, and the like, for electrical interconnection and mechanical attachment of other groups or external components. The solder mask opening 293 can be formed by various methods including lithography, laser drilling, and plasma etching.

[Embodiment 2]

2 is another three-dimensional group according to another embodiment of the present invention. The body 310 has an additional first conductive via 243 in direct contact with the interposer 41 as a cross-sectional view of the ground or electrical connection to the passive component. Also shown in FIG. 2 is a sealing material 71 and a heat sink 81. The sealing material 71 (such as a molding compound) fills the through hole 411 in the upward direction and covers the connection pad 111, the positioning member 113, the first dielectric layer 21, and the interposer 31. The heat sink 81 (such as copper or aluminum) is attached to the reinforcing layer 41 and the semiconductor wafer 51 via the heat conductive adhesive 801 to assist heat dissipation, and the heat sink 81 is covered with the reinforcing layer 41, the sealing material 71, and the semiconductor wafer 51 in the upward direction. .

The above semiconductor package and circuit board are only illustrative examples. The invention can be implemented in other various embodiments. In addition, the above embodiments may be used in combination with each other or in combination with other embodiments based on design and reliability considerations. For example, the reinforcing layer may include a ceramic material or an epoxy-based laminate, and a single-layer wire or a plurality of layers of wires may be embedded. The reinforcement layer may include a plurality of through holes to accommodate additional interposers, passive components, or other electrical The sub-element, and the coreless substrate may include additional wires to accommodate high I/O components, passive components, or other electronic components.

As shown in the above embodiments, the semiconductor component of the present invention is unique Self-use or share an interposer with other semiconductor components. For example, a single semiconductor element may be disposed on the interposer or a plurality of semiconductor elements may be disposed on the interposer. For example, four small wafers arranged in a 2x2 array can be attached to the interposer, and the interposer can provide additional electrical connection points for additional wafers to receive routing of additional wafer pads. This is more economical than providing an interposer for each wafer. Likewise, the vias of the reinforcement layer can include multiple sets of locators to accommodate a plurality of additional interposers therein, and the build-up circuitry can include additional wires to accommodate additional interposers.

The semiconductor component of the present invention can be a packaged or unpackaged wafer. Further, the semiconductor element may be a bare wafer or a wafer level packaged die or the like. The semiconductor component can be mechanically and electrically bonded to the interposer using a variety of bonding media, including the use of gold or solder bumps. The positioning member can be customized according to the interposer. For example, the pattern of the positioning member can be square or rectangular, and the shape of the interlacing layer is the same as or similar to the interposer. A heat dissipating component such as a heat sink or a heat sink may be attached to the semiconductor component via a thermally conductive adhesive or solder material, and the heat dissipating component may also be attached to the reinforcing layer to extend the contact area to increase the heat dissipation path efficiency of the semiconductor component.

In this paper, the term "adjacent" means that the components are integrally formed. (Forming a single individual) or in contact with each other (without or without separation from each other). For example, the first wire is adjacent to the second contact pad but not adjacent to the first contact pad.

The term "overlapping" means located above and extending below a lower element Within the perimeter of the piece. "Overlap" includes extending within, outside of, or within the circumference of the circumference. For example, when the second contact pad surface of the interposer faces upward, the reinforcing layer overlaps the dielectric layer because an imaginary vertical line can penetrate the reinforcing layer and the dielectric layer simultaneously, regardless of the reinforcing layer and the dielectric layer. Is there another element (such as an adhesive) that is also penetrated by the imaginary vertical line between the layers, and whether or not another imaginary vertical line only penetrates the dielectric layer and does not penetrate the reinforcing layer (the through hole in the reinforcing layer) Inside). Similarly, the adhesive is superposed on the dielectric layer, the reinforcing layer is superposed on the adhesive, and the reinforcing layer is overlapped by the adhesive. In addition, "overlap" is synonymous with "below" and "overlap" is synonymous with "below".

The term "contact" means direct contact. For example, wire contact The second contact pad does not contact the first contact pad.

The term "coverage" means not in the vertical and / or side directions. Complete and complete coverage. For example, in a state where the first contact pad surface of the interposer faces upward, the coreless substrate covers the interposer in the downward direction, but the interposer does not cover the coreless substrate from the upward direction.

The "layer" word contains patterned and unpatterned layers. E.g, When the metal layer is disposed on the dielectric layer, the metal layer can be a blank unlithographic and wet etched flat plate. In addition, a "layer" may comprise a plurality of superposed layers.

The words "opening", "through hole" and "perforation" refer to the through hole. hole. For example, when the first contact pad surface of the interposer faces upward, the interposer is inserted into the via hole of the reinforcement layer and is exposed by the reinforcement layer in the upward direction.

The term "insertion" means the relative movement between components. E.g, "Insert the interposer into the through hole" is the intermediary regardless of whether the reinforcement layer is fixed or not The layer moves toward the reinforcement layer; the interposer layer is fixed and moved by the reinforcement layer toward the interposer layer; or the interposer layer and the reinforcement layer abut each other. For another example, "inserting (or extending into) the through-hole" includes: penetrating (through and penetrating) the through-hole; and inserting but not penetrating (penetrating but not piercing) the through-hole.

The term "alignment" means the relative position between components, regardless of the Whether the pieces are spaced apart from each other or abut, or one element is inserted and extends into the other element. For example, when the imaginary horizontal line runs through the positioning member and the interposer, the positioning member is laterally aligned with the interposer, regardless of whether there are other elements intersected by the imaginary horizontal line between the positioning member and the interposer, and whether or not there is another through The interposer does not extend through the imaginary horizontal line of the positioning member. Similarly, the first microvia is aligned with the second contact pad of the interposer, and the interposer and the locating member are aligned with the via.

The term "close" means that the width of the gap between components does not exceed Maximum acceptable range. As is known in the art, when the inter-layer layer and the gap between the positioning members are not sufficiently narrow, the positional error due to the lateral displacement of the interposer in the gap may exceed the acceptable maximum error limit once the interposer is located. When the error exceeds the maximum limit, it is impossible to align the contact pads with the laser beam, resulting in an electrical connection error between the interposer and the coreless substrate. Therefore, according to the size of the contact pads of the interposer, those skilled in the art can confirm the maximum acceptable range of the interposer and the gap between the positioning members through trial and error, thereby avoiding the electrical properties between the interposer and the coreless substrate. connection error. Thus, the term "the locating member is adjacent to the peripheral edge of the interposer" means that the peripheral edge of the interposer and the gap between the locating members are narrow enough to prevent the positional error of the interposer from exceeding an acceptable maximum error limit.

The term "set" includes between a single or multiple support elements Contact and non-contact. For example, the interposer is disposed on the dielectric layer, whether the interposer actually contacts the dielectric layer or is separated from the dielectric layer by an adhesive.

The term "electrical connection" means direct or indirect electrical connection. For example, the first wire provides an electrical connection between the inner connection pad and the second contact pad regardless of whether the first wire abuts the inner connection pad or is electrically connected to the inner connection pad via the second wire.

The word "above" means extending upwards and includes adjacency and non- Adjacent elements as well as overlapping and non-overlapping elements. For example, when the first connection pad of the interposer faces upward, the positioning member extends above it, adjoins the dielectric layer and protrudes from the dielectric layer.

The word "below" is intended to mean extending downwards and includes adjacency and non- Adjacent elements as well as overlapping and non-overlapping elements. For example, when the second connection pad surface of the interposer faces upward, the coreless substrate extends below it, abutting the adhesive and projecting downward from the adhesive. Similarly, the build-up circuit can extend below the reinforcement layer and the interposer even if it is not adjacent to the reinforcement or interposer.

The "first vertical direction" and the "second vertical direction" do not depend on the orientation of the group. Anyone familiar with the art can easily understand the direction in which they actually refer. For example, the first contact pad of the interposer faces in a first vertical direction, and the second contact pad of the interposer faces in a second vertical direction, regardless of whether the group is inverted. Similarly, the locating member aligns the interposer "laterally" along a lateral plane, regardless of whether the board is inverted, rotated or tilted. Therefore, the first and second vertical directions are opposite to each other and perpendicular to the side The, and laterally aligned elements intersect in a lateral plane perpendicular to the first and second perpendicular directions. Furthermore, when the second contact pad surface of the interposer faces upward, the first vertical direction is the downward direction, and the second vertical direction is the upward direction; when the second contact pad surface of the interposer faces the downward direction, the first The vertical direction is the upward direction and the second vertical direction is the downward direction.

The semiconductor package of the present invention has a number of advantages. Semiconductor group The reliability of the body is high, the price is flat and it is very suitable for mass production. The reinforcing layer provides mechanical support, dimensional stability, and control of overall flatness, and thermal expansion of the coreless substrate (such as the interposer), even if the coefficient of thermal expansion (CTE) between the interposer and the coreless substrate is different, in thermal cycling In this case, the interposer can still be firmly connected to the coreless substrate. There is a direct electrical connection between the interposer and the coreless substrate, and the absence of a solder system facilitates high I/O values and high performance. In particular, the positioning member can accurately define the position of the interposer and avoid the electrical connection error between the interposer and the coreless substrate caused by the lateral displacement of the interposer, thereby improving the yield of production.

The production method of this case is highly applicable and unique. The way of progress combines the use of a variety of mature electrical connections and mechanical joining techniques. In addition, the production method of this case can be implemented without expensive tools. As a result, this approach can significantly increase throughput, yield, performance and cost efficiency compared to traditional packaging techniques.

The embodiments described herein are for illustrative purposes, wherein the implementations The elements or steps that are well known in the art may be simplified or omitted in order to avoid obscuring the features of the present invention. Similarly, in order to make the drawings clear, the drawings may also omit redundant or non-essential components and component symbols.

Those skilled in the art will be able to readily appreciate various changes and modifications to the embodiments described herein. For example, the foregoing materials, dimensions, shapes, sizes, steps, and order of steps are merely examples. Variations, adjustments, and equalizations may be made by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

While the invention has been described in terms of the preferred embodiments of the present invention, it is understood that modifications and changes may be made to the present invention without departing from the spirit and scope of the invention.

110‧‧‧Semiconductor group

113‧‧‧ Positioning parts

111‧‧‧Connecting mat

115‧‧‧Configure guides

20‧‧‧ Coreless substrate

241‧‧‧First wire

21‧‧‧First dielectric layer

281‧‧‧second wire

243‧‧‧First conductive micropores

261‧‧‧Second dielectric layer

311‧‧‧ first surface

313‧‧‧ second surface

31‧‧‧Intermediary

312‧‧‧First contact pad

314‧‧‧Second contact pad

321‧‧‧Line

318‧‧‧Electrical perforation

316‧‧‧ joint finger

320‧‧‧lateral circuit

41‧‧‧ Strengthening layer

51‧‧‧Semiconductor wafer

61‧‧‧ solder bumps

Claims (5)

A semiconductor device comprising: an interposer comprising a plurality of first contact pads and a bonding finger on a first surface, and a plurality of second contact pads on a second surface facing the first surface a first vertical direction, and the second surface faces a second perpendicular direction opposite to the first vertical direction, wherein at least one of the first contact pads is electrically connected to one via a conductive via of the interposer Corresponding to the second connection pad; a semiconductor component, which is flip-chip mounted on the first surface of the interposer and connected to the first contact pads; a reinforcement layer including a through hole, and the intermediary a layer extending into the through hole; an adhesive contacting the interposer and a coreless substrate between the interposer and the coreless substrate; and the coreless substrate being attached to the second vertical Orienting the adhesive, the interposer, and the reinforcing layer, and the coreless substrate comprises a connecting pad electrically connected to the bonding finger of the interposer via a wire, and further comprising a conductive micro Hole, the conductive microhole Electrically connected to the second contact pads of the interposer. The semiconductor component of claim 1, wherein the interposer and the electrical connection between the coreless substrates do not contain solder. The semiconductor device of claim 1, wherein the connection pad is exposed from the coreless substrate in the first vertical direction, and the peripheral edge of the interposer and the reinforcement layer are laterally oriented. The sidewalls of the holes extend laterally between each other. The semiconductor component of claim 1, wherein the coreless substrate further comprises a positioning member aligned with the through hole of the reinforcing layer and serving as a guiding guide for the interposer, and close to The peripheral edge of the interposer and the connection pad extend laterally between the peripheral edge of the interposer and the connection pad. The semiconductor component of claim 1, wherein the coreless substrate further comprises a configuration guide adjacent to a peripheral edge of the reinforcement layer and laterally aligned with a peripheral edge of the reinforcement layer, and Extending outwardly from the outer edge of the reinforcing layer.