TW201405230A - Pixel array substrate and display panel - Google Patents
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本發明是有關於一種畫素陣列基板及顯示面板,且特別是有關於一種具有擬走線之畫素陣列基板及顯示面板。 The present invention relates to a pixel array substrate and a display panel, and more particularly to a pixel array substrate and a display panel having a trace.
隨著顯示技術的蓬勃發展,顯示面板已應用於各種尺寸的顯示裝置,如電視、電腦螢幕、筆記型電腦、行動電話等當中。以行動電話為例,消費者除了對顯示面板的顯示性能,如解析度、對比、視角等,有所要求外,對於顯示面板的外觀美感的要求亦日漸提升。因此,顯示面板相關業者多已紛紛投入窄邊框(Narrow boarder)顯示面板的行列中,以使具有相同顯示品質的顯示面板更具有輕薄短小的特性,來滿足消費者需求。 With the rapid development of display technology, display panels have been applied to display devices of various sizes, such as televisions, computer screens, notebook computers, mobile phones, and the like. Taking mobile phones as an example, in addition to the display performance of the display panel, such as resolution, contrast, and viewing angle, the requirements for the aesthetic appearance of the display panel are also increasing. Therefore, many display panel related companies have already invested in the ranks of Narrow boarder display panels, so that display panels with the same display quality are more light, thin and short to meet consumer demand.
為了實現窄邊框的顯示面板,業者需減少周邊走線所分佈的面積,以縮減邊框的寬度。在習知技術中,通常使用精良的黃光製程技術來縮短周邊走線之間的線距以及周邊走線的寬度來實現窄邊框顯示面板。然而,隨著智慧型手機的發展,其顯示面板的解析度越做越高,周邊走線的數量也隨之增加,導致周邊走線之間的線距以及周邊走線的寬度需不斷的縮小。周邊走線也易發生寬度過小或斷線的問題,進而影響顯示面板的品質。 In order to realize a narrow-frame display panel, the operator needs to reduce the area of the surrounding traces to reduce the width of the border. In the prior art, a narrow yellow display panel is generally realized by using a sophisticated yellow light process technique to shorten the line spacing between the peripheral traces and the width of the peripheral traces. However, with the development of smart phones, the resolution of display panels is getting higher and higher, and the number of peripheral traces is also increasing, resulting in the need to continuously reduce the line spacing between peripheral traces and the width of peripheral traces. . The surrounding traces are also prone to problems of too small a width or a broken line, which in turn affects the quality of the display panel.
有鑑於此,本發明提供一種畫素陣列基板,其可改善走線易發生寬度過小或斷線的問題,進而提升顯示面板的顯示品質。 In view of the above, the present invention provides a pixel array substrate, which can improve the problem that the width of the trace is too small or broken, thereby improving the display quality of the display panel.
此外,本發明提供一種顯示面板,其具有高顯示品質。 Further, the present invention provides a display panel having high display quality.
本發明提供一種畫素陣列基板,此畫素陣列基板包括包括基板、多個畫素結構、多條第一走線以及至少一第一擬走線。基板具有顯示區以及位於顯示區外之周邊區。畫素結構陣列排列於顯示區。第一走線位於周邊區且與畫素結構電性連接。第一擬走線(dummy line)位於周邊區且與畫素結構電性絕緣。第一走線位於顯示區與第一擬走線之間。 The present invention provides a pixel array substrate comprising a substrate, a plurality of pixel structures, a plurality of first traces, and at least one first trace. The substrate has a display area and a peripheral area outside the display area. The pixel structure array is arranged in the display area. The first trace is located in the peripheral area and is electrically connected to the pixel structure. The first dummy line is located in the peripheral area and is electrically insulated from the pixel structure. The first trace is located between the display area and the first trace.
本發明提供一種顯示面板,此顯示面板包括上述之畫素陣列基板、對向基板以及顯示介質。對向基板相對於畫素陣列基板。顯示介質位於畫素陣列基板與對向基板之間。 The invention provides a display panel comprising the above pixel array substrate, a counter substrate and a display medium. The opposite substrate is opposed to the pixel array substrate. The display medium is located between the pixel array substrate and the opposite substrate.
在本發明之一實施例中,上述之第一走線呈等間距(pitch)排列。任意二相鄰的第一走線之間存在第一線距。第一擬走線與相鄰的第一走線之間存在第二線距。第二線距實質上等於第一線距。 In an embodiment of the invention, the first traces are arranged in a pitch arrangement. There is a first line spacing between any two adjacent first traces. There is a second line spacing between the first pseudo trace and the adjacent first trace. The second line spacing is substantially equal to the first line spacing.
在本發明之一實施例中,上述之第一走線具有第一寬度。第一擬走線具有第二寬度。第二寬度實質上小於第一寬度。 In an embodiment of the invention, the first trace has a first width. The first pseudo trace has a second width. The second width is substantially smaller than the first width.
在本發明之一實施例中,上述之第一擬走線為最接近基板邊緣的走線。 In an embodiment of the invention, the first pseudo trace is the trace closest to the edge of the substrate.
在本發明之一實施例中,上述之基板具有長邊以及與長邊連接之短邊。第一擬走線於長邊上之正投影涵蓋第一 走線於長邊上之正投影。第一擬走線於短邊上之正投影涵蓋第一走線於短邊上之正投影。 In an embodiment of the invention, the substrate has a long side and a short side connected to the long side. The orthographic projection of the first proposed line on the long side covers the first Orthographic projection of the line on the long side. The orthographic projection of the first pseudo-line on the short side covers the orthographic projection of the first trace on the short side.
在本發明之一實施例中,上述之畫素陣列基板更包括驅動晶片。驅動晶片位於周邊區。驅動晶片透過第一走線與畫素結構電性連接。第一擬走線與驅動晶片電性絕緣。 In an embodiment of the invention, the pixel array substrate further includes a driving wafer. The drive wafer is located in the peripheral zone. The driving chip is electrically connected to the pixel structure through the first trace. The first pseudo trace is electrically insulated from the drive wafer.
在本發明之一實施例中,上述之畫素結構包括主動元件以及畫素電極。主動元件具有源極、閘極以及汲極。畫素電極與主動元件之汲極電性連接。第一走線與畫素結構之閘極電性連接。 In an embodiment of the invention, the pixel structure described above includes an active component and a pixel electrode. The active device has a source, a gate, and a drain. The pixel electrode is electrically connected to the active element. The first trace is electrically connected to the gate of the pixel structure.
在本發明之一實施例中,上述之畫素陣列基板更包括多條第二走線以及至少一第二擬走線。第二走線位於周邊區且與畫素結構之源極電性連接。第二擬走線位於周邊區且與畫素結構電性絕緣。第二走線位於顯示區與第二擬走線之間。 In an embodiment of the invention, the pixel array substrate further includes a plurality of second traces and at least one second trace. The second trace is located in the peripheral region and is electrically connected to the source of the pixel structure. The second pseudo trace is located in the peripheral area and is electrically insulated from the pixel structure. The second trace is located between the display area and the second trace.
在本發明之一實施例中,上述之第二走線呈等線距排列。任意二相鄰的第二走線之間存在第三線距。第二擬走線與相鄰的第二走線之間存在第四線距。第三線距實質上等於第四線距。 In an embodiment of the invention, the second traces are arranged in equal line spacing. There is a third line spacing between any two adjacent second traces. There is a fourth line spacing between the second pseudo-line and the adjacent second line. The third line spacing is substantially equal to the fourth line spacing.
在本發明之一實施例中,上述之第二走線具有第三寬度。第二擬走線具有第四寬度。第四寬度實質上小於第三寬度。 In an embodiment of the invention, the second trace has a third width. The second pseudo trace has a fourth width. The fourth width is substantially smaller than the third width.
基於上述,在本發明一實施例之畫素陣列基板及顯示面板中,透過擬走線的配置可使所有走線的曝光條件較為一致,而減少位於外緣之走線發生寬度過小或斷線的問 題,進而提升顯示面板的顯示效果。 Based on the above, in the pixel array substrate and the display panel according to an embodiment of the present invention, the arrangement of the traces can be made uniform by all the traces, and the width of the traces located at the outer edge is too small or broken. Question The problem is to improve the display of the display panel.
為讓本發明之上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。 The above described features and advantages of the present invention will be more apparent from the following description.
圖1為本發明一實施例之顯示面板的剖面示意圖。請參照圖1,本實施例之顯示面板100包括畫素陣列基板110、對向基板120以及顯示介質130。對向基板120相對於畫素陣列基板110。顯示介質130位於畫素陣列基板110與對向基板120之間。在本實施例中,對向基板120可為彩色濾光片(Color Filter)基板。然而,本發明不限於此,在其他實施例中,對向基板120亦可不包括彩色濾光片,而為具有透光導電層的透光基板。本實施例之顯示介質130例如為液晶(Liquid Crystal),但本發明不限於此,在其他實施例中,顯示介質130亦可為有機發光層、電泳液或其他適當的材料。 1 is a cross-sectional view of a display panel in accordance with an embodiment of the present invention. Referring to FIG. 1 , the display panel 100 of the present embodiment includes a pixel array substrate 110 , a counter substrate 120 , and a display medium 130 . The opposite substrate 120 is opposed to the pixel array substrate 110. The display medium 130 is located between the pixel array substrate 110 and the opposite substrate 120. In this embodiment, the opposite substrate 120 may be a color filter substrate. However, the present invention is not limited thereto. In other embodiments, the opposite substrate 120 may not include a color filter but a light-transmitting substrate having a light-transmitting conductive layer. The display medium 130 of the present embodiment is, for example, a liquid crystal. However, the present invention is not limited thereto. In other embodiments, the display medium 130 may also be an organic light-emitting layer, an electrophoretic liquid, or other suitable material.
圖2為圖1之畫素陣列基板的上視示意圖。請參照圖2,本實施例之畫素陣列基板110包括基板112、多個畫素結構114、多條第一走線L1以及至少一第一擬走線L1’。基板112具有顯示區R1以及位於顯示區R1外之周邊區R2。更進一步地說,本實施例之周邊區R2可為環繞顯示區R1的環形區域。本實施例之基板112的材質可為玻璃、石英、有機聚合物、或是不透光/反射材料(例如:導電材料、晶圓、陶瓷、或其它可適用的材料)、或是其它可適用 的材料。但本發明不以上述為限。 2 is a top plan view of the pixel array substrate of FIG. 1. Referring to FIG. 2, the pixel array substrate 110 of the present embodiment includes a substrate 112, a plurality of pixel structures 114, a plurality of first traces L1, and at least one first trace L1'. The substrate 112 has a display area R1 and a peripheral area R2 located outside the display area R1. Furthermore, the peripheral region R2 of the present embodiment may be an annular region surrounding the display region R1. The substrate 112 of the embodiment may be made of glass, quartz, organic polymer, or an opaque/reflective material (for example, a conductive material, a wafer, a ceramic, or other applicable materials), or other applicable. s material. However, the invention is not limited to the above.
本實施例之畫素結構114是陣列排列於顯示區R1中。本實施例之畫素結構114包括主動元件T以及畫素電極PE。主動元件T具有源極S、閘極G以及汲極D。畫素電極PE與主動元件T之汲極D電性連接。本實施例之畫素陣列基板110更包括多條掃描線SL以及與掃描線SL交錯之多條資料線DL。掃描線SL與主動元件T之閘極G電性連接。資料線DL與主動元件T之源極S電性連接。掃描線SL與資料線DL屬於不同的膜層。基於導電性的考量,掃描線SL與資料線DL一般是使用金屬材料。然而,本發明不限於此,在其他實施例中,掃描線SL與資料線DL也可以使用其他導電材料,例如合金、金屬材料的氮化物、金屬材料的氧化物、金屬材料的氮氧化物、或是金屬材料與其它導電材料的堆疊層。 The pixel structure 114 of this embodiment is arranged in an array in the display area R1. The pixel structure 114 of this embodiment includes an active element T and a pixel electrode PE. The active device T has a source S, a gate G, and a drain D. The pixel electrode PE is electrically connected to the drain D of the active device T. The pixel array substrate 110 of the present embodiment further includes a plurality of scanning lines SL and a plurality of data lines DL interlaced with the scanning lines SL. The scan line SL is electrically connected to the gate G of the active device T. The data line DL is electrically connected to the source S of the active device T. The scan line SL and the data line DL belong to different film layers. Based on the conductivity considerations, the scan line SL and the data line DL are generally made of a metal material. However, the present invention is not limited thereto. In other embodiments, other conductive materials such as an alloy, a nitride of a metal material, an oxide of a metal material, an oxynitride of a metal material, or the like may be used for the scan line SL and the data line DL. Or a stack of metallic materials and other conductive materials.
本實施例之多條第一走線L1位於周邊區R2且與畫素結構114電性連接。詳言之,第一走線L1可與畫素結構114的閘極G電性連接。在本實施例中,第一走線L1可透過掃描線SL與畫素結構114的閘極G電性連接。換言之,本實施例之第一走線L1可為掃描線SL的延伸。本實施例之畫素陣列基板110更包括位於周邊區R2的驅動晶片116。驅動晶片116可透過第一走線L1與畫素結構114電性連接。驅動晶片116是用以驅動畫素結構114,進而使顯示面板100可顯示畫面。 The plurality of first traces L1 of the embodiment are located in the peripheral region R2 and are electrically connected to the pixel structure 114. In detail, the first trace L1 can be electrically connected to the gate G of the pixel structure 114. In the embodiment, the first trace L1 is electrically connected to the gate G of the pixel structure 114 through the scan line SL. In other words, the first trace L1 of the embodiment may be an extension of the scan line SL. The pixel array substrate 110 of this embodiment further includes a driving wafer 116 located in the peripheral region R2. The driving chip 116 can be electrically connected to the pixel structure 114 through the first trace L1. The driving chip 116 is used to drive the pixel structure 114, thereby enabling the display panel 100 to display a picture.
本實施例之第一擬走線L1’位於周邊區R2且與畫素結 構114電性絕緣。第一擬走線L1’亦可與驅動晶片116電性絕緣。第一擬走線L1’與第一走線L1是屬於同一膜層。第一走線L1位於顯示區R1與第一擬走線L1之間。換言之,第一擬走線L1’是位於所有第一走線L1的邊緣處。在本實施例中,第一擬走線L1’可為最接近基板112邊緣E1的走線。本實施例之基板112具有長邊112a及與長邊112a連接之短邊112b。第一擬走線L1’於長邊112a上之正投影涵蓋第一走線L1於長邊112a上之正投影。並且,第一走擬走線L1’於短邊112b上之正投影涵蓋第一走線L1於短邊112b上之正投影。換言之,第一擬走線L1’是順著所有第一走線L1中最靠外緣之一條第一走線L1配置的。 The first pseudo-line L1' of this embodiment is located in the peripheral area R2 and is connected to the pixel Structure 114 is electrically insulated. The first trace L1' can also be electrically insulated from the drive wafer 116. The first pseudo-line L1' and the first trace L1 belong to the same film layer. The first trace L1 is located between the display area R1 and the first dummy line L1. In other words, the first pseudo-line L1' is located at the edge of all the first traces L1. In the present embodiment, the first pseudo trace L1' may be the trace closest to the edge E1 of the substrate 112. The substrate 112 of this embodiment has a long side 112a and a short side 112b connected to the long side 112a. The orthographic projection of the first pseudo-line L1' on the long side 112a covers the orthographic projection of the first trace L1 on the long side 112a. Moreover, the orthographic projection of the first trace L1' on the short side 112b covers the orthographic projection of the first trace L1 on the short side 112b. In other words, the first pseudo-line L1' is disposed along one of the first outermost lines L1 of all the first traces L1.
值得一提的是,本實施例之第一擬走線L1’是用以確保第一走線L1的品質,以避免第一走線L1在形成過程發生寬度過小或斷線的問題,進而提升顯示面板100的顯示效果。以下配合圖示詳細說明第一擬走線L1’確保第一走線L1品質的機制。 It is worth mentioning that the first pseudo-route L1' of the embodiment is used to ensure the quality of the first trace L1, so as to avoid the problem that the width of the first trace L1 is too small or broken during the formation process, thereby improving The display effect of the display panel 100. The mechanism for ensuring the quality of the first trace L1 by the first pseudo trace L1' will be described in detail below with reference to the drawings.
圖3為圖2之局部區域A的放大示意圖。請參照圖3,在本實施例中,多條第一走線L1呈等間距(pitch)排列。任意二相鄰的第一走線L1之間存在第一間距P1。第一擬走線L1’與相鄰的第一走線L1(即最接近第一擬走線L1’的第一走線L1)之間存在第二間距P2。第二間距P2實質上等於第一間距P1。由於在第一走線L1的設計中第一走線L1是呈等間距排列,因此在曝光過程中若無第一擬走線L1’之設計,則所有第一走線L1中靠外緣之第一走線L1其曝 光條件與其他第一走線L1不同。這樣一來,所有第一走線L1中靠外緣之第一走線L1在蝕刻製程後便易發生寬度過小或斷線的問題。然而,透過第一擬走線L1’的配置可使靠外緣之第一走線L1的曝光條件與其他第一走線L1較為一致,進而改善靠外緣之第一走線L1易發生寬度過小或斷線的問題。 FIG. 3 is an enlarged schematic view of a partial area A of FIG. 2. Referring to FIG. 3, in the embodiment, the plurality of first traces L1 are arranged in a pitch. There is a first pitch P1 between any two adjacent first traces L1. There is a second pitch P2 between the first pseudo trace L1' and the adjacent first trace L1 (i.e., the first trace L1 closest to the first trace L1'). The second pitch P2 is substantially equal to the first pitch P1. Since the first traces L1 are arranged at equal intervals in the design of the first trace L1, if there is no design of the first trace L1' during the exposure process, the outer edges of all the first traces L1 are The first trace L1 is exposed The light conditions are different from the other first traces L1. In this way, the first trace L1 of the outer edge of all the first traces L1 is likely to have a problem of too small width or disconnection after the etching process. However, the arrangement of the first trace L1' allows the exposure condition of the first trace L1 of the outer edge to be more consistent with the other first traces L1, thereby improving the width of the first trace L1 by the outer edge. Too small or broken.
請繼續參照圖3,在本實施例中,第一走線L1具有第一寬度W1。第一擬走線L1’具有第二寬度W2。由於形成第一擬走線L1’的曝光條件與形成第一走線L1的曝光條件不同,因此第一擬走線L1’的第二寬度W2實質上會小於第一走線L1的第一寬度W1。然而,第一擬走線L1’未與顯示區R1中的畫素結構114電性連接,因此第一擬走線L1’的寬度大小或斷線與否並不會影響顯示面板100的顯示效果。 With continued reference to FIG. 3, in the present embodiment, the first trace L1 has a first width W1. The first pseudo trace L1' has a second width W2. Since the exposure condition for forming the first dummy trace L1' is different from the exposure condition for forming the first trace L1, the second width W2 of the first dummy trace L1' is substantially smaller than the first width of the first trace L1. W1. However, the first pseudo-line L1 ′ is not electrically connected to the pixel structure 114 in the display area R1 , so the width or disconnection of the first pseudo-line L1 ′ does not affect the display effect of the display panel 100 . .
請繼續參照圖2,本實施例之畫素陣列基板110更包括多條第二走線L2。第二走線L2位於周邊區R2且與畫素結構114之源極S電性連接。在本實施例中,第二走線L2可透過資料線DL與畫素結構114的源極S電性連接。換言之,本實施例之第二走線L2可為資料線DL的延伸。 Referring to FIG. 2, the pixel array substrate 110 of the embodiment further includes a plurality of second traces L2. The second trace L2 is located in the peripheral region R2 and is electrically connected to the source S of the pixel structure 114. In this embodiment, the second trace L2 is electrically connected to the source S of the pixel structure 114 through the data line DL. In other words, the second trace L2 of the embodiment may be an extension of the data line DL.
本實施例之畫素陣列基板110更包括至少一第二擬走線L2’。第二擬走線L2’位於周邊區R2且與畫素結構114電性絕緣。第二擬走線L2’亦可與驅動晶片116電性絕緣。第二擬走線L2’與第二走線L2可屬同一膜層。第二走線L2位於顯示區R1與第二擬走線L2’之間。換言之,第二 擬走線L2’是位於所有第二走線L2的邊緣處。本實施例之基板112具有長邊112a及與長邊112a連接之短邊112b。第二走擬走線L2’於長邊112a上之正投影涵蓋第二走線L2於長邊112a上之正投影。並且,第二擬走線L2’於短邊112b上之正投影涵蓋第二走線L2於短邊112b上之正投影。換言之,第二擬走線L2’是順著所有第二走線L2中最靠外緣之一條第二走線L2配置的。 The pixel array substrate 110 of this embodiment further includes at least one second pseudo-line L2'. The second pseudo-line L2' is located in the peripheral region R2 and is electrically insulated from the pixel structure 114. The second dummy trace L2' can also be electrically insulated from the drive wafer 116. The second pseudo-line L2' and the second trace L2 may belong to the same film layer. The second trace L2 is located between the display area R1 and the second dummy line L2'. In other words, the second The pseudo trace L2' is located at the edge of all the second traces L2. The substrate 112 of this embodiment has a long side 112a and a short side 112b connected to the long side 112a. The orthographic projection of the second trace L2' on the long side 112a covers the orthographic projection of the second trace L2 on the long side 112a. Moreover, the orthographic projection of the second pseudo-line L2' on the short side 112b covers the orthographic projection of the second trace L2 on the short side 112b. In other words, the second pseudo-line L2' is disposed along one of the second outermost lines L2 of the outermost edges of all the second traces L2.
類似地,本實施例之第二擬走線L2’是用以確保第二走線L2的品質,以避免第二走線L2在形成過程發生寬度過小或斷線的問題,進而提升顯示面板100的顯示效果。以下配合圖示詳細說明第二擬走線L2’確保第二走線L2品質的機制。 Similarly, the second dummy trace L2 ′ of the embodiment is used to ensure the quality of the second trace L2 to avoid the problem that the width of the second trace L2 is too small or broken during the formation process, thereby improving the display panel 100. The display effect. The mechanism for ensuring the quality of the second trace L2 by the second pseudo-line L2' will be described in detail below with reference to the drawings.
圖4為圖2之局部區域B的放大示意圖。請參照圖4,在本實施例中,多條第二走線L2呈等間距排列。任意二相鄰的第二走線L1之間存在第三間距P3。第二擬走線L2’與相鄰的第二走線L2(即最接近第二擬走線L2’的第二走線L2)之間存在第四間距P4。第四間距P4實質上等於第三間距P3。由於在第二走線L2的設計中第二走線L2是呈等間距排列,因此在曝光過程中若無第二擬走線L2’之設計,則所有第二走線L2中靠外緣之第二走線L2其曝光條件與其他第二走線L2不同。這樣一來,所有第二走線L2中靠外緣之第二走線L2在蝕刻製程後便易發生寬度過小或斷線的問題。然而,透過第二擬走線L2’的配置可使靠外緣之第二走線L2的曝光條件與其他第二走線L2較為一 致,進而改善靠外緣之第二走線L2易發生寬度過小或斷線的問題。 4 is an enlarged schematic view of a partial area B of FIG. 2. Referring to FIG. 4, in the embodiment, the plurality of second traces L2 are arranged at equal intervals. There is a third pitch P3 between any two adjacent second traces L1. There is a fourth pitch P4 between the second pseudo-line L2' and the adjacent second trace L2 (i.e., the second trace L2 closest to the second trace L2'). The fourth pitch P4 is substantially equal to the third pitch P3. Since the second traces L2 are arranged at equal intervals in the design of the second trace L2, if there is no design of the second trace L2' during the exposure process, the outer edges of all the second traces L2 are The second trace L2 has different exposure conditions than the other second traces L2. In this way, the second trace L2 of the outer edge of all the second traces L2 is prone to a problem of too small width or disconnection after the etching process. However, the arrangement of the second trace L2' can make the exposure condition of the second trace L2 of the outer edge be compared with the other second traces L2. Therefore, it is easy to improve the problem that the width of the second trace L2 on the outer edge is too small or broken.
請繼續參照圖4,在本實施例中,第二走線L2具有第三寬度W3。第二擬走線L2’具有第四寬度W4。由於形成第二擬走線L2’的曝光條件與形成第二走線L2的曝光條件不同,因此第二擬走線L2’的第四寬度W4實質上會小於第二走線L2的第三寬度W3。然而,第二擬走線L2’未與顯示區R1中的畫素結構114電性連接,因此第二擬走線L2’的寬度大小或斷線與否並不會影響顯示面板100的顯示效果。 With continued reference to FIG. 4, in the present embodiment, the second trace L2 has a third width W3. The second pseudo-line L2' has a fourth width W4. Since the exposure condition for forming the second pseudo-line L2' is different from the exposure condition for forming the second trace L2, the fourth width W4 of the second pseudo-line L2' is substantially smaller than the third width of the second trace L2. W3. However, the second pseudo trace L2 ′ is not electrically connected to the pixel structure 114 in the display area R1 , so the width or disconnection of the second pseudo trace L2 ′ does not affect the display effect of the display panel 100 . .
綜上所述,在本發明一實施例之畫素陣列基板及顯示面板中,透過擬走線的配置可使所有走線的曝光條件較為一致,而減少位於外緣之走線發生寬度過小或斷線的問題,進而提升顯示面板的顯示效果。 In summary, in the pixel array substrate and the display panel according to an embodiment of the present invention, the arrangement of the traces can be made to make the exposure conditions of all the traces relatively uniform, and the width of the traces located at the outer edge is too small or The problem of disconnection, which in turn improves the display of the display panel.
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,故本發明之保護範圍當視後附之申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
100‧‧‧顯示面板 100‧‧‧ display panel
110‧‧‧畫素陣列基板 110‧‧‧ pixel array substrate
112‧‧‧基板 112‧‧‧Substrate
112a‧‧‧長邊 112a‧‧‧Longside
112b‧‧‧短邊 112b‧‧‧ Short side
114‧‧‧畫素結構 114‧‧‧ pixel structure
116‧‧‧驅動晶片 116‧‧‧Drive chip
120‧‧‧對向基板 120‧‧‧ opposite substrate
130‧‧‧顯示介質 130‧‧‧Display media
B、B‧‧‧區域 B, B‧‧‧ area
D‧‧‧汲極 D‧‧‧汲
DL‧‧‧資料線 DL‧‧‧ data line
E1‧‧‧邊緣 Edge of E1‧‧
G‧‧‧閘極 G‧‧‧ gate
L1‧‧‧第一走線 L1‧‧‧ first line
L1’‧‧‧第一擬走線 L1’‧‧‧ first proposed to walk
L2‧‧‧第二走線 L2‧‧‧Second line
L2’‧‧‧第二擬走線 L2’‧‧‧ second proposed route
PE‧‧‧畫素電極 PE‧‧‧ pixel electrode
P1~P4‧‧‧間距 P1~P4‧‧‧ spacing
R1‧‧‧顯示區 R1‧‧‧ display area
R2‧‧‧周邊區 R2‧‧‧ surrounding area
S‧‧‧源極 S‧‧‧ source
SL‧‧‧掃描線 SL‧‧‧ scan line
T‧‧‧主動元件 T‧‧‧ active components
W1~W4‧‧‧寬度 W1~W4‧‧‧Width
圖1為本發明一實施例之顯示面板的剖面示意圖。 1 is a cross-sectional view of a display panel in accordance with an embodiment of the present invention.
圖2為圖1之畫素陣列基板的上視示意圖。 2 is a top plan view of the pixel array substrate of FIG. 1.
圖3為圖2之局部區域A的放大示意圖。 FIG. 3 is an enlarged schematic view of a partial area A of FIG. 2.
圖4為圖2之局部區域B的放大示意圖。 4 is an enlarged schematic view of a partial area B of FIG. 2.
110‧‧‧畫素陣列基板 110‧‧‧ pixel array substrate
112‧‧‧基板 112‧‧‧Substrate
112a‧‧‧長邊 112a‧‧‧Longside
112b‧‧‧短邊 112b‧‧‧ Short side
114‧‧‧畫素結構 114‧‧‧ pixel structure
116‧‧‧驅動晶片 116‧‧‧Drive chip
A、B‧‧‧區域 A, B‧‧‧ area
D‧‧‧汲極 D‧‧‧汲
DL‧‧‧資料線 DL‧‧‧ data line
E1‧‧‧邊緣 Edge of E1‧‧
G‧‧‧閘極 G‧‧‧ gate
L1‧‧‧第一走線 L1‧‧‧ first line
L1’‧‧‧第一擬走線 L1’‧‧‧ first proposed to walk
L2‧‧‧第二走線 L2‧‧‧Second line
L2’‧‧‧第二擬走線 L2’‧‧‧ second proposed route
PE‧‧‧畫素電極 PE‧‧‧ pixel electrode
R1‧‧‧顯示區 R1‧‧‧ display area
R2‧‧‧周邊區 R2‧‧‧ surrounding area
S‧‧‧源極 S‧‧‧ source
SL‧‧‧掃描線 SL‧‧‧ scan line
T‧‧‧主動元件 T‧‧‧ active components
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