TW201405230A - Pixel array substrate and display panel - Google Patents

Abstract

A pixel array substrate including a substrate, a plurality of pixel structures, a plurality of first traces and at least one first dummy trace is provided. The substrate has a display region and a periphery region outside the display region. The pixel structures are arranged in an array on the display region. The first traces are disposed on the periphery region and electrically connected to the pixel structures. The first dummy trace are disposed on the periphery region and electrically insulated from the pixel structures. The first traces are disposed between the display region and the first dummy trace. Moreover, a display panel including the pixel array substrate is also provided.

Description

Pixel array substrate and display panel

The present invention relates to a pixel array substrate and a display panel, and more particularly to a pixel array substrate and a display panel having a trace.

With the rapid development of display technology, display panels have been applied to display devices of various sizes, such as televisions, computer screens, notebook computers, mobile phones, and the like. Taking mobile phones as an example, in addition to the display performance of the display panel, such as resolution, contrast, and viewing angle, the requirements for the aesthetic appearance of the display panel are also increasing. Therefore, many display panel related companies have already invested in the ranks of Narrow boarder display panels, so that display panels with the same display quality are more light, thin and short to meet consumer demand.

In order to realize a narrow-frame display panel, the operator needs to reduce the area of the surrounding traces to reduce the width of the border. In the prior art, a narrow yellow display panel is generally realized by using a sophisticated yellow light process technique to shorten the line spacing between the peripheral traces and the width of the peripheral traces. However, with the development of smart phones, the resolution of display panels is getting higher and higher, and the number of peripheral traces is also increasing, resulting in the need to continuously reduce the line spacing between peripheral traces and the width of peripheral traces. . The surrounding traces are also prone to problems of too small a width or a broken line, which in turn affects the quality of the display panel.

In view of the above, the present invention provides a pixel array substrate, which can improve the problem that the width of the trace is too small or broken, thereby improving the display quality of the display panel.

Further, the present invention provides a display panel having high display quality.

The present invention provides a pixel array substrate comprising a substrate, a plurality of pixel structures, a plurality of first traces, and at least one first trace. The substrate has a display area and a peripheral area outside the display area. The pixel structure array is arranged in the display area. The first trace is located in the peripheral area and is electrically connected to the pixel structure. The first dummy line is located in the peripheral area and is electrically insulated from the pixel structure. The first trace is located between the display area and the first trace.

The invention provides a display panel comprising the above pixel array substrate, a counter substrate and a display medium. The opposite substrate is opposed to the pixel array substrate. The display medium is located between the pixel array substrate and the opposite substrate.

In an embodiment of the invention, the first traces are arranged in a pitch arrangement. There is a first line spacing between any two adjacent first traces. There is a second line spacing between the first pseudo trace and the adjacent first trace. The second line spacing is substantially equal to the first line spacing.

In an embodiment of the invention, the first trace has a first width. The first pseudo trace has a second width. The second width is substantially smaller than the first width.

In an embodiment of the invention, the first pseudo trace is the trace closest to the edge of the substrate.

In an embodiment of the invention, the substrate has a long side and a short side connected to the long side. The orthographic projection of the first proposed line on the long side covers the first Orthographic projection of the line on the long side. The orthographic projection of the first pseudo-line on the short side covers the orthographic projection of the first trace on the short side.

In an embodiment of the invention, the pixel array substrate further includes a driving wafer. The drive wafer is located in the peripheral zone. The driving chip is electrically connected to the pixel structure through the first trace. The first pseudo trace is electrically insulated from the drive wafer.

In an embodiment of the invention, the pixel structure described above includes an active component and a pixel electrode. The active device has a source, a gate, and a drain. The pixel electrode is electrically connected to the active element. The first trace is electrically connected to the gate of the pixel structure.

In an embodiment of the invention, the pixel array substrate further includes a plurality of second traces and at least one second trace. The second trace is located in the peripheral region and is electrically connected to the source of the pixel structure. The second pseudo trace is located in the peripheral area and is electrically insulated from the pixel structure. The second trace is located between the display area and the second trace.

In an embodiment of the invention, the second traces are arranged in equal line spacing. There is a third line spacing between any two adjacent second traces. There is a fourth line spacing between the second pseudo-line and the adjacent second line. The third line spacing is substantially equal to the fourth line spacing.

In an embodiment of the invention, the second trace has a third width. The second pseudo trace has a fourth width. The fourth width is substantially smaller than the third width.

Based on the above, in the pixel array substrate and the display panel according to an embodiment of the present invention, the arrangement of the traces can be made uniform by all the traces, and the width of the traces located at the outer edge is too small or broken. Question The problem is to improve the display of the display panel.

The above described features and advantages of the present invention will be more apparent from the following description.

1 is a cross-sectional view of a display panel in accordance with an embodiment of the present invention. Referring to FIG. 1 , the display panel 100 of the present embodiment includes a pixel array substrate 110 , a counter substrate 120 , and a display medium 130 . The opposite substrate 120 is opposed to the pixel array substrate 110. The display medium 130 is located between the pixel array substrate 110 and the opposite substrate 120. In this embodiment, the opposite substrate 120 may be a color filter substrate. However, the present invention is not limited thereto. In other embodiments, the opposite substrate 120 may not include a color filter but a light-transmitting substrate having a light-transmitting conductive layer. The display medium 130 of the present embodiment is, for example, a liquid crystal. However, the present invention is not limited thereto. In other embodiments, the display medium 130 may also be an organic light-emitting layer, an electrophoretic liquid, or other suitable material.

2 is a top plan view of the pixel array substrate of FIG. 1. Referring to FIG. 2, the pixel array substrate 110 of the present embodiment includes a substrate 112, a plurality of pixel structures 114, a plurality of first traces L1, and at least one first trace L1'. The substrate 112 has a display area R1 and a peripheral area R2 located outside the display area R1. Furthermore, the peripheral region R2 of the present embodiment may be an annular region surrounding the display region R1. The substrate 112 of the embodiment may be made of glass, quartz, organic polymer, or an opaque/reflective material (for example, a conductive material, a wafer, a ceramic, or other applicable materials), or other applicable. s material. However, the invention is not limited to the above.

The pixel structure 114 of this embodiment is arranged in an array in the display area R1. The pixel structure 114 of this embodiment includes an active element T and a pixel electrode PE. The active device T has a source S, a gate G, and a drain D. The pixel electrode PE is electrically connected to the drain D of the active device T. The pixel array substrate 110 of the present embodiment further includes a plurality of scanning lines SL and a plurality of data lines DL interlaced with the scanning lines SL. The scan line SL is electrically connected to the gate G of the active device T. The data line DL is electrically connected to the source S of the active device T. The scan line SL and the data line DL belong to different film layers. Based on the conductivity considerations, the scan line SL and the data line DL are generally made of a metal material. However, the present invention is not limited thereto. In other embodiments, other conductive materials such as an alloy, a nitride of a metal material, an oxide of a metal material, an oxynitride of a metal material, or the like may be used for the scan line SL and the data line DL. Or a stack of metallic materials and other conductive materials.

The plurality of first traces L1 of the embodiment are located in the peripheral region R2 and are electrically connected to the pixel structure 114. In detail, the first trace L1 can be electrically connected to the gate G of the pixel structure 114. In the embodiment, the first trace L1 is electrically connected to the gate G of the pixel structure 114 through the scan line SL. In other words, the first trace L1 of the embodiment may be an extension of the scan line SL. The pixel array substrate 110 of this embodiment further includes a driving wafer 116 located in the peripheral region R2. The driving chip 116 can be electrically connected to the pixel structure 114 through the first trace L1. The driving chip 116 is used to drive the pixel structure 114, thereby enabling the display panel 100 to display a picture.

The first pseudo-line L1' of this embodiment is located in the peripheral area R2 and is connected to the pixel Structure 114 is electrically insulated. The first trace L1' can also be electrically insulated from the drive wafer 116. The first pseudo-line L1' and the first trace L1 belong to the same film layer. The first trace L1 is located between the display area R1 and the first dummy line L1. In other words, the first pseudo-line L1' is located at the edge of all the first traces L1. In the present embodiment, the first pseudo trace L1' may be the trace closest to the edge E1 of the substrate 112. The substrate 112 of this embodiment has a long side 112a and a short side 112b connected to the long side 112a. The orthographic projection of the first pseudo-line L1' on the long side 112a covers the orthographic projection of the first trace L1 on the long side 112a. Moreover, the orthographic projection of the first trace L1' on the short side 112b covers the orthographic projection of the first trace L1 on the short side 112b. In other words, the first pseudo-line L1' is disposed along one of the first outermost lines L1 of all the first traces L1.

It is worth mentioning that the first pseudo-route L1' of the embodiment is used to ensure the quality of the first trace L1, so as to avoid the problem that the width of the first trace L1 is too small or broken during the formation process, thereby improving The display effect of the display panel 100. The mechanism for ensuring the quality of the first trace L1 by the first pseudo trace L1' will be described in detail below with reference to the drawings.

FIG. 3 is an enlarged schematic view of a partial area A of FIG. 2. Referring to FIG. 3, in the embodiment, the plurality of first traces L1 are arranged in a pitch. There is a first pitch P1 between any two adjacent first traces L1. There is a second pitch P2 between the first pseudo trace L1' and the adjacent first trace L1 (i.e., the first trace L1 closest to the first trace L1'). The second pitch P2 is substantially equal to the first pitch P1. Since the first traces L1 are arranged at equal intervals in the design of the first trace L1, if there is no design of the first trace L1' during the exposure process, the outer edges of all the first traces L1 are The first trace L1 is exposed The light conditions are different from the other first traces L1. In this way, the first trace L1 of the outer edge of all the first traces L1 is likely to have a problem of too small width or disconnection after the etching process. However, the arrangement of the first trace L1' allows the exposure condition of the first trace L1 of the outer edge to be more consistent with the other first traces L1, thereby improving the width of the first trace L1 by the outer edge. Too small or broken.

With continued reference to FIG. 3, in the present embodiment, the first trace L1 has a first width W1. The first pseudo trace L1' has a second width W2. Since the exposure condition for forming the first dummy trace L1' is different from the exposure condition for forming the first trace L1, the second width W2 of the first dummy trace L1' is substantially smaller than the first width of the first trace L1. W1. However, the first pseudo-line L1 ′ is not electrically connected to the pixel structure 114 in the display area R1 , so the width or disconnection of the first pseudo-line L1 ′ does not affect the display effect of the display panel 100 . .

Referring to FIG. 2, the pixel array substrate 110 of the embodiment further includes a plurality of second traces L2. The second trace L2 is located in the peripheral region R2 and is electrically connected to the source S of the pixel structure 114. In this embodiment, the second trace L2 is electrically connected to the source S of the pixel structure 114 through the data line DL. In other words, the second trace L2 of the embodiment may be an extension of the data line DL.

The pixel array substrate 110 of this embodiment further includes at least one second pseudo-line L2'. The second pseudo-line L2' is located in the peripheral region R2 and is electrically insulated from the pixel structure 114. The second dummy trace L2' can also be electrically insulated from the drive wafer 116. The second pseudo-line L2' and the second trace L2 may belong to the same film layer. The second trace L2 is located between the display area R1 and the second dummy line L2'. In other words, the second The pseudo trace L2' is located at the edge of all the second traces L2. The substrate 112 of this embodiment has a long side 112a and a short side 112b connected to the long side 112a. The orthographic projection of the second trace L2' on the long side 112a covers the orthographic projection of the second trace L2 on the long side 112a. Moreover, the orthographic projection of the second pseudo-line L2' on the short side 112b covers the orthographic projection of the second trace L2 on the short side 112b. In other words, the second pseudo-line L2' is disposed along one of the second outermost lines L2 of the outermost edges of all the second traces L2.

Similarly, the second dummy trace L2 ′ of the embodiment is used to ensure the quality of the second trace L2 to avoid the problem that the width of the second trace L2 is too small or broken during the formation process, thereby improving the display panel 100. The display effect. The mechanism for ensuring the quality of the second trace L2 by the second pseudo-line L2' will be described in detail below with reference to the drawings.

4 is an enlarged schematic view of a partial area B of FIG. 2. Referring to FIG. 4, in the embodiment, the plurality of second traces L2 are arranged at equal intervals. There is a third pitch P3 between any two adjacent second traces L1. There is a fourth pitch P4 between the second pseudo-line L2' and the adjacent second trace L2 (i.e., the second trace L2 closest to the second trace L2'). The fourth pitch P4 is substantially equal to the third pitch P3. Since the second traces L2 are arranged at equal intervals in the design of the second trace L2, if there is no design of the second trace L2' during the exposure process, the outer edges of all the second traces L2 are The second trace L2 has different exposure conditions than the other second traces L2. In this way, the second trace L2 of the outer edge of all the second traces L2 is prone to a problem of too small width or disconnection after the etching process. However, the arrangement of the second trace L2' can make the exposure condition of the second trace L2 of the outer edge be compared with the other second traces L2. Therefore, it is easy to improve the problem that the width of the second trace L2 on the outer edge is too small or broken.

With continued reference to FIG. 4, in the present embodiment, the second trace L2 has a third width W3. The second pseudo-line L2' has a fourth width W4. Since the exposure condition for forming the second pseudo-line L2' is different from the exposure condition for forming the second trace L2, the fourth width W4 of the second pseudo-line L2' is substantially smaller than the third width of the second trace L2. W3. However, the second pseudo trace L2 ′ is not electrically connected to the pixel structure 114 in the display area R1 , so the width or disconnection of the second pseudo trace L2 ′ does not affect the display effect of the display panel 100 . .

In summary, in the pixel array substrate and the display panel according to an embodiment of the present invention, the arrangement of the traces can be made to make the exposure conditions of all the traces relatively uniform, and the width of the traces located at the outer edge is too small or The problem of disconnection, which in turn improves the display of the display panel.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧ display panel

110‧‧‧ pixel array substrate

112‧‧‧Substrate

112a‧‧‧Longside

112b‧‧‧ Short side

114‧‧‧ pixel structure

116‧‧‧Drive chip

120‧‧‧ opposite substrate

130‧‧‧Display media

B, B‧‧‧ area

D‧‧‧汲

DL‧‧‧ data line

Edge of E1‧‧

G‧‧‧ gate

L1‧‧‧ first line

L1’‧‧‧ first proposed to walk

L2‧‧‧Second line

L2’‧‧‧ second proposed route

PE‧‧‧ pixel electrode

P1~P4‧‧‧ spacing

R1‧‧‧ display area

R2‧‧‧ surrounding area

S‧‧‧ source

SL‧‧‧ scan line

T‧‧‧ active components

W1~W4‧‧‧Width

1 is a cross-sectional view of a display panel in accordance with an embodiment of the present invention.

2 is a top plan view of the pixel array substrate of FIG. 1.

FIG. 3 is an enlarged schematic view of a partial area A of FIG. 2.

4 is an enlarged schematic view of a partial area B of FIG. 2.

110‧‧‧ pixel array substrate

112‧‧‧Substrate

112a‧‧‧Longside

112b‧‧‧ Short side

114‧‧‧ pixel structure

116‧‧‧Drive chip

A, B‧‧‧ area

D‧‧‧汲

DL‧‧‧ data line

Edge of E1‧‧

G‧‧‧ gate

L1‧‧‧ first line

L1’‧‧‧ first proposed to walk

L2‧‧‧Second line

L2’‧‧‧ second proposed route

PE‧‧‧ pixel electrode

R1‧‧‧ display area

R2‧‧‧ surrounding area

S‧‧‧ source

SL‧‧‧ scan line

T‧‧‧ active components

Claims (20)

A pixel array substrate includes: a substrate having a display area and a peripheral area outside the display area; a plurality of pixel structures arranged in the display area; and a plurality of first traces located in the peripheral area Electrically connecting with the pixel structures; and at least one first trace, located in the peripheral region and electrically insulated from the pixel structures, wherein the first traces are located in the display region and the first Between the lines. The pixel array substrate of claim 1, wherein the first traces are arranged at equal intervals, and a first spacing exists between any two adjacent first traces, the first There is a second spacing between the trace and the adjacent first trace, the second pitch being substantially equal to the first pitch. The pixel array substrate of claim 1, wherein any one of the first traces has a first width, and the first trace has a second width, the second width being substantially smaller The first width. The pixel array substrate of claim 1, wherein the first pseudo trace is a trace closest to an edge of the substrate. The pixel array substrate of claim 1, wherein the substrate has a long side and a short side connected to the long side, and the orthographic projection of the first trace on the long side covers the An Orthographic projection of the first trace on the long side, and the orthographic projection of the first trace on the short side covers an orthographic projection of any of the first traces on the short side . The pixel array substrate of claim 1, further comprising: a driving chip located in the peripheral region, wherein the driving chip is electrically connected to the pixel structures through the first traces, and the A dummy trace is electrically insulated from the drive wafer. The pixel array substrate of claim 1, wherein each of the pixel structures comprises an active component and a pixel electrode, the active component having a source, a gate and a drain. The anode electrode is electrically connected to the anode of the active device, and the first traces are electrically connected to the gates of the pixel structures. The pixel array substrate of claim 7, further comprising: a plurality of second traces located in the peripheral region and electrically connected to the sources of the pixel structures; and at least a second The trace is located in the peripheral region and is electrically insulated from the pixel structures, wherein the second traces are located between the display region and the second trace. The pixel array substrate of claim 8, wherein the second traces are arranged at equal intervals, and a second spacing exists between any two adjacent second traces. There is a fourth spacing between the trace and the adjacent second trace, the third pitch being substantially equal to the fourth pitch. The pixel array substrate of claim 8, wherein any one of the second traces has a third width, and the second trace has a fourth width, the fourth width being substantially smaller The third width. A display panel comprising: a pixel array substrate, comprising: a substrate having a display area and a peripheral area outside the display area; a plurality of pixel structures arranged in the display area; and a plurality of first traces located in the peripheral area Electrically connecting with the pixel structures; and at least one first trace, located in the peripheral region and electrically insulated from the pixel structures, wherein the first traces are located in the display region and the first Between the traces; a pair of substrates, relative to the pixel array substrate; and a display medium between the pixel array substrate and the counter substrate. The display panel of claim 11, wherein the first traces are arranged at equal intervals, and a first pitch exists between any two adjacent first traces, the first trace There is a second spacing between the adjacent first traces, the second pitch being substantially equal to the first pitch. The display panel of claim 11, wherein any one of the first traces has a first width, and the first trace has a second width, the second width being substantially smaller than the first a width. The pixel array substrate of claim 11, wherein the first pseudo trace is a trace closest to an edge of the substrate. The display panel of claim 11, wherein the substrate has a long side and a short side connected to the long side, and the orthographic projection of the first walking line on the long side covers the first An orthographic projection of any one of the traces on the long side, and the first projection of the first trace on the short side Orthographic projection of any of the first traces on the short side. The display panel of claim 11, wherein the pixel array substrate further comprises: a driving chip located in the peripheral region, wherein the driving chip is electrically connected to the pixel structures through the first traces And the first pseudo trace is electrically insulated from the driving chip. The display panel of claim 11, wherein each of the pixel structures comprises an active component and a pixel electrode, the active component having a source, a gate and a drain, the pixel electrode The first electrode is electrically connected to the gates of the pixel structures. The display panel of claim 17, wherein the pixel array substrate further comprises: a plurality of second traces located in the peripheral region and electrically connected to the sources of the pixel structures; At least one second trace is located in the peripheral region and electrically insulated from the pixel structures, wherein the second traces are located between the display region and the second trace. The display panel of claim 18, wherein the second traces are arranged at equal intervals, and a second pitch exists between any two adjacent second traces, the second trace There is a fourth pitch between the adjacent second traces, and the third pitch is substantially equal to the fourth pitch. The display panel of claim 18, wherein any one of the second traces has a third width, and the second trace has a fourth width, the fourth width being substantially smaller than the first Three widths.