TW201403753A - Semiconductor structure formation method - Google Patents

Abstract

The invention discloses a semiconductor structure formation method, which comprises the following steps: providing a substrate, and forming a dielectric layer on the substrate; forming a first mask layer on the dielectric layer, wherein the first mask layer is provided with an opening for exposing the surface of the dielectric layer; and carrying out plasma etching on the dielectric layer through taking the first mask layer as a mask, when a bias power source is opened, etching part of the dielectric layer, and when the bias power source is closed, forming polymers on the surface of the first mask layer, and repeating the processes of opening the bias power source and closing the bias power source until a dual damascene structure with grooves and through holes is formed, wherein the bias power source outputs bias power in a pulse mode. Through adopting the plasma etching and repeating the etching step and the polymer formation step, a certain thickness of the polymer can be kept, and the first mask layer is protected from being damaged or the damage rate is reduced, thereby improving the etching selection ratio of the dielectric layer relative to the first mask layer.

Description

Method of forming a semiconductor structure

The present invention relates to the field of semiconductor fabrication, and more particularly to a method of forming a semiconductor structure.

As integrated circuits move toward sub-micron dimensions, the density of devices and the complexity of the process continue to increase, and strict control of the process becomes more important. Wherein, the recess is used to fill the metal to form a metal interconnect structure, as a connection between the active region and the active region, and between the active region and the external circuit, due to its important role in the structural composition of the device. The process of forming the grooves has always been valued by those skilled in the art.

1 to 3 are schematic structural views of a conventional groove forming process.

Referring to FIG. 1, a semiconductor substrate 100 is provided on which a dielectric layer 101 is formed, which is a single layer structure or a multilayer stack structure, for example, the dielectric layer 101 is a single layer of a ruthenium oxide layer. Structure; a mask layer 102 is formed on the surface of the dielectric layer 101, the mask layer 102 having an opening 103 exposing the surface of the dielectric layer 101, and the material of the mask layer 102 is titanium nitride.

Referring to FIG. 2, the dielectric layer 101 is etched along the opening 103 by a plasma etching process to form a recess 104 that exposes the surface of the semiconductor substrate 100. The gas used for plasma etching is CF ₄ or C ₄ F ₈ .

However, in actual production, since the material of the mask layer 102 has a certain stress, the thickness of the mask layer 102 is thin (less than 100 nm), and the fluorine radical erodes the mask layer during plasma etching. To make the mask layer thin or damaged (refer to Figure 3), the thinning or damage of the mask layer will reduce the etching selectivity of the dielectric layer relative to the mask layer, which will cause deformation of the groove formed by etching. Or bridging.

For more details on the formation of the grooves, please refer to US Patent Publication No. US2009/0224405A1.

Accordingly, it is an object of the present invention to provide a method of forming a semiconductor structure for increasing the etching selectivity of a dielectric layer relative to a mask layer.

The technical means for solving the problems of the prior art is a method for forming a semiconductor structure, comprising: providing a substrate, forming a dielectric layer on the substrate; forming a first mask layer on the dielectric layer, The first mask layer has an opening exposing a surface of the dielectric layer; the first mask layer is used as a mask, and the dielectric layer is plasma etched, and the bias power source outputs a bias power in a pulse manner. When the bias power source is turned on, etching part of the dielectric layer, when the bias power source is turned off, forming a polymer on the surface of the first mask layer, repeating the process of biasing the power source to turn on and off the bias power source, Until a double damascene structure with grooves and through holes is formed.

In an embodiment of the invention, the gas used in the plasma etching is one or more of CF ₄ , C ₄ F ₈ , C ₄ F ₆ , CHF ₃ , CH ₂ F ₂ , and CO.

In an embodiment of the invention, the gas used in the plasma etching further includes O ₂ and Ar.

In an embodiment of the invention, the plasma etched RF power source has a power of 0 to 2000 watts, the RF frequency is 60 to 120 megahertz, and the bias power source has a power of 100 to 4000 watts. The etch chamber pressure is 20~200 mTorr for 2~15 MHz.

In an embodiment of the present invention, the bias power source is turned on for a first time, and the bias power source is turned off for a second time. The ratio of the first time to the sum of the first time and the second time is the first duty cycle, and the first duty cycle remains unchanged during the plasma etching process.

In an embodiment of the invention, the first duty ratio ranges from 10% to 90%.

In an embodiment of the invention, when the plasma etching is performed, when the RF power source is turned on, the etching gas is ionized, and the bias power source lags the RF power source for a period of time.

In an embodiment of the invention, the time during which the bias power source is delayed to open is less than or equal to the second time when the bias power source is turned off.

In an embodiment of the invention, the radio frequency power source outputs the radio frequency power in a pulse manner, and the radio frequency power source is turned on for a third time in a pulse period of the output of the radio frequency power source, the radio frequency The time when the power source is turned off is the fourth time, and the ratio of the third time to the sum of the third time and the fourth time is the second duty ratio, and the second duty ratio remains unchanged during the plasma etching.

In an embodiment of the invention, the frequency of the RF power source output pulse is equal to the frequency of the bias power source output pulse.

In an embodiment of the invention, the frequency of the RF power source output pulse and the frequency of the bias power source output pulse are less than or equal to 50 kHz.

In an embodiment of the invention, the first duty cycle of the bias power source output pulse is less than the second duty cycle of the RF power source output pulse.

In an embodiment of the invention, the first duty ratio ranges from 10% to 80%, and the second duty ratio ranges from 30% to 90%.

In an embodiment of the invention, when the plasma etching is performed, when the RF power source is turned on, the etching gas is ionized, and the corresponding bias power source is also turned on.

In an embodiment of the invention, when the plasma etching is performed, when the RF power source is turned on, the etching gas is ionized, and the bias power source lags the RF power source for a period of time.

In an embodiment of the invention, the time during which the bias power source is delayed to open is less than or equal to a third time when the RF power source is turned on.

In an embodiment of the invention, the material of the dielectric layer is a low-k dielectric material or an ultra-low-K dielectric material, and the material of the first mask layer is titanium nitride.

In an embodiment of the invention, the dielectric layer has a thickness greater than 200 nanometers, and the first mask layer has a thickness less than 60 nanometers.

In an embodiment of the invention, the dual damascene structure is formed by etching the first mask layer to form a first sub-opening exposing a surface of the dielectric layer; forming a photolithography on the first mask layer a glue layer, a photoresist layer filling the first sub-opening, patterning the photoresist layer to form a second sub-opening, the position of the second sub-opening corresponding to the position of the first sub-opening, the second sub- Opening the surface of the dielectric layer, the width of the second sub-opening is smaller than the width of the first sub-opening; along the second sub-opening, the dielectric layer is etched by plasma to form a first sub-via through the dielectric layer; The patterned photoresist layer; along the second sub-opening, partially etching the dielectric layer to form a first sub-groove, the first sub-via and the first sub-groove forming a double damascus structure.

In an embodiment of the invention, the dielectric layer is a multi-layer stacked structure, including: a first dielectric layer, a second mask layer on a surface of the first dielectric layer, and a second dielectric layer on a surface of the second mask layer. The second mask layer has a third sub-opening exposing the surface of the first dielectric layer, and the second dielectric layer fills the third sub-opening.

In an embodiment of the invention, the material of the first dielectric layer and the second dielectric layer is a low-K dielectric material, an ultra-low-K dielectric material or yttrium oxide, and the material of the second mask layer is nitrogen. The ruthenium oxide, the ruthenium oxynitride, the tantalum carbide or the tantalum carbonitride, and the material of the first mask layer is photoresist or amorphous carbon.

In an embodiment of the present invention, the dual damascene structure is formed by: using a first mask layer as a mask, plasma etching the first dielectric layer to form a second sub-groove, and second The sub-groove exposes the surface of the second mask layer, the position of the second sub-groove corresponds to the position of the third sub-opening, the width of the first sub-groove is greater than the width of the third sub-opening; along the third sub-opening, The second dielectric layer is plasma etched to form a second sub-via through the second dielectric layer, and the second sub-groove and the second sub-via form a recess.

Through the technical means adopted by the present invention, during plasma etching, the RF power source turns on the ionizing etching gas to form a plasma, and the bias power source outputs the bias power in a pulse manner, when the bias power source is turned on, Etching a portion of the dielectric layer, when the bias power source is turned off, forming a polymer on the surface of the first mask layer, and protecting the first mask layer from damage or reducing the first mask during subsequent etching The rate of damage of the film layer increases the etching selectivity of the dielectric layer relative to the first mask layer.

Furthermore, the RF power source continuously outputs the RF power, and the bias power source outputs the pulse power in a pulse manner. When the plasma etching is performed, when the RF power source is turned on, the etching gas is ionized, and the corresponding bias is applied. The power source lags the RF power source for a period of time, that is, the lag power source is turned off for a period of time, and the polymer forming step is performed; after a period of time, the bias power source is turned on, and the bias power source is turned on. The normal pulse mode outputs the bias power. Before the etching step begins, the polymer forming step is performed to form a polymer on the surface of the first mask layer, so that the first mask layer is not protected at the beginning of the etching. Will be etched and damaged.

Moreover, when plasma etching is performed, the RF power source and the bias power source output the RF power and the pulse power in a pulse manner, and the output frequencies of the RF power source and the bias power source pulse are equal, the phases are the same, and the bias power source is the same. The first duty cycle of the output pulse is less than the second duty cycle of the output pulse of the RF power source. After the etching step, the RF power source is turned on, and the bias power source is turned off early, so some of the polymer is deposited in the mask. After the etching step, the RF power source and the bias power source are both turned off, the polymer forming step (deposition of the polymer is further deposited), the polymer is formed on the surface of the first mask layer, and the etching step is added. Forming a part of the polymer to make the thickness of the polymer thicker, thereby better protecting the first mask layer from being damaged or damaged, and increasing the etching selectivity of the dielectric layer relative to the first mask layer And the formation and etching effect of the polymer is better. The first duty ratio is less than the second duty ratio, the first duty ratio ranges from 10% to 80%, and the second duty ratio ranges from 30% to 90%, while improving the etching efficiency, A sufficient amount of polymer can be formed on the surface of the first mask layer.

The specific embodiments of the present invention will be further described by the following examples and the accompanying drawings.

The inventor found in the process of etching the dielectric layer by using the existing plasma etching process that since the mask layer material has a certain stress, the thickness of the mask layer is thin, and fluorine is free during plasma etching. The etched mask layer will make the mask layer thin or damaged, and the thinning or damage of the mask layer will reduce the etching selectivity ratio of the dielectric layer to the mask layer, which will cause the groove formed by etching. Deformation or bridging, which subsequently affects the stability of the device when forming an interconnect structure in the recess.

In order to solve the above problems, the inventors have proposed a method for forming a semiconductor structure. Referring to FIG. 4, FIG. 4 is a schematic flow chart of a method for forming a semiconductor structure according to a first embodiment of the present invention, including:

Step S21, providing a substrate on which a dielectric layer is formed;

Step S22, forming a first mask layer on the dielectric layer, the first mask layer having an opening exposing a surface of the dielectric layer;

Step S23, using the first mask layer as a mask, performing plasma etching on the dielectric layer, the RF power source outputs RF power in a continuous manner, and the bias power source outputs the bias power in a pulse manner. The first duty cycle of the output pulse of the bias power source remains unchanged. When the plasma etching is performed, when the RF power source is turned on, the etching gas is ionized, and the corresponding bias power source is also turned on.

5 to FIG. 8 are schematic cross-sectional structural views showing a process of forming a semiconductor structure according to a first embodiment of the present invention; FIG. 9 is a diagram showing a bias power signal outputted by a radio frequency power source and a bias power source output according to a first embodiment of the present invention; .

Referring to FIG. 5, a substrate 200 is provided on which a dielectric layer 202 is formed; a first mask layer 203 is formed on a surface of the dielectric layer 202, the first mask layer 203 having an opening exposing a surface of the dielectric layer 202 205.

The substrate 200 is one of a germanium substrate, a germanium substrate, a germanium substrate, a tantalum carbide substrate, and a gallium nitride substrate. An ion doping region, a germanium via hole, or the like (not shown) is formed in the substrate 200; a semiconductor device such as a transistor, a resistor, a capacitor, or a memory may be formed on the substrate 200 (not shown in the drawing) ).

In other embodiments of the present invention, the substrate 200 is further formed with one or more interlayer dielectric layers (not shown), and the interlayer dielectric layer is made of yttria, low-k dielectric material or ultra-low a K dielectric material in which a semiconductor structure such as a metal interconnection or a conductive plug is formed.

The material of the dielectric layer 202 is a low-k dielectric material or an ultra-low-K dielectric material, the dielectric layer has a thickness greater than 200 nm, and the material of the first mask layer 203 is titanium nitride, followed by plasma. The dielectric layer 202 is etched to form a double damascene structure having grooves and via holes. During the plasma etching process, a polymer is formed on the surface of the first mask layer 203 to protect the first mask layer 203. It will be etched to increase the etch selectivity of the dielectric layer material to the first mask layer material. Since a polymer is formed on the surface of the first mask layer 203 during the etching process, the loss of the first mask layer 203 is reduced during the etching process, and the thickness of the first mask layer 203 is less than 60 nm to reduce The stress applied to the dielectric layer 202 is small.

The double damascene structure is formed by etching the first mask layer to form a first sub-opening exposing a surface of the dielectric layer; forming a photoresist layer on the first mask layer, and filling the photoresist layer The first sub-opening, patterning the photoresist layer to form a second sub-opening, the position of the second sub-opening corresponding to the position of the first sub-opening, the second sub-opening exposing the surface of the dielectric layer, the second sub- The width of the opening is smaller than the width of the first sub-opening; along the second sub-opening, the dielectric layer is etched by plasma to form a first sub-via through the dielectric layer; and the patterned photoresist layer is removed And along the second sub-opening, the dielectric layer is partially etched by plasma to form a first sub-groove, and the first sub-via and the first sub-groove constitute a double damascene structure. When the dielectric layer is plasma etched, a polymer is formed on the surface of the photoresist layer or the first mask layer, thereby improving etching selection of the dielectric layer material and the first mask layer material or the photoresist material. ratio.

Since the process for forming the double damascene structure is a well-known technique, the embodiment of the present invention provides an improvement for forming a double damascene structure etching process. In order to explain the intention of the present invention more simply and clearly, the present embodiment and subsequent embodiments and the description are attached. In the figure, a groove is formed in the dielectric layer instead of forming a double damascene structure as an example.

In other embodiments of the present invention, the dielectric layer is a multi-layer stacked structure, including: a first dielectric layer, a second mask layer on a surface of the first dielectric layer, and a second dielectric layer on a surface of the second mask layer. The second mask layer has a third sub-opening exposing the surface of the first dielectric layer, and the second dielectric layer fills the third sub-opening. The material of the first dielectric layer and the second dielectric layer is a low-k dielectric material, an ultra-low-K dielectric material or yttrium oxide, and the material of the second mask layer is tantalum nitride, niobium oxynitride, niobium carbide Or bismuth carbonitride, the material of the first mask layer is photoresist or amorphous carbon. Subsequently, the stacked structure is etched to form a double damascene structure, and the double damascene structure is formed by: using a first mask layer as a mask, plasma etching the first dielectric layer to form a second sub-concave a second sub-groove exposing a surface of the second mask layer, the position of the second sub-groove corresponding to the position of the third sub-opening, the width of the first sub-groove being greater than the width of the third sub-opening; a sub-opening, the second dielectric layer is etched by plasma to form a second sub-via through the second dielectric layer, and the second sub-groove and the second sub-via form a dual damascene structure. When the first dielectric layer and the second dielectric layer are plasma etched, a polymer is formed on the surfaces of the first mask layer and the second mask layer, thereby increasing the first dielectric layer relative to the first mask layer. The etch selectivity ratio and the etch selectivity ratio of the second dielectric layer to the first mask layer and the second mask layer.

Referring to FIG. 6 and FIG. 7, the dielectric layer 202 is plasma etched by using the first mask layer 203 as a mask, and the RF power source outputs RF power in a continuous manner, and the bias power source is pulsed. The method outputs a bias power, and the plasma etching includes an etching step and a polymer forming step. When the RF power source is turned on and the bias power source is also turned on, the RF power is ionized to etch the gas, form a plasma, and perform etching. Step of etching a portion of the dielectric layer 202 to form an etched recess 206. When the bias power source remains open and the bias power source is turned off, a polymer forming step is performed to form a polymer on the surface of the first mask layer 203. 204.

It should be noted that the etching device used for plasma etching in this embodiment and subsequent embodiments may be an inductively coupled plasma etching device (ICP) or a capacitively coupled plasma etching device (CCP). The coupled plasma etching device and the capacitively coupled plasma etching device provide a radio frequency power source with a frequency greater than or equal to 27 MHz and a bias power source frequency of 15 MHz or less. When the etching device is a capacitively coupled plasma etching device, a radio frequency power source may be applied to the upper electrode or applied to the upper and lower electrodes for generating radio frequency power, ionizing the etching gas, generating a plasma, and controlling the plasma. The density of the body; a bias power source is applied to the lower electrode for generating bias power, affecting sheath properties (sheath voltage or accelerating voltage), and controlling the energy distribution of the plasma. When the etching device is an inductively coupled plasma etching device, a radio frequency power source can be applied to the inductor coil for generating radio frequency power, ionizing the etching gas, generating a plasma, and controlling the density of the plasma; bias power A source is applied to the lower electrode for generating bias power, affecting sheath properties (sheath voltage or accelerating voltage), and controlling the energy distribution of the plasma.

Referring to FIG. 9, FIG. 9 is a diagram of a bias power signal outputted by a radio frequency power source and a bias power source output of the RF power source according to the embodiment. The RF power source continuously outputs the RF power, and the bias power source outputs the pulse power in a pulse manner. When the plasma etching is performed, when the RF power source is turned on, the ionizing etching gas is turned on, and the corresponding bias power source is also turned on, and the bias power source is turned on within one pulse period C1 of the bias power source output. The time is the first time T1, the time when the bias power source is off is the second time T2, and the ratio of the first time T1 to the sum of the first time T1 and the second time T2 is the first duty ratio, the bias power source The first duty cycle of the output pulse remains unchanged. During plasma etching, the RF power source continuously outputs RF power (always open), the RF power ionizes the etching gas to form a plasma, and when the bias power source is turned on (output bias power), the etching step is performed; When the power source is turned off (no bias power is output), a polymer formation step is performed. The first duty ratio is 10% to 90%, and the first duty ratio is preferably 30% to 70%, so that the etching step and the polymer forming step are kept for a certain period of time, and the plasma is engraved. In the etch, while increasing the etching efficiency, a sufficient amount of polymer is formed on the surface of the first mask layer, so that the rate at which the first mask layer is not damaged or damaged is reduced, and the dielectric layer is increased relative to the first layer. The etching selectivity of the mask layer.

Continuing to refer to FIG. 6 and FIG. 7 , when the plasma etching is started, when the RF power source is turned on and the bias power source is simultaneously turned on, the etching step is performed, and the RF power is ionized to etch the gas, and the plasma is excited and etched. a portion of the dielectric layer 202 forms an etched recess 206; when the RF power source remains open and the bias power source is turned off, a polymer forming step is performed to form a polymer 204 on the surface of the first mask layer 203. The polymer 204 protects the first mask layer 203 from being damaged or damaged at the rate of etching the dielectric layer 202 along the etched recess 206 during the next etch cycle, thereby increasing the dielectric layer 202 relative to the first mask. The etching selectivity of the film layer 203. In the polymer forming step, the sidewall of the etched recess 206 also forms a portion of the polymer (not shown), and the sidewall of the protective etched trench 206 is not overetched during the next etch cycle. The resulting groove sidewalls have a better morphology.

The plasma etched RF power source has a power of 0 to 2000 watts, an RF frequency of 60 to 120 megahertz, a bias power source of 100 to 4000 watts, a bias frequency of 2 to 15 MHz, and etching. The cavity pressure is 20~200 mTorr, and the bias power source is turned on and off at a frequency of 50 kHz or less. When plasma etching is performed, the etching efficiency is improved while the surface of the first mask layer 203 is increased. A sufficient amount of polymer is formed such that the first mask layer 203 is not damaged, increasing the etching selectivity of the dielectric layer 202 relative to the first mask layer 203.

The gas used in the plasma etching is one or more of CF ₄ , C ₄ F ₈ , C ₄ F ₆ , CHF ₃ , CH ₂ F ₂ , CO, and the gas used for the etching further includes O _{2 .} And Ar. CF ₄ , C ₄ F ₈ , C ₄ F _{6 are} used to provide a fluorocarbon reactant, CHF ₃ , CH ₂ F _{2 are} used to increase the concentration of the polymer, O _{2 is} used to control the amount of the polymer, and Ar is used to form a positive Ions, CO are used to control the proportion of fluorocarbon, and Ar is used to provide the energy of the reaction.

The gas used in the plasma etching in this embodiment is a mixed gas of CF ₄ , C ₄ F ₈ , C ₄ F ₆ , CHF ₃ , CH ₂ F ₂ , O ₂ , CO and Ar to ensure plasma engraving. During the etching process, sufficient polymer is formed on the surface of the mask layer 203. When the RF power source is turned on and the bias power source is also turned on, CF ₄ , C ₄ F ₈ , C ₄ F ₆ , CHF ₃ , CH ₂ F ₂ etc. will be ionized by RF power to generate F radicals, neutral CF _{2 .} When the molecular fragments are generated, some positive ions such as CF ₃ ⁺ are also generated. Ar also loses electrons to form Ar ⁺ positive ions. The positive ions are accelerated by the plasma sheath and the bias power, which will bombard the medium. The layer material removes part of the dielectric layer, and the F radical also chemically reacts with the dielectric layer material to remove part of the dielectric layer material; when the RF power source is turned on and the bias power source is turned off, the ionization process of the etching gas is always performed. The neutral active component such as CF ₂ formed by ionization will form a fluorocarbon polymer and deposit on the surface of the first mask layer 203. Since there is no accelerating electric field or the acceleration electric field is small, the positive ions are not formed by bombardment. The polymer 204 or the bombardment force is reduced, so that all or part of the formed polymer 204 is preserved. When the etching is continued, the first mask layer 203 is protected from damage due to the presence of the polymer 204 of a certain thickness. The rate of damage is reduced.

Referring to FIG. 8, the above etching step and polymer forming step are repeated, and the dielectric layer 202 is etched along the etching recess 203 until a recess is formed.

Repeating the etching step and the polymer forming step, so that the polymer 204 can always maintain a certain thickness, thereby protecting the first mask layer 203 from being damaged or being damaged at a reduced rate during the entire etching process, thereby improving The etch selectivity ratio of the dielectric layer 202 relative to the first mask layer 203 is such that the etch selectivity ratio of the dielectric layer 202 relative to the first mask layer 203 is greater than 15:1.

Referring to FIG. 10, FIG. 10 is a schematic flow chart of a method for forming a semiconductor structure according to a second embodiment of the present invention, including:

Step S31, providing a substrate on which a dielectric layer is formed;

Step S32, forming a first mask layer on the dielectric layer, the first mask layer having an opening exposing a surface of the dielectric layer;

Step S33, using the first mask layer as a mask, performing plasma etching on the dielectric layer, the RF power source outputs RF power in a continuous manner, and the bias power source outputs the bias power in a pulse manner. The first duty cycle of the output pulse of the bias power source remains unchanged. When the plasma etching is performed, when the RF power source is turned on, the etching gas is ionized, and the bias power source lags the RF power source for a period of time.

11 to FIG. 14 are schematic cross-sectional structural views showing a process of forming a semiconductor structure according to a second embodiment of the present invention; FIG. 15 is a diagram showing a bias power signal output of a radio frequency power source and a bias power source output according to a second embodiment of the present invention; .

Referring to FIG. 11, a substrate 300 is provided on which a dielectric layer 302 is formed; a first mask layer 303 is formed on a surface of the dielectric layer 302, the first mask layer 303 having an opening exposing a surface of the dielectric layer 302 305.

The substrate 300 is one of a germanium substrate, a germanium substrate, a germanium substrate, a tantalum carbide substrate, and a gallium nitride substrate. An ion doping region, a germanium via hole, or the like (not shown) is formed in the substrate 300; a semiconductor device such as a transistor, a resistor, a capacitor, or a memory may be formed on the substrate 300 (not shown in the drawing) ).

In other embodiments of the present invention, the substrate 300 is further formed with one or more interlayer dielectric layers (not shown), and the interlayer dielectric layer is made of yttria, low-k dielectric material or ultra-low a K dielectric material in which a semiconductor structure such as a metal interconnection or a conductive plug is formed.

The material of the dielectric layer 302 is a low-k dielectric material or an ultra-low-K dielectric material, the dielectric layer has a thickness greater than 200 nm, and the material of the first mask layer 303 is titanium nitride, followed by plasma. The dielectric layer 302 is etched to form a double damascene structure having grooves and via holes. During the plasma etching process, a polymer is formed on the surface of the first mask layer 303 to protect the first mask layer 303. It will be etched to increase the etch selectivity of the dielectric layer material to the first mask layer material. Since the polymer is formed in the first mask layer 303 during the etching process, the loss of the first mask layer 303 is reduced during the etching process, and the thickness of the first mask layer 303 is less than 60 nm to reduce The stress applied to the dielectric layer 302.

The double damascene structure is formed by etching the first mask layer to form a first sub-opening exposing a surface of the dielectric layer; forming a photoresist layer on the first mask layer, and filling the photoresist layer The first sub-opening, patterning the photoresist layer to form a second sub-opening, the position of the second sub-opening corresponding to the position of the first sub-opening, the second sub-opening exposing the surface of the dielectric layer, the second sub- The width of the opening is smaller than the width of the first sub-opening; along the second sub-opening, the dielectric layer is etched by plasma to form a first sub-via through the dielectric layer; and the patterned photoresist layer is removed And along the second sub-opening, the dielectric layer is partially etched by plasma to form a first sub-groove, and the first sub-via and the first sub-groove constitute a double damascene structure. When the dielectric layer is plasma etched, a polymer is formed on the surface of the photoresist layer or the first mask layer, thereby improving etching selection of the dielectric layer material and the first mask layer material or the photoresist material. ratio.

In other embodiments of the present invention, the dielectric layer is a multi-layer stacked structure, including: a first dielectric layer, a second mask layer on a surface of the first dielectric layer, and a second dielectric layer on a surface of the second mask layer. The second mask layer has a third sub-opening exposing the surface of the first dielectric layer, and the second dielectric layer fills the third sub-opening. The material of the first dielectric layer and the second dielectric layer is a low-k dielectric material, an ultra-low-K dielectric material or yttrium oxide, and the material of the second mask layer is tantalum nitride, niobium oxynitride, niobium carbide Or bismuth carbonitride, the material of the first mask layer is photoresist or amorphous carbon. Subsequently, the stacked structure is etched to form a double damascene structure, and the double damascene structure is formed by: using a first mask layer as a mask, plasma etching the first dielectric layer to form a second sub-concave a second sub-groove exposing a surface of the second mask layer, the position of the second sub-groove corresponding to the position of the third sub-opening, the width of the first sub-groove being greater than the width of the third sub-opening; a sub-opening, the second dielectric layer is etched by plasma to form a second sub-via through the second dielectric layer, and the second sub-groove and the second sub-via form a dual damascene structure. When the first dielectric layer and the second dielectric layer are plasma etched, a polymer is formed on the surfaces of the first mask layer and the second mask layer, thereby increasing the first dielectric layer relative to the first mask layer. The etch selectivity ratio and the etch selectivity ratio of the second dielectric layer to the first mask layer and the second mask layer.

Referring to FIG. 12 and FIG. 13 , the dielectric layer 302 is plasma etched by using the first mask layer 303 as a mask, and the RF power source outputs RF power in a continuous manner, and the bias power source is pulsed. The output bias power is maintained, and the first duty ratio of the output pulse of the bias power source remains unchanged. The plasma etching includes an etching step and a polymer forming step, and when the plasma etching is started, when the RF power source is Opening, ionizing the etching gas to form a plasma, the bias power source lags the RF power source for a period of time, that is, the bias power source is turned off, and the polymer forming step is performed to form a polymerization on the surface of the first mask layer 303. The RF power source remains open, then the bias power source is turned on, an etching step is performed, and the dielectric layer 302 is etched along the opening 305 to form an etched recess 306.

In this embodiment, when the plasma etching is started, when the RF power source is turned on, the etching gas is ionized to form a plasma, and the bias power source lags the RF power source for a period of time, compared to the first embodiment. Before the etching step begins, a polymer forming step is performed to form a polymer on the surface of the first mask layer 303, thereby protecting the first mask layer 303 from etching damage at the beginning of etching.

Referring to FIG. 15, FIG. 15 is a diagram showing a bias power signal outputted by a radio frequency power source and a bias power source output of the RF power source according to the embodiment, a continuous output RF power of the RF power source, and a bias power source outputting a pulse power in a pulse manner. When the plasma etching is performed, when the RF power source is turned on, the etching gas is ionized, and the corresponding bias power source lags the RF power source for a period of time ΔT1 is turned on, that is, ΔT1 time, the bias power source Is closed, at this time the polymer formation step; after ΔT1, the bias power source is turned on, the bias power source outputs the bias power in a normal pulse manner, and the bias power source outputs a pulse period C1, The time when the bias power source is turned on is the first time T1, and the time when the bias power source is turned off is the second time T2, and the ratio of the first time T1 to the sum of the first time T1 and the second time T2 is the first duty ratio. The first duty cycle of the output pulse of the bias power source remains unchanged. When the plasma is etched, the RF power source continuously outputs the RF power (always open), and the RF power ionizes the etching gas to form a plasma. The bias power source is turned on (the bias power output), the step of etching; when the bias power source is turned off (no bias power output), a step for forming the polymer. The hysteresis time ΔT1 is less than or equal to the second time T2 when the bias power source is turned off, and a certain thickness of the polymer is formed without affecting the etching efficiency, and the first duty ratio is 10% to 90. Preferably, the first duty ratio is 30% to 70%, so that the etching step and the polymer forming step are maintained for a certain period of time, and during the plasma etching, while improving the etching efficiency, The surface of the first mask layer forms a sufficient amount of polymer such that the rate at which the first mask layer is not damaged or damaged is reduced, increasing the etching selectivity of the dielectric layer relative to the first mask layer.

Continuing to refer to FIG. 12 and FIG. 13 , the plasma etched RF power source has a power of 0 to 2000 watts, an RF frequency of 60 to 120 MHz, and a bias power source of 100 to 4,000 watts. 2~15 MHz, the etching chamber pressure is 20~200 mTorr, and the bias power source is turned on and off at a frequency of 50 kHz or less. When plasma etching is performed, the etching efficiency is improved. A sufficient amount of polymer is formed on the surface of the first mask layer 303 such that the first mask layer 303 is not damaged, and the etching selectivity ratio of the dielectric layer 302 to the first mask layer 303 is increased.

The gas used in the plasma etching is one or more of CF ₄ , C ₄ F ₈ , C ₄ F ₆ , CHF ₃ , CH ₂ F ₂ , CO, and the gas used for the etching further includes O _{2 .} And Ar. CF ₄ , C ₄ F ₈ , C ₄ F _{6 are} used to provide a fluorocarbon reactant, CHF ₃ , CH ₂ F _{2 are} used to increase the concentration of the polymer, O _{2 is} used to control the amount of the polymer, and Ar is used to form a positive Ions, CO are used to control the proportion of fluorocarbon, and Ar is used to provide the energy of the reaction.

The gas used in the plasma etching in this embodiment is a mixed gas of CF ₄ , C ₄ F ₈ , C ₄ F ₆ , CHF ₃ , CH ₂ F ₂ , O ₂ , CO and Ar to ensure plasma engraving. During the etching process, sufficient polymer is formed on the surface of the mask layer 303. When the RF power source is turned on and the bias power source is also turned on, CF ₄ , C ₄ F ₈ , C ₄ F ₆ , CHF ₃ , CH ₂ F ₂ etc. will be dissociated by RF power to generate F radicals, neutral CF _{2 .} When the molecular fragments are generated, some positive ions such as CF ₃ ⁺ are also generated. Ar also loses electrons to form Ar ⁺ positive ions. The positive ions are accelerated by the plasma sheath and the bias power, which will bombard the medium. The layer material removes part of the dielectric layer, and the F radical also chemically reacts with the dielectric layer material to remove part of the dielectric layer material; when the RF power source is turned on and the bias power source is turned off, the active component is still present in the chamber. Neutral active ingredients such as CF ₂ may be combined to form a fluorocarbon polymer deposited on the surface of the first mask layer 303. Since there is no accelerating electric field or the acceleration electric field is small, the positive ions do not bombard the formed polymer 304. Or the bombardment force is reduced, so that all or part of the formed polymer 304 is preserved, and when the etching is continued, the first mask layer 303 is protected from damage or damage due to the presence of the polymer 304 of a certain thickness. small. In this embodiment, since the bias power source lags the RF power source for a period of time, a polymer is first formed on the surface of the first mask layer 303 before the etching step begins, thereby protecting the first at the beginning of the etching. The mask layer 303 is not damaged by etching.

Referring to FIG. 14, the above etching step and polymer forming step are repeated, and the dielectric layer 302 is etched along the etching recess 303 until a recess is formed.

The bias power source outputs the bias power in a pulsed manner, and during the plasma etching, the etching step and the polymer forming step are repeated, so that the polymer 304 can always maintain a certain thickness, thereby protecting the entire etching process. The first mask layer 303 is not damaged or the rate of damage is reduced, and the etching selectivity ratio of the dielectric layer 302 relative to the first mask layer 303 is increased, so that the dielectric layer 302 is inscribed with respect to the first mask layer 303. The eccentricity selection ratio is greater than 15:1.

Referring to FIG. 16, FIG. 16 is a schematic flowchart diagram of a method for forming a semiconductor structure according to a third embodiment of the present invention, including:

Step S41, providing a substrate on which a dielectric layer is formed;

Step S42, forming a first mask layer on the dielectric layer, the first mask layer having an opening exposing a surface of the dielectric layer;

Step S43, using the first mask layer as a mask, performing plasma etching on the dielectric layer, and the RF power source and the bias power source output the RF power and the pulse power in a pulse manner, and the RF power source and the bias voltage The output frequency of the power source pulse is equal, and the first duty ratio of the output pulse of the bias power source is smaller than the second duty ratio of the output pulse of the RF power source. When the plasma etching is performed, when the RF power source is turned on, the ionization is performed. The etching gas is applied, and the corresponding bias power source is also turned on.

17 to FIG. 20 are schematic cross-sectional structural views showing a process of forming a semiconductor structure according to a third embodiment of the present invention; and FIG. 21 is a diagram showing a bias power signal of an output of a radio frequency power source and a bias power source output according to a third embodiment of the present invention; .

Referring to FIG. 17, a substrate 400 is provided on which a dielectric layer 402 is formed; a first mask layer 403 is formed on a surface of the dielectric layer 402, the first mask layer 403 having an opening exposing a surface of the dielectric layer 402 405.

The substrate 400 is one of a germanium substrate, a germanium substrate, a germanium substrate, a tantalum carbide substrate, and a gallium nitride substrate. An ion doping region, a germanium via hole, or the like (not shown) is formed in the substrate 400; a semiconductor device such as a transistor, a resistor, a capacitor, or a memory may be formed on the substrate 400 (not shown in the drawing) ).

In other embodiments of the present invention, the substrate 400 is further formed with one or more interlayer dielectric layers (not shown), and the interlayer dielectric layer is made of yttria, low-k dielectric material or ultra-low a K dielectric material in which a semiconductor structure such as a metal interconnection or a conductive plug is formed.

The material of the dielectric layer 402 is a low-k dielectric material or an ultra-low-K dielectric material, the dielectric layer has a thickness greater than 200 nm, and the material of the first mask layer 403 is titanium nitride, followed by plasma. The dielectric layer 402 is etched to form a double damascene structure having grooves and via holes. During the plasma etching process, a polymer is formed on the surface of the first mask layer 403 to protect the first mask layer 403. It will be etched to increase the etch selectivity of the dielectric layer material to the first mask layer material. Since the polymer is formed in the first mask layer 403 during the etching process, the loss of the first mask layer 303 is reduced during the etching process, and the thickness of the first mask layer 403 is less than 60 nm to reduce The stress applied to the dielectric layer 402.

The double damascene structure is formed by etching the first mask layer to form a first sub-opening exposing a surface of the dielectric layer; forming a photoresist layer on the first mask layer, and filling the photoresist layer The first sub-opening, patterning the photoresist layer to form a second sub-opening, the position of the second sub-opening corresponding to the position of the first sub-opening, the second sub-opening exposing the surface of the dielectric layer, the second sub- The width of the opening is smaller than the width of the first sub-opening; along the second sub-opening, the dielectric layer is etched by plasma to form a first sub-via through the dielectric layer; and the patterned photoresist layer is removed And along the second sub-opening, the dielectric layer is partially etched by plasma to form a first sub-groove, and the first sub-via and the first sub-groove constitute a double damascene structure. When the dielectric layer is plasma etched, a polymer is formed on the surface of the photoresist layer or the first mask layer, thereby improving etching selection of the dielectric layer material and the first mask layer material or the photoresist material. ratio.

In other embodiments of the present invention, the dielectric layer is a multi-layer stacked structure, including: a first dielectric layer, a second mask layer on a surface of the first dielectric layer, and a second dielectric layer on a surface of the second mask layer. The second mask layer has a third sub-opening exposing the surface of the first dielectric layer, and the second dielectric layer fills the third sub-opening. The material of the first dielectric layer and the second dielectric layer is a low-k dielectric material, an ultra-low-K dielectric material or yttrium oxide, and the material of the second mask layer is tantalum nitride, niobium oxynitride, niobium carbide Or bismuth carbonitride, the material of the first mask layer is photoresist or amorphous carbon. Subsequently, the stacked structure is etched to form a double damascene structure, and the double damascene structure is formed by: using a first mask layer as a mask, plasma etching the first dielectric layer to form a second sub-concave a second sub-groove exposing a surface of the second mask layer, the position of the second sub-groove corresponding to the position of the third sub-opening, the width of the first sub-groove being greater than the width of the third sub-opening; a sub-opening, the second dielectric layer is etched by plasma to form a second sub-via through the second dielectric layer, and the second sub-groove and the second sub-via form a dual damascene structure. When the first dielectric layer and the second dielectric layer are plasma etched, a polymer is formed on the surfaces of the first mask layer and the second mask layer, thereby increasing the first dielectric layer relative to the first mask layer. The etch selectivity ratio and the etch selectivity ratio of the second dielectric layer to the first mask layer and the second mask layer.

Referring to FIG. 18 and FIG. 19, the dielectric layer 402 is plasma etched by using the first mask layer 403 as a mask, and the RF power source and the bias power source output the RF power and the pulse power in a pulse manner. The output frequency of the RF power source and the bias power source pulse are equal, and the first duty ratio of the output pulse of the bias power source is smaller than the second duty ratio of the output pulse of the RF power source, when the plasma etching is performed, when The RF power source is turned on, ionizing the etching gas, and the corresponding bias power source is also turned on. The plasma etching includes an etching step and a polymer forming step. When the plasma etching is started, an etching step is performed, and the dielectric layer 402 is etched along the opening 405 to form an etching recess 406; when the RF power is When the source is turned off and the bias power source is also turned off, the polymer 404 is formed on the surface of the first mask layer 303, and when the etching is continued, the first mask layer 303 is protected from damage or the rate of damage is reduced.

Referring to FIG. 21, FIG. 21 is a diagram of a bias power signal outputted by a radio frequency power source and a bias power source output of the RF power source according to the embodiment. The RF power source outputs the RF power in a pulsed manner, and the bias power source is pulsed. Output pulse power, the frequency of the output pulse of the RF power source and the bias power source are equal, the phase is the same, and the bias power source is turned on for one pulse period C1, and the bias power source is turned on for the first time T1, the bias power source The closing time is the second time T2, and the ratio of the first time T1 to the sum of the first time T1 and the second time T2 is the first duty ratio, and the RF power source is turned on within one pulse period C2 of the RF power source output. The time is the third time T3, the time when the RF power source is off is the fourth time T4, and the ratio of the third time T3 to the sum of the third time T3 and the fourth time T4 is the second duty ratio, and the first duty ratio is less than The second duty ratio, the first duty ratio ranges from 10% to 80%, and the second duty ratio ranges from 30% to 90%, for example, the first duty ratio is 40%, and the second ratio is The air ratio is 60%, and while improving the etching efficiency, it can be in the first Sufficient polymer film layer formed on the surface.

In this embodiment, when plasma etching is performed, the RF power source and the bias power source output the RF power and the pulse power in a pulse manner, and the output frequencies of the RF power source and the bias power source pulse are equal, the phases are the same, and the offset is The first duty cycle of the output pulse of the power source is less than the second duty cycle of the output pulse of the RF power source. After the etching step, the RF power source is turned on, and the bias power source is turned off early, so part of the polymer Deposited on the surface of the mask layer. After the etching step, the RF power source and the bias power source are both turned off, the polymer forming step is performed, a polymer is formed on the surface of the first mask layer, and a partial polymerization is formed in the etching step. To make the thickness of the polymer thicker, thereby better protecting the first mask layer from being damaged or damaged, increasing the etching selectivity of the dielectric layer relative to the first mask layer, and polymerizing The formation and etching effect of the object is better.

With continued reference to FIG. 18 and FIG. 19, the plasma etched RF power source has a power of 0 to 2000 watts, an RF frequency of 60 to 120 megahertz, and a bias power source of 100 to 4,000 watts. 2~15 MHz, the etching chamber pressure is 20~200 mTorr, and the frequency of opening and closing the RF power source is less than or equal to 50 kHz. When performing plasma etching, while improving the etching efficiency, A sufficient amount of polymer is formed on the surface of the first mask layer 403 such that the first mask layer 403 is not damaged, and the etching selectivity ratio of the dielectric layer 402 to the first mask layer 403 is increased.

The gas used in the plasma etching is one or more of CF ₄ , C ₄ F ₈ , C ₄ F ₆ , CHF ₃ , CH ₂ F ₂ , CO, and the gas used for the etching further includes O _{2 .} And Ar. CF ₄ , C ₄ F ₈ , C ₄ F _{6 are} used to provide a fluorocarbon reactant, CHF ₃ , CH ₂ F _{2 are} used to increase the concentration of the polymer, O _{2 is} used to control the amount of the polymer, and Ar is used to form a positive Ions, CO are used to control the proportion of fluorocarbon, and Ar is used to provide the energy of the reaction.

The gas used in the plasma etching in this embodiment is a mixed gas of CF ₄ , C ₄ F ₈ , C ₄ F ₆ , CHF ₃ , CH ₂ F ₂ , O ₂ , CO and Ar to ensure plasma engraving. During the etching process, sufficient polymer is formed on the surface of the mask layer 403. In the etching step, when the RF power source is turned on and the bias power source is also turned on, CF ₄ , C ₄ F ₈ , C ₄ F ₆ , CHF ₃ , CH ₂ F _{2 ,} etc. are dissociated by RF power to generate F radicals. Neutral molecular fragments such as CF ₂ will also generate some positive ions such as CF ₃ ^+, etc. Ar will also lose electrons to form Ar ⁺ positive ions, and positive ions pass through the plasma sheath and bias power. Acceleration will bombard the dielectric layer material and remove part of the dielectric layer. At the same time, the F radical will chemically react with the dielectric layer material to remove part of the dielectric layer material. In the latter part of the etching step, the bias power source is turned off in advance. The polymer is deposited on the surface of the first mask layer 403; after the etching step, the polymer forming step is performed, the RF power source is turned off, and the bias power source is also turned off. At this time, the active component is still present in the chamber, and the neutral activity is present. A component such as CF ₂ or the like is compounded to form a fluorocarbon polymer deposited on the surface of the first mask layer 403. Since there is no accelerating electric field, the positive ions do not bombard the formed polymer, so that all or part of the formed polymer is preserved. ,by After the etching step, a part of the polymer is formed on the surface of the first mask layer 403, and the polymer formed by the polymer forming step is added to make the thickness of the polymer 404 thicker, and then further etching is performed, thereby being better. The rate at which the first mask layer 403 is protected from damage or damage is reduced.

Referring to FIG. 20, the above etching step and polymer forming step are repeated, and the dielectric layer 402 is etched along the etching recess 403 until a recess is formed.

When plasma etching is performed, the RF power source and the bias power source output the RF power and the pulse power in a pulse manner, and the output frequencies of the RF power source and the bias power source pulse are equal, the phases are the same, and the bias power source outputs the pulse. The first duty ratio is less than the second duty ratio of the RF power source output pulse, and the etching step and the polymer forming step are repeated, so that the polymer 404 can always maintain a certain thickness, thereby protecting the entire etching process. The mask layer 403 is not damaged or the rate of damage is reduced, and the etching selectivity of the dielectric layer 402 relative to the first mask layer 403 is increased, so that the dielectric layer 402 is etched relative to the first mask layer 403. The selection ratio is greater than 15:1.

Referring to FIG. 22, FIG. 22 is a schematic flowchart diagram of a method for forming a semiconductor structure according to a fourth embodiment of the present invention, including:

Step S51, providing a substrate on which a dielectric layer is formed;

Step S52, forming a first mask layer on the dielectric layer, the first mask layer having an opening exposing a surface of the dielectric layer;

Step S53, using the first mask layer as a mask, performing plasma etching on the dielectric layer, and the RF power source and the bias power source output the RF power and the pulse power in a pulse manner, and the RF power source and the bias voltage The output frequency of the power source pulse is equal, and the first duty ratio of the output pulse of the bias power source is smaller than the second duty ratio of the output pulse of the RF power source. When the plasma etching is performed, when the RF power source is turned on, the ionization is performed. Etching the gas, the bias power source lags the RF power source for a period of time.

23 to FIG. 26 are schematic cross-sectional structural views showing a process of forming a semiconductor structure according to a fourth embodiment of the present invention; FIG. 27 is a diagram showing a bias power signal outputted by a radio frequency power source and a bias power source output according to a fourth embodiment of the present invention; .

Referring to FIG. 23, a substrate 500 is provided on which a dielectric layer 502 is formed; a first mask layer 503 is formed on a surface of the dielectric layer 502, the first mask layer 503 having an opening exposing a surface of the dielectric layer 502 505.

The substrate 500 is one of a germanium substrate, a germanium substrate, a germanium substrate, a tantalum carbide substrate, and a gallium nitride substrate. An ion doping region, a germanium via hole, or the like (not shown) is formed in the substrate 500; a semiconductor device such as a transistor, a resistor, a capacitor, or a memory may be formed on the substrate 500 (not shown in the drawing) ).

In other embodiments of the present invention, the substrate 500 is further formed with one or more interlayer dielectric layers (not shown), and the interlayer dielectric layer is made of yttria, low-k dielectric material or ultra-low a K dielectric material in which a semiconductor structure such as a metal interconnection or a conductive plug is formed.

The material of the dielectric layer 502 is a low-k dielectric material or an ultra-low-K dielectric material, the dielectric layer has a thickness greater than 200 nm, and the material of the first mask layer 503 is titanium nitride, followed by plasma. The dielectric layer 502 is etched to form a double damascene structure having grooves and through holes. During the plasma etching process, a polymer is formed on the surface of the first mask layer 503 to protect the first mask layer 503. It will be etched to increase the etch selectivity of the dielectric layer material to the first mask layer material. Since the polymer is formed in the first mask layer 503 during the etching process, the loss of the first mask layer 503 is reduced during the etching process, and the thickness of the first mask layer 503 is less than 60 nm to reduce The stress applied to the dielectric layer 502.

The double damascene structure is formed by etching the first mask layer to form a first sub-opening exposing a surface of the dielectric layer; forming a photoresist layer on the first mask layer, and filling the photoresist layer The first sub-opening, patterning the photoresist layer to form a second sub-opening, the position of the second sub-opening corresponding to the position of the first sub-opening, the second sub-opening exposing the surface of the dielectric layer, the second sub- The width of the opening is smaller than the width of the first sub-opening; along the second sub-opening, the dielectric layer is etched by plasma to form a first sub-via through the dielectric layer; and the patterned photoresist layer is removed And along the second sub-opening, the dielectric layer is partially etched by plasma to form a first sub-groove, and the first sub-via and the first sub-groove constitute a double damascene structure. When the dielectric layer is plasma etched, a polymer is formed on the surface of the photoresist layer or the first mask layer, thereby improving etching selection of the dielectric layer material and the first mask layer material or the photoresist material. ratio.

In other embodiments of the present invention, the dielectric layer is a multi-layer stacked structure, including: a first dielectric layer, a second mask layer on a surface of the first dielectric layer, and a second dielectric layer on a surface of the second mask layer. The second mask layer has a third sub-opening exposing the surface of the first dielectric layer, and the second dielectric layer fills the third sub-opening. The material of the first dielectric layer and the second dielectric layer is a low-k dielectric material, an ultra-low-K dielectric material or yttrium oxide, and the material of the second mask layer is tantalum nitride, niobium oxynitride, niobium carbide Or bismuth carbonitride, the material of the first mask layer is photoresist or amorphous carbon. Subsequently, the stacked structure is etched to form a double damascene structure, and the double damascene structure is formed by: using a first mask layer as a mask, plasma etching the first dielectric layer to form a second sub-concave a second sub-groove exposing a surface of the second mask layer, the position of the second sub-groove corresponding to the position of the third sub-opening, the width of the first sub-groove being greater than the width of the third sub-opening; a sub-opening, the second dielectric layer is etched by plasma to form a second sub-via through the second dielectric layer, and the second sub-groove and the second sub-via form a dual damascene structure. When the first dielectric layer and the second dielectric layer are plasma etched, a polymer is formed on the surfaces of the first mask layer and the second mask layer, thereby increasing the first dielectric layer relative to the first mask layer. The etch selectivity ratio and the etch selectivity ratio of the second dielectric layer to the first mask layer and the second mask layer.

Referring to FIG. 24 and FIG. 25, the dielectric layer 502 is plasma etched by using the first mask layer 503 as a mask, and the RF power source and the bias power source output the RF power and the pulse power in a pulse manner. The output frequency of the RF power source and the bias power source pulse are equal, the first duty ratio of the bias power source output pulse is smaller than the second duty ratio of the RF power source output pulse, and the plasma etching includes an etching step And a polymer forming step, when the plasma etching is started, when the RF power source is turned on, ionizing the etching gas to form a plasma, and the bias power source lags the RF power source for a period of time, that is, the bias power source at this time Closing, performing a polymer forming step, forming a polymer on the surface of the first mask layer 503; maintaining the RF power source on, then turning on the bias power source, performing an etching step, etching the dielectric layer 502 along the opening 505, forming The groove 506 is etched.

Referring to FIG. 27, FIG. 27 is a diagram of a bias power signal outputted by a radio frequency power source and a bias power source output of the RF power source according to the embodiment. The RF power source outputs the RF power in a pulsed manner, and the bias power source is pulsed. Outputting pulse power, the frequency of the output voltage of the RF power source and the bias power source are equal, the bias power source lags behind the RF power source for a period of time, and when the plasma etching is performed, when the RF power source is turned on, ionization etching The gas, the corresponding bias power source lags the RF power source for a period of time ΔT2 is turned on, that is, the ΔT2 time, the bias power source is turned off, and the polymer forming step is performed; after ΔT2, the bias is The power source is turned on and the bias power source outputs the bias power in a normal pulse. During one pulse period C1 of the bias power source output, the bias power source is turned on for the first time T1, and the bias power source is turned off for the second time T2, the first time T1 and the first time T1 and the second time. The ratio of the sum of the times T2 is the first duty ratio, and within one pulse period C2 of the output of the RF power source, the time when the RF power source is turned on is the third time T3, and the time when the RF power source is turned off is the fourth time T4, the third time The ratio of the time T3 to the sum of the third time T3 and the fourth time T4 is a second duty ratio, the first duty ratio is less than the second duty ratio, and the first duty ratio ranges from 10% to 80%. The second duty ratio ranges from 30% to 90%, for example, the first duty ratio is 40%, and the second duty ratio is 60%, and the etching efficiency is improved while being in the first mask layer. The surface forms enough polymer.

The hysteresis time ΔT2 is less than or equal to the third time T3 when the radio frequency power source is turned on, and a certain thickness of the polymer is formed without affecting the etching efficiency. Since the bias power source lags the RF power source for a period of time, a polymer is first formed on the surface of the first mask layer 503 before the etching step starts, so that the first mask layer 503 is not protected at the beginning of the etching. Will be etched and damaged.

Continuing to refer to FIG. 24 and FIG. 25, the plasma etched RF power source has a power of 0 to 2000 watts, an RF frequency of 60 to 120 megahertz, and a bias power source of 100 to 4000 watts, and the bias frequency is 2~15 MHz, the etching chamber pressure is 20~200 mTorr, and the frequency of opening and closing the RF power source is less than or equal to 50 kHz. When performing plasma etching, while improving the etching efficiency, A sufficient amount of polymer is formed on the surface of the first mask layer 503 such that the first mask layer 503 is not damaged, and the etching selectivity ratio of the dielectric layer 502 to the first mask layer 503 is increased.

The gas used in the plasma etching is one or more of CF ₄ , C ₄ F ₈ , C ₄ F ₆ , CHF ₃ , CH ₂ F ₂ , CO, and the gas used for the etching further includes O _{2 .} And Ar. CF ₄ , C ₄ F ₈ , C ₄ F _{6 are} used to provide a fluorocarbon reactant, CHF ₃ , CH ₂ F _{2 are} used to increase the concentration of the polymer, O _{2 is} used to control the amount of the polymer, and Ar is used to form a positive Ions, CO are used to control the proportion of fluorocarbon, and Ar is used to provide the energy of the reaction.

The gas used in the plasma etching in this embodiment is a mixed gas of CF ₄ , C ₄ F ₈ , C ₄ F ₆ , CHF ₃ , CH ₂ F ₂ , O ₂ , CO and Ar to ensure plasma engraving. During the etching process, sufficient polymer is formed on the surface of the mask layer 503. When the RF power source is turned on and the bias power source is also turned on, CF ₄ , C ₄ F ₈ , C ₄ F ₆ , CHF ₃ , CH ₂ F ₂ etc. will be dissociated by RF power to generate F radicals, neutral CF _{2 .} When the molecular fragments are generated, some positive ions such as CF ₃ ⁺ are also generated. Ar also loses electrons to form Ar ⁺ positive ions. The positive ions are accelerated by the plasma sheath and the bias power, which will bombard the medium. The layer material removes part of the dielectric layer, and the F radical also chemically reacts with the dielectric layer material to remove part of the dielectric layer material; when the RF power source is turned on or off, and the bias power source is turned off, the active component is still present in the chamber. And a neutral active ingredient such as CF ₂ will be combined to form a fluorocarbon polymer deposited on the surface of the first mask layer 503. Since there is no accelerating electric field, the positive ions do not bombard the formed polymer, so that the formed polymerization All or part of the material is preserved, thereby protecting the first mask layer 503 from damage or a reduced rate of damage. In this embodiment, since the bias power source lags the RF power source for a period of time, a polymer is formed on the surface of the first mask layer 503 before the etching step begins, thereby protecting the first at the beginning of the etching. The mask layer 503 is not damaged by etching.

Referring to FIG. 26, the above etching step and polymer forming step are repeated, and the dielectric layer 502 is etched along the etching recess 503 until a groove is formed.

When performing plasma etching, the RF power source and the bias power source output the RF power and the pulse power in a pulse manner, and the output frequencies of the RF power source and the bias power source pulse are equal, and the bias power source lags the RF power source for a period of time. Turning on, the first duty cycle of the bias power source output pulse is less than the second duty cycle of the RF power source output pulse, repeating the etching step and the polymer forming step, so that the polymer 504 can always maintain a certain thickness, thereby During the entire etching process, the first mask layer 503 is protected from damage or the rate of damage is reduced, and the etching selectivity ratio of the dielectric layer 502 relative to the first mask layer 503 is increased, so that the dielectric layer 502 is opposite to the dielectric layer 502. The first mask layer 503 has an etch selectivity ratio greater than 15:1.

In summary, the method for forming a semiconductor structure provided by the embodiment of the present invention, when plasma etching, the RF power source turns on the ionizing etching gas to form a plasma, and the bias power source outputs the bias power in a pulse manner. When the power source is turned on, the dielectric layer is etched, and when the bias power source is turned off, a polymer is formed on the surface of the first mask layer, and the first mask layer is protected from damage during subsequent etching of the polymer. Or reducing the rate of damage of the first mask layer and increasing the etching selectivity of the dielectric layer relative to the first mask layer.

The RF power source continuously outputs the RF power, and the bias power source outputs the pulse power in a pulse manner. When the plasma etching is performed, when the RF power source is turned on, the etching gas is ionized, and the corresponding bias power source is The lag RF power source is turned on for a period of time, that is, the lag power source is turned off for a period of time, and the polymer forming step is performed; after a period of time, the bias power source is turned on, and the bias power source is turned to a normal pulse. In the manner of outputting the bias power, a polymer formation step is performed before the etching step begins, and a polymer is formed on the surface of the first mask layer, so that the first mask layer is not engraved at the beginning of the etching. Corrosion damage.

When plasma etching is performed, the RF power source and the bias power source output the RF power and the pulse power in a pulse manner, and the output frequencies of the RF power source and the bias power source pulse are equal, the phases are the same, and the bias power source outputs the pulse. The first duty ratio is less than the second duty cycle of the output pulse of the RF power source. After the etching step, the RF power source is turned on, and the bias power source is turned off early, so part of the polymer is deposited on the mask. After the etching step, the RF power source and the bias power source are both turned off, the polymer forming step is performed, a polymer is formed on the surface of the first mask layer, and a part of the polymer is formed in the etching step to make the polymer The thickness is thicker, thereby better protecting the first mask layer from being damaged or damaged, reducing the etching selectivity of the dielectric layer relative to the first mask layer, and forming and engraving the polymer The eclipse effect is better. The first duty ratio is less than the second duty ratio, the first duty ratio ranges from 10% to 80%, and the second duty ratio ranges from 30% to 90%, while improving the etching efficiency, A sufficient amount of polymer can be formed on the surface of the first mask layer.

The above description is only for the preferred embodiment of the present invention, and those skilled in the art can make other improvements according to the above description, but these changes still belong to the inventive spirit of the present invention and the patents defined below. In the scope.

200, 300, 400, 500. . . Base

202, 302, 402, 502. . . Dielectric layer

203, 303, 403, 503. . . First mask layer

204, 304, 404, 504. . . polymer

205, 305, 405, 505. . . Opening

206, 306, 406, 506. . . Etched groove

C1. . . Pulse period

T1. . . first timing

T2. . . Second time

T3. . . Third time

T4. . . Fourth time

△T1. . . a period of time

S21, S31, S41, S51. . . Providing a substrate on which a dielectric layer is formed

S22, S32, S42, S52. . . Forming a first mask layer on the dielectric layer

S23, S33, S43, S53. . . Plasma etching the dielectric layer

1 to 3 are schematic structural views of a conventional recess forming process; FIG. 4 is a schematic flow chart of a method for forming a semiconductor structure according to a first embodiment of the present invention; and FIGS. 5 to 8 are diagrams showing a semiconductor structure forming process according to a first embodiment of the present invention; FIG. 9 is a schematic diagram of a bias power signal outputted by a radio frequency power source and a bias power source output according to a first embodiment of the present invention; FIG. 10 is a flowchart of a method for forming a semiconductor structure according to a second embodiment of the present invention; 1 to FIG. 14 are schematic cross-sectional structural views showing a process of forming a semiconductor structure according to a second embodiment of the present invention; FIG. 15 is a diagram showing a bias power of a radio frequency power source output and a bias power source output according to a second embodiment of the present invention; FIG. 16 is a schematic flow chart of a method for forming a semiconductor structure according to a third embodiment of the present invention; and FIGS. 17 to 20 are schematic cross-sectional structural views showing a process of forming a semiconductor structure according to a third embodiment of the present invention; Embodiment RF power source output RF power and bias power source output bias power signal diagram; FIG. 22 is a fourth embodiment of the present invention FIG. 23 is a cross-sectional structural view showing a process of forming a semiconductor structure according to a fourth embodiment of the present invention; FIG. 27 is a diagram showing an output of a radio frequency power source and a bias power source outputted by a radio frequency power source according to a fourth embodiment of the present invention; Bias power signal diagram.

S51. . . Providing a substrate on which a dielectric layer is formed

S52. . . Forming a mask layer on the dielectric layer

S53. . . Plasma etching the dielectric layer

Claims (22)

A method of forming a semiconductor structure, comprising: providing a substrate, forming a dielectric layer on the substrate; forming a first mask layer on the dielectric layer, the first mask layer having an opening exposing a surface of the dielectric layer; The first mask layer is a mask, the dielectric layer is plasma etched, the bias power source outputs a bias power in a pulse manner, and when the bias power source is turned on, the dielectric layer is etched. When the bias power source is turned off, a polymer is formed on the surface of the first mask layer, and the process of biasing the power source to turn on and biasing the power source off is repeated until a double damascene structure having grooves and via holes is formed. The method for forming a semiconductor structure according to claim 1, wherein the gas used in the plasma etching is one of CF ₄ , C ₄ F ₈ , C ₄ F ₆ , CHF ₃ , CH ₂ F ₂ , CO or Several. The method of forming a semiconductor structure according to claim 2, wherein the gas used in the plasma etching further comprises O ₂ and Ar. The method for forming a semiconductor structure according to claim 2, wherein the plasma etched RF power source has a power of 0 to 2000 watts, the RF frequency is 60 to 120 MHz, and the bias power source has a power of 100 to 4000. Tile, the bias frequency is 2~15 MHz, and the etching chamber pressure is 20~200 mTorr. The method of forming a semiconductor structure according to claim 2, wherein a time during which the bias power source is turned on is a first time and a time when the bias power source is turned off in one pulse period of the output of the bias power source For the second time, the ratio of the first time to the sum of the first time and the second time is the first duty cycle, and the first duty cycle remains unchanged during the plasma etching process. The method of forming a semiconductor structure according to claim 5, wherein the first duty ratio ranges from 10% to 90%. The method for forming a semiconductor structure according to claim 5, wherein the RF power source outputs RF power in a continuous manner, and when the plasma etching is performed, when the RF power source is turned on, ionizing the etching gas, the bias Set the power source to lag the RF power source for a while. The method of forming a semiconductor structure according to claim 7, wherein the bias power source is delayed to open for a second time or less than a second time when the bias power source is turned off. The method for forming a semiconductor structure according to claim 5, wherein the RF power source outputs RF power in a pulsed manner, and the RF power source is turned on for a pulse period of the RF power source output. Time, the time when the RF power source is turned off is a fourth time, and the ratio of the third time to the sum of the third time and the fourth time is the second duty ratio, and the second duty is during the plasma etching process The ratio remains the same. A method of forming a semiconductor structure according to claim 9, wherein the frequency of the RF power source output pulse is equal to the frequency of the bias power source output pulse. The method of forming a semiconductor structure according to claim 10, wherein the frequency of the RF power source output pulse and the frequency of the bias power source output pulse are less than or equal to 50 kHz. A method of forming a semiconductor structure according to claim 10, wherein the first duty cycle of the bias power source output pulse is less than the second duty cycle of the RF power source output pulse. The method of forming a semiconductor structure according to claim 12, wherein the first duty ratio ranges from 10% to 80%, and the second duty ratio ranges from 30% to 90%. The method of forming a semiconductor structure according to claim 12, wherein when the plasma etching is performed, when the RF power source is turned on, the etching gas is ionized, and the corresponding bias power source is also turned on. The method of forming a semiconductor structure according to claim 12, wherein when the plasma etching is performed, when the RF power source is turned on to ionize the etching gas, the bias power source lags the RF power source for a period of time. The method of forming a semiconductor structure according to claim 15, wherein the bias power source is delayed to open for a third time or less than a third time that the RF power source is turned on. The method of forming a semiconductor structure according to claim 1, wherein the material of the dielectric layer is a low-k dielectric material or an ultra-low-K dielectric material, and the material of the first mask layer is titanium nitride. The method of forming a semiconductor structure according to claim 17, wherein the dielectric layer has a thickness greater than 200 nm, and the first mask layer has a thickness less than 60 nm. The method of forming a semiconductor structure according to claim 18, wherein the forming process of the dual damascene structure is: etching the first mask layer to form a first sub-opening exposing a surface of the dielectric layer; Forming a photoresist layer on the layer, the photoresist layer filling the first sub-opening, patterning the photoresist layer to form a second sub-opening, and the position of the second sub-opening is opposite to the position of the first sub-opening Correspondingly, the second sub-opening exposes the surface of the dielectric layer, the width of the second sub-opening is smaller than the width of the first sub-opening; along the second sub-opening, the dielectric layer is etched by plasma to form a first through the dielectric layer Sub-via; removing the patterned photoresist layer; etching a portion of the dielectric layer along the second sub-opening to form a first sub-groove, the first sub-via and the first sub-port The grooves form a double damascene structure. The method of forming a semiconductor structure according to claim 1, wherein the dielectric layer is a multi-layer stacked structure, comprising: a first dielectric layer, a second mask layer on a surface of the first dielectric layer, and a surface of the second mask layer a second dielectric layer having a third sub-opening in the second mask layer exposing the surface of the first dielectric layer, the second dielectric layer filling the third sub-opening. The method of forming a semiconductor structure according to claim 20, wherein the material of the first dielectric layer and the second dielectric layer is a low-k dielectric material, an ultra-low-k dielectric material or yttrium oxide, the second mask The material of the layer is tantalum nitride, tantalum oxynitride, tantalum carbide or tantalum carbonitride, and the material of the first mask layer is photoresist or amorphous carbon. The method for forming a semiconductor structure according to claim 21, wherein the forming process of the double damascene structure is: using a first mask layer as a mask, plasma etching the first dielectric layer to form a second sub-layer a groove, the second sub-groove exposing a surface of the second mask layer, the position of the second sub-groove corresponding to the position of the third sub-opening, the width of the first sub-groove being greater than the width of the third sub-opening; a three sub-opening, the second dielectric layer is etched by plasma to form a second sub-via through the second dielectric layer, and the second sub-groove and the second sub-via form a recess.