TW201403752A - Method for forming semiconductor structure - Google Patents

Abstract

The invention discloses a method for forming a semiconductor structure, which comprises the following steps: providing a substrate and forming a dielectric layer on the substrate; forming a mask layer provided with an opening for exposing the surface of the dielectric layer on the dielectric layer; carrying out a plasma etching on the dielectric layer by taking the mask layer as a mask, wherein a bias power source outputs a bias power in pulse mode, when the bias power resource is switched on, etching part of the dielectric layer to form an etch-hole, when the bias power resource is switched off, forming a polymer on the surface of the mask layer, repeating the process of switching on the bias power resource and switching off the bias power resource till a through hole is formed. When forming the through hole, the etching step and the polymer forming step are repeated so that the polymer can keep a certain thickness, therefore, in the entire etching process, the mask layer is protected from damaging or the damage rate is reduced, and the etching ratio of the dielectric layer relative to the mask layer is increased.

Description

Method of forming a semiconductor structure

The present invention relates to the field of semiconductor fabrication, and more particularly to a method of forming a semiconductor structure.

As integrated circuits move toward sub-micron dimensions, the density of devices and the complexity of the process continue to increase, and strict control of the process becomes more important. Wherein, the via hole serves as a channel for interconnecting the multilayer metal layers and the connection between the active region of the device and the external circuit, and the formation process of the via hole has been conventionally known to those skilled in the art due to its important role in the structural composition of the device. Pay attention to it.

1 to 3 are schematic structural views of a conventional through hole forming process.

Referring to FIG. 1, a semiconductor substrate 100 is provided on which a dielectric layer 101 is formed, which is a single layer structure or a multilayer stack structure, for example, the dielectric layer 101 is a single layer of a ruthenium oxide layer. Structure; a mask layer 102 is formed on the surface of the dielectric layer 101, and the mask layer 102 has an opening 103 exposing the surface of the dielectric layer 101, and the material of the mask layer 102 is a photoresist.

Referring to FIG. 2, the dielectric layer 101 is etched along the opening 103 by a plasma etching process to form a via 104 that exposes the surface of the semiconductor substrate 100. The gas used for plasma etching is CF _{4 .} Or C ₄ F ₈ .

However, in actual production, it has been found that as the size of the device is reduced, the size of the via hole is also reduced, especially when an existing plasma etching process is used to form a via having a high aspect ratio. As the etching progresses, the gas exchange in the through hole becomes slower and slower, so it is necessary to strengthen the bias power to enhance the gas exchange and the reaction rate in the through hole, and the bias power is increased to make the high energy ion during etching. The physical bombardment becomes stronger, and the mask layer 102 becomes thinner or damaged (refer to FIG. 3). Thinning or damage of the mask layer reduces the etching selectivity ratio of the dielectric layer to the mask layer, which may cause etching. Deformation of the formed through holes or bridging between adjacent through holes.

For more details on the formation of vias, please refer to US Patent Publication No. US 2009/0224405 A1.

Accordingly, it is a primary object of the present invention to provide an etch selectivity ratio for a dielectric layer relative to a mask layer.

The technical means for solving the problems of the prior art is a method for forming a semiconductor structure, comprising: providing a substrate, forming a dielectric layer on the substrate; forming a mask layer on the dielectric layer, the mask The film layer has an opening exposing a surface of the dielectric layer, the mask layer material is photoresist or amorphous carbon; using the mask layer as a mask, plasma etching the dielectric layer, biasing the power source The bias power is outputted in a pulsed manner. When the bias power source is turned on, a portion of the dielectric layer is etched to form an etched hole. When the bias power source is turned off, a polymer is formed on the surface of the mask layer, and the bias is repeated. The power source turns on and biases the power source off until a via is formed.

In an embodiment of the invention, the dielectric layer is a single layer or a stacked structure of a tantalum oxide layer, a tantalum nitride layer, and a tantalum carbide layer.

In an embodiment of the invention, the gas used in the plasma etching is one or more of C ₄ F ₈ , C ₄ F ₆ , CHF ₃ , CH ₂ F ₂ , and CO.

In an embodiment of the invention, the gas used in the plasma etching further includes O2 and Ar.

In an embodiment of the invention, the plasma etched RF power source has a power of 500 to 4000 watts, an RF frequency of 60 to 120 MHz, and a bias power source of 2000 to 8000 watts, and the bias frequency is 2~15 MHz, the etching chamber pressure is 20~200 mTorr.

In an embodiment of the present invention, the bias power source is turned on for a first time, and the bias power source is turned off for a second time. The ratio of the first time to the sum of the first time and the second time is the first duty cycle, and the first duty cycle remains unchanged during the plasma etching process.

In an embodiment of the invention, the first duty ratio ranges from 10% to 90%.

In an embodiment of the present invention, the bias power source is turned on for a first time, and the bias power source is turned off for a second time. The ratio of the first time to the sum of the first time and the second time is the first duty ratio, and during the plasma etching, the first duty ratio is gradually decreased, and the first time and the first time in each pulse period The sum of the two times remains the same.

In an embodiment of the invention, the first duty cycle is gradually reduced from 90% to 10%.

In an embodiment of the invention, the RF power source outputs RF power in a pulsed manner.

In an embodiment of the invention, the frequency of the bias power source output pulse is equal to the frequency of the RF power source output pulse.

In an embodiment of the invention, the frequency of the bias power source and the RF power source output pulse is less than or equal to 50 kHz.

In an embodiment of the present invention, the time during which the RF power source is turned on is the third time, and the time when the RF power source is turned off is the fourth time, the third time. The ratio to the sum of the third time and the fourth time is a second duty cycle, the second duty cycle being equal to the first duty cycle.

In an embodiment of the invention, the second duty ratio is 10% to 90%.

In an embodiment of the present invention, the time during which the RF power source is turned on is the third time, and the time when the RF power source is turned off is the fourth time, the third time. The ratio to the sum of the third time and the fourth time is a second duty cycle, the first duty cycle being less than the second duty cycle.

In an embodiment of the invention, the first duty ratio is 40% to 90% of the second duty ratio.

In an embodiment of the invention, the second duty ratio is 30% to 90%, and the first duty ratio is 10% to 80%.

In an embodiment of the invention, the through hole formed has an aspect ratio of 10:1 or more.

Through the technical means adopted by the present invention, when a through-hole is formed by using a bias power source to pulse-output a bias power plasma etch, the bias power source outputs the bias power in a pulsed manner, repeating the etching step and The step of forming the polymer allows the polymer to maintain a certain thickness, so that the rate at which the protective mask layer is not damaged or damaged is reduced throughout the etching process, and the etching selectivity of the dielectric layer relative to the mask layer is improved. ratio.

Further, the plasma etching using the first duty ratio of the bias power is continuously reduced. As the etching process progresses, the RF power source is turned on in one etching cycle due to the continuous decrease of the first duty ratio. The time is shortened, that is, the time of the etching step is decreased, and the time of the polymer forming step is increased, so that a sufficient amount of polymer is formed on the surface of the mask layer while etching forms the via holes.

Further, both the RF power source and the bias power source output the RF power in a pulsed manner, and the frequency of the output pulse of the RF power source and the bias power source are equal, and the second duty ratio of the output pulse of the RF power source remains unchanged. The first duty cycle of the output pulse of the power source is equal to the second duty cycle of the output pulse of the RF power source, that is, when the polymer is formed, both the bias power source and the RF power source are turned off, and the etching step remains in the cavity. The positive ion receives an acceleration electric field of 0, and the formed polymer is not damaged by the bombardment of positive ions. The polymer is always maintained at a certain thickness and the uniformity is good, so that the protective mask layer is not damaged or damaged. The rate is reduced.

Further, both the RF power source and the bias power source output the RF power in a pulse manner, and the frequency of the output pulse of the RF power source and the bias power source are equal, and the second duty ratio of the output pulse of the RF power source remains unchanged. The first duty cycle of the output pulse of the power source is less than the second duty cycle of the output pulse of the RF power source, so that in the latter part of the etching step of each etch cycle, the etch is due to the closing of the bias power source In the step, part of the polymer is deposited on the surface of the mask layer. After the etching step, the RF power source and the bias power source are both turned off, and the polymer deposition step is performed to deposit more polymer, thereby protecting the mask layer from being affected. The rate of damage or damage is reduced. The first duty ratio is 40% to 90% of the second duty ratio, the second duty ratio is 30% to 90%, and the first duty ratio is 10% to 80%, thereby improving etching efficiency. At the same time, sufficient polymer can be formed on the surface of the mask layer.

The specific embodiments of the present invention will be further described by the following examples and the accompanying drawings.

The inventors found in the process of etching the dielectric layer by the existing plasma etching process that as the aspect ratio of the via holes formed in the dielectric layer increases, the gas exchange rate in the via holes becomes slower and slower. The sidewall morphology affecting the etching rate and the via hole formation, in order to increase the gas exchange rate in the via hole, it is necessary to increase the bias power during plasma etching, and the increase of the bias power causes the positive ion during etching. The bombardment effect becomes stronger, which makes the mask layer thin or damaged, and reduces the etching selectivity ratio of the dielectric layer to the mask layer, which is less than 4:1, and continues to be masked by thinning or damaged mask layer. In the case of the dielectric layer, the via holes formed in the dielectric layer may be deformed or the adjacent via holes may be directly bridged, and subsequent formation of the interconnect structure in the via holes may affect the stability of the device.

In order to solve the above problems, the inventors have proposed a method for forming a semiconductor structure. Referring to FIG. 4, FIG. 4 is a schematic flow chart of a method for forming a semiconductor structure according to a first embodiment of the present invention, including:

Step S21, providing a substrate on which a dielectric layer is formed;

Step S22, forming a mask layer on the dielectric layer, the mask layer having an opening exposing a surface of the dielectric layer;

Step S23, using the mask layer as a mask, performing plasma etching on the dielectric layer, the RF power source outputs RF power in a continuous manner, and the bias power source outputs the bias power in a pulse manner, and the bias is offset. The first duty cycle of the power source output pulse remains unchanged. When the bias power source is turned on, a portion of the dielectric layer is etched to form an etch hole, and when the bias power source is turned off, a polymerization is formed on the surface of the mask layer. The above process is repeated until a through hole is formed.

5 to FIG. 8 are schematic cross-sectional structural views showing a process of forming a semiconductor structure according to a first embodiment of the present invention; and FIG. 9 is a signal of a bias power of an output of a radio frequency power source and a bias power source output according to a first embodiment of the present invention; Figure.

Referring to FIG. 5, a substrate 200 is provided on which a dielectric layer 202 is formed; a mask layer 203 is formed on the dielectric layer 202, the mask layer 203 having an opening 205 exposing a surface of the dielectric layer 202.

The substrate 200 is one of a germanium substrate, a germanium substrate, a germanium substrate, a tantalum carbide substrate, and a gallium nitride substrate. An ion doping region, a germanium via hole, or the like (not shown) is formed in the substrate 200; a semiconductor device such as a transistor, a resistor, a capacitor, or a memory may be formed on the substrate 200 (not shown in the drawing) ).

In other embodiments of the present invention, the substrate 200 is further formed with one or more interlayer dielectric layers (not shown), and the interlayer dielectric layer is made of yttria, low-k dielectric material or ultra-low a K dielectric material in which a semiconductor structure such as a metal interconnection or a conductive plug is formed.

The dielectric layer 202 is a single layer structure of a hafnium oxide layer, a tantalum nitride layer or a tantalum carbide layer; the dielectric layer 202 may be a two-layer structure of a hafnium oxide layer and a tantalum nitride layer or a multi-layer stack structure of a two-layer structure. The dielectric layer 202 may be a two-layer structure of a ruthenium oxide layer and a tantalum carbide layer or a multilayer structure of a two-layer structure; the dielectric layer 202 may be a two-layer structure or a double layer of a tantalum nitride layer and a tantalum carbide layer; The multilayer stack structure of the structure; the dielectric layer 202 may be a three-layer structure of a ruthenium oxide layer, a tantalum nitride layer, a tantalum carbide layer or a multilayer structure of a three-layer structure. A through hole is formed in the dielectric layer 202, and the through hole is used to fill the metal to form a plug.

In the embodiment, the dielectric layer 202 is a single layer structure of a ruthenium oxide layer.

The mask layer 203 is made of photoresist or amorphous carbon as a mask for subsequently etching the dielectric layer 202. The mask layer has a thickness of 200-600 nm, and the mask layer 203 is patterned. An opening 205 is formed which exposes a surface of the dielectric layer 202, the position of the opening 205 corresponding to the position of the subsequently etched via.

Referring to FIG. 6 and FIG. 7 , the dielectric layer is plasma etched by using the mask layer 203 as a mask, and the RF power source outputs RF power in a continuous manner, and the bias power source is outputted in a pulse manner. Setting the power, the first duty cycle of the output pulse of the bias power source remains unchanged, and an etching cycle of the plasma etching includes an etching step and a polymer forming step, and when the bias power source is turned on, the etching is performed. In the etching step, a portion of the dielectric layer 202 is etched to form an etched hole 206; when the bias power source is turned off, a polymer forming step is performed to form a polymer 204 on the surface of the mask layer 203.

It should be noted that the etching device used for plasma etching in this embodiment and subsequent embodiments may be an inductively coupled plasma etching device (ICP) or a capacitively coupled plasma etching device (CCP). The coupled plasma etching device and the capacitively coupled plasma etching device provide a radio frequency power source with a frequency greater than or equal to 27 MHz and a bias power source frequency of 15 MHz or less. When the etching device is a capacitively coupled plasma etching device, a radio frequency power source may be applied to the upper electrode or applied to the upper and lower electrodes for generating radio frequency power, ionizing the etching gas, generating a plasma, and controlling the plasma. The density of the body; a bias power source is applied to the lower electrode for generating bias power, affecting sheath properties (sheath voltage or accelerating voltage), and controlling the energy distribution of the plasma. When the etching device is an inductively coupled plasma etching device, a radio frequency power source can be applied to the inductor coil for generating radio frequency power, ionizing the etching gas, generating a plasma, and controlling the density of the plasma; bias power A source is applied to the lower electrode for generating bias power, affecting sheath properties (sheath voltage or accelerating voltage), and controlling the energy distribution of the plasma.

During plasma etching, the bias power source periodically outputs the bias power in a pulsed manner, that is, the bias power source interval is turned on or off, the bias power source is turned on, and the bias power source is turned off, and the bias power source is turned off. There is no bias power output. Referring to Figure 9, Figure 9 is a signal diagram of the RF power output from the RF power source and the bias power output from the bias power source. The RF power source continuously outputs RF power. The RF power is always high. When the RF power source is turned on, the RF power is used to ionize the etching gas to form a plasma, and the bias power source outputs the bias power in a pulsed manner, and the bias power of the bias power source is outputted within one pulse period C1. The time when the bias power source is turned on is the first time T1, and the time when the bias power source is turned off is the second time T2, and the ratio of the first time T1 to the sum of the first time T1 and the second time T2 is The first duty ratio, when the bias power is turned on, the etching step is performed, and when the bias power is turned off, the polymer forming step is performed. In this embodiment, each pulse of the bias power is used in the plasma etching process. The duty ratio remains unchanged during the period, and the first duty ratio ranges from 10% to 90%. Preferably, the first duty ratio ranges from 40% to 60%, so that etching is performed. The step and the polymer forming step are maintained for a certain period of time. When the plasma etching is performed, a sufficient amount of polymer is formed on the surface of the mask layer while the etching efficiency is increased, so that the mask layer is not damaged or damaged. Small, increasing the etching selectivity of the dielectric layer relative to the mask layer.

Continuing to refer to FIG. 6 and FIG. 7, during a pulse period of plasma etching, the RF power source is turned on, and when the bias power source is also turned on, an etching step is performed, and the RF power is ionized to etch the gas to excite the plasma to form a plasma. The power is supplied to provide an accelerating electric field, and a portion of the dielectric layer 202 is etched to form an etched hole 206; then the RF power source remains open, and when the bias power source is turned off, the accelerating electric field is absent or small, and the polymer forming step is performed. A polymer 204 is formed on the surface of the mask layer 203, and the polymer 204 reduces the rate at which the mask layer 203 is not damaged or damaged when the dielectric layer 202 is subsequently etched along the etch hole 206, thereby increasing the medium. The etch selectivity ratio of layer 202 relative to mask layer 203. In the polymer forming step, the sidewall of the etched hole 206 also forms a part of the polymer (not shown). In the etching step of the next pulse period, the sidewall of the etched via 206 is not overetched. .

The plasma etched RF power source has a power of 500 to 4000 watts, an RF frequency of 60 to 120 MHz, a bias power source of 2000 to 8000 watts, and an offset frequency of 2 to 15 MHz. The pressure is 20~200 mTorr, and the frequency of the bias power source is turned on and off by 50 kHz or less. When the plasma etching is performed, a sufficient amount is formed on the surface of the mask layer 203 while improving the etching efficiency. The polymer is such that the mask layer 203 is not damaged or damaged, and the etching selectivity of the dielectric layer 202 relative to the mask layer 203 is increased.

The gas used in the plasma etching is one or more of C ₄ F ₈ , C ₄ F ₆ , CHF ₃ , CH ₂ F ₂ , CO, and C ₄ F ₈ and C ₄ F _{6 are} used to provide fluorocarbon. The reactant, the gas used for the etching further includes O ₂ and Ar, CHF ₃ , CH ₂ F ₂ for increasing the concentration of the polymer, O ₂ for controlling the amount of the polymer, and CO for controlling the proportion of the fluorocarbon. , Ar is used to form positive ions, providing the energy of the reaction.

The gas used in the plasma etching in this embodiment is a mixed gas of C ₄ F ₈ , C ₄ F ₆ , CHF ₃ , CH ₂ F ₂ , O ₂ , CO and Ar to ensure plasma etching. A sufficient polymer is formed on the surface of the mask layer 203. When the RF power source is turned on and the bias power source is also turned on, the etching step is performed, and C ₄ F ₈ , C ₄ F ₆ , CHF ₃ , CH ₂ F ₂ and the like are ionized to generate F radicals under the action of RF power. Neutral molecular fragments such as CF ₂ will also generate some positive ions such as CF ₃ ^+, etc. Ar will also lose electrons to form Ar ⁺ positive ions, and positive ions pass through the plasma sheath and bias power. Acceleration, the dielectric layer material is bombarded to remove part of the dielectric layer, and the F radicals also chemically react with the dielectric layer material to remove part of the dielectric layer material; when the RF power source is turned on and the bias power source is turned off, polymer formation is performed. In this step, a portion of the active group remaining in the etching step and a reactive group formed by the new ionization are present in the chamber, and a neutral active component such as CF ₂ is compounded to form a fluorocarbon polymer deposited on the surface of the mask layer 203. Since the bias power source is turned off, there is no accelerating electric field or the accelerating electric field is small, the positive ions do not bombard the formed polymer 204 or the bombardment effect is small, so that all or part of the formed polymer 204 is preserved, and then continues. During etching, the rate at which the mask layer is protected from damage or damage is reduced due to the presence of the polymer 204 of a certain thickness.

Referring to FIG. 8, the above etching step and polymer formation step are repeated, and the dielectric layer 204 is etched along the etching hole 206 until a via hole is formed.

The through hole has an aspect ratio of 10:1 or more, and the bias power source is pulsed to form a high aspect ratio via hole by plasma etching to output a bias power. The output mode bias power, the first duty cycle of the bias power source output pulse remains unchanged, the etching step and the polymer forming step are repeated, so that the polymer 204 can always maintain a certain thickness, thereby etching the entire During the process, the rate at which the mask layer 203 is not damaged or damaged is reduced, and the etching selectivity of the dielectric layer 202 relative to the mask layer 203 is increased, so that the etching of the dielectric layer 202 relative to the mask layer 203 is selected. The ratio is greater than 10:1.

Referring to FIG. 10, FIG. 10 is a schematic flow chart of a method for forming a semiconductor structure according to a second embodiment of the present invention, including:

Step S31, providing a substrate on which a dielectric layer is formed;

Step S32, forming a mask layer on the dielectric layer, the mask layer having an opening exposing a surface of the dielectric layer;

Step S33, using the mask layer as a mask, performing plasma etching on the dielectric layer, the RF power source outputs the RF power in a continuous manner, and the bias power source outputs the bias power in a pulse manner, and the bias is offset. The first duty cycle of the power source output pulse is continuously reduced. When the bias power source is turned on, a portion of the dielectric layer is etched to form an etch hole, and when the bias power source is turned off, an aggregation is formed on the surface of the mask layer. The above process is repeated until a through hole is formed.

11 to FIG. 14 are schematic cross-sectional structural views showing a process of forming a semiconductor structure according to a second embodiment of the present invention; FIG. 15 is a diagram showing a signal of a bias power of a radio frequency power source and a bias power source outputted by a radio frequency power source according to a second embodiment of the present invention; Figure 16 is a schematic diagram showing the relationship between the first duty ratio and the etching time or etching depth.

Referring to FIG. 11, a substrate 300 is provided on which a dielectric layer 302 is formed; a mask layer 303 is formed on the dielectric layer 302, the mask layer 303 having an opening 305 exposing a surface of the dielectric layer 302.

The substrate 300 is one of a germanium substrate, a germanium substrate, a germanium substrate, a tantalum carbide substrate, and a gallium nitride substrate. An ion doping region, a germanium via hole, or the like (not shown) is formed in the substrate 300; a semiconductor device such as a transistor, a resistor, a capacitor, or a memory may be formed on the substrate 300 (not shown in the drawing) ).

In other embodiments of the present invention, the substrate 300 is further formed with one or more interlayer dielectric layers (not shown), and the interlayer dielectric layer is made of yttria, low-k dielectric material or ultra-low a K dielectric material in which a semiconductor structure such as a metal interconnection or a conductive plug is formed.

The dielectric layer 302 is a single layer structure of a hafnium oxide layer, a tantalum nitride layer or a tantalum carbide layer; the dielectric layer 302 may be a two-layer structure of a hafnium oxide layer and a tantalum nitride layer or a multi-layer stack structure of a two-layer structure. The dielectric layer 302 may be a two-layer structure of a ruthenium oxide layer and a tantalum carbide layer or a multilayer structure of a two-layer structure; the dielectric layer 302 may be a two-layer structure or a double layer of a tantalum nitride layer and a tantalum carbide layer; The multilayer stack structure of the structure; the dielectric layer 302 may be a three-layer structure of a ruthenium oxide layer, a tantalum nitride layer, a tantalum carbide layer or a multilayer structure of a three-layer structure. A through hole is formed in the dielectric layer 302, and the through hole is used to fill the metal to form a plug.

In the embodiment, the dielectric layer 302 is a single layer structure of a ruthenium oxide layer.

The mask layer 303 is made of photoresist or amorphous carbon. As a mask for subsequently etching the dielectric layer 302, an opening 305 is formed by patterning the mask layer 303, and the opening 305 exposes the dielectric layer 302. The surface, the position of the opening 305 corresponds to the position of the subsequently etched via.

Referring to FIG. 12 and FIG. 13 , the dielectric layer is plasma etched by using the mask layer 303 as a mask, and the RF power source outputs RF power in a continuous manner, and the bias power source is outputted in a pulse manner. Setting a power, the first duty cycle of the output pulse of the bias power source is continuously reduced, and an etching cycle of the plasma etching includes an etching step and a polymer forming step, and when the bias power source is turned on, engraving In the etching step, a portion of the dielectric layer 302 is etched to form an etched hole 306; when the bias power source is turned off, a polymer forming step is performed to form a polymer 304 on the surface of the mask layer 303.

When the through hole is formed by the first duty cycle constant plasma etching method of the radio frequency power of the first embodiment, the inventors have found that as the etching hole depth increases or the etching time is lengthened, due to etching The loss, the amount of polymer remaining on the surface of the mask layer will gradually decrease, and the protection of the mask layer will be weakened. Therefore, in this embodiment, the plasma with the first duty ratio of the bias power is continuously reduced. Etching, as the etching process progresses, the first time the duty cycle is continuously reduced, the bias power source is turned on for a short period of time, that is, the etching step time is reduced, and the etching time is reduced. The time for the object formation step is increased to form a sufficient amount of polymer on the surface of the mask layer while etching to form the via holes.

Referring to FIG. 15, FIG. 15 is a signal diagram of the RF power output from the RF power source and the bias power output from the bias power source. The RF power source continuously outputs the RF power. When the RF power is always “High” (the RF power source is turned on) The RF power is used to ionize the etching gas to form a plasma, and the bias power source outputs the bias power in a pulsed manner, and the bias power source is biased within a pulse period C1 of the bias power output from the power source. The opening time is the first time T1, the time when the bias power source is off is the second time T2, and the ratio of the first time T1 to the sum of the first time T1 and the second time T2 is the first duty ratio, During the plasma etching process, the time of each pulse period is equal, the first duty ratio is continuously decreased, and the first duty ratio in the pulse period C2 after the RF power in FIG. 15 is smaller than that in the previous pulse period C1. The first duty cycle, in other embodiments of the present invention, the duty cycle may be further reduced after a period of time or after at least two pulse cycles, that is, the same duty cycle is maintained for a period of time to simplify the control process and improve Etching efficiency The interval of each period is equal to 2 times greater than the pulse period.

The first duty ratio is gradually reduced from 90% to 10%. Preferably, the first duty ratio is gradually reduced from 70% to 20%, so that the etching time and the polymer deposition time are kept reasonable. The state improves the etching efficiency while forming sufficient polymer on the surface of the mask layer.

The manner in which the first duty ratio is continuously reduced is a stepwise decrease with an etch time or an etch depth. Referring to FIG. 16, FIG. 16 is a schematic diagram showing a relationship between a first duty ratio and an etch time or an etch depth. The first duty ratio decreases stepwise as the etching time increases or the etching depth increases, so that the control process is simplified, and the reduction of the first duty ratio between adjacent steps can be equal. Not equal, making the control process diversified.

Continuing to refer to FIG. 12 and FIG. 13, during a pulse period of plasma etching, when the RF power source is turned on, and the bias power source is also turned on, an etching step is performed, and the RF power is ionized to etch the gas to excite the plasma to form a plasma. The power is supplied to provide an accelerating electric field, and a portion of the dielectric layer 302 is etched to form an etched hole 306; then, the RF source power source remains open, and when the bias power source is turned off, a polymer forming step is performed to form a surface of the mask layer 303. The polymer 304, the polymer 304, reduces the rate at which the mask layer 303 is not damaged or damaged when the dielectric layer 302 is subsequently etched along the etched holes 306, thereby increasing the dielectric layer 302 relative to the mask layer 303. The etching selectivity ratio. In the polymer forming step, the sidewall of the etched hole 306 also forms a part of the polymer (not shown). In the etching step of the next pulse period, the sidewall of the etched hole 306 is not overetched. eclipse.

The plasma etched RF power source has a power of 500 to 4000 watts, an RF frequency of 60 to 120 MHz, a bias power source of 2000 to 8000 watts, and an offset frequency of 2 to 15 MHz. The pressure is 20~200 mTorr, and the frequency of the bias power source is turned on and off by 50 kHz or less. When the plasma etching is performed, a sufficient amount is formed on the surface of the mask layer 303 while improving the etching efficiency. The polymer is such that the mask layer 303 is not damaged or damaged, and the etching selectivity of the dielectric layer 302 relative to the mask layer 303 is increased.

The gas used in the plasma etching is one or more of C ₄ F ₈ , C ₄ F ₆ , CHF ₃ , CH ₂ F ₂ , CO, and C ₄ F ₈ and C ₄ F _{6 are} used to provide fluorocarbon. The reactant, the gas used for the etching further includes O ₂ and Ar, CHF ₃ , CH ₂ F ₂ for increasing the concentration of the polymer, O ₂ for controlling the amount of the polymer, and CO for controlling the proportion of the fluorocarbon. , Ar is used to form positive ions, providing the energy of the reaction.

The gas used in the plasma etching in this embodiment is a mixed gas of C ₄ F ₈ , C ₄ F ₆ , CHF ₃ , CH ₂ F ₂ , O ₂ , CO and Ar to ensure plasma etching. A sufficient polymer is formed on the surface of the mask layer 303. When the RF power source is turned on and the bias power source is also turned on, the etching step is performed. C ₄ F ₈ , C ₄ F ₆ , CHF ₃ , CH ₂ F ₂ and the like are ionized to generate F radicals under the action of RF power. Neutral CF ₂ and other molecular fragments, also generate some positive ions, such as: CF ₃ ^+, etc., Ar will also lose electrons to generate Ar ⁺ positive ions, positive ions through the plasma sheath (plasma sheath) and bias The acceleration of the power will bombard the dielectric layer material and remove part of the dielectric layer, and the F radical will also chemically react with the dielectric layer material to remove part of the dielectric layer material; when the RF power source is turned on and the bias power source is turned off, the power is accelerated. a polymer forming step in which a part of the active group remaining in the etching step and a reactive group formed by the new ionization are present in the chamber, and a neutral active ingredient such as CF ₂ is compounded to form a fluorocarbon polymer deposited on the mask layer. The surface of 303, because the bias power source is turned off, there is no acceleration electric field or the acceleration electric field is reduced, the positive ions do not bombard the formed polymer 304 or the bombardment effect is small, so that all or part of the formed polymer 304 is preserved, after When the etching continues, the rate at which the mask layer is protected from damage or damage is reduced due to the presence of the polymer 304 of a certain thickness. During the etching process, as the first duty cycle of the bias power is continuously reduced, the etching time is continuously reduced in each pulse period, and the formation time of the polymer is continuously increased, as the depth of the via etching is increased. Increasing or increasing the etching time, the amount of polymer 304 formed on the mask layer 303 is consumed while being more replenished, so that the formation of the polymer 304 on the mask layer 303 is always sufficient during the etching process. The amount of protective mask layer 303 is never compromised or the rate of damage is reduced.

Referring to FIG. 14, the above etching step and polymer formation step are repeated, and the dielectric layer 304 is etched along the etching hole 306 until a via hole is formed.

The through hole has an aspect ratio of 10:1 or more, and the etching step and the polymerization are repeated when a bias power source is used to pulse-output a bias power plasma etching to form a high aspect ratio via hole. In the step of forming the object, the first duty ratio of the bias power is continuously reduced, the etching time is continuously reduced in each pulse period, the time for forming the polymer is continuously increased, and the etching depth of the via hole is increased or engraved. As the etch time increases, the amount of polymer 304 formed on the mask layer 303 is increased while being consumed, so that the formation of the polymer 304 on the mask layer 303 is always maintained in a sufficient amount during the etching process. The rate at which the protective mask layer 303 is not damaged or damaged at all is reduced, and the etching selectivity ratio of the dielectric layer 302 to the mask layer 303 is increased, so that the etching selectivity ratio of the dielectric layer 302 to the mask layer 303 is greater than 15:1.

Referring to FIG. 17, FIG. 17 is a schematic flowchart diagram of a method for forming a semiconductor structure according to a third embodiment of the present invention, including:

Step S41, providing a substrate on which a dielectric layer is formed;

Step S42, forming a mask layer on the dielectric layer, the mask layer having an opening exposing a surface of the dielectric layer;

Step S43, using the mask layer as a mask, performing plasma etching on the dielectric layer, and the RF power source and the bias power source output the RF power in a pulse manner, the RF power source and the bias power source pulse. The output frequency is equal, the second duty ratio of the output pulse of the RF power source remains unchanged, and the first duty ratio of the output pulse of the bias power source is equal to the second duty ratio of the output pulse of the RF power source, when the RF power source is turned on. When the bias power source is also turned on, the dielectric layer is etched to form an etched hole. When the RF power source is turned off and the bias power source is also turned off, a polymer is formed on the surface of the mask layer, and the process is repeated until the process is repeated. A through hole is formed.

18 to FIG. 21 are schematic cross-sectional structural views showing a process of forming a semiconductor structure according to a third embodiment of the present invention; and FIG. 22 is a diagram showing a bias power signal of an output of a radio frequency power source and a bias power source output according to a third embodiment of the present invention; .

Referring to FIG. 18, a substrate 400 is provided on which a dielectric layer 402 is formed; a mask layer 403 is formed on the dielectric layer 402, the mask layer 403 having an opening 405 exposing a surface of the dielectric layer 402.

The substrate 400 is one of a germanium substrate, a germanium substrate, a germanium substrate, a tantalum carbide substrate, and a gallium nitride substrate. An ion doping region, a germanium via hole, or the like (not shown) is formed in the substrate 400; a semiconductor device such as a transistor, a resistor, a capacitor, or a memory may be formed on the substrate 400 (not shown in the drawing) ).

In other embodiments of the present invention, the substrate 400 is further formed with one or more interlayer dielectric layers (not shown), and the interlayer dielectric layer is made of yttria, low-k dielectric material or ultra-low a K dielectric material in which a semiconductor structure such as a metal interconnection or a conductive plug is formed.

The dielectric layer 402 is a single layer structure of a hafnium oxide layer, a tantalum nitride layer or a tantalum carbide layer; the dielectric layer 402 may be a two-layer structure of a hafnium oxide layer and a tantalum nitride layer or a multi-layer stack structure of a two-layer structure. The dielectric layer 402 may be a two-layer structure of a ruthenium oxide layer and a tantalum carbide layer or a multilayer structure of a two-layer structure; the dielectric layer 402 may be a two-layer structure or a double layer of a tantalum nitride layer and a tantalum carbide layer; The multilayer stack structure of the structure; the dielectric layer 402 may be a three-layer structure of a ruthenium oxide layer, a tantalum nitride layer, a tantalum carbide layer or a multilayer structure of a three-layer structure. A through hole is formed in the dielectric layer 402, and the through hole is used to fill the metal to form a plug.

In the embodiment, the dielectric layer 402 is a single layer structure of a ruthenium oxide layer.

The mask layer 403 is made of photoresist or amorphous carbon. As a mask for subsequently etching the dielectric layer 402, an opening 405 is formed by patterning the mask layer 403, and the opening 405 exposes the dielectric layer 402. The surface, the position of the opening 405 corresponds to the position of the subsequently etched through hole.

Referring to FIG. 19 and FIG. 20, the dielectric layer is plasma etched by using the mask layer 403 as a mask, and the RF power source and the bias power source both output RF power in a pulse manner, and the RF power source and The frequency of the output pulse of the bias power source is equal, the phase is the same, the second duty ratio of the output pulse of the RF power source remains unchanged, and the first duty ratio of the output pulse of the bias power source is equal to the second duty of the output pulse of the RF power source. Empty ratio, one etching cycle of plasma etching includes an etching step and a polymer forming step. When the RF power source is turned on and the bias power source is also turned on, an etching step is performed to excite the plasma, and the etching portion is described. The dielectric layer 402 forms an etched hole 406; when the RF power source is turned off and the bias power source is also turned off, a polymer forming step is performed to form a polymer 404 on the surface of the mask layer 403.

In this embodiment, both the RF power source and the bias power source output the RF power in a pulse manner, and the RF power source and the bias power source output pulse have the same frequency, and the second duty ratio of the RF power source output pulse remains unchanged. The first duty ratio of the output pulse of the bias power source is equal to the second duty ratio of the output pulse of the RF power source, that is, when the polymer is formed, the RF power source does not output the RF power, and the bias power source does not output the bias power. It is not affected by factors such as a large proportion of positive ions in the plasma with new ionization of RF power, so that the polymer is always maintained at a certain thickness and has good uniformity, and the RF power and the bias power are both turned off. The positive ions are subjected to an accelerating electric field of zero, which does not cause any bombardment of the formed polymer, thereby better protecting the mask layer from being damaged or damaged.

Referring to FIG. 22, FIG. 22 is a diagram showing the RF power output of the RF power source and the bias power signal outputted by the bias power source. The upper curve is the pulsed RF power output by the RF power source, and the lower curve is the output of the bias power source. Pulse bias power, the frequency of the output pulse of the RF power source and the bias power source are equal, that is, the time of one pulse period of the RF power is equal to the time of one pulse period of the bias power, and the RF power and the bias power output by the RF power source The bias power of the source output is in phase.

During one pulse period of the bias power, the bias power source is turned on for a first time T1, and the bias power source is turned off for a second time T2, the first time T1 and the first time T1 The ratio of the sum of the second time T2 is the first duty ratio, and during the plasma etching, the first duty ratio remains unchanged, and the time period of the pulse period of each radio frequency power is equal. When the RF power source is turned on and the bias power source is also turned on, an etching step is performed, the dielectric layer is etched, the RF power source is turned off, and when the bias power source is also turned off, a polymer deposition step is performed to form a surface of the mask layer. polymer.

During a pulse period of the RF power, the RF power source is turned on for a third time T3, and the RF power source is turned off for a fourth time T4, a third time T3, and a third time T3 and a fourth time. The ratio of the sum of T4 is a second duty ratio, the second duty ratio is equal to the first duty ratio during plasma etching, the opening and closing of the bias power source and the opening and closing of the RF power source Correspondingly, when the polymer is formed, the RF power source does not output the RF power, the bias power source does not output the bias power, and the residual positive ions in the etching step in the cavity are subjected to an acceleration electric field of 0, forming an aggregate. The material is not damaged by the bombardment of positive ions, so that the polymer maintains a certain thickness and has good uniformity when the polymer is formed, and the mask layer is better protected after the etching process. The rate of damage or damage is reduced.

The first duty ratio and the second duty ratio range from 10% to 90%, and the frequency of the output pulse of the bias power source and the RF power source is less than or equal to 50 kHz, which improves the etching efficiency and can be masked. A sufficient polymer is formed on the surface of the film layer.

Continuing to refer to FIG. 19 and FIG. 20, during an etch cycle of the plasma etch, the RF power source is turned on, and when the bias power source is also turned on, an etching step is performed, and the RF power is ionized to etch the gas to excite the plasma. The dielectric layer 402 is etched to form an etched hole 406; then the RF power source is turned off, the bias power source is also turned off, and a polymer forming step is performed to form a polymer 404 on the surface of the mask layer 403. 404 reduces the rate at which the mask layer 403 is not damaged or damaged when the dielectric layer 402 is subsequently etched along the etch holes 406, thereby increasing the etch selectivity of the dielectric layer 402 relative to the mask layer 403. In the polymer forming step, the sidewall of the etched hole 406 also forms a part of the polymer (not shown). In the etching step of the next pulse period, the sidewall of the protective etched hole 406 is not overetched. .

The plasma etched RF power source has a power of 500 to 4000 watts, an RF frequency of 60 to 120 MHz, a bias power source of 2000 to 8000 watts, and an offset frequency of 2 to 15 MHz. The pressure is 20~200 mTorr, the frequency of the RF power source is turned on and off is less than or equal to 50 kHz, the frequency of the RF power source is turned on and off is less than or equal to 50 kHz, and the etching is improved during plasma etching. At the same time, a sufficient amount of polymer is formed on the surface of the mask layer 403, so that the mask layer 403 is not damaged or damaged, and the etching selectivity ratio of the dielectric layer 402 to the mask layer 403 is increased.

The gas used in the plasma etching is one or more of C ₄ F ₈ , C ₄ F ₆ , CHF ₃ , CH ₂ F ₂ , CO, and C ₄ F ₈ and C ₄ F _{6 are} used to provide fluorocarbon. The reactant, the gas used for the etching further includes O ₂ and Ar, CHF ₃ , CH ₂ F ₂ for increasing the concentration of the polymer, O ₂ for controlling the amount of the polymer, and CO for controlling the proportion of the fluorocarbon. , Ar is used to form positive ions, providing the energy of the reaction.

The gas used in the plasma etching in this embodiment is a mixed gas of C ₄ F ₈ , C ₄ F ₆ , CHF ₃ , CH ₂ F ₂ , O ₂ , CO and Ar to ensure plasma etching. A sufficient polymer is formed on the surface of the mask layer 403. When the RF power source is turned on and the bias power source is also turned on, the etching step is performed, and C ₄ F ₈ , C ₄ F ₆ , CHF ₃ , CH ₂ F _{2 ,} etc. are ionized to generate F radicals under the action of RF power. Neutral CF ₂ and other molecular fragments, and also generate some positive ions such as: CF ₃ ^+, etc., Ar will lose electrons to generate Ar ⁺ positive ions, positive ions pass through the plasma sheath (plasma sheath) and bias power Acceleration will bombard the dielectric layer material and remove part of the dielectric layer. At the same time, F radicals will chemically react with the dielectric layer material to remove part of the dielectric layer material. When the RF power source is turned off and the bias power source is turned off, polymer formation is performed. In this step, the chamber has a portion of the reactive groups remaining in the etching step, and a neutral active component such as CF ₂ is compounded to form a fluorocarbon polymer deposited on the surface of the mask layer 403 due to the RF power source and bias. The power source is turned off, there is no accelerating electric field, the positive ions will not bombard the formed polymer, so that the formed polymer 404 is all preserved and has good uniformity, and there is a certain thickness when the etching is continued later. The polymer 404, thereby protecting the mask layer from damage or damage, is reduced in rate. Since both the bias power and the RF power are output in a pulsed manner.

Referring to FIG. 21, the above etching step and polymer formation step are repeated, and the dielectric layer 404 is etched along the etching hole 406 until a via hole is formed.

The aspect ratio of the through hole is greater than or equal to 10:1, and the RF power source and the bias power source respectively output the RF power in a pulse manner, and the RF power source and the bias power source output pulse have the same frequency, and the RF power source outputs The second duty cycle of the pulse remains unchanged, and the first duty cycle of the output pulse of the bias power source is equal to the second duty cycle of the output pulse of the RF power source, that is, when the polymer is formed, the bias power source is not output biased. When the power is set, the residual positive ions in the etching step in the cavity are subjected to an acceleration electric field of 0, and the formed polymer 404 is not damaged by the bombardment of positive ions, and the polymer 404 is always maintained as the etching process proceeds. A certain thickness, thereby reducing the rate at which the mask layer 403 is not damaged or damaged, increases the etching selectivity of the dielectric layer 402 relative to the mask layer 403 such that the dielectric layer 402 is inscribed with respect to the mask layer 403. The eccentricity selection ratio is greater than 15:1.

Referring to FIG. 23, FIG. 23 is a schematic flowchart diagram of a method for forming a semiconductor structure according to a fourth embodiment of the present invention, including:

Step S51, providing a substrate on which a dielectric layer is formed;

Step S52, forming a mask layer on the dielectric layer, the mask layer having an opening exposing a surface of the dielectric layer;

Step S53, using the mask layer as a mask, performing plasma etching on the dielectric layer, and the RF power source and the bias power source output the RF power in a pulse manner, the RF power source and the bias power source pulse. The output frequency is equal, the second duty ratio of the output pulse of the RF power source remains unchanged, and the first duty ratio of the output pulse of the bias power source is less than the second duty ratio of the output pulse of the RF power source, when the RF power source is turned on. When the bias power is also turned on, the dielectric layer is etched to form an etched hole. When the RF power source is turned on or off, when the bias power is turned off, a polymer is formed on the surface of the mask layer, and the process is repeated until the process is repeated. A through hole is formed.

24 to FIG. 27 are schematic cross-sectional structural views showing a process of forming a semiconductor structure according to a fourth embodiment of the present invention; FIG. 28 is a diagram showing a bias power signal outputted by a radio frequency power source and a bias power source output according to a fourth embodiment of the present invention; .

Referring to FIG. 24, a substrate 500 is provided on which a dielectric layer 502 is formed; a mask layer 503 is formed on the dielectric layer 502, the mask layer 503 having an opening 505 exposing a surface of the dielectric layer 502.

The substrate 500 is one of a germanium substrate, a germanium substrate, a germanium substrate, a tantalum carbide substrate, and a gallium nitride substrate. An ion doping region, a germanium via hole, or the like (not shown) is formed in the substrate 500; a semiconductor device such as a transistor, a resistor, a capacitor, or a memory may be formed on the substrate 500 (not shown in the drawing) ).

In other embodiments of the present invention, the substrate 500 is further formed with one or more interlayer dielectric layers (not shown), and the interlayer dielectric layer is made of yttria, low-k dielectric material or ultra-low a K dielectric material in which a semiconductor structure such as a metal interconnection or a conductive plug is formed.

The dielectric layer 502 is a single layer structure of a hafnium oxide layer, a tantalum nitride layer or a tantalum carbide layer; the dielectric layer 502 may be a two-layer structure of a hafnium oxide layer and a tantalum nitride layer or a multi-layer stack structure of a two-layer structure. The dielectric layer 502 may be a two-layer structure of a ruthenium oxide layer and a tantalum carbide layer or a multilayer structure of a two-layer structure; the dielectric layer 502 may be a two-layer structure or a double layer of a tantalum nitride layer and a tantalum carbide layer; The multilayer structure of the structure; the dielectric layer 502 may be a three-layer structure of a ruthenium oxide layer, a tantalum nitride layer, a tantalum carbide layer or a multilayer structure of a three-layer structure. A through hole is formed in the dielectric layer 502, and the through hole is used to fill the metal to form a plug.

In the embodiment, the dielectric layer 502 is a single layer structure of a ruthenium oxide layer.

The mask layer 503 is made of photoresist or amorphous carbon. As a mask for subsequently etching the dielectric layer 502, an opening 505 is formed by patterning the mask layer 503, and the opening 505 exposes the dielectric layer 502. The surface, the position of the opening 505 corresponds to the position of the subsequently etched through hole.

Referring to FIG. 25 and FIG. 26, the dielectric layer is plasma etched by using the mask layer 503 as a mask, and the RF power source and the bias power source both output RF power in a pulse manner, and the RF power source and The frequency of the output pulse of the bias power source is equal, the phase is the same, the second duty ratio of the output pulse of the RF power source remains unchanged, and the first duty ratio of the output pulse of the bias power source is less than the second duty of the output pulse of the RF power source. Empty ratio, one etching cycle of plasma etching includes an etching step and a polymer forming step. When the RF power source is turned on and the bias power source is also turned on, an etching step is performed to excite the plasma, and the etching portion is described. The dielectric layer 502 forms an etched hole 506; when the RF power source is turned on or off and the bias power source is turned off, a polymer forming step is performed to form a polymer 504 on the surface of the mask layer 503.

Both the RF power source and the bias power source output the RF power in a pulsed manner. The RF power source and the bias power source output pulses have the same frequency and the same phase, and the second duty ratio of the RF power source output pulse remains unchanged. The first duty cycle of the power source output pulse is less than the second duty cycle of the RF power source output pulse, such that the RF power source is turned on in the etch step, due to the bias power source being turned off, in the etching step A part of the polymer is deposited on the surface of the mask layer. After the etching step, the RF power source and the bias power source are both turned off, and the polymer deposition step is performed to deposit more polymer, thereby protecting the mask layer from damage. Or the rate of damage is reduced. Referring to FIG. 28, FIG. 28 is a diagram showing the RF power output of the RF power source and the bias power signal of the bias power source output. The upper curve is the pulsed RF power of the output of the RF power source, and the lower curve is the bias power source. The output pulse bias power, the frequency of the RF power source and the bias power source output pulse are equal, that is, the time of one pulse period of the RF power is equal to the time of one pulse period of the bias power, and the RF power and the bias of the RF power source output. The bias power of the power source output is in phase, and the first duty cycle of the bias power source output pulse is less than the second duty cycle of the RF power source output pulse.

During a pulse period of the RF power, the RF power source is turned on for a third time T3, and the RF power source is turned off for a fourth time T4, a third time T3, and a third time T3 and a fourth time. The ratio of the sum of T4 is the second duty ratio, and during the plasma etching, the second duty ratio remains unchanged, and the time period of the pulse period of each RF power is equal.

During one pulse period of the bias power, the bias power source is turned on for a first time T1, and the bias power source is turned off for a second time T2, the first time T1 and the first time T1 The ratio of the sum of the second time T2 is the first duty ratio, and during the plasma etching, the first duty ratio is less than the second duty ratio, and the bias power source is turned on after the bias power source is turned on. Will be turned off before the RF power source, due to the off bias power source, some of the polymer will be deposited on the surface of the mask layer during the etching step, plus the polymer formed by the polymer formation step, so that the total amount of polymer Increasing, in the polymer forming step, the RF power source does not output the RF power, the bias power source does not output the bias power, and the residual positive ions in the etching step in the cavity are subjected to an acceleration electric field of 0, forming an aggregate. The material is not damaged by the bombardment of positive ions, and the polymer is always maintained at a certain thickness as the etching process proceeds, thereby reducing the rate at which the mask layer is not damaged or damaged.

The first duty ratio is 40%~90% of the second duty ratio, the second duty ratio is 30%~90%, and the first duty ratio is 10%~80%, for example: second The duty ratio is 80%, and the first duty ratio can be 60%, which improves the etching efficiency while forming sufficient polymer on the surface of the mask layer.

Continuing to refer to FIG. 25 and FIG. 26, during an etch cycle of plasma etching, when the RF power source is turned on and the bias power source is also turned on, an etching step is performed, and the RF power is ionized to etch the gas to excite the plasma. The dielectric layer 502 is etched to form an etch hole 506. After the etch step, a part of the polymer is formed on the surface of the mask layer 503 due to the bias power source being turned off in advance; then the RF power source is turned off. The bias power source is also turned off, and a polymer forming step is performed to form a polymer 504 on the surface of the mask layer 503. The polymer 504 does not protect the mask layer 503 when the dielectric layer 502 is subsequently etched along the etch hole 506. The rate of damage or damage is reduced, thereby increasing the etch selectivity of dielectric layer 502 relative to mask layer 503. In the polymer forming step, the sidewall of the etch hole 506 also forms a part of the polymer (not shown). In the etching step of the next pulse period, the sidewall of the etch hole 506 is not overetched. eclipse.

The plasma etched RF power source has a power of 500 to 4000 watts, an RF frequency of 60 to 120 MHz, a bias power source of 2000 to 8000 watts, and an offset frequency of 2 to 15 MHz. The pressure is 20~200 mTorr, and the frequency of the RF power source is turned on and off by 50 kHz or less. When the plasma etching is performed, a sufficient amount is formed on the surface of the mask layer 503 while improving the etching efficiency. The polymer is such that the mask layer 503 is not damaged or damaged, and the etching selectivity of the dielectric layer 502 with respect to the mask layer 503 is increased.

The gas used in the plasma etching is one or more of C ₄ F ₈ , C ₄ F ₆ , CHF ₃ , CH ₂ F ₂ , CO, and C ₄ F ₈ and C ₄ F _{6 are} used to provide fluorocarbon. The reactant, the gas used for the etching further includes O ₂ and Ar, CHF ₃ , CH ₂ F ₂ for increasing the concentration of the polymer, O ₂ for controlling the amount of the polymer, and CO for controlling the proportion of the fluorocarbon. , Ar is used to form positive ions, providing the energy of the reaction.

The gas used in the plasma etching in this embodiment is a mixed gas of C ₄ F ₈ , C ₄ F ₆ , CHF ₃ , CH ₂ F ₂ , O ₂ , CO and Ar to ensure plasma etching. A sufficient polymer is formed on the surface of the mask layer 503. When the RF power source is turned on and the bias power is also turned on, the etching step is performed. C ₄ F ₈ , C ₄ F ₆ , CHF ₃ , CH ₂ F _{2 ,} etc. are ionized under the action of RF power to generate F radicals. Sexual CF ₂ and other molecular fragments, also generate some positive ions, such as: CF ₃ ^+, etc., Ar will also lose electrons to generate Ar ⁺ positive ions, positive ions through the plasma sheath (plasma sheath) and bias power Acceleration, will bombard the dielectric layer material, remove part of the dielectric layer, and F radicals will also chemically react with the dielectric layer material to remove part of the dielectric layer material. In the latter part of the etching step, due to the closure of the bias power source, During the etching step, part of the polymer is deposited on the surface of the mask layer; when the RF power source is turned off and the RF power source is turned off, the polymer formation step is performed, and at this time, active groups are still present in the chamber, and neutral active ingredients such as CF ₂ and the like will form a fluorocarbon polymer deposited on the surface of the mask layer 503. Since the RF power source does not output RF power, the bias power source does not output bias power, the accelerating electric field does not exist, and the positive ions do not bombard The formed polymer 504 allows all of the formed polymer 504 to be preserved, and a part of the polymer formed by the etching step is added, so that the total amount of the polymer is increased, and the polymer is not removed by the etching process after the subsequent etching. The large loss or loss is caused by the process, so that the polymer 504 is always maintained at a certain thickness, thereby protecting the mask layer from being damaged or damaged at a reduced rate.

Referring to FIG. 27, the above etching step and polymer formation step are repeated, and the dielectric layer 504 is etched along the etching hole 506 until a via hole is formed.

The aspect ratio of the through hole is greater than or equal to 10:1, and the RF power source and the bias power source respectively output the RF power in a pulse manner, and the RF power source and the bias power source output pulse have the same frequency, and the RF power source outputs The second duty cycle of the pulse remains unchanged, the first duty cycle of the bias power source output pulse is less than the second duty cycle of the RF power source output pulse, such that in the latter part of the etching step of each pulse period, Due to the shutdown of the bias power source, part of the polymer is deposited on the surface of the mask layer during the etching step. After the etching step, the RF power source and the bias power source are both turned off, and the polymer deposition step is performed to deposit more The polymer, as the etching process proceeds, the polymer 504 is maintained at a constant thickness, thereby protecting the mask layer 502 from damage or damage, reducing the rate of the dielectric layer 502 relative to the mask layer 504. The etch selectivity ratio is such that the etch selectivity ratio of dielectric layer 502 relative to mask layer 504 is greater than 15:1.

In summary, in the method for forming a semiconductor structure provided by the embodiment of the present invention, when a bias power source is used to output a bias voltage by plasma etching to form a via hole, the bias power source outputs a bias power in a pulse manner. Repeating the etching step and the polymer forming step so that the polymer can maintain a certain thickness, so that the rate at which the protective mask layer is not damaged or damaged is reduced throughout the etching process, and the dielectric layer is increased relative to the mask. The etching selectivity of the film layer.

Further, the plasma etching using the first duty ratio of the bias power is continuously reduced. As the etching process progresses, the RF power source is turned on in one etching cycle as the first duty ratio is continuously reduced. The time becomes shorter, that is, the time of the etching step is decreased, and the time of the polymer forming step is increased, thereby forming a sufficient amount of polymer on the surface of the mask layer while etching to form the via hole.

Further, both the RF power source and the bias power source output the RF power in a pulsed manner, and the frequency of the output pulse of the RF power source and the bias power source are equal, and the second duty ratio of the output pulse of the RF power source remains unchanged. The first duty cycle of the output pulse of the power source is equal to the second duty cycle of the output pulse of the RF power source, that is, when the polymer is formed, both the bias power source and the RF power source are turned off, and the etching step remains in the cavity. The positive ion receives an acceleration electric field of 0, and the formed polymer is not damaged by the bombardment of positive ions. The polymer is always maintained at a certain thickness and the uniformity is good, so that the protective mask layer is not damaged or damaged. The rate is reduced.

Further, both the RF power source and the bias power source output the RF power in a pulse manner, and the frequency of the output pulse of the RF power source and the bias power source are equal, and the second duty ratio of the output pulse of the RF power source remains unchanged. The first duty cycle of the output pulse of the power source is less than the second duty cycle of the output pulse of the RF power source, so that in the latter part of the etching step of each etch cycle, the etch is due to the closing of the bias power source In the step, part of the polymer is deposited on the surface of the mask layer. After the etching step, the RF power source and the bias power source are both turned off, and the polymer deposition step is performed to deposit more polymer, thereby protecting the mask layer from being affected. The rate of damage or damage is reduced. The first duty ratio is 40% to 90% of the second duty ratio, the second duty ratio is 30% to 90%, and the first duty ratio is 10% to 80%, thereby improving etching efficiency. At the same time, sufficient polymer can be formed on the surface of the mask layer.

The above description is only for the preferred embodiment of the present invention, and those skilled in the art can make other improvements according to the above description, but these changes still belong to the inventive spirit of the present invention and the patents defined below. In the scope.

200, 300, 400, 500. . . Base

202, 302, 402, 502. . . Dielectric layer

203, 303, 403, 503. . . Mask layer

204, 304, 404, 504. . . polymer

205, 305, 405, 505. . . Opening

206, 306, 406, 506. . . Etched hole

C1. . . Pulse period

T1. . . first timing

T2. . . Second time

T3. . . Third time

T4. . . Fourth time

S21, S31, S41, S51. . . Providing a substrate on which a dielectric layer is formed

S22, S32, S42, S52. . . Forming a mask layer on the dielectric layer

S23, S33, S43, S53. . . Plasma etching the dielectric layer

1 to FIG. 3 are schematic diagrams showing a structure of a conventional via hole forming process; FIG. 4 is a schematic flow chart showing a method of forming a semiconductor structure according to a first embodiment of the present invention; and FIGS. 5 to 8 are a process of forming a semiconductor structure according to a first embodiment of the present invention. FIG. 9 is a signal diagram of a radio frequency power output from a radio frequency power source and a bias power output from a bias power source according to a first embodiment of the present invention; FIG. 10 is a view showing a method of forming a semiconductor structure according to a second embodiment of the present invention; FIG. 11 is a cross-sectional structural view showing a process of forming a semiconductor structure according to a second embodiment of the present invention; FIG. 15 is a diagram showing an output of a radio frequency power source and an offset of a bias power source output according to a second embodiment of the present invention; FIG. 16 is a schematic diagram showing a relationship between a first duty ratio and an etching time or an etching depth; FIG. 17 is a schematic flow chart showing a method of forming a semiconductor structure according to a third embodiment of the present invention; FIG. 18 to FIG. FIG. 22 is a schematic cross-sectional structural view showing a process of forming a semiconductor structure according to a third embodiment of the present invention; FIG. 22 is an output of a radio frequency power source and a bias power source outputted by a radio frequency power source according to a third embodiment of the present invention; FIG. 23 is a schematic flow chart of a method for forming a semiconductor structure according to a fourth embodiment of the present invention; and FIG. 24 to FIG. 27 are schematic cross-sectional structural views showing a process of forming a semiconductor structure according to a fourth embodiment of the present invention; In the fourth embodiment of the invention, the RF power output from the RF power source and the bias power signal output from the bias power source are output.

S51. . . Providing a substrate on which a dielectric layer is formed

S52. . . Forming a mask layer on the dielectric layer

S53. . . Plasma etching the dielectric layer

Claims (18)

A method of forming a semiconductor structure, comprising: providing a substrate, forming a dielectric layer on the substrate; forming a mask layer on the dielectric layer, the mask layer having an opening exposing a surface of the dielectric layer The mask layer material is photoresist or amorphous carbon; the dielectric layer is plasma etched by using the mask layer as a mask, and the bias power source outputs the bias power in a pulse manner. When the power source is turned on, a portion of the dielectric layer is etched to form an etched hole. When the bias power source is turned off, a polymer is formed on the surface of the mask layer, and the process of repeatedly biasing the power source to turn on and biasing the power source to turn off is repeated. Until a through hole is formed. The method of forming a semiconductor structure according to claim 1, wherein the dielectric layer is a single layer or a stacked structure of a tantalum oxide layer, a tantalum nitride layer, or a tantalum carbide layer. The method of forming a semiconductor structure according to claim 1, wherein the gas used in the plasma etching is one or more of C ₄ F ₈ , C ₄ F ₆ , CHF ₃ , CH ₂ F ₂ , and CO. The method of forming a semiconductor structure according to claim 3, wherein the gas used in the plasma etching further comprises O ₂ and Ar. The method for forming a semiconductor structure according to claim 3, wherein the plasma etched RF power source has a power of 500 to 4000 watts, an RF frequency of 60 to 120 MHz, and a bias power source of 2000 to 8000 watts. The bias frequency is 2~15 MHz, and the etching chamber pressure is 20~200 mTorr. The method of forming a semiconductor structure according to claim 5, wherein the bias power source is turned on for a first time and the bias power source is turned off within one pulse period of the bias power source output. For the second time, the ratio of the first time to the sum of the first time and the second time is the first duty cycle, and the first duty cycle remains unchanged during the plasma etching process. The method of forming a semiconductor structure according to claim 6, wherein the first duty ratio ranges from 10% to 90%. The method of forming a semiconductor structure according to claim 5, wherein the bias power source is turned on for a first time and the bias power source is turned off within one pulse period of the bias power source output. For the second time, the ratio of the first time to the sum of the first time and the second time is the first duty cycle, and during the plasma etching, the first duty cycle is gradually decreased, within each pulse period. The sum of the first time and the second time remains unchanged. The method of forming a semiconductor structure according to claim 8, wherein the first duty ratio is gradually reduced from 90% to 10%. The method of forming a semiconductor structure according to claim 6, wherein the RF power source outputs the RF power in a pulsed manner. A method of forming a semiconductor structure according to claim 10, wherein the frequency of the bias power source output pulse is equal to the frequency of the RF power source output pulse. The method of forming a semiconductor structure according to claim 11, wherein the bias power source and the RF power source output pulse have a frequency of 50 kHz or less. The method for forming a semiconductor structure according to claim 10, wherein a time during which the RF power source is turned on is a third time, and a time when the RF power source is turned off is a fourth period in a pulse period of the RF power source output. The ratio of the third time to the sum of the third time and the fourth time is a second duty ratio, the second duty ratio being equal to the first duty ratio. The method of forming a semiconductor structure according to claim 11, wherein the second duty ratio is 10% to 90%. The method for forming a semiconductor structure according to claim 10, wherein a time during which the RF power source is turned on is a third time, and a time when the RF power source is turned off is a fourth period in a pulse period of the RF power source output. The ratio of the third time to the sum of the third time and the fourth time is a second duty ratio, and the first duty ratio is less than the second duty ratio. The method of forming a semiconductor structure according to claim 15, wherein the first duty ratio is 40% to 90% of the second duty ratio. The method of forming a semiconductor structure according to claim 15, wherein the second duty ratio is 30% to 90%, and the first duty ratio is 10% to 80%. The method of forming a semiconductor structure according to claim 15, wherein the formed via hole has an aspect ratio of 10:1 or more.