CN111952286B - Manufacturing method and structure of capacitor - Google Patents
Manufacturing method and structure of capacitor Download PDFInfo
- Publication number
- CN111952286B CN111952286B CN201910408619.9A CN201910408619A CN111952286B CN 111952286 B CN111952286 B CN 111952286B CN 201910408619 A CN201910408619 A CN 201910408619A CN 111952286 B CN111952286 B CN 111952286B
- Authority
- CN
- China
- Prior art keywords
- groove
- pulse
- bias
- capacitor
- side wall
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
Abstract
The invention provides a manufacturing method and a structure of a capacitor, wherein the method comprises the following steps: etching a groove with a rough side wall on the substrate by adopting a plasma etching method and utilizing the alternate complementary action of the bias pulse and the source pulse; forming a dielectric layer in the groove, wherein the dielectric layer is conformally lined on the inner surface of the groove; forming a conductive layer in the groove, wherein the conductive layer is filled in the groove and is separated from the substrate through a dielectric layer; when the groove is etched, the bias pulse is turned on and off alternately to control the bias power generated alternately, the source pulse is kept on, and the power of the source pulse is adjusted according to the change of the bias power to compensate. The invention forms the capacitance groove with rough side wall by utilizing the alternate complementary action of the bias pulse and the source pulse, so that the side wall of the groove has alternate convex-concave fluctuation in the depth direction of the groove, the capacitance area can be increased, and the capacitance density of the capacitor is improved.
Description
Technical Field
The present invention relates to the field of semiconductor devices, and more particularly, to a method and structure for manufacturing a capacitor.
Background
Silicon capacitors are devices fabricated on a silicon substrate that increase the integration of complex electronic circuits. However, in order to reduce the consumption of semiconductor substrate area, it is also necessary to continue to increase the capacitance density of silicon capacitors, i.e., the capacitance per unit semiconductor substrate area. One existing approach is to extend the coverage of the electrodes.
U.S. patent publication No. US 8283750B 2 discloses a trench capacitor based on a trench formed in a substrate, in which trench a stack of capacitor layers is formed, with a pillar extending from the bottom of the trench all the way to the substrate surface. To improve mechanical stability, the electrical elements extend the length of the struts primarily by crossing the struts perpendicularly. In order to increase the capacitance, the capacitance is changed by deep trench and shrinking critical dimension, or a trench crossing stack is formed in the trench to increase the electrode coverage area.
In addition, a three-dimensional cell (3D-cell) capacitor formed on a silicon substrate can also achieve a higher capacitor density. For example, a 3D cell Capacitor formed on a silicon substrate as disclosed in U.S. Pat. Nos. 3D-cell and 3D-Capacitor structure, publication No. US 9647057B 2, may result in a low equivalent series resistance and a high surface density of the Capacitor.
However, in practical production applications, how to improve the capacitance density of the capacitor through simpler structure and process is still a technical problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above-mentioned prior art, an object of the present invention is to provide a method and a structure for manufacturing a capacitor, which are used to improve the capacitance density of the capacitor.
To achieve the above and other related objects, the present invention provides a method for manufacturing a capacitor, comprising the steps of:
providing a substrate;
etching to form a groove with a rough side wall on the substrate by adopting a plasma etching method and utilizing the alternate complementary action of the bias pulse and the source pulse;
forming a dielectric layer in the groove, wherein the dielectric layer is conformally lined on the inner surface of the groove; and
forming a conductive layer in the groove, wherein the conductive layer is filled in the groove and is separated from the substrate through the dielectric layer;
and when the groove is etched, the bias pulse is alternately switched on and off to control the bias power to be alternately generated, the source pulse is kept on, and the power of the source pulse is adjusted according to the change of the bias power to compensate.
Optionally, when the bias pulse is turned off, the power of the source pulse is increased for compensation, and when the bias pulse is turned on, the power of the source pulse is decreased.
Optionally, the bias pulse is periodically turned on and off while the trench is etched.
Further optionally, the bias pulse switching cycle has a frequency of 1-500 times per second.
Further optionally, the bias pulse has an on-time of 20-80% of the total switching cycle time within one switching cycle.
Optionally, the bias power ranges from 0 to 2000W, the power of the source pulse ranges from 10 to 1000W, and the etching gas pressure ranges from 5 to 1000mtorr.
Optionally, when the trench is etched, a carbon fluoride plasma is used for etching.
To achieve the above and other related objects, the present invention also provides a capacitor structure made by the above method, comprising:
the device comprises a substrate, a groove with rough side walls and a first electrode wrapping the groove;
a dielectric layer conformally lining the inner surface of the trench;
the conducting layer is filled in the groove and is separated from the first electrode through the dielectric layer; and
a second electrode connected to the conductive layer;
the groove is formed by etching by using a plasma etching method and utilizing the alternate complementary action of bias pulses and source pulses, and the side wall of the groove is provided with alternate concave-convex fluctuation shapes in the depth direction of the groove according to the alternate switch of the bias pulses.
Alternatively, the side wall of the trench has a periodic concave-convex shape from the opening of the trench toward the bottom in accordance with the periodic switching of the bias pulse.
As described above, the manufacturing method and structure of the capacitor according to the present invention have the following advantages:
the invention forms the capacitance groove with rough side wall by utilizing the alternate complementary action of the bias pulse and the source pulse in the plasma etching, so that the side wall of the groove has alternate convex-concave fluctuation in the depth direction of the groove, the capacitance area can be increased, and the capacitance density of the capacitor can be improved. Compared with the prior art, the method is simple and easy to realize, the shape of the side wall of the groove can be accurately controlled, and the method has high practical value.
Drawings
Fig. 1 is a schematic diagram illustrating a method for manufacturing a capacitor according to an embodiment of the present invention.
FIG. 2 is a schematic diagram illustrating the complementary alternating action of bias pulses and source pulses during a plasma etch of a trench according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of a capacitor structure according to an embodiment of the invention.
Description of the element reference numerals
100. Substrate
101. Groove
200. A first electrode
300. Dielectric layer
400. Conductive layer
500. Second electrode
600. Passivation layer
S1-S4 steps
Detailed Description
The following embodiments of the present invention are provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.
It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Referring to fig. 1, the present embodiment provides a method for manufacturing a capacitor, including the following steps:
s1, providing a substrate;
s2, etching to form a groove with a rough side wall on the substrate by adopting a plasma etching method and utilizing the alternate complementary action of the bias pulse and the source pulse;
s3, forming a dielectric layer in the groove, wherein the dielectric layer is conformally lined on the inner surface of the groove; and
and S4, forming a conducting layer in the groove, wherein the conducting layer is filled in the groove and is separated from the substrate through the dielectric layer.
In step S2, when the trench is etched by using plasma, the bias pulse is turned on and off alternately to control the bias power generated alternately, the source pulse is kept on, and the power of the source pulse is adjusted to compensate according to the change of the bias power.
The invention can make the side wall of the groove form an alternate concave-convex undulation shape in the depth direction of the groove under the alternate complementary action of the bias pulse and the source pulse, thereby increasing the side wall area of the groove.
In particular, the power of the source pulse may be increased as a compensation when the bias pulse is off and decreased when the bias pulse is on. In particular the power value can be adjusted according to the actual situation.
Since a silicon substrate is generally used at present, carbon fluoride (C) may be used when etching the trench x F y ) And etching by using the plasma. In this embodiment, the bias power may be in a range of 0-2000W, the power of the source pulse may be in a range of 10-1000W, and the etching gas pressure may be in a range of 5-1000mtorr.
As one of preferable aspects of the present invention, the bias pulse may be periodically turned on and off while the trench is etched. To obtain more electrode coverage area, the frequency of bias pulse on/off should be moderate. One on and off of the bias pulse is used as a switching cycle, and the frequency of the switching cycle of the bias pulse can be 1-500 times per second. The bias pulse may have an on-time of 20-80% of the total switching cycle time, i.e. a duty cycle of 20-80%, during one switching cycle.
As a preferred aspect of this embodiment, the alternating complementary action of the bias pulses and the source pulses can be as shown in fig. 2, wherein the solid line represents the bias pulses and the dashed line represents the source pulses. In a switching cycle, when the bias pulse is started, the source pulse adopts lower power, when the bias pulse is closed, the source pulse adopts higher power to compensate than before, the bias pulse and the source pulse are periodically and circularly controlled in the whole etching process according to the mode, and the periodic concave-convex fluctuation of the side wall of the groove from top to bottom can be correspondingly obtained.
The corresponding resulting capacitor structure is shown in fig. 3. The capacitor structure includes: a substrate 100, a first electrode 200, a dielectric layer 300, a conductive layer 400, and a second electrode 500. The dielectric layer 300 is used as a capacitor dielectric between the first electrode 200 and the second electrode 500, and a suitable dielectric material may be selected according to practical situations, which is not limited in the present invention. The substrate 100 may be a silicon substrate or other suitable semiconductor material, and the substrate 100 has a trench 101 with rough sidewalls. A first electrode 200 is disposed on the substrate 100, wrapping the trench 101, in contact with the dielectric layer 300. A dielectric layer 300 conformally lines the inner surfaces of the trench 101. The conductive layer 400 is filled in the trench 101 and separated from the first electrode 200 by the dielectric layer 300. The second electrode 500 and the conductive layer 400 may be integrally connected. The first electrode 200 may serve as a lower electrode of a capacitor, the second electrode 500 may serve as an upper electrode of the capacitor, and the first electrode 200, the second electrode 500 and the conductive layer 400 may be made of any suitable conductive material, which is not limited in the present invention. The passivation layer 600 may also be covered at the edge of the second electrode 500.
The groove 101 is formed by etching by using the alternating complementary action of the bias pulse and the source pulse by adopting a plasma etching method, and the side wall of the groove 101 has an alternating concave-convex shape in the depth direction of the groove according to the alternating switch of the bias pulse. Such sidewall topography provides a greater surface area for dielectric layer 300 to conform to, thereby increasing electrode coverage.
When the alternating complementary action of the bias pulse and the source pulse is as shown in fig. 2, that is, the bias pulse and the source pulse are periodically controlled cyclically, the sidewall of the trench 101 formed from the opening to the bottom of the trench 101 has a periodic concave-convex shape according to the periodic switching of the bias pulse.
As shown in the enlarged portion of fig. 3, inward protrusion of the trench sidewall is gradually formed when the bias pulse is off, and the degree of protrusion may be determined by the duration of the bias pulse off and the compensated source pulse power, and outward protrusion of the trench sidewall is gradually formed when the bias pulse is on, and the degree of protrusion may be determined by the duration of the bias pulse on and the bias power. The solid arrows in fig. 3 indicate that the bias pulse primarily contributes to the trench profile when the bias pulse is on, and the dashed arrows indicate that the compensation of the source pulse primarily contributes to the trench profile when the bias pulse is off. In this way, in practical applications, the roughness of the sidewall can be controlled by adjusting the bias pulse and the source pulse, for example, the concave-convex frequency of the trench sidewall can be controlled by controlling the frequency of the switching cycle of the bias pulse, and the degree of concave-convex can be controlled by controlling the working time of the bias pulse in the switching cycle, the bias power and the power of the source pulse.
In summary, the invention utilizes the alternating complementary action of the bias pulse and the source pulse in the plasma etching to form the capacitance trench with rough side wall, so that the side wall of the trench has alternating convex-concave fluctuation in the depth direction of the trench, the capacitance area can be increased, and the capacitance density of the capacitor can be improved. Compared with the prior art, the method is simple and easy to realize, the shape of the side wall of the groove can be accurately controlled, and the method has high practical value.
Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (8)
1. A method of manufacturing a capacitor, comprising the steps of:
providing a substrate;
etching a groove with a rough side wall on the substrate by adopting a plasma etching method and utilizing the alternate complementary action of the bias pulse and the source pulse;
forming a dielectric layer in the groove, wherein the dielectric layer is conformally lined on the inner surface of the groove; and
forming a conductive layer in the groove, wherein the conductive layer is filled in the groove and is separated from the substrate through the dielectric layer;
when the groove is etched, the carbon fluoride plasma is adopted for etching, the bias pulse is alternately opened and closed to control the bias power to be alternately generated, the source pulse is kept opened, the power of the source pulse is adjusted according to the change of the bias power for compensation, when the bias pulse is closed, the inward bulge of the side wall of the groove is gradually formed, and when the bias pulse is opened, the outward bulge of the side wall of the groove is gradually formed.
2. The method for manufacturing a capacitor according to claim 1, wherein: when the bias pulse is turned off, the power of the source pulse is increased for compensation, and when the bias pulse is turned on, the power of the source pulse is decreased.
3. The method for manufacturing a capacitor according to claim 1, wherein: and when the groove is etched, the bias pulse is periodically switched on and off.
4. The method for manufacturing a capacitor according to claim 3, wherein: the frequency of the bias pulse switching cycle is 1-500 times per second.
5. A method for manufacturing a capacitor according to claim 3, wherein: the working time of the bias pulse in one switching cycle accounts for 20% -80% of the total time of the switching cycle.
6. The method for manufacturing a capacitor according to claim 1, wherein: the bias power range is 0-2000W, the power range of the source pulse is 10-1000W, and the etching gas pressure is 5-1000mtorr.
7. A capacitor structure produced by the method for producing a capacitor according to any one of claims 1 to 6, comprising:
the device comprises a substrate, a groove with rough side walls and a first electrode wrapping the groove;
a dielectric layer conformally lining the inner surface of the trench;
the conducting layer is filled in the groove and is separated from the first electrode through the dielectric layer; and
a second electrode connected to the conductive layer;
the groove is formed by etching by using a plasma etching method and utilizing the alternate complementary action of bias pulses and source pulses, and the side wall of the groove is provided with alternate concave-convex fluctuation shapes in the depth direction of the groove according to the alternate switch of the bias pulses.
8. The capacitor structure of claim 7, wherein: the side wall of the trench has a periodic concave-convex shape from the opening of the trench toward the bottom in accordance with the periodic switching of the bias pulse.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910408619.9A CN111952286B (en) | 2019-05-16 | 2019-05-16 | Manufacturing method and structure of capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910408619.9A CN111952286B (en) | 2019-05-16 | 2019-05-16 | Manufacturing method and structure of capacitor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111952286A CN111952286A (en) | 2020-11-17 |
| CN111952286B true CN111952286B (en) | 2022-11-22 |
Family
ID=73335958
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910408619.9A Active CN111952286B (en) | 2019-05-16 | 2019-05-16 | Manufacturing method and structure of capacitor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111952286B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102737984A (en) * | 2012-07-06 | 2012-10-17 | 中微半导体设备(上海)有限公司 | Semiconductor structure formation method |
| CN107017237A (en) * | 2015-12-29 | 2017-08-04 | 台湾积体电路制造股份有限公司 | Deep-trench capacitor with scalloped profile |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030052088A1 (en) * | 2001-09-19 | 2003-03-20 | Anisul Khan | Method for increasing capacitance in stacked and trench capacitors |
-
2019
- 2019-05-16 CN CN201910408619.9A patent/CN111952286B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102737984A (en) * | 2012-07-06 | 2012-10-17 | 中微半导体设备(上海)有限公司 | Semiconductor structure formation method |
| CN107017237A (en) * | 2015-12-29 | 2017-08-04 | 台湾积体电路制造股份有限公司 | Deep-trench capacitor with scalloped profile |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111952286A (en) | 2020-11-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6609712B2 (en) | 3D capacitor structure | |
| CN101682252B (en) | DC-to-DC converter comprising reconfigurable capacitor unit | |
| TW201724532A (en) | Integrated chip and method of forming deep trench capacitor | |
| CN109979823B (en) | Shielding gate power device and manufacturing method thereof | |
| US9960237B2 (en) | Termination structure with multiple embedded potential spreading capacitive structures for trench MOSFET | |
| EP2203931A1 (en) | Multilayer structure and method of producing the same | |
| CN107204323A (en) | Semiconductor structure and its manufacture method | |
| CN110061000A (en) | Semiconductor storage with and preparation method thereof | |
| KR102631107B1 (en) | High aspect ratio bosch deep etch | |
| US11881358B2 (en) | Capacitor | |
| CN111952286B (en) | Manufacturing method and structure of capacitor | |
| CN104022073B (en) | The manufacturing method of microelectronic component | |
| CN103227101A (en) | Semiconductor devices and methods of manufacture thereof | |
| CN106711149B (en) | Vertical channel structure | |
| US11309382B2 (en) | Electronic product comprising a component having triskelion-pillars, and corresponding fabrication method | |
| TWI471978B (en) | Semiconductor device and fabricating method thereof | |
| CN112018089B (en) | Semiconductor capacitor and method for manufacturing the same | |
| KR20100003069A (en) | Pumping mos capacitor | |
| TWI466239B (en) | Stack capacitor structure and forming method | |
| JP4868683B2 (en) | Variable capacitor | |
| CN107706147B (en) | Preparation method of vertical contact hole | |
| TWI223387B (en) | Method for increasing the capacitance of deep trench capacitors | |
| CN104752154A (en) | Method for manufacturing capacitor | |
| KR102289246B1 (en) | 3D semiconductor capacitor and method for fabricating the same | |
| JP2008124466A (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |