TW201339603A - Testing board for burn-in tester - Google Patents

Abstract

A test board for a burn-in tester is provided to increase data processing speed by applying a test signal to a semiconductor device through a fly-by structure. A test board(20) for a burn-in tester comprises multiple sockets(21), a circuit board(22), and a connector(23). A semiconductor device to be tested is loaded on the sockets. The circuit board has an electric circuit for applying a test signal from a tester board to the sockets. The connector is coupled to one side of the circuit board and is electrically connected to the tester board.

Description

Test board for aging test equipment

The present invention relates to a test board for a burn-in tester for testing the reliability of thermal stress of a semiconductor element when the packaged semiconductor element is powered on.

The semiconductor element is subjected to various tests after being manufactured, and the burn-in test relating to the present invention is a test for confirming the thermal stress tolerance of the semiconductor element when the semiconductor element is turned on to operate the semiconductor element. Moreover, the equipment that performs such an aging test is called an aging test equipment.

The burn-in test apparatus includes an aging chamber for accommodating a semiconductor element and a test chamber for accommodating a test substrate for reading a feedback signal of a feed back after applying a test signal to a semiconductor element housed in the aging chamber.

The semiconductor element is mounted on the test board in a matrix form, and is housed in the aging chamber in this state to simultaneously test a plurality of semiconductor elements. In order to further increase the processing capacity, the aging chamber has a structure in which a plurality of test boards are simultaneously accommodated. Moreover, the semiconductor component mounted on the test board passes through the test board Some board connectors are electrically connected to the test substrate.

In general, as disclosed in Korean Laid-Open Utility Model No. 1999-004919 (Aging Board for Semiconductor Package Testing, hereinafter referred to as "Prior Art"), a test board (named "aging board" in the prior art) has many A socket, a circuit board (known in the prior art as "PCB"), and a connector (named "connecting portion" in the prior art). Moreover, according to the test board of such a structure, the test signal transmitted from the test substrate through the connector is applied to the semiconductor element loaded on each of the sockets on which the semiconductor element is mounted through the circuit in the board.

However, as shown in FIG. 1, the test signal transmitted from the test substrate through the connector in the prior art is applied to the semiconductor element D mounted on each socket through the circuit C of the tree structure, at this time due to the radiation generated by the tree structure. This causes the test signal to become weak, and this problem eventually causes the response speed of the semiconductor element to be slow, resulting in a consequence of reducing the processing speed.

It is an object of the present invention to provide a test board that does not emit radiation of a test signal.

The test board for an aging test apparatus provided by the present invention as described above includes: a plurality of sockets loaded with semiconductor elements to be tested, arranged in a matrix form; and a circuit board having circuits for having A test signal on the test substrate side is applied to the transfer line group of the plurality of sockets; a connector is coupled to one side of the circuit board and electrically connected to the test substrate side. The sockets belonging to the same column among the plurality of sockets are simultaneously arranged on one transmission line On the group, there is a Fly by structure.

At least two rows of sockets are disposed in each of the transmission line groups of the circuit board.

The circuit on the circuit board is set such that an impedance of a set region in which the plurality of sockets are disposed is different from an impedance of an unset region located before a test signal transmitted through the connector into a set region, preferably set The impedance of the region is higher than the impedance of the unset region. Further, in a more preferred manner, the difference between the impedances of the set region and the unset region is set to be such that the impedance of the set region and the impedance of the unset region can be made when the plurality of sockets are loaded with the semiconductor component equal.

Preferably, the end of the transmission line group is terminated.

And, the test board for aging test apparatus provided by the present invention as described above includes: a plurality of sockets loaded with semiconductor elements to be tested, arranged in a matrix form; and a circuit board having a circuit having A test signal from the test substrate side is applied to the transmission line group of the plurality of sockets; a connector is coupled to one side of the circuit board and electrically connected to the test substrate side. At least one of the at least one transmission line group of the transmission line group is disposed at the same time with a fly-by structure.

According to the invention as described above, the radiation of the test signal does not occur, and the test signal is applied to the semiconductor element by the fly-by structure, so that the response speed of the semiconductor element is fast, and the data can be processed at a high speed, thereby having an effect of improving the processing speed. .

Symbol Description:

20‧‧‧ test board

21‧‧‧ socket

22‧‧‧ Circuit board

23‧‧‧Connector

Ca to Ch‧‧‧ transmission line group

Fig. 1 is a reference diagram for explaining the application of a test signal in the prior art.

2 is a conceptual diagram of a test board provided by an embodiment of the present invention.

FIG. 3 is a reference diagram for explaining the test board of FIG. 2.

Hereinafter, preferred embodiments of the present invention as described above will be described with reference to the accompanying drawings. In order to simplify the description, the repeated explanation is omitted or simplified as much as possible.

2 is a schematic conceptual diagram of a test board 20 for an aging test apparatus according to an embodiment of the present invention.

The test board 20 provided in this embodiment includes a plurality of sockets 21, a circuit board 22, a connector 23, and the like.

Each of the sockets 21 is loaded with semiconductor elements D to be tested, and these sockets 21 are disposed on the circuit board 22 in a matrix form.

The circuit board 22 has a circuit including eight transmission line groups (Ca to Ch, as a reference, a transmission line group including a number of transmission lines equivalent to a number of channels for applying signals to the semiconductor elements) for After the test signal on the test substrate side (the signal for operating the semiconductor element) is applied to the semiconductor elements D respectively mounted on the plurality of sockets 21, the result signal fed back according to the operation of the semiconductor element D is sent to the test substrate (not shown) side. . Here, the socket 21 included in two of the plurality of sockets 21 is simultaneously disposed in each of the plurality of transmission line groups (Ca to Ch) provided on the circuit board 22. Ie, one transmission A socket 21 belonging to two columns is arranged on the line group (Ca to Ch), and by using a Fly by structure, a test signal from the test substrate can be applied to the semiconductor element mounted on the socket 21 without radiation or the like. Therefore, as the test signal from the test substrate is applied to the semiconductor element to be tested, the semiconductor elements respectively loaded in the two column sockets 21 can be sequentially operated, so that high-speed processing of the material can be realized.

Of course, depending on the specific implementation, a structure in which only the sockets 21 included in one column are arranged on one transmission line group or a structure in which the sockets 21 included in three or more columns are arranged on one transmission line group may be employed. The problem that the sockets D included in several columns are arranged on one transmission line group can be arbitrarily designed depending on the number of sockets, the processing speed, and the like. Further, it is entirely conceivable to arrange a plurality of outlets not belonging to the same row or the same column in a flying structure on one transmission line group.

Moreover, the end of the transmission line group (Ca to Ch) is terminated, so that no carrier occurs. This is because the time length of the resultant signal is shortened with high-speed processing, and therefore it is necessary to prevent the occurrence of a carrier that acts as a signal distortion.

In addition, when the semiconductor element D is mounted on the socket 21, the impedance is lowered. Therefore, it is preferable to set the circuit on the circuit substrate 22 such that the impedance of the set region B in which the plurality of sockets 21 are provided is different from the impedance of the unset region A before the test signal transmitted through the connector 23 enters the set region B. That is, since the impedance of the semiconductor element D is low when it is mounted on the socket 21, the impedance of the installation area B is set higher than the impedance of the unmounted area A. For example, when the impedance of the region A is not set to 40 ohms, the impedance of the region B is preferably set. Set to 60 ohms higher than the impedance of the unset area A, so that the impedances of the two areas A, B have a gap of 20 ohms, so that when the semiconductor element D is subsequently loaded on the socket 21, the impedance of the set area B is lowered by 20 ohms. It becomes 40 ohms and becomes the same impedance as the unset area A.

The connector 23 is used to electrically connect to the test substrate side.

According to the test board 20 having the above configuration, as shown in FIG. 3, the semiconductor element D belonging to two adjacent columns among the mounted semiconductor elements D can be used as an object from the semiconductor element No. 0 to the semiconductor element No. 31. The semiconductor elements selected in the order are sequentially tested by applying a test signal. Therefore, data can be processed at high speed.

As described above, the present invention has been specifically described by referring to the embodiments of the drawings, but the above-described embodiments are only for the purpose of illustrating the preferred embodiments. It is understood as the scope of the scope of patent application and its equivalent concept.

20‧‧‧ test board

21‧‧‧ socket

22‧‧‧ Circuit board

23‧‧‧Connector

Ca to Ch‧‧‧ transmission line group

Claims (7)

A test board for an aging test apparatus, comprising: a plurality of sockets loaded with semiconductor elements to be tested, arranged in a matrix form; and a circuit board having a circuit for bringing the side from the test substrate a test signal is applied to the transmission line group of the plurality of sockets; and a connector is coupled to one side of the circuit board and electrically connected to the test substrate side, wherein the sockets belonging to the same column of the plurality of sockets are simultaneously disposed at On a transmission line group, it has a flying structure. A test board for an aging test apparatus according to claim 1, characterized in that at least two rows of sockets are arranged in each of the transmission line groups of the circuit board. The test board for aging test equipment according to claim 1, wherein the circuit on the circuit board is configured to: an impedance of a set region in which the plurality of sockets are disposed is different from being located through the connector The transmitted test signal enters the impedance of the unset area of the position before the set area. A test board for an aging test apparatus according to claim 3, characterized in that the impedance of the set area is higher than the impedance of the unset area. A test board for an aging test apparatus according to claim 4, wherein a difference between an impedance of the set area and an impedance of the unset area is set to enable when the plurality of sockets are loaded with semiconductor elements The impedance of the set region is equal to the impedance of the unset region. A test board for an aging test apparatus according to claim 1, characterized in that the end of the transmission line group is subjected to termination processing. A test board for an aging test device, comprising: a plurality of sockets loaded with semiconductor elements to be tested, arranged in a matrix form; a circuit board having circuitry having a transmission line group for applying test signals from the test substrate side to the plurality of sockets; and The device is coupled to one side of the circuit board and electrically connected to the test substrate side, and at least one of the transmission line groups is disposed with at least two sockets at the same time, and has a flying structure.