TW201339544A - An integrated MEMS pressure sensor with mechanical electrical isolation - Google Patents

Abstract

An integrated MEMS pressure sensor is provided, including, a CMOS substrate layer, an N+ implant doped silicon layer, a field oxide (FOX) layer, a plurality of implant doped silicon areas forming CMOS wells, a two-tier polysilicon layer with selective ion implantation forming a membrane, further including an implant doped polysilicon layer and a non-doped polysilicon layer, a second non-doped polysilicon layer, a plurality of implant doped silicon areas 207 forming CMOS source/drain, a gate poly layer made of polysilicon to form CMOS transistor gates, said CMOS wells, said CMOS transistor sources/drains and said CMOS gates forming CMOS transistors, an oxide layer embedded with an interconnect contact layer, a plurality of metal layers interleaved with a plurality of via hole layers, a Nitride deposition layer, an under bump metal (UBM) layer and a plurality of solder spheres. N+ implant doped silicon layer and implant doped/un-doped composition polysilicon layer 206 form a sealed vacuum chamber.

Description

Microelectromechanical pressure sensor with electromechanical isolation

The present invention relates to an integrated single-wafer micro electro mechanical system (MEMS) device, in particular, a complementary metal oxide semiconductor (CMOS) process, flip chip bumping package (Flip Chip Bumping package) Or MEMS devices with mechanical/electrical isolation capabilities built by Wafer Level Package (WLP) technology.

Due to the wide range of applications in portable electronic devices, microelectromechanical systems (MEMS) devices have long been closed. For example, MEMS pressure sensors, which are used as altimeters, have recently gained attention due to the application of portable electronic devices, such as smart phones. MEMS pressure sensors can be classified as resistive or capacitive. However, most MEMS pressure sensors are fabricated using separate MEMS pressure sensors and Application Specific Integrated Circuit (ASIC) dual-chips, and the final product is on printed circuit board (PCB) substrates. The wire on the top is connected and assembled.

Figure 1 shows a conventional structural schematic of a MEMS pressure sensor having a dual die structure. As shown in FIG. 1, the dual-wafer structure of the MEMS pressure sensor includes a PCB 101 as a substrate, a plurality of connection pads 102, a complementary gold-oxide half (CMOS) circuit 103, and an epoxy resin 104 covering the CMOS circuit 103. The MEMS circuit 105, the side wall 106 for surrounding the entire structure, the wire pad 107, the upper cover 108, and the air flow hole 109 for ambient air pressure, wherein the MEMS circuit 105 further includes a glass/german circuit 105a and a film 105b. As shown in Figure 1, conventional two-chip MEMS pressure sensors require wire bonding and complex packaging, such as air flow holes for ambient air pressure in the side walls, upper cover, and upper cover.

The problem with a twin-chip solution using wire bonding is that the wiring is basically a conductive antenna that picks up high-frequency noise, and the resonance of high-frequency noise interferes with signals in its frequency range if it is in the low frequency band. Another disadvantage of the above described two-chip technology is that the packaging cost is too high. Therefore, there is a great need for a MEMS pressure sensor with high reliability and at the same time low cost.

The MEMS pressure sensor fabricated by the present invention overcomes the shortcomings of the above conventional techniques. SUMMARY OF THE INVENTION A primary object of the present invention is to provide an integrated single-wafer MEMS device that utilizes flip chip packaging and ion implantation techniques to achieve electromechanical isolation.

Another object of the present invention is to provide an integrated single-wafer MEMS pressure sensor with high reliability and low manufacturing cost.

To achieve the above objectives, the present invention provides an integrated single wafer MEMS pressure sensor having a flip chip bump or wafer level package (WLP) capability. The integrated single-wafer MEMS pressure sensor of the present invention is fabricated in conjunction with special application integrated circuit (ASIC) CMOS and MEMS and flip chip packaging techniques. From bottom to top, the structure of the integrated single-wafer MEMS pressure sensor of the present invention comprises a CMOS substrate, an N+ implant doped germanium layer, a field oxide (FOX) layer, and a plurality of CMOS wells. The implanted doped germanium region, a double junction polysilicon layer, a second undoped polysilicon layer, a plurality of implanted germanium source/drain electrodes, a gate polysilicon layer, and a hafnium oxide layer a plurality of metal layers, a nitride deposited layer, an under bump metal (UBM) layer, and a plurality of solder balls, wherein the double junction polysilicon layer further comprises an implanted doped germanium layer and an undoped germanium layer, The gate polysilicon layer is formed of polysilicon, thereby forming a plurality of CMOS transistor gates, which are embedded by interconnecting contact layers, which are interlaced with a plurality of contact hole layers, metal layers and staggered contacts. The number of hole layers can be adjusted according to the ASIC design, and the UBM layer and the solder balls form a flip chip layer. It is also worth noting that the N+ implanted doped germanium layer and the implanted doped/undimated doped combined polycrystalline germanium layer form a sealed vacuum chamber.

The above and other objects, features, aspects and advantages of the present invention will become apparent from

The embodiments of the present invention will be described in more detail below with reference to the drawings and the <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt;

2 shows an exemplary cross-sectional view of a MEMS device having a single wafer structure fabricated with MEMS pressure sensor functionality in accordance with the present invention. As shown in FIG. 2, the integrated single-wafer MEMS pressure sensor of the present invention is fabricated in combination with ASIC CMOS and MEMS and flip chip packaging techniques. From bottom to top, the structure of the integrated single-wafer MEMS pressure sensor of the present invention comprises a CMOS base layer 201, an N+ implant doped germanium layer 202, a field oxide germanium (FOX) layer 203, and a plurality of CMOS layers. The implanted doped germanium region 204, a two-tier polysilicon layer 205, a second undoped polysilicon layer 206, and a plurality of implant dopings forming a CMOS transistor source/drain a germanium region 207, a gate polysilicon layer 208, a hafnium oxide layer 217, a plurality of metal layers, a nitride deposited layer 218, a bump metal (UBM) layer 219, and a plurality of solder balls 220, wherein the double junction polysilicon layer 205 Further comprising an implanted germanium layer 205a and an undoped germanium layer 205b, the gate polysilicon layer 208 is formed of polysilicon, thereby forming a plurality of CMOS transistor gates, and the interconnect contact hole layer 209 is embedded in the germanium oxide layer. In the layer 217, the metal layers are interlaced with a plurality of contact hole layers, and the UBM layer 219 and the solder balls 220 form a flip chip layer. The exemplary embodiment shows a four metal and three contact hole layer, including a first metal layer 210, a first contact hole layer 211, a second metal layer 212, Two of the contact hole layer 213, third metal layer 214, the third contact hole 215 and a fourth layer of metal layer 216. It is also worth noting that the N+ implant doped germanium layer 202 and the second undoped polysilicon layer 206 form a sealed vacuum chamber 206a.

A plurality of preferred materials can be used for each layer. The following description is for illustrative purposes only and is not limiting. Relative materials can also be used in place of the materials illustrated. For example, the CMOS base layer 201 is a P-doped CMOS base layer. The field yttrium oxide (FOX) layer 203 may be made of yttria SiO ₂ , and a plurality of implanted germanium regions 207 form a CMOS transistor source/drain. The CMOS wells, the CMOS transistor source/drain electrodes, and the CMOS gates (ie, the gate polysilicon layer 208) form a plurality of CMOS transistors. The interconnect contact layer 209, the first contact hole layer 211, the second contact hole layer 213, and the third contact hole layer 215 are preferably made of, for example, Ti/TiN/CVD-W. The first metal layer 210, the second metal layer 212, the third metal layer 214, and the fourth metal layer 216 are made of CMOS metal, such as TiN/Cu/TiN or TiN/AlSi/TiN. It should be noted that the number of the metal layers and the interlaced contact hole layers can be adjusted according to the ASIC design, and the metal layers interlaced with the contact hole layers together form a scribe seal. The nitride deposited layer 218 may be made of, for example, tantalum nitride (Si ₃ N ₄ ). The UBM layer 219 is preferably Al/NiV/Cu, and the solder balls 220 may be made of, for example, tin (Sn).

3A through 3R show schematic views of an embodiment of a fabrication process for fabricating an integrated single wafer MEMS pressure sensor structure of the present invention. However, the processes and construction steps in Figures 3A through 3R are merely illustrative and not limiting. Integrated single wafer MEMS pressure sensors fabricated in other processes are also within the scope of the integrated single wafer MEMS pressure sensor architecture of the present invention.

FIG. 3A shows the wet 矽 etched CMOS substrate 201 in the MEMS region, which is the first step of the MEMS Deep Trench Oxide (DTO) process. The depth of the erbium etch defines the gap between the two capacitor plates of the MEMS capacitive pressure sensor device in accordance with the present invention. The depth of the etch is preferably about 1-3 um. The schematic of FIG. 3B shows that the photoresist pattern 201a is then used for selective N+ ion implantation doping to form an N+ implant doped germanium layer 202, and then forms an N+P junction to the P-base layer 201. The N+ implanted doped germanium layer 202 acts as the bottom plate electrode of the MEMS device. Figure 3B shows that the N+ implant doped germanium layer 202 is offset from the recessed germanium region 202a. The purpose of this deviation is to isolate the mechanical MEMS function and the electrical MEMS function so that the electrical function is optimized without being limited by the mechanical purpose of the MEMS device, the purpose of which will become more apparent in the following description. As shown in FIG. 3C, a low-pressure chemical vapor deposition (LPCVD) thick yttria deposition of about 1-3 um and a chemical mechanical polishing (CMP) process of yttrium oxide were performed to planarize the wafer surface. At the end of Figure 3C, the MEMS DTO process is also completed. The N+ ion can be arsenic or phosphorus, or a combination of the two.

In FIG. 3D, the wafer is subjected to a standard CMOS Shallow Trench Isolation (STI) process to form a field oxide germanium (FOX) layer 203 in the CMOS region. In the present invention, the MEMS DTO process described above forms deep trench yttrium oxide in the MEMS region, and the STI process forms shallow trench yttrium oxide isolation in the CMOS region. In FIG. 3E, a CMOS well photoresist pattern 203a with high energy ion implantation is performed. FIG. 3F shows that after removing the photoresist pattern 203a, an undoped germanium layer 205b is subsequently deposited to form a MEMS film, preferably having a thickness of 0.3-0.6 um, followed by selective ion implantation (planting The heteropolysilicon layer 205a) is doped to dope the film for electromechanical isolation. The implant doped polysilicon layer 205a and the undoped polysilicon layer 205b together form a double junction polysilicon layer 205. Figure 3G shows a schematic of the MEMS film immediately after etching with a photoresist pattern to remove the photoresist. In FIG. 3H, a CMOS high temperature well drive-in process, typically 1000-1100 ° C, for 3-4 hours, is performed to form a plurality of CMOS wells 204. Since the polysilicon film has been deposited on top of the DTO and the ion implanted impurities have been formed before the CMOS high temperature well is driven in, the high temperature of the CMOS well drive process will anneal the implanted doped polysilicon film. Since high temperature annealing also greatly reduces the mechanical stress of the polysilicon, the present invention uses a CMOS high temperature well drive process to obtain a low mechanical stress film. Low mechanical stress films are a better choice for MEMS applications. The same high temperature also anneals the implanted N+ ions in Figure 3B, whereby the doped germanium layer 202 is implanted with N+ as the bottom plate of the capacitor to form an N+ junction to the P-base layer. The DTO process therefore provides three key objectives: (a) defining the distance between the capacitor plates and the capacitance value, and (b) by placing the implant film on top of the yttrium oxide surface and driving the process anneal by CMOS high temperature wells to mitigate The mechanical stress of the film, and (c) the formation of a sealed chamber for film movement, will become more apparent in later description.

As shown in Figure 3F above, the ion implantation on the film is off the DTO region. The purpose of deviating from ion implantation is to reduce the parasitic capacitance of the capacitor plate. The undoped regions of the capacitor plates are non-conductive and have dielectric properties. The selective ion implantation doping adjusts the distance of the conductive regions of the top and bottom capacitor plates in the horizontal direction such that the parasitic capacitance value is minimized and the effective active capacitance value of the conductive plate is maximized. By using the appropriate layout of the implant layer to dope the electrodes of the MEMS capacitor plate, the parasitic coupling capacitance between the two electrodes can be greatly reduced to near zero, and the effective active moving film capacitance value becomes the dominant capacitance value of the entire MEMS capacitor. Therefore, as shown in FIG. 3H, by ion implantation of the film, the parasitic capacitance between the capacitor electrodes is reduced to a value close to zero after the mechanical purpose of holding the film at the edge is achieved. It is worth noting that N+ implanted doped polysilicon is used as an example of a thin film, however, P+ boron doped polysilicon can also be used when the mechanical properties of the polycrystalline germanium film are considered necessary or otherwise considered. As shown in FIG. 3I, the process then performs a polysilicon pattern and an etching step to form a plurality of ytterbium oxide release openings 205c in the film region. Then, a ruthenium oxide release resist pattern 205d and a ruthenium oxide release step are performed as shown in FIG. 3J. After the photoresist pattern 205d is removed, the wafer is then deposited by isotropic conformal LPCVD undoped polysilicon to form an undoped polysilicon layer. Due to the isotropic nature of the deposition, the bottom and sidewalls of the cavity are filled with undoped LPCVD polysilicon (second undoped polysilicon layer 206) until the hole through which the polysilicon is passed is completely filled and sealed, as shown in the figure. Shown in 3K. When the hole diameter D is equal to twice the deposited polysilicon thickness T, D = 2T, the openings are sealed. 3L shows a schematic diagram of a structure in which a second undoped polysilicon layer 206 on a CMOS region is patterned and etched away. The parasitic capacitance between the two capacitor plates forming the capacitive pressure sensor is greatly deviated from the implanted area in the bottom plate (N+ implanted doped layer 202) and the top plate (double junction polysilicon layer 205). reduce. The overlap region of the N+ implanted doped germanium layer 202 and the doped polysilicon layer 205a in the double junction polysilicon layer is an effective active capacitor plate. Since the overlap region in the mechanical anchor region is undoped and thus non-conductive, the parasitic capacitance value is minimized. The process continues to pattern and etch away residual yttrium oxide on the surface of the CMOS region. A high quality gate yttrium oxide is then thermally grown and then deposited using polysilicon to form a gate polysilicon layer 208. The gate polysilicon layer 208 is then patterned and etched to form a plurality of CMOS transistor gates, followed by the transistor source/drain electrodes implanted and annealed to form a plurality of CMOS transistors, as shown in FIG. 3M. The CMOS transistor source/drain annealing process also anneals the second undoped polysilicon layer 206, which reduces mechanical stress. The resulting wafer is then deposited with CMOS Inter-Level-Oxide (ILD), and the planarized CMOS ILD is shown in Figure 3N. Contact hole layer 209 and first metal layer 210 are then formed.

30 shows that the top plate doped polysilicon (planted doped polysilicon layer 205a) electrode and the bottom plate N+ electrode (N+ implanted doped layer 202) are in contact with the first metal layer 210 via the interconnect contact layer 209. In FIG. 3P, the wafer is then subjected to a CMOS interconnect process. The first contact hole layer 211, the second contact hole layer 213 and the third contact hole layer 215, and the second metal layer 212 are included in the CMOS multi-level-Oxide (MLD) between the metal layers. To the fourth metal layer 216. The difference capacitance between the two capacitor plates (N+ implanted doped germanium layer 202 and implanted doped polysilicon layer 205a) is connected through the first metal layer 210 to the fourth metal layer 216 through the interleaved contact hole layer. Feed into the ASIC input. When the external pressure increases, the gap between the capacitor electrodes becomes small, and thus the capacitance value increases. The increased capacitance value change will be amplified by the ASIC circuit on the wafer, so the pressure change is converted into an electrical signal and further signal processed to display absolute pressure or altitude above sea level, which is the function of a typical pressure sensor. And purpose. At the end of this step, a plurality of metal layers and a plurality of contact hole layers are embedded inside the yttrium oxide layer 217.

In FIG. 3Q, a large area of yttrium oxide is patterned and etched in the MEMS region, and the etching stops at the second undoped polysilicon layer 206. At this stage, in order to be compatible with the CMOS process, the layer of yttrium oxide may be selectively deposited before the protective overcoat (PO) tantalum nitride deposition. In FIG. 3R, a PO tantalum nitride layer 218 is subsequently deposited, followed by a flip chip bump process for the under bump metal (UBM) layer 219 and the solder ball 220, which is a complete wafer level package (WLP) capability. CMOS circuit. At this point, an integrated single-chip MEMS capacitive pressure sensor with flip-chip bumps and WLP capability utilizes selective ion implantation doping technology to achieve electromechanical isolation in MEMS devices and deep trench yttrium oxide DTO in CMOS processes (Deep Trench Oxide) technology is thus formed and completed.

4 shows a flow chart of an exemplary process for making an integrated single wafer MEMS pressure sensor of the present invention. As shown in FIG. 4, step 401 performs a MEMS deep trench germanium oxide (DTO) process on the MEMS substrate, further comprising: a germanium recess wet etching; a photoresist pattern for selective N+ ion implantation, thereby forming a pair of P- The junction of the base layer forms the bottom plate electrode and the electromechanical isolation; and the LPCVD yttrium oxide deposition fills the MEMS defect region and the oxide chemical mechanical polishing (CMP) planarizes the wafer surface. Step 402 is performed by a Shallow Trench Isolation (STI) process to form field yttrium oxide. Step 403 forms a CMOS well high energy ion implant. Step 404 performs polycrystalline germanium deposition, thin film pattern etching, and thin film ion implantation for the MEMS film, thereby doping the film for electrical connection and electromechanical isolation. Step 405 is to perform high temperature driving of the CMOS well to form a deep well. It is worth noting that the high temperature will also anneal the implanted doped polysilicon film to reduce mechanical stress; therefore, a low mechanical stress film can be obtained. Step 406 is performed by performing a polysilicon pattern and etching and performing cerium oxide release. Step 407 and the like are deposited onto the conformal LPCVD undoped polysilicon. Step 408 is to perform CMOS ILD planarization. Step 409 is to perform a CMOS contact hole and a first metal process. Step 410 is to form an interconnect layer of the remaining metal layers and the staggered contact hole layers, such as the second metal layer, the third metal layer, the fourth metal layer, and the contact hole layer of FIG. Step 411 is to perform large area ILD and MLD yttrium yttrium development and etching on the top of the MEMS region. Step 412 is a CMOS protective outer layer (PO) process for tantalum nitride deposition with multiple micropits. Step 413 is a CMOS back-end bump process to form the final structure of the integrated single-wafer MEMS pressure sensor.

The above is only a preferred embodiment for explaining the present invention, and is not intended to limit the present invention in any way, and any modifications or alterations to the present invention made in the spirit of the same invention. All should still be included in the scope of the intention of the present invention.

101. . . Printed circuit board (PCB)

102. . . Connection pad

103. . . CMOS circuit

104. . . Epoxy resin

105. . . MEMS circuit

105a. . . Glass/矽 circuit

105b. . . film

106. . . Side wall

107. . . Line mat

108. . . Upper cover

109. . . Air circulation hole

201. . . CMOS base layer

201a. . . Resistive pattern

202. . . N+ implanted doped layer

202a. . . Sag area

203. . . Field yttrium oxide (FOX) layer

203a. . . Resistive pattern

204. . . Buried doped germanium (CMOS well)

205. . . Double junction polycrystalline layer

205a. . . Buried doped (polycrystalline) layer

205b. . . Undoped (polycrystalline) germanium layer

205c. . . Opening

205d. . . Resistive pattern

206. . . Second undoped polysilicon layer

206a. . . Sealed vacuum chamber

207. . . Planting doped area

208. . . Gate polysilicon layer

209. . . Interconnect contact layer

210. . . First metal layer

211. . . First contact hole layer

212. . . Second metal layer

213. . . Second contact hole layer

214. . . Third metal layer

215. . . Third contact hole layer

216. . . Fourth metal layer

217. . . Cerium oxide layer

218. . . Nitride deposit layer (tantalum nitride layer)

219. . . Lower convex metal (UBM) layer

220. . . Solder balls

401~413. . . step

The present invention can be understood in more detail by reading the above detailed description, in conjunction with the examples and the referenced drawings, wherein:

Figure 1 shows a schematic view of a conventional structure of a MEMS pressure sensor having a dual wafer structure;

2 shows a cross-sectional view of a MEMS capacitive pressure sensor with a single wafer in accordance with the present invention;

3A through 3R are diagrams showing an exemplary embodiment of a fabrication process for fabricating an integrated single wafer MEMS pressure sensor structure of the present invention;

4 shows a flow chart of an exemplary process for making an integrated single wafer MEMS pressure sensor of the present invention.

201. . . CMOS base layer

202. . . N+ implanted doped layer

203. . . Field yttrium oxide (FOX) layer

204. . . Planting doped area

205. . . Double junction polycrystalline layer

205a. . . Implanted doped layer

205b. . . Undoped layer

206. . . Second undoped polysilicon layer

206a. . . Sealed vacuum chamber

207. . . Planting doped area

208. . . Gate polysilicon layer

209. . . Interconnect contact layer

210. . . First metal layer

211. . . First contact hole layer

212. . . Second metal layer

213. . . Second contact hole layer

214. . . Third metal layer

215. . . Third contact hole layer

216. . . Fourth metal layer

217. . . Cerium oxide layer

218. . . Nitride deposit

219. . . Lower convex metal (UBM) layer

220. . . Solder balls

Claims (13)

A micro electro mechanical system (MEMS) pressure sensor with electromechanical isolation function includes: a complementary metal oxide semiconductor (CMOS) base layer; an N+ implant doped germanium layer from bottom to top; a layer of field oxide (FOX) layer; a plurality of implanted germanium regions forming a plurality of CMOS wells; and a second ion implanted doped germanium layer to form a CMOS source/drain; The double junction polysilicon layer further comprises an implanted doped germanium layer and an undoped germanium layer; a implanted doped/undimated doped combined polycrystalline germanium layer, the N+ implanted doped germanium layer is used to form a Sealing the vacuum chamber; a gate polysilicon layer is formed by using polysilicon to form a plurality of CMOS transistor gates, and the CMOS wells, the CMOS transistor source/drain electrodes, and the CMOS gates are formed in plurality a CMOS transistor; a ruthenium oxide layer embedded in an interconnect contact layer, a plurality of metal layers interleaved with a plurality of contact hole layers, the interconnect contact layer providing contact to the CMOS transistors; a nitride Deposited layer; a convex metal (UBM) layer; and a plurality of tin a ball, the UBM layer and the solder balls form a flip chip layer, wherein the CMOS substrate has a recessed germanium layer, and the N+ implant doped germanium layer serves as a bottom plate of a capacitor, and the implant The doped/unlaid doped combined polysilicon layer is used as a top plate for the capacitor. A microelectromechanical pressure sensor having an electromechanical isolation function according to claim 1, wherein the number of the metal layers and the number of staggered contact hole layers are adjustable. A microelectromechanical pressure sensor having an electromechanical isolation function according to claim 1, wherein the sealed vacuum chamber forms a gap for the capacitor plates and determines a capacitance value of the capacitor. A microelectromechanical pressure sensor having an electromechanical isolation function according to claim 3, wherein a depth of the recessed region on the CMOS substrate determines a gap of the sealed vacuum chamber. A microelectromechanical pressure sensor having an electromechanical isolation function according to claim 1, wherein the capacitor plates comprise ion implantation for electrical conductivity. The microelectromechanical pressure sensor with electromechanical isolation function according to claim 1, wherein the implanted doped/unplanted doped polycrystalline germanium layer is a combined polycrystalline germanium layer, including a implanted doped layer And an unimplanted doped layer is formed by selective ion implantation for electrical functions. According to the microelectromechanical pressure sensor with electromechanical isolation function according to claim 1, the isolated N+P junction is formed by selective ion implantation on the depressed region of the CMOS substrate. According to the microelectromechanical pressure sensor with electromechanical isolation function according to claim 1, wherein the yttrium oxide region on the top of the MEMS is etched, thereby lowering the thickness of the MEMS film and increasing the sensitivity. A microelectromechanical pressure sensor having an electromechanical isolation function according to claim 1, wherein the electromechanical isolation of the MEMS pressure sensor is achieved by a plurality of MEMS layers with selective ion implantation. A fabrication process for forming a microelectromechanical pressure sensor having an electromechanical isolation function includes the steps of: performing a MEMS deep trench oxide (DTO) process on a MEMS substrate; performing a CMOS Shallow trench isolation (STI) process to form field yttrium oxide; high energy ion implantation to form CMOS wells; polycrystalline germanium deposition for MEMS films, thin film pattern etching and thin film ion implantation for doping Thin film for electrical connection and electromechanical isolation; high temperature drive in CMOS well to form deep well; polycrystalline germanium film pattern and etching and yttrium oxide release; isotropic conformal LPCVD undoped polysilicon deposition; CMOS inner layer Inter-level-Oxide (ILD) planarization; CMOS contact and first metal process; formation of interconnect layers of a plurality of residual metal layers and a plurality of staggered contact holes; performing large-area ILD at the top of the MEMS region MLD yttrium oxide development and etching for a CMOS protective overcoat (PO) process for tantalum nitride deposition with multiple micropits; and performing a CMOS The back bump process forms the final structure of the integrated single wafer MEMS pressure sensor. According to the manufacturing process described in claim 10, wherein the DTO process further comprises the steps of: performing a germanium depression etching; a photoresist pattern for selective N+ ion implantation, thereby forming a junction with a P-type base layer, It is used for the bottom plate electrode and electromechanical isolation; and LPCVD yttrium oxide deposition fills the MEMS 矽 recessed area and chemical mechanical polishing (CMP) to planarize the wafer surface. According to the manufacturing process described in claim 10, a Flip Chip Bumping package and a Wafer Level Package (WLP) are employed. According to the manufacturing process described in claim 10, the CMOS well high temperature drive also anneals the implanted doped polysilicon film to obtain a low mechanical stress film.