TW201333610A - Display device and drive method for same - Google Patents

Abstract

Provided is a display device that can improve viewing angle characteristics while increasing display quality over the conventional. A pixel forming unit (10) includes first and second sub-pixel forming units (11, 12). The first sub-pixel forming unit (11) includes a first thin-film transistor (T1), a first pixel electrode (Epix1), a first liquid crystal capacitor (Clc1), a first auxiliary capacitor (CcsA), and a second auxiliary capacitor (CcsB), where CcsA > CcsB. One end of each of the first and second auxiliary capacitors (CcsA, CcsB) is connected to the first pixel electrode (Epix1). The connection destination of other end of each of the first and second auxiliary capacitors (CcsA, CcsB) is a first CS line (CSL1) or a second CS line (CSL2). The other end connection destination to the first and second auxiliary capacitors (CcsA, CcsB) changes alternately for each column. The second sub-pixel forming part (12) includes a second thin-film transistor (T2), a second pixel electrode (Epix2), and a second liquid crystal capacitor (Clc2).

Description

Display device and driving method thereof

The present invention relates to a display device, and more particularly to a display device and a driving method thereof for dividing a pixel into a plurality of sub-pixels to improve viewing angle characteristics.

Conventionally, improvement in viewing angle characteristics has been demanded in liquid crystal display devices such as VA (Vertical Alignment) mode. As a problem of the viewing angle characteristics, for example, a gamma characteristic at the time of front observation and a gamma characteristic at the time of oblique observation may be different. Therefore, as a liquid crystal display device for improving the viewing angle correlation of such gamma characteristics, a liquid crystal display device in which one pixel is divided into a plurality of (typically two) sub-pixels has been proposed. This configuration is generally referred to as "multi-pixel structure". In the multi-pixel structure, by applying different voltages to the liquid crystal layer between the two sub-pixels (that is, setting relatively bright bright pixels and relatively dark dark pixels), mixing different gamma characteristics for observation Therefore, the viewing angle correlation of the gamma characteristic is improved.

FIG. 27 is an equivalent circuit diagram showing a configuration of a pixel formation portion of a multi-pixel structure disclosed in Patent Document 1. As shown in FIG. 27, the pixel formation portion 20(i, j) arranged corresponding to the intersection of the source line SLj and the gate line GLi includes the first sub-pixel formation portion 21 (i, j) and the second sub-pixel. The portion 22 (i, j) is formed. Two CS (series capacitor) lines CSL1 and CSL2 are provided along the gate line GLi. The pixel electrode Epix1 of the first pixel formation portion 21 (i, j) is connected to the source line SLj via the thin film transistor T1, and is connected via the capacitor Ccs1. On the CS line CSL1. A liquid crystal capacitor Clc1 is formed between the pixel electrode Epix1 and the common electrode COM. The pixel electrode Epix2 of the second pixel formation portion 22 (i, j) is connected to the source line SLj via the thin film transistor T2, and is connected to the CS line CSL2 via the capacitor Ccs2. A liquid crystal capacitor Clc2 is formed between the pixel electrode Epix2 and the common electrode COM. The CS lines CSL1 and CSL2 are opposite to each other and are driven at a fixed period. Therefore, the potentials of the pixel electrodes Epix1 and Epix2 (more specifically, their effective values) are different from each other. Thereby, the voltage applied to the liquid crystal layer can be made different from each other in the first sub-pixel formation portion 21 (i, j) and the second sub-pixel formation portion 22 (i, j). In the multi-pixel structure, one of the pixel electrodes Epix1 and Epix2 is boosted, and the other is stepped down. In the following description, the case where the pixel electrode is boosted or stepped down is referred to as "the boosting or stepping down of the sub-pixel forming portion". In the present specification, the term "boosting" means that the potential is increased based on the common potential Vcom which is the potential of the common electrode COM when the display of the positive polarity is performed, and is common to the display of the negative polarity. The potential Vcom is used as a reference to lower the potential. In the same manner, the "buck-down" means that the potential is lowered by the common potential Vcom when the display of the positive polarity is performed, and the potential is raised with the common potential Vcom as a reference when the display of the negative polarity is performed.

[Previous Technical Literature] [Patent Literature]

[Patent Document 1] Japanese Patent Laid-Open Publication No. 2009-244884

[Patent Document 2] Japanese Patent Laid-Open Publication No. 2009-80197

In the multi-pixel structure disclosed in Patent Document 1, it is considered to perform polarity inversion driving other than line inversion driving (polarity inversion driving in column units). For example, in order to perform dot inversion driving (polarity inversion driving in units of one pixel), it is necessary to connect the first sub-pixel forming portion 21 (i, j) and the second sub-pixel forming portion 22 (i, j). The CS line is replaced every 1 pixel by the polarity in the column direction (in the present specification, the direction in which the gate line extends). In the above configuration, in a certain frame, the pixel forming portion 20 (i, j) corresponds to the positive polarity, and the pixel forming portion 20 (i, j+1) adjacent in the column direction corresponds to the negative polarity. In this case, the first pixel formation unit 21 (i, j) is boosted, and the first sub-pixel formation unit 21 (i, j+1) is stepped down. Further, the second sub-pixel forming unit 22 (i, j) is stepped down, and the second sub-pixel forming unit 22 (i, j+1) is boosted. In other words, the first sub-pixel forming units 21 (i, j) and 21 (i, j+1) correspond to bright pixels and dark pixels, respectively, and second sub-pixel forming portions 22 (i, j) and 22 (i, j). +1) correspond to dark pixels and bright pixels, respectively. As a result, the bright pixels and the dark pixels are alternately arranged side by side in the column direction and the row direction (in the present specification, the direction in which the source lines extend) (that is, the bright pixels and the dark pixels are arranged in a so-called zigzag shape), and thus the display quality is lowered. . Moreover, in order to maintain a high aperture ratio in the arrangement of such bright pixels and dark pixels, it is necessary to fix the area ratio of bright pixels to dark pixels to 1:1. Therefore, it is difficult to adopt an area ratio of bright pixels to dark pixels such as to obtain better display quality.

Accordingly, it is an object of the present invention to provide a display device having improved display quality higher than that of the prior art and improved driving angle characteristics and a driving method thereof.

A first aspect of the present invention is a display device characterized in that it is an active matrix type display device, and includes a plurality of image signal lines and a plurality of scanning signal lines crossing the plurality of image signal lines, corresponding to a plurality of pixels arranged in a matrix in a plurality of the image signal lines and the plurality of scanning signal lines, and a common electrode disposed in the plurality of pixel forming portions in common, and at least in a direction in which the scanning signal lines extend The polarity of the potential is different for each of the first specific number of image signal lines to perform polarity inversion driving, and the display device further includes: a first auxiliary capacitance line and a second auxiliary capacitance line corresponding to each of the scanning signal lines In the mode, the potentials are different from each other, and the potential changes at least after the selection period of the scanning signal line is completed. Each of the pixel forming portions includes a first pixel electrode and a second pixel electrode, which are respectively provided corresponding to the image to be displayed. a first display capacitor formed between the first pixel electrode and the common electrode; and a second display capacitor; The first switching element is connected to the scanning signal line at the control terminal, the video signal line is connected to the first conductive terminal, and the first pixel electrode is connected to the second conductive terminal. a second switching element, wherein the scanning signal line is connected to the control terminal, the image signal line is connected to the first conduction terminal, and the second pixel electrode is connected to the second conduction terminal; a first auxiliary capacitor formed between one of the first auxiliary capacitance line and the second auxiliary capacitance line and the first pixel electrode; and a second auxiliary capacitor formed on the first auxiliary capacitance line And the first auxiliary capacitance line between the other of the second auxiliary capacitance lines and the first pixel electrode and having a capacitance value smaller than the first auxiliary capacitance; and the first auxiliary capacitance line to be connected to the first auxiliary capacitance The other one of the first auxiliary capacitance line and the other of the first auxiliary capacitance line and the second auxiliary capacitance line to be connected to the second auxiliary capacitance line are in a direction in which the scanning signal line extends The pixel formation portion is replaced by the first specific number of the first specific number.

According to a second aspect of the invention, the first aspect of the invention is characterized in that the first specific number is one.

According to a second aspect of the present invention, in the second aspect of the present invention, the potential of the first auxiliary capacitance line is performed in a pixel formation portion including a first auxiliary capacitance connected to the first auxiliary capacitance line. In the case of the positive polarity display, the selection period of the scanning signal line corresponding to the pixel formation portion is changed to the direction of the rise, and when the negative polarity display is performed, the selection period of the scanning signal line corresponding to the pixel formation portion is completed. The potential of the second auxiliary capacitance line is changed to a scanning signal corresponding to the pixel forming portion when the pixel forming portion including the first auxiliary capacitor connected to the second auxiliary capacitance line performs positive polarity display. When the selection period of the line is changed, the direction of the change is changed, and when the negative polarity display is performed, the selection period of the scanning signal line corresponding to the pixel formation portion is changed and then changes in the direction of the downward direction.

A fourth aspect of the invention is the third aspect of the invention, characterized in that: The potential of the first auxiliary capacitance line and the second auxiliary capacitance line is changed in a selection period in which the second specific number of the scanning signal lines are in a selected state for each of the second specific numbers.

According to a fourth aspect of the present invention, in the fourth aspect of the present invention, the first auxiliary capacitance line and the second auxiliary capacitance line to be connected to the first auxiliary capacitor are one of The other one of the first auxiliary capacitance line and the second auxiliary capacitance line to be connected to the second auxiliary capacitor is the pixel of the second specific number in the direction in which the video signal line extends. Formed and replaced.

According to a sixth aspect of the present invention, in a fourth aspect or a fifth aspect of the present invention, the pixel forming portion of the plurality of pixel forming portions adjacent to the direction in which the image signal line extends is characterized by The first switching element of the first switching element and the second switching element, and the first switching element of the other pixel forming portion of the plurality of pixel forming portions and the first conductive terminal of the second switching element They are respectively connected to one of the two adjacent image signal lines adjacent to each other and the other.

A seventh aspect of the present invention is the fourth aspect or the fifth aspect of the present invention, characterized in that the second specific number is 1.

The eighth aspect of the present invention is the fourth aspect or the fifth aspect of the present invention, characterized in that the second specific number is a plural number.

The ninth aspect of the invention is the first aspect of the invention, characterized in that: Each of the pixel formation portions further includes a third storage capacitor formed between the other of the first storage capacitor line and the second storage capacitor line and the second pixel electrode, and a fourth auxiliary capacitor. The method is formed between the first auxiliary capacitance line and the second auxiliary capacitance line and the second pixel electrode, and the capacitance value is smaller than the third auxiliary capacitance.

According to a tenth aspect of the present invention, in the first aspect of the invention, the pixel forming portion further includes: a third auxiliary capacitor formed on the first auxiliary capacitance line and the second auxiliary capacitance line And the fourth auxiliary capacitor is formed between the other of the first auxiliary capacitance line and the second auxiliary capacitance line and the second pixel electrode; And the capacitance value is smaller than the third auxiliary capacitor.

According to a first aspect of the present invention, in a first aspect of the invention, the invention further includes: an auxiliary capacitance line driving circuit that independently drives the pixel forming portion arranged in a direction along which the image signal line extends 1 auxiliary capacitor line and second auxiliary capacitor line.

According to a twelfth aspect of the present invention, in a first aspect of the present invention, the third auxiliary capacitance line is provided in a manner corresponding to each of the scanning signal lines, and is given a fixed potential, and each pixel The forming portion further includes an adjustment capacitor, and the adjustment capacitor is formed on the capacitor The capacitance between the third auxiliary capacitance line and the second pixel electrode is such that the potential of the first pixel electrode and the second pixel electrode when the selection period of the scanning signal line corresponding to the pixel formation portion ends The changes are set in such a way that they are roughly equal.

According to a thirteenth aspect of the present invention, in the first aspect of the present invention, the pixel forming portion further includes: a first adjustment capacitor formed between the scanning signal line and the first pixel electrode And a second adjustment capacitor formed between the scanning signal line and the second pixel electrode; and a capacitance value of each of the first adjustment capacitor and the second adjustment capacitor is configured to be The potential change of the first pixel electrode and the second pixel electrode at the end of the selection period of the scanning signal line corresponding to the pixel formation portion is set to be substantially equal to each other.

According to a fourth aspect of the present invention, in the first aspect of the present invention, the first conductive terminal of the second switching element or the first conductive terminal of the first switching element is respectively connected to the first switch The element or the second switching element is connected to the video signal line.

According to a fifteenth aspect of the invention, the first aspect of the invention, wherein the first switching element and the second switching element are each an oxide semiconductor Or a microcrystalline germanium to form a thin film transistor having a channel layer.

A sixteenth aspect of the present invention is a driving method of a display device, characterized in that it is a driving method of an active matrix type display device, the display device comprising a plurality of image signal lines crossing the plurality of image signal lines a plurality of scanning signal lines, a plurality of pixels arranged in a matrix corresponding to the plurality of image signal lines and the plurality of scanning signal lines, and a common electrode disposed in common to the plurality of pixel forming portions, and at least In the direction in which the scanning signal line extends, polarity inversion driving is performed for each of the first specific number of image signal lines to make the polarity of the potential different, and the driving method includes: a potential control step, which is paired to correspond to each scanning signal line The first auxiliary capacitance line and the second auxiliary capacitance line provided in the manner are different from each other, and the potential to be applied is changed at least after the selection period of the scanning signal line is completed; and each pixel forming portion includes: the first pixel The electrode and the second pixel electrode are respectively given potentials corresponding to the image to be displayed; the first display capacitor is a second display capacitor is formed between the second pixel electrode and the common electrode; and a first switching element is connected to the scan signal line at the control terminal. Connecting the image signal line to the first conductive terminal, connecting the first pixel electrode to the second conductive terminal, and connecting the scanning signal line to the control terminal by the second switching element. Connecting the video signal line to the first conductive terminal, and connecting the second pixel electrode to the second conductive terminal; the first auxiliary capacitor is formed on one of the first auxiliary capacitance line and the second auxiliary capacitance line And a second auxiliary capacitor formed between the other of the first auxiliary capacitance line and the second auxiliary capacitance line and the first pixel electrode, and the capacitance value is smaller than the first And a storage capacitor; and the first auxiliary capacitor line and the second auxiliary capacitor line to which the first auxiliary capacitor is to be connected, and the first auxiliary capacitor to be connected to the second auxiliary capacitor The other of the line and the second auxiliary capacitance line is exchanged for each of the first specific number of pixel formation portions in the direction in which the scanning signal line extends.

According to a seventeenth aspect of the invention, the first aspect of the invention is characterized in that the first specific number is one.

According to a seventeenth aspect of the present invention, in the potential control step, the potential applied to the first auxiliary capacitance line is controlled in such a manner as to be connected to the first When the pixel formation portion of the first storage capacitor of the storage capacitor line performs positive polarity display, the selection period of the scanning signal line corresponding to the pixel formation portion changes in the direction of rising, and when the negative polarity display is performed, When the selection period of the scanning signal line corresponding to the pixel formation portion ends, the direction of the change is changed, and The potential applied to the second storage capacitor line is controlled such that a scan signal corresponding to the pixel formation portion is performed when the pixel formation portion including the first storage capacitor connected to the second storage capacitor line performs positive polarity display When the selection period of the line is changed, the direction of the change is changed, and when the negative polarity display is performed, the selection period of the scanning signal line corresponding to the pixel formation portion is changed and then changes in the direction of the downward direction.

According to a ninth aspect of the present invention, in the potential control step, the potential of the first auxiliary capacitance line and the second auxiliary capacitance line are controlled as follows: The scanning signal lines of the two specific numbers are changed in the selection period of each of the second specific numbers in the selected state.

According to the first aspect or the sixteenth aspect of the present invention, in the display device using the multi-pixel structure, the first auxiliary capacitor is provided in the first pixel electrode and the second capacitance is smaller than the first auxiliary capacitor. Auxiliary capacitor. A storage capacitor line (a first auxiliary capacitance line or a second auxiliary capacitance line) that is different from each other is connected to the first auxiliary capacitor and the second auxiliary capacitor, and a storage capacitor line to which the first storage capacitor and the second storage capacitor are connected is arranged in a column The direction (the direction in which the scanning signal line extends) is exchanged every pixel formation portion of the first specific number. Further, the polarity of the potential is different for each of the first specific number of video signal lines in the direction in which the scanning signal line extends, and the electric power of the first auxiliary capacitance line and the second auxiliary capacitance line is located at the end of the selection period of each scanning signal line. Variety. Here, for example, a case is considered in which a storage capacitor that is a connection target of the first storage capacitor is used. When the selection period of the scanning signal line corresponding to the pixel formation portion for performing the positive polarity display is completed, the line is changed in the rising direction, and the selection period of the scanning signal line corresponding to the pixel formation portion for performing the negative polarity display is completed. The direction of the decline changes. In either case, in each of the positive polarity display and the negative polarity display, bright pixels are realized in accordance with the potential of the first pixel electrode in each of the pixel formation portions, and dark is realized in accordance with the potential of the second pixel electrode. Pixel. Thereby, the bright pixel and the dark pixel are arranged side by side in the column direction. The area ratio of the bright pixel to the dark pixel can be arbitrarily set by arranging the bright pixel and the dark pixel in parallel in the column direction. Therefore, for example, in order to prevent the low gray scale pixel from being brighter than the actual darkness, the area of the second pixel electrode can be set larger than the area of the first pixel electrode. According to the above, according to the first aspect of the present invention, the display quality can be made higher than before, and the viewing angle characteristics can be improved. Further, since the display polarity (the polarity of the potential of the first pixel electrode and the second pixel electrode of the pixel formation portion) is different for at least the pixel formation portion of the first specific number in the column direction, at least the row unit of the first specific number is performed. The line reverse drive (inverse drive in row units).

According to the second aspect or the seventeenth aspect of the invention, the row inversion driving of at least one line unit can be performed.

According to the third aspect or the eighteenth aspect of the present invention, the electric power of the auxiliary capacitance line (the first auxiliary capacitance line or the second auxiliary capacitance line) to be connected to the first auxiliary capacitor is formed in the pixel for performing positive polarity display. When the selection period of the scanning signal line corresponding to the portion is changed, the direction of the change is changed, and the selection period of the scanning signal line corresponding to the pixel formation portion for performing the negative polarity display changes in the direction of the falling direction. Thereby, the second aspect or the first aspect of the present invention can be obtained 17 the same effect.

According to the fourth aspect or the ninth aspect of the present invention, for example, the display polarity can be made different for each pixel formation portion in the row direction (the direction in which the image signal line extends).

According to the fifth aspect of the present invention, in the configuration in which the auxiliary capacitance line to which the first auxiliary capacitor and the second auxiliary capacitor are connected is replaced by the second specific number of pixel formation portions in the row direction, The fourth aspect of the invention has the same effect.

According to a sixth aspect of the present invention, the video signal line of the connection target of the pixel formation portion arranged in the row direction is one of the two video signal lines adjacent to each other and the other one The same effect as the fourth aspect of the present invention or the fifth aspect of the present invention can be obtained.

According to the seventh aspect of the present invention, for example, by changing the polarity of the potential of the image signal line for each selection period, or fixing the polarity of the potential of the image signal line in each frame, it is possible to make every pixel in the row direction. The display portion has different display polarities.

According to the eighth aspect of the present invention, for example, by changing the polarity of the potential of the video signal line for each selection period, the display polarity can be made different for each pixel forming portion in the row direction.

According to the ninth aspect of the present invention, the potential difference between the potential of the first pixel electrode and the potential of the second pixel electrode is larger than the first aspect of the present invention. Therefore, the luminance corresponding to the potential of the first pixel electrode is larger than the luminance of the luminance corresponding to the potential of the second pixel electrode, so that the blackout defect can be further suppressed.

According to the tenth aspect of the present invention, the potential of the second pixel electrode and the first pixel The potential of the electrode changes in the same direction, and the potential change of the second pixel electrode is smaller than the potential change of the first pixel electrode. Therefore, in each pixel formation portion, a bright pixel is realized in accordance with the potential of the first pixel electrode, and a dark pixel is realized in accordance with the potential of the second pixel electrode, and the driving amplitude of the video signal line is reduced. Thereby, it is possible to reduce power consumption.

According to the eleventh aspect of the present invention, the first auxiliary capacitance line and the second auxiliary capacitance line are independently driven by the pixel formation portion arranged in the row direction by the auxiliary capacitance line drive circuit, and thus the pixel formation portion is formed in each pixel formation portion. During the period from the end of the selection period of the scanning signal line to the start of the selection period of the next frame, the potential of each of the first auxiliary capacitance line and the second auxiliary capacitance line is fixed. Therefore, in the positive polarity display, the potential of the first pixel electrode is higher than that of the first aspect of the present invention, and when the negative polarity is displayed, the potential of the first pixel electrode is lower than that of the first aspect of the present invention. Thereby, the luminance difference corresponding to the potential of the first pixel electrode and the luminance corresponding to the potential of the second pixel electrode can be made larger, so that the anti-black defect can be further suppressed.

According to the twelfth aspect of the present invention, by providing the adjustment capacitor, the deviation between the potential fluctuations of the first pixel electrode and the second pixel electrode at the end of the selection period of the scanning signal line is suppressed.

According to the thirteenth aspect of the present invention, by providing the first adjustment capacitor and the second adjustment capacitor, variations in potential fluctuations between the first pixel electrode and the second pixel electrode at the end of the selection period of the scanning signal line are suppressed.

According to the fourteenth aspect of the invention, the parasitic capacitance formed between the image signal line and the scanning signal line is relatively small. Therefore, the capacitance of the image signal line is reduced, so that power consumption can be reduced.

According to a fifteenth aspect of the invention, the first switching element and the second switching element are each a thin film transistor, and a channel layer thereof is formed of an oxide semiconductor or a microcrystalline germanium. Since the mobility of the oxide semiconductor and the microcrystalline germanium is higher than that of the amorphous germanium or the like, the size of the first switching element and the second switching element can be reduced. Therefore, it is possible to improve the aperture ratio of the pixel formation portion and the reduction of the load on the bus line (the video signal line and the scanning signal line).

Hereinafter, the first to ninth embodiments of the present invention will be described with reference to the accompanying drawings. In the present specification, m and n are integers of 2 or more, i is an integer of 1 or more and m or less, and j is an integer of 1 or more and n or less. Further, the number based on the column direction corresponds to the first specific number, and the number based on the row direction corresponds to the second specific number.

<1. First embodiment> <1.1 Overall configuration and operation summary>

1 is a block diagram showing an overall configuration of an active matrix display device according to a first embodiment of the present invention. As shown in FIG. 1, the liquid crystal display device of the present embodiment includes a display unit 100, a display control circuit 200, a source driver 300 as an image signal line driver circuit, and a gate driver 400 as a scanning signal line driver circuit. In the display unit 100, a plurality of (n) are formed as the source lines SL1 to SLn of the video signal lines (hereinafter, the symbol SL is used when the distinction is not made), and a plurality of (m) are used as the scanning signals. The gate lines GL1 to GLm of the line (hereinafter, indicated by the symbol GL when they are not distinguished), and corresponding to the n source lines SL1 to SLn and the m gate lines GL1 to GLm, respectively. Multiple (m × n) images set at the intersection Forming a part. Further, along the gate lines GL, a first CS line CSL1 as a first auxiliary capacitance line and a second CS line CSL2 as a second auxiliary capacitance line are provided. Hereinafter, the first CS line CSL1 and the second CS line CSL2 along the gate line GLi are referred to as "the first CS line CSL1 of the i-th column" and "the second CS line CSL2 of the i-th column", respectively. Each of the first CS lines CSL1 is connected to the first CS bus line CB1, and each of the second CS lines CSL2 is connected to the second CS bus line CB2. A detailed description relating to the configuration of the pixel forming portion will be described below.

The display control circuit 200 receives the image data DAT sent from the outside and the timing signal group TG such as the horizontal synchronization signal or the vertical synchronization signal, and outputs the digital image signal DV to control the source start pulse of the image display of the display unit 100. The signal SSP, the source clock signal SCK, the latch strobe signal LS, the gate start pulse signal GSP, and the gate clock signal GCK. Further, in the present embodiment, the potential control step is executed by the display control circuit 200. In other words, the display control circuit 200 supplies the first auxiliary capacitance signal and the second auxiliary capacitance signal to the first CS bus line CB1 and the second CS bus line CB2, respectively. However, the present invention is not limited thereto, and the first auxiliary capacitance signal and the second auxiliary capacitance signal may be supplied to the first CS bus line CB1 and the second CS bus line CB2 from other circuits, respectively. Further, the detailed description relating to the first storage capacitor signal and the second storage capacitor signal will be described below.

The source driver 300 receives the digital video signal DV, the source start pulse signal SSP, the source clock signal SCK, and the latch strobe signal LS output from the display control circuit 200, and applies driving to each source line SL. Use image signals.

The gate driver 400 receives the gate from the output of the display control circuit 200. The pulse signal GSP and the gate clock signal GCK are applied to the gate lines GL to apply a scan signal.

By applying a scanning signal to each of the gate lines GL as described above, a driving image signal is applied to each of the source lines SL, and an image based on the image data DAT transmitted from the outside is displayed on the display unit 100.

<1.2 Configuration of Pixel Formation Section>

FIG. 2 is an equivalent circuit diagram showing a configuration of a part of the pixel formation portion (four pixel formation portions) in the display unit 100 in the present embodiment. In the present specification, the pixel formation portion provided in correspondence with the i-th column gate line GLi and the j-th row source line SLj, that is, the pixel formation portion of the i-th column and the j-th row is represented by a symbol 10 (i, j) . Further, when the m×n pixel formation portions are not particularly distinguished, the pixel formation portion is indicated by only the reference numeral 10.

As shown in FIG. 2, the pixel formation portion 10 has a multi-pixel structure. In other words, the pixel formation unit 10 includes the first sub-pixel formation unit 11 and the second sub-pixel formation unit 12 . In the present specification, the first sub-pixel forming portion 11 and the second sub-pixel forming portion 12 of the pixel forming portion 10 (i, j) of the i-th column and the j-th row are denoted by symbols 11 (i, j) and 12, respectively. i, j) indicates. In addition, the first sub-pixel forming unit 11 (i, j) and the second sub-pixel forming unit 12 (i, j) are referred to as "the first sub-pixel forming portion of the i-th column and the j-th row" and "the first". The case of the second pixel formation unit in the jth row of i column. In the present embodiment, the first sub-pixel forming portion 11 corresponds to a bright pixel, and the second sub-pixel forming portion 12 corresponds to a dark pixel.

The first pixel formation portion 11 includes a first thin film transistor T1 as a first switching element, a first pixel electrode Epix1, a first liquid crystal capacitor Clc1 as a first display capacitor, a first auxiliary capacitor CcsA, and a second auxiliary. Capacitor CcsB. Take In the following, the capacitance values of the first liquid crystal capacitor, the first auxiliary capacitor, and the second auxiliary capacitor are also indicated by Clc1, CcsA, and CcsB, respectively. In the present embodiment and each of the following embodiments, CcsA>CcsB. The connection relationship between the constituent elements of the first pixel formation unit 11 is as follows. In the first thin film transistor T1, the gate line GL is connected to a gate electrode as a control terminal, the source line SL is connected to a source electrode as a first conduction terminal, and the first pixel electrode Epix1 is connected to the second conduction terminal. The drain electrode. A first liquid crystal capacitor Clc is formed between the first pixel electrode Epix1 and the common electrode COM that is provided in common to each of the pixel formation portions 10. A common potential Vcom of, for example, a fixed potential is applied to the common electrode COM. One of the first auxiliary capacitor CcsA and the second auxiliary capacitor CcsB is connected to the first pixel electrode Epix1. The connection destination of the other end of each of the first storage capacitor CcsA and the second storage capacitor CcsB alternates every line. That is, in the first sub-pixel forming portion 11 (i, j) of the jth row of the i-th column, the other end of the first storage capacitor CcsA is connected to the first CS line CSL1, and the other end of the second storage capacitor CcsB is connected to the 2 CS line CSL2, in contrast, in the first sub-pixel forming portion 11 (i, j+1) of the j+1th row of the i-th column, the other end of the first auxiliary capacitor CcsA is connected to the second CS line CSL2, The other end of the second storage capacitor CcsB is connected to the first CS line CSL1. Further, although not shown, the other end of the first auxiliary capacitance CcsA is connected to the first CS line CSL1 in the first sub-pixel forming portion 11 (i, j+2) in the j+2th row of the i-th column, and The other end of the auxiliary capacitor CcsB is connected to the second CS line CSL2. In addition, in the row direction, the connection destination of the other end of each of the first storage capacitor CcsA and the second storage capacitor CcsB is the same in each of the first sub-pixel formation portions 11.

The second pixel formation unit 12 includes the second thin film electric power as the second switching element. The crystal T2, the second pixel electrode Epix2, and the second liquid crystal capacitor Clc2 as the second display capacitor. Further, a specific auxiliary capacitance may be provided in parallel with the second liquid crystal capacitor Clc2, that is, between the second pixel electrode Epix2 and the common electrode COM. The connection relationship between the constituent elements of the second pixel formation unit 12 is as follows. In the second thin film transistor T2, the gate line GL is connected to the gate electrode as the control terminal, the source line SL is connected to the source electrode as the first conduction terminal, and the second pixel electrode Epix2 is connected to the second conduction terminal. The drain electrode. Further, the gate lines GL and the source lines SL are connected to the first thin film forming portion 11 of the pixel forming portion 10 including the second sub-pixel forming portion 12, and are connected to the first thin film transistor T1. The gate line GL of the gate electrode and the source line SL connected to the source electrode of the first thin film transistor T1 are the same. A second liquid crystal capacitor Clc2 is formed between the second pixel electrode Epix2 and the common electrode COM.

The channel layers of the first and second thin film transistors T1 and T2 in the present embodiment and the following embodiments are formed of, for example, an oxide semiconductor. However, the present invention is not limited thereto, and a microcrystalline germanium may be used instead of the oxide semiconductor. Further, although the mobility of the first and second thin film transistors T1 and T2 is lowered as compared with the case of using an oxide semiconductor or a microcrystalline germanium, an amorphous germanium or the like may be used for the channel layers.

<1.3 layout>

Fig. 3 is a view showing a layout in the vicinity of a pixel formation portion for realizing the circuit configuration shown in Fig. 2. The gate metal forming the gate line GL, the gate metal forming the first CS line CSL1, and the gate metal forming the second CS line CSL2 are disposed in parallel with each other. Furthermore, in this specification, the gate will be formed The other metal of the gate metal of the line GL is also called the gate metal. The gate metal and the source metal forming the source line SL are disposed to be orthogonal to each other. A portion other than a region where the gate line GL is disposed in a region between the adjacent two source lines SL (except for a partial region of the first CS line CSL1), and the first pixel electrode Epix1 is formed. And the second pixel electrode Epix2. The first pixel electrode Epix1 and the second pixel electrode Epix2 are formed as transparent electrodes. Further, as shown in FIG. 3, the area ratio of the first pixel electrode Epix1 corresponding to the bright pixel to the second pixel electrode Epix2 corresponding to the dark pixel is larger than the area of the second pixel electrode Epix2 by the area of the first pixel electrode Epix1. The way to set. By making the ratio of the dark pixels relatively large in this way, the so-called anti-black defect in which the low-gradation pixels are brighter than the actual one can be sufficiently suppressed. Such an area ratio setting is disclosed, for example, in Patent Document 2. However, the present invention is not limited thereto, and the area ratio of the first pixel electrode Epix1 and the second pixel electrode Epix2 can be arbitrarily set.

The first electrode of the first thin film transistor T1 of the first pixel formation portion 11 and the first pixel electrode Epix1 are electrically connected to each other by the source metal SE1 and the contact CT1. The first sub-pixel forming portion 11 (i, j) in the jth row of the i-th column is set as the area of the source metal SE1 that is opposite to the first CS line CSL1 of the i-th column (hereinafter referred to as " The first opposing area ") is larger than the area of the source metal SE1 that is opposite to the second CS line CSL2 (hereinafter referred to as "second opposing area"). In the first sub-pixel forming portion 11 (i, j) of the jth row of the i-th column, the first auxiliary capacitor CcsA is formed at a portion where the source metal SE1 and the first CS line CSL1 of the i-th column overlap each other. The portion where the metal SE1 and the second CS line CSL2 overlap each other forms the second storage capacitor CcsB. In the direction of the column and the first pixel shape The first sub-pixel forming portion 11 (i, j+1) of the i-th column j+1th row adjacent to the portion 11 (i, j) is set such that the first opposing area is smaller than the area of the second opposing area. More specifically, the first opposing area and the second opposing area of the first sub-pixel forming portion 11 (i, j+1) of the j+1th row of the i-th column are respectively the first and the j-th row of the i-th column The second opposing area and the first opposing area of the primary pixel forming unit 11 (i, j) are substantially the same. In the first sub-pixel forming portion 11 (i, j+1) of the j+1th row of the i-th column, the second auxiliary capacitor CcsB is formed at a portion where the source metal SE1 and the first CS line CSL1 overlap each other. The portion where the metal SE1 and the second CS line CSL2 overlap each other forms the first storage capacitor CcsA. Further, although not shown, the layout of the first sub-pixel forming portion 11 (i+1, j) in the j-th row of the i+1th column and the first sub-pixel forming portion 11 in the j-th row of the i-th column ( The layout of i, j) is the same, the layout of the first sub-pixel forming portion 11 (i+1, j+1) of the j+1th row of the i+1th column and the first sub-j+1th row of the i-th column The layout of the pixel formation sections 11 (i, j+1) is the same.

In this case, the first auxiliary capacitor CcsA or the second auxiliary capacitor CcsB is formed in a portion where the source metal SE1 and the first CS line CSL1 or the second CS line CSL2 overlap each other. A portion where the CS line CSL1 or the second CS line CSL2 overlaps with the first pixel electrode Epix1 also forms a capacitor (hereinafter referred to as "capacitor to be considered in design"). Therefore, in actuality, the total capacitance to be considered in design and the first auxiliary capacitor CcsA or the second auxiliary capacitor CcsB are respectively designed as the first auxiliary capacitor CcsA or the second auxiliary capacitor CcsB. This situation is also the same in the description of the layout below.

The drain electrode of the second thin film transistor T2 of the second pixel formation portion 12 and the second pixel electrode Epix2 are electrically connected to each other by the source metal SE2 and the contact CT2.

<1.4 Action>

Fig. 4 is a signal waveform diagram for explaining the driving method in the embodiment. More specifically, it is a description of a selection period (a period during which the pixel forming unit 10 writes the first pixel electrode Epix1 and the second pixel electrode Epix2 in accordance with an image to be displayed) and A signal waveform diagram of the operation of the pixel forming portion 10 (i, j) of the i-th column and the jth row in the following sub-pixel CS driving period. The length of the selection period corresponds to the length of one horizontal scanning period (indicated by "1H" in FIG. 4) in the liquid crystal display device. The sub-pixel CS driving period is a period in which the electric power is located in the first pixel electrode Epix1 and the second pixel electrode Epix2, and specifically refers to the N-th frame (N is an integer of 1 or more). The period from the end of the selection period to the beginning of the selection period in the N+1 frame. Here, the pixel formation portion 10(i, j) of the jth row of the i-th column is displayed in the Nth frame for positive polarity display, and the negative polarity display is performed in the N+1th frame. In the following, the potential of the first pixel electrode Epix1 is referred to as "first pixel potential" and is represented by the symbol Vpix1. Similarly, the potential of the second pixel electrode Epix2 is referred to as "second pixel potential" and is represented by a symbol Vpix2. The potentials of the first pixel potentials Vpix1 and Vpix2 are represented by the Vpix1 and Vpix2, respectively.

As shown in FIG. 4, in the present embodiment, the polarity based on the common potential Vcom of the potential of the source line SLj is inverted every one horizontal scanning period and every frame. Further, although not shown, the polarity is reversed between the source lines SL adjacent to each other. Further, the potentials of the first CS line CSL1 and the second CS line CSL2 repeat the high level Vch and the low level Vcl every one horizontal scanning period, and the potentials are inverted from each other. In the following, Vch and Vcl are also used to indicate high level Vch and low level. The case of the size of the quasi Vcl.

First, the action in the Nth frame will be described. When the selection period is reached, the first thin film transistor T1 and the second thin film transistor T2 having the gate terminals connected to the gate line GLi are turned on. Therefore, the image signal potential Vdata (positive polarity) is applied to the first pixel electrode Epix1 and the second pixel electrode Epix2 from the source line SLj. The image signal potential Vdata is a potential determined based on the display image. Hereinafter, the case where the video signal potential Vdata is also indicated by Vdata is used. The first pixel potential Vpix1 and the second pixel potential Vpix2 in the selection period are obtained by the following formula (1).

Vpix1=Vpix2=Vdata...(1)

In this case, the first CS line CSL1 becomes the low level Vcl, and the second CS line CSL2 becomes the high level Vch.

When the sub-pixel CS driving period is completed (the selection period is completed), the first thin film transistor T1 and the second thin film transistor T2 having the gate terminals connected to the gate line GLi are turned off. Therefore, the first pixel electrode Epix1 and the second pixel electrode Epix2 are in a floating state. Further, as shown in FIG. 4, in the first horizontal scanning period (hereinafter referred to as "first horizontal scanning period") of the sub-pixel CS driving period, the first CS line CSL1 is changed to the high level Vch, and the second CS line is changed. CSL2 changes to a low level Vcl. Thereby, the first pixel potential Vpix1 changes as in the following equation (2).

Vpix1=Vdata+((CcsA-CcsB)/Ctot)‧△Vc...(2)

Ctot and ΔVc are obtained according to the following formulas (3) and (4), respectively.

Ctot=Clc1+CcsA+CcsB+Cp...(3)

△Vc=Vch-Vcl...(4)

In the formula (3), Cp is a parasitic capacitance in the first sub-pixel forming portion 10. For convenience, the parasitic capacitance Cp is formed on the first pixel electrode Epix1 and an electrode (for example, a gate line or the like) that operates at an amplitude or a timing different from the potential change of the first CS line CSL1 and the second CS line CSL2. between. In the present embodiment, since the first CS line CSL1 and the second CS line CSL2 are not connected to the second pixel potential Vpix2, the potential change as in the equation (2) does not occur.

Further, actually, at the end of the selection period, a feed-through voltage ΔVg is generated due to a potential change of the gate line GLi and a parasitic capacitance. Therefore, the first pixel potential Vpix1 represented by the formula (2) is actually obtained by the following formula (5).

Vpix1=Vdata+((CcsA-CcsB)/Ctot)‧△Vc-△Vg...(5)

For the same reason, the second pixel potential Vpix2 is actually obtained according to the following formula (6).

Vpix2=Vdata-△Vg...(6)

However, for convenience of illustration, in FIG. 4 and each of the following signal waveform diagrams, it is described that the feedthrough voltage ΔVg is not generated.

In the second one horizontal scanning period (hereinafter referred to as "second one horizontal scanning period") of the sub-pixel CS driving period, the first CS line CSL1 changes to the low level Vcl, and the second CS line CSL2 changes to the high level Vch. Therefore, the first pixel potential Vpix1 changes as in the following equation (7).

Vpix1=Vdata-△Vg...(7)

Furthermore, the second pixel potential Vpix2 does not change. In other words, in the second horizontal scanning period, the first pixel potential Vpix1 is equal to the second pixel potential Vpix2.

Hereinafter, the first horizontal scanning period of the sub-pixel CS driving period is sequentially repeated The action between the two and the second horizontal scanning period until the selection period of the (N+1)th frame starts. Therefore, the first pixel potential Vpix1 that is effective when the positive polarity is displayed is obtained by the following equation (8).

Vpix1=Vdata+((CcsA-CcsB)/Ctot)‧△Vc‧(1/2)-△Vg...(8)

In addition, the second pixel potential Vpix2 which is effective when the positive polarity is displayed is as shown in the formula (6).

CcsA>CcsB, and the electric power of the first CS line CSL1 to be connected to the first storage capacitor CcsA is changed to the direction in which the first pixel potential Vpix1 is boosted after the selection period of the positive polarity display is completed. Therefore, according to the equations (8) and (6), it is understood that the first pixel potential Vpix1 is higher than the second pixel potential Vpix2 which is the same as the pixel potential in the liquid crystal display device not having the multi-pixel structure when the positive polarity display is performed. . As described above, when the display of the positive polarity is performed, the first sub-pixel formation portion 11 (i, j) in the jth row of the i-th column realizes a bright pixel, and the second sub-pixel formation portion in the j-th row of the i-th column 12 (i, j) implements dark pixels.

Next, the operation in the frame of the N+1th will be described. When the selection period is reached, the first thin film transistor T1 and the second thin film transistor T2 having the gate terminals connected to the gate line GLi are turned on. Therefore, the image signal potential Vdata (negative polarity) is applied to the first pixel electrode Epix1 and the second pixel electrode Epix2 from the source line SLj. The first pixel potential Vpix1 and the second pixel potential Vpix2 in the selection period are obtained based on the above formula (1). At this time, unlike the Nth frame, the first CS line CSL1 becomes the high level Vch, and the second CS line CSL2 becomes the low level Vcl.

When the sub-pixel CS driving period is completed (the selection period is completed), the first thin film transistor T1 and the second thin film electromorph are connected to the gate terminal GLi with the gate terminal. The body T2 is in an off state. Therefore, the first pixel electrode Epix1 and the second pixel electrode Epix2 are in a floating state. Further, as shown in FIG. 4, during the first horizontal scanning period, the first CS line CSL1 changes to the low level Vcl, and the second CS line CSL2 changes to the high level Vch. Thereby, the first pixel potential Vpix1 changes as in the following equation (9).

Vpix1=Vdata-((CcsA-CcsB)/Ctot)‧△Vc...(9)

When the feedthrough voltage ΔVg is considered, the first pixel potential Vpix1 represented by the equation (9) is actually obtained by the following equation (10).

Vpix1=Vdata-((CcsA-CcsB)/Ctot)‧△Vc-△Vg...(10)

Further, the second pixel potential Vpix2 is obtained based on the above formula (6).

During the second horizontal scanning period of the sub-pixel CS driving period, the first CS line CSL1 changes to the high level Vch, and the second CS line CSL2 changes to the low level Vcl. Therefore, the first pixel potential Vpix1 changes as in the above formula (7). Furthermore, the second pixel potential Vpix2 does not change. In other words, similarly to the Nth frame, the first pixel potential Vpix1 is equal to the second pixel potential Vpix2 in the second horizontal scanning period of the sub-pixel CS driving period.

Hereinafter, the operation of the first horizontal scanning period and the second horizontal scanning period of the sub-pixel CS driving period are sequentially repeated until the selection period of the (N+1)th frame is started. Therefore, the first pixel potential Vpix1 which is effective when the display of the negative polarity is performed is obtained by the following formula (11).

Vpix1=Vdata-((CcsA-CcsB)/Ctot)‧△Vc‧(1/2)-△Vg...(11)

In addition, the second pixel potential Vpix2 which is effective when the negative polarity is displayed is as shown in the above formula (6).

CcsA>CcsB, and the first CS of the first auxiliary capacitor CcsA is connected. The electric power of the line CSL1 is changed to the direction in which the first pixel potential Vpix1 is boosted after the selection period of the negative polarity display is completed. Therefore, according to the equations (11) and (6), it is understood that the first pixel potential Vpix1 is lower than the second pixel potential Vpix2 which is the same as the pixel potential in the liquid crystal display device not having the multi-pixel structure when the display of the negative polarity is performed. . As described above, when the display of the negative polarity is performed, the first sub-pixel forming portion 11 (i, j) in the jth row of the i-th column realizes a bright pixel, and the second sub-pixel forming portion in the j-th row of the i-th column 12 (i, j) implements dark pixels.

In the present embodiment, the connection destination of the other end of each of the first storage capacitor CcsA and the second storage capacitor CcsB is changed every line, and the polarity of the source line SLj is one horizontal scanning period and one line per line. Reverse. Therefore, although not shown, the operation of the pixel forming portion 10 (i, j+1) in the j+1th row of the i-th column is the action of the pixel forming portion 10 (i, j) in the jth row of the i-th column. The polarity of the first pixel potential Vpix1 and the second pixel potential Vpix2 is reversed. Further, the operation of the pixel forming portion 10 (i+1, j) in the jth row of the i+1th column is the first pixel potential in the operation of the pixel forming portion 10 (i, j) in the jth row of the i-th column The polarity of Vpix1 and the second pixel potential Vpix2 is reversed, and the potential change is delayed by one horizontal scanning period. Further, the operation of the pixel forming portion 10 (i+1, j+1) of the j+1th row and the j+1th row is the pixel forming portion 10 (i+1, j) of the jth row of the i+1th column. In the operation, the polarities of the first pixel potential Vpix1 and the second pixel potential Vpix2 are reversed. In other words, in the present embodiment, the display polarity (which is the polarity of the first pixel potential Vpix1 and the second pixel potential Vpix2 of the pixel formation portion 10) is different between the pixel formation portions 10 adjacent to each other in the column direction and the row direction. . Therefore, in the present embodiment, so-called dot inversion driving is performed.

As described above, in the present embodiment, in each of the positive electrode display and the negative polarity display, the bright pixels are realized by the first sub-pixel forming portion 11 in each of the pixel forming portions 10, and the second sub-pixels are formed. The section 12 implements dark pixels. Further, the second pixel potential Vpix2 of the second sub-pixel forming portion 12 is the same as the potential when the multi-pixel structure is not employed.

<1.5 effect>

According to the present embodiment, in the liquid crystal display device having the multi-pixel structure, the first auxiliary capacitance CcsA and the second auxiliary capacitance CcsB are provided in the first sub-pixel formation portion 11 among the two sub-pixel formation portions constituting the pixel formation portion 10. . The relationship between the capacitance values of the first storage capacitor CcsA and the second storage capacitor CcsB is CcsA>CcsB. The first auxiliary capacitor CcsA and the second auxiliary capacitor CcsB are connected to different CS lines, and the CS line to which the first auxiliary capacitor CcsA and the second auxiliary capacitor CcsB are connected is the CS line to which the first auxiliary capacitor CcsA is connected. The manner in which the potential changes to the CS line in which the direction in which the first pixel potential Vpix1 is boosted after the end of the selection period is changed in the column direction per pixel forming portion. Therefore, in each of the positive electrode display and the negative polarity display, the bright pixels are realized by the first sub-pixel forming portion 11 in each of the pixel forming portions 10, and the dark pixels are realized by the second sub-pixel forming portion 12. Thereby, the bright pixel and the dark pixel are arranged side by side in the column direction. The area ratio of the bright pixel to the dark pixel can be arbitrarily set by arranging the bright pixel and the dark pixel in parallel in the column direction. Therefore, for example, in order to prevent the blackout defect, the area of the second pixel electrode Epix2 can be set larger than the area of the first pixel electrode Epix1. According to the above, according to the present embodiment, the display quality can be made higher than before, and the viewing angle characteristics can be improved. Furthermore, by using the first CS line CSL1 and the second CS line The CSL 2 boosts the first pixel potential Vpix1 without using an image signal for realizing a large amplitude of bright pixels, so that power consumption can be reduced.

Further, according to the present embodiment, since the second pixel potential Vpix2 of the second sub-pixel forming portion 12 corresponding to the dark pixel is the same as the potential when the multi-pixel structure is not used, the luminance is not lowered (set to the normally black mode). (normally black mode)). Therefore, the display quality can be further improved.

Further, according to the present embodiment, since the display polarities are different from each other between the pixel forming portions 10 adjacent to each other in the column direction and the row direction, dot inversion driving (inversion driving in units of one pixel) can be performed.

Further, according to the present embodiment, the channel layers of the first and second thin film transistors T1 and T2 are formed of an oxide semiconductor. Since the mobility of the oxide semiconductor is higher than that of the amorphous germanium or the like, the sizes of the first and second thin film transistors T1 and T2 can be reduced. Therefore, it is possible to improve the aperture ratio of the pixel formation portion 10 and the reduction of the load on the bus bars (the source line SL and the gate line GL). Further, when the microcrystalline germanium is used for the channel layer of the first and second thin film transistors T1 and T2, the same effect can be obtained.

<2. Second embodiment> <2.1 Configuration of Pixel Forming Section>

FIG. 5 is an equivalent circuit diagram showing a configuration of a part of the pixel formation portion (eight pixel formation portions) in the display unit 100 according to the second embodiment of the present invention. In the components of the present embodiment, the same components as those in the above-described first embodiment are denoted by the same reference numerals, and the description thereof will be omitted as appropriate. In the present embodiment, in the configuration of the first embodiment, the first auxiliary is further provided. The connection destination of the other end of each of the capacitor CcsA and the second auxiliary capacitor CcsB is different for each specific number of columns (two columns). In other words, for example, when focusing on the j-th row, the first sub-pixel forming portion 11 (i-1, j) (not shown) in the j-th row of the i-1th column and the first sub-j-th row of the i-th column In the sub-pixel formation portion 11 (i, j), the other end of the first storage capacitor CcsA is connected to the first CS line CSL1, and the other end of the second storage capacitor CcsB is connected to the second CS line CSL2. Further, the first sub-pixel forming portion 11 (i+1, j) in the i-th column and the jth row, and the first sub-pixel forming portion 11 (i+2, j) in the i-th column and the j-th row in the i-th column The other end of the first storage capacitor CcsA is connected to the second CS line CSL2, and the other end of the second storage capacitor CcsB is connected to the first CS line CSL1. Further, the first sub-pixel forming portion 11 (i+3, j) in the jth row of the i+3 column and the first sub-pixel forming portion 11 (i+4, j) in the jth row of the i+4th column (not shown), the other end of the first storage capacitor CcsA is connected to the first CS line CSL1, and the other end of the second storage capacitor CcsB is connected to the second CS line CSL2. In addition, attention is paid to the connection between the other end of each of the first auxiliary capacitor CcsA and the second auxiliary capacitor CcsB in the j+1th row, focusing on the first auxiliary capacitor CcsA and the second auxiliary capacitor CcsB in the jth row. The connection object at the other end of each of them is reversed. In addition, since the layout in the vicinity of the pixel formation portion is the same as that of the above-described first embodiment, the description thereof will be omitted.

<2.2 Action>

Fig. 6 is a signal waveform diagram for explaining the driving method in the embodiment. More specifically, it is a signal waveform diagram for explaining the operation of the pixel forming portion 10 (i, j) in the jth row of the i-th column in the selection period. In addition, the description of the part common to the above-described first embodiment will be appropriately omitted. As shown in FIG. 6, in the present embodiment, unlike the first embodiment, the potentials of the first CS line CSL1 and the second CS line CSL2 are repeated every two horizontal scanning periods. The quasi Vch and the low level Vcl, and the potentials are inverted.

First, in the Nth frame, when the selection period is reached, the image signal potential Vdata (positive polarity) is applied to the first pixel electrode Epix1 and the second pixel electrode Epix2 from the source line SLj. In this case, the first CS line CSL1 becomes the low level Vcl, and the second CS line CSL2 becomes the high level Vch.

When the first horizontal scanning period of the sub-pixel CS driving period is completed, unlike the above-described first embodiment, in the present embodiment, the potentials of the first CS line CSL1 and the second CS line CSL2 do not change. Although not shown, the image signal is given to the first pixel electrode Epix1 and the second pixel electrode Epix2 of the pixel formation portion 10 (i+1, j) of the i-th column and the j-th row from the source line SLj. Potential Vdata (negative polarity). Further, when the second horizontal scanning period of the sub-pixel CS driving period ends, the first CS line CSL1 changes to the high level Vch, and the second CS line CSL2 changes to the low level Vcl. Thereby, the first pixel electrode Epix1 changes as in the above formula (5).

Thereafter, in the third one horizontal scanning period (hereinafter referred to as "the third horizontal scanning period") of the sub-pixel CS driving period, the first CS line CSL1 and the 2 CS line are similar to the first one horizontal scanning period. The potential of CSL2 does not change. Further, in the fourth one horizontal scanning period (hereinafter referred to as "fourth horizontal scanning period") of the sub-pixel CS driving period, the first CS line CSL1 changes to the low level Vcl, and the second CS line CSL2 changes to the high level. Vch. Thereby, the first pixel electrode Epix1 changes as in the above formula (7).

Hereinafter, the operations of the first and second horizontal scanning periods of the sub-pixel CS driving period and the operations of the third and fourth horizontal scanning periods are sequentially repeated until the selection period of the (N+1)th frame is started. Therefore, the positive polarity is displayed. The first pixel potential Vpix1 that is effective at the time is given by the above formula (8). Further, since the operation in the N+1th frame is in the operation of the Nth frame, the polarity is reversed, and the description thereof is omitted.

In the present embodiment, the connection destination of the other end of each of the first storage capacitor CcsA and the second storage capacitor CcsB is switched every one row and every two columns, and the polarity of the source line SLj is every one horizontal scanning period. Reverse every 1 line. Therefore, although not shown, the operation of the pixel forming portion 10 (i+1, j) in the jth row of the i+1th column is the action of the pixel forming portion 10(i, j) in the jth row of the i-th column. The polarity of the first pixel potential Vpix1 and the second pixel potential Vpix2 is reversed, and the operation of the pixel forming portion 10 (i, j) of the i-th column j-th row is omitted, which corresponds to the first horizontal scanning period. Part of it. Further, the operation of the pixel forming portion 10 (i+2, j) in the jth row of the i+2th column is the first pixel potential in the operation of the pixel forming portion 10(i, j) in the jth row of the i-th column The potential change of Vpix1 and the second pixel potential Vpix2 is delayed by two horizontal scanning periods. Further, the operation of the pixel forming portion 10 (i+3, j) in the jth row of the i+3th column is performed by the pixel forming portion 10 (i+2, j) to make the first pixel potential Vpix1 and the second pixel. The polarity of the potential Vpix2 is inverted, and the portion corresponding to the first horizontal scanning period of the operation of the pixel forming portion 10 (i+2, j) of the jth row of the i+2th column is omitted. Furthermore, the action of the jth column is based on the action of the i-th column to reverse the polarity. As described above, in the present embodiment, the display polarities are different from each other between the pixel formation portions 10 adjacent to each other in the column direction and the row direction. That is, in the present embodiment, so-called dot inversion driving is performed.

<2.3 effect>

According to this embodiment, the first auxiliary capacitor CcsA and the second auxiliary capacitor are used In the configuration in which the connection destination of the other end of each of CcsB is switched every one line and every two columns, the potential of the first CS line CSL1 and the second CS line CSL2 is changed every two horizontal scanning periods. The same effects as those of the first embodiment described above. Further, since the driving frequency of the first CS line CSL1 and the second CS line CSL2 is about 1/2 of that of the first embodiment, power consumption can be further reduced.

<3. Third embodiment> <3.1 Configuration of Pixel Formation Section>

FIG. 7 is an equivalent circuit diagram showing a configuration of a part of the pixel formation portion (four pixel formation portions) in the display unit 100 according to the third embodiment of the present invention. In the components of the present embodiment, the same components as those in the above-described first embodiment are denoted by the same reference numerals, and the description thereof will be omitted as appropriate. As shown in FIG. 7, in the configuration of the first embodiment, the connection destination of the other end of each of the first storage capacitor CcsA and the second storage capacitor CcsB is different for each row. In other words, for example, when focusing on the j-th row, the other end of the first auxiliary capacitance CcsA is connected to the first CS line CSL1 in the first sub-pixel forming portion 11 (i, j) of the j-th row of the i-th column, and the second The other end of the storage capacitor CcsB is connected to the second CS line CSL2. Further, in the first sub-pixel forming portion 11 (i+1, j) of the jth row of the i+1th column, the other end of the first storage capacitor CcsA is connected to the second CS line CSL2, and the second auxiliary capacitor CcsB is another. One end is connected to the first CS line CSL1. Further, in the first sub-pixel forming portion 11 (i+2, j) of the jth row of the i+2th column (not shown), the other end of the first storage capacitor CcsA is connected to the first CS line CSL1, and the second The other end of the storage capacitor CcsB is connected to the second CS line CSL2. Furthermore, since the first auxiliary capacitor CcsA is focused on the j+1th row The other end of each of the second auxiliary capacitors CcsB is connected to the other end of the first auxiliary capacitor CcsA and the second auxiliary capacitor CcsB in the jth row, so that the connection is reversed. Description. In addition, since the layout in the vicinity of the pixel formation portion is the same as that of the above-described first embodiment, the description thereof will be omitted.

<3.2 Action>

Fig. 8 is a signal waveform diagram for explaining the driving method in the embodiment. More specifically, it is a signal waveform diagram for explaining the operation of the pixel forming portion 10 (i, j) in the jth row of the i-th column in the selection period. In addition, the description of the part common to the above-described first embodiment will be appropriately omitted. As shown in Fig. 8, in the present embodiment, unlike the first embodiment, the polarity of the source line SLj does not change in each frame. Here, the polarity of the source line SLj is positive in the Nth frame, and negative in the N+1th frame. Further, although not shown, the polarity is reversed between the source lines SL adjacent to each other.

As shown in Fig. 8, the operation of the pixel forming portion 10 (i, j) in the nth column and the jth row in the Nth frame and the N+1th frame is the same as that in the first embodiment. In the present embodiment, the connection destination of the other end of each of the first storage capacitor CcsA and the second storage capacitor CcsB is switched every one row and one column, and the polarity of the source line SLj is every frame and every 1 line reversed. Therefore, although not shown, the operation of the pixel forming portion 10 (i, j+1) in the j+1th row of the i-th column is the action of the pixel forming portion 10 (i, j) in the jth row of the i-th column. The polarity of the first pixel potential Vpix1 and the second pixel potential Vpix2 is reversed. Further, the operation of the pixel forming portion 10 (i+1, j) in the jth row of the i+1th column is the first pixel potential in the operation of the pixel forming portion 10 (i, j) in the jth row of the i-th column Vpix1 and the second pixel potential Vpix2 The potential change is delayed by one during the horizontal scanning period. Further, the operation of the pixel forming portion 10 (i+1, j+1) of the j+1th row and the j+1th row is the pixel forming portion 10 (i+1, j) of the jth row of the i+1th column. In the operation, the polarities of the first pixel potential Vpix1 and the second pixel potential Vpix2 are reversed. In other words, in the present embodiment, the display polarities are different from each other between the pixel formation portions 10 adjacent to each other in the column direction, and the display polarities are the same between the pixel formation portions 10 adjacent to each other in the row direction. Therefore, in the present embodiment, so-called line inversion driving (line inversion driving in units of source lines SL) can be performed.

<3.3 effect>

According to the present embodiment, in the configuration in which the other end of each of the first storage capacitor CcsA and the second storage capacitor CcsB is switched in one row and one column, the potential of the source line SL is made The polarity is inverted every one line and inverted every line, and the line inversion driving can be performed, and the same effects as those of the first embodiment described above can be obtained. Further, since the driving amplitude in the frame of the source line SL is smaller than that of the first embodiment, the power consumption can be further reduced.

<4. Fourth embodiment> <4.1 Configuration of Pixel Forming Section>

FIG. 9 is an equivalent circuit diagram showing a configuration of a part of the pixel formation portion (four pixel formation portions) in the display unit 100 according to the fourth embodiment of the present invention. In the components of the present embodiment, the same components as those in the above-described first embodiment are denoted by the same reference numerals, and the description thereof will be omitted as appropriate. As shown in FIG. 9, in the third embodiment, the two pixel formation portions 10 adjacent to each other in the row direction are connected to the two source lines SL adjacent to each other. That is, the first pixel forming portion 11 (i, j) of the jth row of the i-th column is the first The source terminal of the thin film transistor T1 and the source terminal of the second thin film transistor T2 of the second sub-pixel forming portion 12 (i, j) of the i-th column j-th row are connected to the j-th source line SLj, and In contrast, the source terminal of the first thin film transistor T1 and the second row of the i+1th column and the jth row of the first pixel forming portion 11 (i+1, j) of the i+1th column and the jth row The source terminal of the second thin film transistor T2 of the pixel formation portion 12 (i+1, j) is connected to the source line SLj+1 of the j+1th row. Further, although not shown, the source terminal of the first thin film transistor T1 and the i+1th column of the first pixel forming portion 11 (i+2, j) of the i-th column and the j-th row of the i-th column The source terminal of the second thin film transistor T2 of the second subpixel forming portion 12 (i+2, j) of the j row is connected to the jth row source line SLj. Furthermore, since the description relating to the j-1th line shown in FIG. 9 is only for the description related to the jth line, the source lines SLj and SLj+1 of the jth line and the j+1th line are respectively exchanged. The j-1th row and the jth row source lines SLj-1 and SLj are omitted, and thus the details thereof are omitted.

<4.2 Action>

The operation of the pixel forming portion 10 (i, j) in the i-th column of the i-th column in the present embodiment is the same as that in the third embodiment. However, in the present embodiment, the connection destination of the other end of each of the first storage capacitor CcsA and the second storage capacitor CcsB is switched every one line, and the polarity of the source line SLj is one frame and one line. The two pixel formation portions 10 that are inverted and adjacent to each other in the row direction are respectively connected to the two source lines SL adjacent to each other. In other words, the source line SL to which the pixel formation portion is connected is exchanged every one row. Therefore, although not shown, the operation of the pixel forming portion 10 (i, j-1) in the j-1th row of the i-th column is the action of the pixel forming portion 10 (i, j) in the j-th row of the i-th column. The polarity of the first pixel potential Vpix1 and the second pixel potential Vpix2 is reversed. Also, the pixel shape of the jth row of the i+1th column The operation of the portion 10 (i+1, j) is such that the polarity of the first pixel potential Vpix1 and the second pixel potential Vpix2 is reversed during the operation of the pixel formation portion 10 (i, j) in the jth row of the i-th column. And the potential change is delayed by one horizontal scanning period. Further, the operation of the pixel forming portion 10 (i+1, j-1) of the j-1th row of the i+1th column is the pixel forming portion 10 (i+1, j) of the jth row of the i+1th column. In the operation, the polarities of the first pixel potential Vpix1 and the second pixel potential Vpix2 are reversed. Therefore, in the present embodiment, so-called dot inversion driving is performed.

<4.3 effect>

In the configuration in which the connection destination of the other end of each of the first storage capacitor CcsA and the second storage capacitor CcsB is changed every line, and the source line SL of the connection target of the pixel formation unit 10 is switched one by one. By inverting the polarity of the potential of the source line SL every one frame and every line, the same effects as those of the first embodiment described above can be obtained.

<4.4 Modifications>

FIG. 10 is an equivalent circuit diagram showing a configuration of a part of the pixel formation portion (eight pixel formation portions) in the display unit 100 in the modification of the embodiment. In the present modification, in the configuration of the fourth embodiment, the connection destination of the other end of each of the first storage capacitor CcsA and the second storage capacitor CcsB is different for each specific number of columns (two columns). In other words, for example, when focusing on the j-th row, the first sub-pixel forming portion 11 (i-1, j) in the j-th row of the i-1th column and the first sub-pixel forming portion 11 in the i-th column and the jth row are 11 (i, j), the other end of the first storage capacitor CcsA is connected to the first CS line CSL1, and the other end of the second storage capacitor CcsB is connected to the second CS line CSL2. Further, the first sub-pixel forming portion 11 (i+1, j) in the i-th column and the jth row, and the first sub-pixel forming portion 11 (i+2, j) in the i-th column and the j-th row in the i-th column , the first The other end of the storage capacitor CcsA is connected to the second CS line CSL2, and the other end of the second storage capacitor CcsB is connected to the first CS line CSL1. Further, the first sub-pixel forming portion 11 (i+3, j) (not shown) in the jth row of the i+3th column and the first sub-pixel forming portion 11 of the i+th column j-th row (i) +4, j) (not shown), the other end of the first storage capacitor CcsA is connected to the first CS line CSL1, and the other end of the second storage capacitor CcsB is connected to the second CS line CSL2. In addition, attention is paid to the connection between the other end of each of the first auxiliary capacitor CcsA and the second auxiliary capacitor CcsB in the j-1th row, focusing on the first auxiliary capacitor CcsA and the second auxiliary capacitor CcsB in the jth row. The connection object at the other end of each of them is reversed.

Fig. 11 is a signal waveform diagram for explaining a driving method in the present modification. More specifically, it is a signal waveform diagram for explaining the operation of the pixel forming portion 10 (i, j) in the jth row of the i-th column in the selection period. As shown in FIG. 11, in the present modification, unlike the fourth embodiment, the potentials of the first CS line CSL1 and the second CS line CSL2 repeat the high level Vch and the low level Vcl every two horizontal scanning periods, and The potentials are reversed from each other. In addition, since the operation in the present modification is the same as the operation in the second embodiment except that the polarity of the source line SLj does not change in each frame, the detailed description thereof will be omitted. According to the present modification, since the display polarity is different for each of the pixel formation portions in the column direction and the row direction, so-called dot inversion driving is also performed.

In the present modification, since the potentials of the first CS line CSL1 and the second CS line CSL2 are inverted every two horizontal scanning periods, the first CS line CSL1 and the second CS line CSL2 are compared with the fourth embodiment. The drive frequency is reduced. Therefore, it is possible to reduce power consumption.

Furthermore, in the fourth embodiment and the modifications described above, it is assumed that the pixel shape is used. The source line SL of the connection target of the part 10 is replaced every one row, but the present invention is not limited thereto. For example, the source line SL to which the pixel formation unit 10 is connected may be replaced by a plurality of rows. In this case, the potentials of the first CS line CSL1 and the second CS line CSL2 are inverted every plurality of horizontal scanning periods. Therefore, in this case, as in the above-described modification, the driving frequencies of the first CS line CSL1 and the second CS line CSL2 are also reduced. Therefore, it is possible to reduce power consumption.

<5. Fifth embodiment> <5.1 Configuration of Pixel Formation Section>

FIG. 12 is an equivalent circuit diagram showing a configuration of a part of the pixel formation portion (four pixel formation portions) in the display unit 100 according to the fifth embodiment of the present invention. In the components of the present embodiment, the same components as those in the above-described first embodiment are denoted by the same reference numerals, and the description thereof will be omitted as appropriate. As shown in FIG. 12, in the first embodiment, the first sub-capacitor CcsA and the second auxiliary capacitor CcsB are further provided in the second sub-pixel forming unit 12. In the present embodiment, the first auxiliary capacitor CcsA and the second auxiliary capacitor CcsB provided in the first sub-pixel forming portion 11 are referred to as "the first auxiliary capacitor Ccs1A for bright pixels" and "for the bright pixel". 2 auxiliary capacitor Ccs1B". The first auxiliary capacitance CcsA and the second auxiliary capacitance CcsB provided in the second sub-pixel formation unit 12 are referred to as "dark pixel first storage capacitor Ccs2A" and "dark pixel second storage capacitor Ccs2B", respectively. In the following, Ccs1A, Ccs1B, Ccs2A, and Ccs2B are used to indicate the first auxiliary capacitor Ccs1A for bright pixels, the second storage capacitor Ccs1B for bright pixels, the first storage capacitor Ccs2A for dark pixels, and the second auxiliary for dark pixels. The capacitance value of the auxiliary capacitor Ccs2B. Here, Ccs1A>Ccs1B, Ccs2A>Ccs2B. In addition, since the configuration of the first pixel formation portion 11 is the same as that of the above-described first embodiment, the description thereof will be omitted.

In the present embodiment, two second CS lines CSL2 are provided along each gate line GL. One of the two second CS lines CSL2 corresponds to the first sub-pixel forming portion 11 and the other corresponds to the second sub-pixel forming portion 12. However, it is also possible to adopt a configuration in which the second CS line CSL2 is set to one. Further, two first CS lines CSL1 may be provided instead of the two second CS lines CSL2.

In the second sub-pixel forming unit 12, one of the first auxiliary capacitor Ccs2A for dark pixels and the second auxiliary capacitor Ccs2B for dark pixels is connected to the first pixel electrode Epix1. The connection target of the other end of each of the first auxiliary capacitor Ccs2A and the second second auxiliary capacitor Ccs2B for the dark pixel is the same as the connection target of the first auxiliary capacitor Ccs1A for the bright pixel and the second auxiliary capacitor Ccs1B for the bright pixel. Change every 1 line. In other words, in the second sub-pixel forming portion 12 (i, j) of the j-th row in the i-th column, the other end of the first auxiliary capacitor Ccs2A for the dark pixel is connected to the second CS line CSL2 in the i-th column, and the dark pixel is used. 2, the other end of the auxiliary capacitor Ccs2B is connected to the first CS line CSL1 of the (i+1)th column, and the second sub-pixel forming unit 12(i, j+1) of the j+1th line of the i-th column, The other end of the dark pixel first auxiliary capacitor Ccs2A is connected to the first CS line CSL1 of the i+1th column, and the other end of the dark pixel second auxiliary capacitor Ccs2B is connected to the second CS line CSL2 of the i-th column. In addition, in the row direction, the connection destination of the other end of each of the first auxiliary capacitor Ccs2A and the second auxiliary capacitor Ccs2B for dark pixels is the same in each of the second sub-pixel forming portions 12. In other words, in each of the pixel formation portions 10, the other end of the first auxiliary capacitor Ccs2A for the dark pixel is connected. The connection target of the other end of the first auxiliary capacitor Ccs1A for bright pixels is different from each other, and the connection destination of the other end of the dark auxiliary pixel auxiliary capacitor Ccs2B and the second auxiliary capacitor Ccs1B for bright pixels are different from each other.

<5.2 Layout>

Fig. 13 is a view showing a layout in the vicinity of a pixel formation portion for realizing the circuit configuration shown in Fig. 12. In addition, the part common to the layout in the above-described first embodiment (the layout of the first pixel formation portion 11 and the like) will be appropriately omitted. As shown in FIG. 13, in the present embodiment, the area of the second CS line CSL2 corresponding to the second sub-pixel forming unit 12 that faces the second pixel electrode Epix2 (hereinafter referred to as "dark pixel CS area") The area of the second CS line CSL2 corresponding to the first pixel formation unit 11 that is opposite to the first pixel electrode Epix1 (hereinafter referred to as "bright pixel CS area") is set to be substantially the same. In the second sub-pixel forming portion 12 (i, j) of the i-th column, the area of the source metal SE2 that is opposite to the second CS line CSL2 of the i-th column (hereinafter referred to as "third" The opposing area ") is set to be larger than the area of the source metal SE2 that is opposite to the first CS line CSL1 of the (i+1)th column (hereinafter referred to as "fourth opposing area"). In the second sub-pixel forming portion 12 (i, j) of the jth row of the i-th column, the first auxiliary capacitor Ccs2A for the dark pixel is formed in a portion where the source metal SE2 and the second CS line CSL2 of the i-th column overlap each other. A second auxiliary capacitor Ccs2B for dark pixels is formed in a portion where the source metal SE2 and the first CS line CSL1 of the (i+1)th column overlap each other. The second sub-pixel forming portion 12 (i, j+1) of the i-th column j+1th row adjacent to the second-order pixel forming portion 12 (i, j) in the column direction is set to the third opposing area Less than the 4th opposite area. The second sub-pixel forming portion 12 (i, j+1) in the j+1th row of the i-th column is mutually in the source metal SE2 and the second CS line CSL2 in the i-th column In the overlapping portion, the second auxiliary capacitor Ccs2B for dark pixels is formed, and the first auxiliary capacitor Ccs2A for dark pixels is formed in a portion where the source metal SE2 and the first CS line CSL1 of the (i+1)th column overlap each other. Further, although not shown, the layout of the second sub-pixel forming portion 12 (i+1, j) in the j-th row of the i+1th column and the second sub-pixel forming portion 12 in the j-th row of the i-th column ( i, j) are the same, the layout of the second sub-pixel forming portion 12 (i+1, j+1) of the j+1th row of the i+1th column and the second subpixel formation of the j+1th row of the i-th column The part 12 (i, j+1) is the same.

<5.3 Action>

Fig. 14 is a signal waveform diagram for explaining the driving method in the embodiment. More specifically, it is a signal waveform diagram for explaining the operation of the pixel forming portion 10 (i, j) in the jth row of the i-th column in the selection period. In addition, the description of the part common to the above-described first embodiment will be appropriately omitted. As shown in Fig. 14, in the first embodiment, the first pixel potential Vpix1 is the same as that of the above-described first embodiment, and the potential change is the same as that of the first embodiment. In addition, the potential change of the second pixel potential Vpix2 is reversed based on the video signal potential Vdata (more specifically, Vdata-ΔVg) based on the potential change of the first pixel potential Vpix1 during the sub-pixel CS driving period.

First, in the Nth frame, when the selection period is reached, the image signal potential Vdata (positive polarity) is applied to the first pixel electrode Epix1 and the second pixel electrode Epix2 from the source line SLj. In this case, the first CS line CSL1 becomes the low level Vcl, and the second CS line CSL2 becomes the high level Vch.

During the first horizontal scanning period of the sub-pixel CS driving period, the first CS line CSL1 changes to the high level Vch, and the second CS line CSL2 changes to the low level Vcl. Thereby, the first pixel potential Vpix1 changes as in the following equation (12).

Vpix1=Vdata+((Ccs1A-Ccs1B)/Ctotl)‧△Vc-△Vg...(12)

Here, Ctot1 is given by the following formula (13).

Ctot1=Clc1+Ccs1A+Ccs1B+Cp1...(13)

In the formula (13), Cp1 is a parasitic capacitance in the first sub-pixel forming portion 11. For convenience, the parasitic capacitance Cp is formed on the first pixel electrode Epix1 and an electrode (for example, a gate line or the like) that operates at an amplitude or a timing different from the potential change of the first CS line CSL1 and the second CS line CSL2. between. Further, ΔVc is imparted according to the above formula (4).

Further, during the first horizontal scanning period of the sub-pixel CS driving period, the second pixel potential Vpix2 changes as in the following equation (14).

Vpix2=Vdata-((Ccs2A-Ccs2B)/Ctot2)‧△Vc-△Vg...(14)

Here, Ctot2 is given by the following formula (15).

Ctot2=Clc2+Ccs2A+Ccs2B+Cp2...(15)

In the formula (15), Cp2 is a parasitic capacitance in the second sub-pixel forming portion 12. For convenience, the parasitic capacitance Cp2 is formed between the second pixel electrode Epix2 and an electrode (for example, a gate line or the like) that operates at an amplitude or a timing different from the potential change of the first CS line CSL1 and the second CS line CSL2. .

As described above, in the first horizontal scanning period during the sub-pixel CS driving period, the first pixel potential Vpix1 and the second pixel potential Vpix2 are changed in the positive and negative directions. Further, during the second horizontal scanning period of the sub-pixel CS driving period, the first CS line CSL1 changes to the low level Vcl, and the second CS line CSL2 changes to the high level Vch. Therefore, the first pixel potential Vpix1 and the second pixel potential Vpix2 are changed as in the above equations (7) and (6), respectively. That is, during the second horizontal scanning period, the first pixel potential Vpix1 and the second pixel potential Vpix2 is equal.

Hereinafter, the operation of the first horizontal scanning period and the second horizontal scanning period of the sub-pixel CS driving period are sequentially repeated until the selection period of the (N+1)th frame is started. Therefore, the first pixel potential Vpix1 and the second pixel potential Vpix2 which are effective when the positive polarity display is performed are respectively given by the following equations (16) and (17).

Vpix1=Vdata+((Ccs1A-Ccs1B)/Ctot1)‧△Vc‧(1/2)-△Vg...(16)

Vpix2=Vdata-((Ccs2A-Ccs2B)/Ctot2)‧△Vc‧(1/2)-△Vg...(17)

When the selection period of the display of the positive polarity is completed, the potential of the first CS line CSL1 to which the first auxiliary capacitor Ccs1A for bright pixels and the second auxiliary capacitor Ccs2B for dark pixels are connected is set to the first pixel potential Vpix1 and The second pixel potential Vpix2 is changed in the direction of the boosting, and the potential of the second CS line CSL2 to be connected to the second auxiliary capacitor Ccs1B for the bright pixel and the first auxiliary capacitor Ccs2A for the dark pixel is shifted to the first pixel potential Vpix1 and The direction of the step-down of the 2-pixel potential Vpix2 changes. Also, Ccs1A>Ccs1B, and Ccs2A>Ccs2B. Therefore, according to the equations (16) and (17), it is understood that the first pixel potential Vpix1 is higher than the second pixel potential Vpix2 when the positive polarity display is performed. As described above, when the display of the positive polarity is performed, the first sub-pixel formation portion 11 (i, j) in the jth row of the i-th column realizes a bright pixel, and the second sub-pixel formation portion in the j-th row of the i-th column 12 (i, j) implements dark pixels. Further, in the present embodiment, the potential difference between the first pixel potential Vpix1 and the second pixel potential Vpix2 is larger than that of the first embodiment.

Furthermore, the action in the N+1th frame is in the action of the Nth frame to reverse the polarity. The first pixel potential effective when the display of the negative polarity is performed Vpix1 and the second pixel potential Vpix2 are respectively given by the following equations (18) and (19).

Vpix1=Vdata-((Ccs1A-Ccs1B)/Ctot1)‧△Vc‧(1/2)-△Vg...(18)

Vpix2=Vdata+((Ccs2A-Ccs2B)/Ctot2)‧△Vc‧(1/2)-△Vg...(19)

When the selection period of the display of the negative polarity is completed, the potential of the first CS line CSL1 to which the first auxiliary capacitor Ccs1A for bright pixels and the second auxiliary capacitor Ccs2B for dark pixels are connected is raised to the first pixel potential Vpix1. The direction of the pressure changes, and the potential of the second CS line CSL2 to which the first auxiliary capacitor Ccs1B for the bright pixel and the first auxiliary capacitor Ccs2A for the dark pixel are connected is changed in the direction in which the first pixel potential Vpix1 is stepped down. Also, Ccs1A>Ccs1B, and Ccs2A>Ccs2B. Therefore, according to the equations (18) and (19), it is understood that the first pixel potential Vpix1 is lower than the second pixel potential Vpix2 when the display of the negative polarity is performed. As described above, when the display of the negative polarity is performed, the first sub-pixel forming portion 11 (i, j) in the jth row of the i-th column realizes a bright pixel, and the second sub-pixel forming portion in the j-th row of the i-th column 12 (i, j) implements dark pixels. Further, in the present embodiment, the potential difference between the first pixel potential Vpix1 and the second pixel potential Vpix2 is larger than that of the first embodiment. Further, in the present embodiment, dot inversion driving is performed in the same manner as in the first embodiment.

<5.4 effect>

According to the present embodiment, the potential difference between the first pixel potential Vpix1 and the second pixel potential Vpix2 in the sub-pixel CS driving period is larger than that of the first embodiment. Therefore, the luminance difference between the first sub-pixel forming portion 11 and the second sub-pixel forming portion 12 is larger than that of the first embodiment. Thereby, the so-called anti-black defect can be further suppressed.

<6. Sixth embodiment> <6.1 Configuration of Pixel Forming Section>

FIG. 15 is an equivalent circuit diagram showing a configuration of a part of the pixel formation portion (four pixel formation portions) in the display unit 100 according to the sixth embodiment of the present invention. In the components of the present embodiment, the same components as those in the first embodiment or the fifth embodiment are denoted by the same reference numerals, and the description thereof will be omitted as appropriate. As shown in FIG. 15, in the configuration of the fifth embodiment, the connection target of the other end of the first auxiliary capacitor Ccs2A for dark pixels and the other end of the second auxiliary capacitor Ccs2B for dark pixels are connected. Exchanger. In other words, in each of the pixel formation portions 10, the connection target of the other end of the dark auxiliary pixel auxiliary capacitor Ccs2A and the other end of the bright auxiliary pixel auxiliary capacitor Ccs1A are mutually identical, and the second auxiliary capacitor Ccs2B for the dark pixel is used. The other end of the connection target and the bright pixel second auxiliary capacitor Ccs1B are identical to each other. However, in the present embodiment, Ccs1A>Ccs1B, Ccs2A>Ccs2B, and Ccs1A-Ccs1B>Ccs2A-Ccs2B.

<6.2 layout>

Fig. 16 is a view showing the layout in the vicinity of the pixel formation portion for realizing the circuit configuration shown in Fig. 15. In addition, the description of the portions common to the layouts of the first embodiment or the fifth embodiment will be appropriately omitted. As shown in Fig. 16, unlike the fifth embodiment described above, in the present embodiment, the dark pixel CS area is set to be smaller than the bright pixel CS area. In the second sub-pixel forming portion 12 (i, j) of the jth row of the i-th column, the third opposing area is set to be smaller than the fourth opposing area. The second sub-pixel forming portion 12 (i, j) in the jth row of the i-th column forms a dark image in a portion where the source metal SE2 and the second CS line CSL2 of the i-th column overlap each other. The second auxiliary capacitor Ccs2B is used, and the first auxiliary capacitor Ccs2A for dark pixels is formed in a portion where the source metal SE2 and the first CS line CSL1 of the (i+1)th column overlap each other. Here, in the pixel formation portion 10 (i, j) of the jth row in the i-th column, the fourth opposing area is smaller than the first opposing area. Further, in the case where the dark pixel CS area is smaller than the bright pixel CS area, the third opposing area and the second opposing area are substantially the same. With this layout, the settings of Ccs1A>Ccs1B, Ccs2A>Ccs2B, and Ccs1A-Ccs1B>Ccs2A-Ccs2B are realized. In the second sub-pixel forming portion 12 (i, j+1) of the j+1th row of the i-th column, the third opposing area is set larger than the fourth opposing area. The second sub-pixel forming portion 12 (i, j+1) in the j+1th row of the i-th column forms a portion for the dark pixel in a portion where the source metal SE2 and the second CS line CSL2 of the i-th column overlap each other. The auxiliary capacitor Ccs2A forms a second auxiliary capacitor Ccs2B for dark pixels in a portion where the source metal SE2 and the first CS line CSL1 of the (i+1)th column overlap each other. Here, in the pixel formation portion 10 (i, j) of the jth row in the i-th column, the fourth opposing area is substantially the same as the first opposing area. Further, in the case where the dark pixel CS area is smaller than the bright pixel CS area, the third opposing area is smaller than the second opposing area. With this layout, the settings of Ccs1A>Ccs1B, Ccs2A>Ccs2B, and Ccs1A-Ccs1B>Ccs2A-Ccs2B are realized. Further, although not shown, the layout of the second sub-pixel forming portion 12 (i+1, j) in the j-th row of the i+1th column and the second sub-pixel forming portion 12 in the j-th row of the i-th column ( i, j) are the same, the layout of the second sub-pixel forming portion 12 (i+1, j+1) of the j+1th row of the i+1th column and the second subpixel formation of the j+1th row of the i-th column The part 12 (i, j+1) is the same.

<6.3 Action>

Figure 17 is a diagram for explaining the driving method in the embodiment. Waveform diagram. More specifically, it is a signal waveform diagram for explaining the operation of the pixel forming portion 10 (i, j) in the jth row of the i-th column in the selection period. In addition, the description of the part common to the above-described first embodiment will be appropriately omitted. As shown in FIG. 17, in the operation of the fifth embodiment, the potential change of the second pixel potential Vpix2 during the sub-pixel CS driving period and the potential of the first pixel potential Vpix1 are changed to the same direction. And it is smaller than the potential change of the first pixel potential Vpix1. Since the potential change of the first pixel potential Vpix1 is the same as that of the fifth embodiment, the following description will be focused on the potential change of the second pixel potential Vpix2.

First, in the first horizontal scanning period of the sub-pixel CS driving period of the Nth frame, the first CS line CSL1 changes to the high level Vch, and the second CS line CSL2 changes to the low level Vcl. Thereby, the second pixel potential Vpix2 changes as in the following equation (20).

Vpix2=Vdata+((Ccs2A-Ccs2B)/Ctot2)‧△Vc-△Vg...(20)

Further, during the second horizontal scanning period of the sub-pixel CS driving period, the first CS line CSL1 changes to the low level Vcl, and the second CS line CSL2 changes to the high level Vch. At this time, the second pixel potential Vpix2 changes as shown in the above formula (6) as in the fifth embodiment.

Hereinafter, the operations of the first horizontal scanning period and the second horizontal scanning period are sequentially repeated until the selection period of the (N+1)th frame is started. Therefore, the second pixel potential Vpix2 that is effective when the positive polarity is displayed is given by the following formula (21).

Vpix2=Vdata+((Ccs2A-Ccs2B)/Ctot2)‧△Vc‧(1/2)-△Vg...(21)

As a bright pixel after the selection period at which the display of the positive polarity is completed The potential of the first CS line CSL1 to be connected to the first auxiliary capacitor Ccs1A and the dark auxiliary pixel Ccs2A is changed in the direction in which the first pixel potential Vpix1 and the second pixel potential Vpix2 are boosted, and is used as a bright pixel. The potential of the second CS line CSL2 to be connected to the second auxiliary capacitor Ccs1B and the second auxiliary capacitor Ccs2B for dark pixels changes in a direction in which the first pixel potential Vpix1 and the second pixel potential Vpix2 are stepped down. Further, Ccs1A>Ccs1B, Ccs2A>Ccs2B, and Ccs1A-Ccs1B>Ccs2A-Ccs2B. Therefore, according to the equations (16) and (21), it is understood that the first pixel potential Vpix1 is higher than the second pixel potential Vpix2 when the positive polarity display is performed. As described above, when the display of the positive polarity is performed, the first sub-pixel formation portion 11 (i, j) in the jth row of the i-th column realizes a bright pixel, and the second sub-pixel formation portion in the j-th row of the i-th column 12 (i, j) implements dark pixels. Further, in the present embodiment, the boosting is also performed in the second pixel potential Vpix2.

Furthermore, the action in the N+1th frame is in the action of the Nth frame to reverse the polarity. The second pixel potential Vpix2 that is effective when the negative polarity is displayed is given by the following formula (22).

Vpix2=Vdata-((Ccs2A-Ccs2B)/Ctot2)‧△Vc‧(1/2)-△Vg...(22)

When the selection period of the display of the negative polarity is completed, the potential of the first CS line CSL1 to be connected to the first auxiliary capacitor Ccs1A for the bright pixel and the first auxiliary capacitor Ccs2A for the dark pixel is shifted to the first pixel potential Vpix1 and The second pixel potential Vpix2 is changed in the direction of the boosting, and the potential of the second CS line CSL2 to be connected to the second auxiliary capacitor Ccs1B for the bright pixel and the second auxiliary capacitor Ccs2B for the dark pixel is shifted to the first pixel potential Vpix1 and The direction of the step-down of the 2-pixel potential Vpix2 changes. Also, Ccs1A>Ccs1B, Ccs2A>Ccs2B, and Ccs1A-Ccs1B>Ccs2A-Ccs2B. Therefore, according to the above formulas (20) and (24), it is understood that the first pixel potential Vpix1 is lower than the second pixel potential Vpix2 when the display of the negative polarity is performed. As described above, when the display of the negative polarity is performed, the first sub-pixel forming portion 11 (i, j) in the jth row of the i-th column realizes a bright pixel, and the second sub-pixel forming portion in the j-th row of the i-th column 12 (i, j) implements dark pixels. Further, in the present embodiment, the boosting is also performed in the second pixel potential Vpix2. Further, in the present embodiment, so-called dot inversion driving is performed in the same manner as in the first and fifth embodiments described above.

<6.4 effect>

According to the present embodiment, not only the first pixel potential Vpix1 but also the second pixel potential Vpix2 is boosted, and the first pixel potential Vpix1 is boosted more than the second pixel potential Vpix2. Therefore, the bright pixels can be realized by the first sub-pixel forming unit 11, and the dark pixels can be realized by the second sub-pixel forming unit 12, and the driving amplitude of the source lines can be reduced. Thereby, it is possible to reduce power consumption.

<7. Seventh embodiment> <7.1 Overall Configuration and Operation Outline>

Fig. 18 is a block diagram showing the overall configuration of an active matrix display device according to a seventh embodiment of the present invention. In the components of the present embodiment, the same components as those in the above-described first embodiment are denoted by the same reference numerals, and the description thereof will be omitted as appropriate. As shown in FIG. 18, the liquid crystal display device of the present embodiment includes a CS driver 500 as a storage capacitor line drive circuit in addition to the respective components in the first embodiment. Furthermore, in the present embodiment, the first CS bus bar line CB1 and the second CS bus bar are not provided. Line CB2.

The display control circuit 200 outputs a CS start pulse signal CCP and a CS clock signal CCK for controlling the operation of the CS driver 500 instead of outputting the first auxiliary capacitance signal and the second auxiliary capacitance signal.

The CS driver 500 receives the CS start pulse signal CCP and the CS clock signal CCK outputted from the display control circuit 200, and drives the first CS line CSL1 and the second CS line CSL2 of each column. In the present embodiment, the first CS line and the second CS line of the i-th column are indicated by the symbols "CSL1(i)" and "CSL2(i)", respectively. Unlike the above-described respective embodiments, the first CS line CSL1 of each column in the present embodiment is independently driven. Similarly, the second CS line CSL2 of each column is also driven independently.

<7.2 Configuration of Pixel Formation Section>

FIG. 19 is an equivalent circuit diagram showing a configuration of a part of the pixel formation portion (four pixel formation portions) in the display unit 100 in the present embodiment. As shown in FIG. 19, the configuration of the pixel formation portion in the present embodiment is basically the same as that of the first embodiment (the symbols of the first CS line and the second CS line are different), and thus the description thereof will be omitted. In addition, since the layout in the vicinity of the pixel formation portion is the same as that of the above-described first embodiment, the description thereof will be omitted.

<7.3 Action>

Fig. 20 is a signal waveform diagram for explaining the driving method in the embodiment. More specifically, it is a signal waveform diagram for explaining the operation of the pixel forming portion 10 (i, j) in the jth row of the i-th column in the selection period. In addition, the description of the part common to the above-described first embodiment will be appropriately omitted. Each of the first CS line CSL1 and each of the second CS lines CSL2 in the present embodiment is driven by CS. Since the device 500 is driven, as shown in FIG. 20, the potential changes of the first CS line CSL1 and the second CS line CSL2 are different from those of the first embodiment. More specifically, after the selection period of each column is completed, the potentials of the first CS line CSL1 and the second CS line CSL2 of the column are changed, and the equal power is located during the driving process of the sub-pixel CS (ie, until the next frame) Fixed at the beginning of the selection period). In addition, since the change of the second pixel potential Vpix2 is the same as that of the above-described first embodiment, the description thereof will be omitted. In the present embodiment, the potential control step is performed by the CS driver 500.

First, in the Nth frame, when the selection period is reached, the image signal potential Vdata (positive polarity) is applied to the first pixel electrode Epix1 and the second pixel electrode Epix2 from the source line SLj. At this time, the first CS line CSL1(i) of the i-th column becomes the low level Vcl, and the second CS line CSL2(i) of the i-th column becomes the high level Vch.

During the first horizontal scanning period of the sub-pixel CS driving period, the first CS line CSL1(i) of the i-th column changes to the high level Vch, and the second CS line CSL2(i) of the i-th column changes to the low level Vcl. Thereby, the first pixel potential Vpix1 changes as in the above formula (5). Thereafter, during the sub-pixel CS driving period (that is, when the selection period until the next frame is started), the first pixel potential Vpix1 maintains the potential represented by the above formula (5). In other words, in the present embodiment, the first pixel potential Vpix1 that is effective when the positive polarity is displayed is given by the following formula (23).

Vpix1=Vdata+((CcsA-CcsB)/Ctot)‧△Vc-△Vg...(23)

CcsA>CcsB, and the electric power of the first CS line CSL1 to be connected to the first storage capacitor CcsA is changed to the direction in which the first pixel potential Vpix1 is boosted after the selection period of the positive polarity display is completed. Therefore, according to the formulas (23) and (6), it is understood that the first pixel potential is displayed when the positive polarity is displayed. Vpix1 is higher than the second pixel potential Vpix2 which is the same as the pixel potential in the liquid crystal display device which is not in the multi-pixel structure. As described above, when the display of the positive polarity is performed, the first sub-pixel formation portion 11 (i, j) in the jth row of the i-th column realizes a bright pixel, and the second sub-pixel formation portion in the j-th row of the i-th column 12 (i, j) implements dark pixels. Further, in the present embodiment, the potential difference between the first pixel potential Vpix1 and the second pixel potential Vpix2 is larger than that of the first embodiment.

Furthermore, the action in the N+1th frame is in the action of the Nth frame to reverse the polarity. The first pixel potential Vpix1 that is effective when the display of the negative polarity is performed is given by the following formula (24).

Vpix1=Vdata-((CcsA-CcsB)/Ctot)‧△Vc-△Vg...(24)

CcsA>CcsB, and the electric power of the first CS line CSL to which the first storage capacitor CcsA is connected is located in the direction in which the first pixel potential Vpix1 is boosted after the selection period of the negative polarity display is completed. Therefore, according to the equations (24) and (6), it is understood that the first pixel potential Vpix1 is lower than the second pixel potential Vpix2 which is the same as the pixel potential in the liquid crystal display device not using the multi-pixel structure when the display of the negative polarity is performed. . As described above, when the display of the negative polarity is performed, the first sub-pixel forming portion 11 (i, j) in the jth row of the i-th column realizes a bright pixel, and the second sub-pixel forming portion in the j-th row of the i-th column 12 (i, j) implements dark pixels. Further, in the present embodiment, the potential difference between the first pixel potential Vpix1 and the second pixel potential Vpix2 is larger than that of the first embodiment.

In the present embodiment, the connection destination of the other end of each of the first storage capacitor CcsA and the second storage capacitor CcsB is changed every line, and the polarity of the source line SLj is one horizontal scanning period and one line per line. Reverse. Therefore, in the present embodiment, images adjacent to each other in the column direction and the row direction are adjacent to each other. The prime forming portions 10 have different display polarities. Therefore, in the present embodiment, so-called dot inversion driving is performed in the same manner as in the first embodiment.

As described above, in the present embodiment, in each of the positive electrode display and the negative polarity display, the bright pixels are realized by the first sub-pixel forming portion 11 in each of the pixel forming portions 10, and the second sub-pixels are formed. The section 12 implements dark pixels. Further, the second pixel potential Vpix2 of the second sub-pixel forming portion 12 is the same as the potential when the multi-pixel structure is not employed.

<7.4 effect>

According to the present embodiment, in the aspect in which the first CS line CSL1 and the second CS line CSL2 are driven by the CS driver 500, the same effects as those of the first embodiment described above can be obtained. Further, the second pixel potential Vpix2 of the second sub-pixel forming unit 12 is the same as the potential when the multi-pixel structure is not used, and the potential difference between the first pixel potential Vpix1 and the second pixel potential Vpix2 in the sub-pixel CS driving period is larger than the above. The first embodiment. Thereby, the luminance reduction of the second sub-pixel formation portion 12 corresponding to the dark pixel can be suppressed, and the anti-black defect can be further suppressed.

<8. Eighth Embodiment> <8.1 Configuration of Pixel Formation Section>

Fig. 21 is an equivalent circuit diagram showing a configuration of a pixel formation portion 10 (i, j) of the i-th column and the j-th row in the eighth embodiment of the present invention. In the components of the present embodiment, the same components as those in the above-described first embodiment are denoted by the same reference numerals, and the description thereof will be omitted as appropriate. As shown in FIG. 21, in the configuration of the first embodiment, the third CS line CSL3 as the third storage capacitor line is provided along each gate line GL, and the second sub-pixel is formed. The portion 12 is further provided with a third auxiliary capacitor CcsC as an adjustment capacitor. Further, a specific fixed potential is given to the third CS line CSL3. One end of the third storage capacitor CcsC is connected to the second pixel electrode Epix2, and the other end is connected to the third CS line CSL3.

A parasitic capacitance is formed in the pixel formation portion 10. For example, as shown in FIG. 21, the first parasitic capacitance Cgdt1 is formed between the gate and the drain of the first thin film transistor T1, and the second parasitic capacitance Cgdt2 is formed between the gate and the drain of the second thin film transistor T2. Further, in practice, parasitic capacitance may be formed in other portions, but the illustration is omitted here for convenience. When the gate line GL is switched from the selected state to the non-selected state by the presence of the parasitic capacitance (the selection period ends), the first pixel potential Vpix1 and the second pixel potential Vpix2 fluctuate. In other words, the feedthrough voltage ΔVg is generated in the first pixel electrode Epix1 and the second pixel electrode Epix2. However, the first storage capacitor CcsA and the second storage capacitor CcsB are connected to the first pixel electrode Epix1, and the second pixel electrode Epix2 is not connected to the first pixel electrode Epix1. Therefore, the first pixel electrode Epix1 and the second pixel electrode Epix2 are connected. The feedthrough voltage ΔVg generated in the middle is different from each other. As a result, the potential fluctuations of the first pixel potential Vpix1 and the second pixel potential Vpix2 at the time of selection are different. The third storage capacitor CcsC is provided to suppress variations in such potential fluctuations.

The relationship between the capacitance values of the respective capacitances shown in Fig. 21 is expressed by the following formula (25).

Cgdt1/(CcsA+CcsB+Clc1+Cp1) =Cgdt2/(CcsC+Clc2+Cp2)...(25)

Here, Cp1 is a parasitic capacitance other than the first parasitic capacitance Cgdt1 formed in the first sub-pixel formation portion 11, and Cp2 is formed in the second sub-pixel formation. The parasitic capacitance other than the second parasitic capacitance Cgdt2 in the portion 12. As described above, Cgdt1 and Cgdt2 are the feedthrough voltage ΔVg in the first pixel electrode Epix1 which is generated by the potential change of the gate line GL at the end of the selection period and the first parasitic capacitance Cgdt1, and the end of the selection period. The change in the potential of the gate line GL and the feedthrough voltage ΔVg in the second pixel electrode Epix2 generated by the second parasitic capacitance Cgdt2 are set to be substantially equal.

<8.2 layout>

Fig. 22 is a view showing the layout in the vicinity of the pixel formation portion for realizing the circuit configuration shown in Fig. 21. In addition, the description of the part common to the layout in the above-described first embodiment will be omitted. As shown in FIG. 22, in the present embodiment, the third auxiliary capacitor CcsC is formed in a portion where the source metal SE2 and the third CS line CSL3 (gate metal) overlap each other.

<8.3 effect>

According to the present embodiment, by providing the third storage capacitor CcsB satisfying the equation (25), the deviation of the potential fluctuation between the first pixel potential Vpix1 and the second pixel potential Vpix2 at the end of the selection period of the gate line GL is suppressed. .

<8.4 Modifications>

Fig. 23 is an equivalent circuit diagram showing the configuration of the pixel formation portion 10 (i, j) of the i-th column and the j-th row in the modification of the embodiment. In the components of the present embodiment, the same components as those in the first embodiment or the eighth embodiment are denoted by the same reference numerals, and the description thereof will be omitted as appropriate. As shown in FIG. 23, in the present modification, the first adjustment capacitor Cgd1 and the second adjustment capacitor Cgd2 are provided instead of the third CS line CSL3 and the third storage capacitor CcsC. One end of the first adjustment capacitor Cgd1 is connected to the first pixel electrode Epix1, and the other end Connected to the gate line GLi. One end of the second adjustment capacitor Cgd2 is connected to the second pixel electrode Epix2, and the other end is connected to the gate line GLi. Similarly to the third auxiliary capacitor CcsC, the first adjustment capacitor Cgd1 and the second adjustment capacitor Cgd2 are the first pixel potential Vpix1 and the second pixel potential Vpix2 when the selection period of the gate line GL is stopped. Set by the non-uniformity of the potential variation.

The relationship between the capacitance values of the respective capacitances shown in Fig. 23 is expressed by the following formula (26).

(Cgdt1+Cgd1)/(CcsA+CcsB+Clc1+Cp1) =(Cgdt2+Cgd2)/(Clc2+Cp2)...(26)

As described above, Cgd1 and Cgd2 are the feedthrough voltage ΔVg in the first pixel electrode Epix1 which is generated by the potential change of the gate line GL at the end of the selection period and the first parasitic capacitance Cgdt1, and the end of the selection period. The change in the potential of the gate line GL and the feedthrough voltage ΔVg in the second pixel electrode Epix2 generated by the second parasitic capacitance Cgdt2 are set to be substantially equal.

Fig. 24 is a view showing the layout in the vicinity of the pixel formation portion for realizing the circuit configuration shown in Fig. 23. In addition, the description of the part common to the layout in the above-described first embodiment will be omitted. As shown in FIG. 24, a portion of the gate line GL (gate metal) other than the portion where the first thin film transistor T1 and the second thin film transistor T2 are provided overlaps with the source metal SE1 and the source metal SE2. . The first adjustment capacitor Cgd1 is formed in a portion where the source metal SE1 and the gate line GL overlap each other, and the second adjustment capacitor Cgd2 is formed in a portion where the source metal SE2 and the gate line GL overlap each other.

According to the present modification, the selection of the gate line GL is suppressed by providing the first adjustment capacitor Cgd1 and the second adjustment capacitor Cgd2 satisfying the equation (26). The deviation between the potential fluctuations of the first pixel potential Vpix1 and the second pixel potential Vpix2 at the end of the period.

Furthermore, the eighth embodiment of the present invention and its modifications can be combined and applied. In other words, the third storage capacitor CcsC, the first adjustment capacitor Cgd1, and the second adjustment capacitor Cgd2 may be provided in each of the pixel formation portions 10.

<9. Ninth Embodiment> <9.1 Configuration of Pixel Forming Section>

Fig. 25 is an equivalent circuit diagram showing a configuration of a pixel formation portion 10 (i, j) of the i-th column and the j-th row in the ninth embodiment of the present invention. In the components of the present embodiment, the same components as those in the above-described first embodiment are denoted by the same reference numerals, and the description thereof will be omitted as appropriate. In the above embodiments, the first thin film transistor T1 and the second thin film transistor T2 are arranged in parallel. However, in the present embodiment, as shown in FIG. 25, the first thin film transistor T1 and the second thin film transistor T2 are provided. Tandem configuration. In other words, the source terminal (first conduction terminal) of the second thin film transistor T2 is connected to the source line SLj via the first thin film transistor T1. In other words, the first thin film transistor T1 and the second thin film transistor T2 share the source terminal of the first terminal (the second conductive terminal) of the first thin film transistor T1 and the second thin film transistor T2. Further, the pixel forming portions other than the pixel forming portion 10 (i, j) of the jth row of the i-th column are also configured in the same manner. Further, the configuration is not limited to the configuration shown in FIG. 25, and the source terminal of the first thin film transistor T1 may be connected to the source line SLj via the second thin film transistor T1. In other words, the source terminal of the first thin film transistor T1 and the second terminal of the second thin film transistor T2 are shared by the first thin film transistor T1 and the second thin film transistor T2.

<9.2 layout>

Fig. 26 is a view for explaining the layout of the first thin film transistor T1 and the second thin film transistor T2 in the present embodiment. More specifically, FIG. 26(A) is a plan view showing the layout of the first thin film transistor T1 and the second thin film transistor T2. Fig. 26 (B) is a cross-sectional view taken along line A-A of Fig. 26 (A). In the layout of each of the above embodiments, the first thin film transistor T1 and the second thin film transistor T2 are arranged in parallel (see FIGS. 3, 13, 16, 22, and 24). However, in the present embodiment, as shown in FIG. 26(A), the first thin film transistor T1 and the second thin film transistor T2 are arranged in series. As shown in FIG. 26(B), the series arrangement of the first thin film transistor T1 and the second thin film transistor T2 is configured to share the first thin film electric power between the first thin film transistor T1 and the second thin film transistor T2. The anode terminal (second conduction terminal) of the crystal T1 and the source terminal (first conduction terminal) of the second thin film transistor T2 are realized. Further, as shown in Fig. 26, in the present embodiment, the channel layer 13b is shared by the first thin film transistor T1 and the second thin film transistor T2, but it should be noted that it is not necessary to share the channel layer 13. Chemical. A gate insulating film 13a is formed between the channel layer 13a and the gate line GL.

By disposing the first thin film transistor T1 and the second thin film transistor T2 in series as described above, it is possible to reduce the vicinity of the first thin film transistor T1 and the second thin film transistor T2 as compared with the case where these are arranged in parallel. The area where the small source line SL and the gate line GL overlap each other (see FIGS. 26(A), 3, 13, 16, 22, and 24). Therefore, the parasitic capacitance formed between the source line SL and the gate line GL is relatively small.

In the configuration in which the first thin film transistor T1 and the second thin film transistor T2 are arranged in series, the current supplied to the second pixel electrode Epix2 via the source metal SE2 is supplied to the first via the source metal SE1. Pixel electrode The current of Epix1 can be reduced. However, by using a high mobility semiconductor such as an oxide semiconductor or a microcrystalline germanium in the channel layer 13b, it is possible to eliminate insufficient charging in the second pixel electrode Epix2 due to a decrease in current supplied through the source metal SE2. Further, in consideration of the decrease in the current supplied through the source metal SE2, the pixel capacitance of the first sub-pixel forming portion 11 (for example, Clc1+CcsA+CcsB in the first embodiment) and the second time are preferable. In the pixel capacitance of the pixel formation portion 12 (for example, Clc2 in the first embodiment), when the pixel capacitance of the first sub-pixel formation portion 11 is large, the first pixel electrode Epix1 is connected to the source metal SE1. When the pixel capacitance of the second sub-pixel forming portion 12 is large, the second pixel electrode Epix2 is connected to the source metal SE1.

<9.3 effect>

According to the present embodiment, the parasitic capacitance formed between the source line SL and the gate line GL is relatively small. Therefore, the capacitance of the source line SL is reduced, so that power consumption can be reduced. Furthermore, this embodiment can be applied to each of the above embodiments.

<10. Others>

In addition, the present invention is not limited to the above-described embodiments, and the polarity inversion drive is performed by changing the polarity of the potential at least every predetermined number (first specific number) of the image signal lines in the column direction, and the first storage capacitor CcsA and the first The connection target of the other end of each of the auxiliary capacitors CcsB is switched in the column direction for each specific number of rows. When the positive polarity display is performed, after the selection period of the gate line GL is completed, the first auxiliary capacitor CcsA and the first (2) The potential of the other end of the auxiliary capacitor CcsB changes in the direction of rising and falling, and when the negative polarity display is performed, after the selection period of the gate line GL is completed, the first auxiliary capacitor The potentials at the other ends of the CcsA and the second storage capacitor CcsB may be changed in the direction of decreasing and rising, respectively. Thereby, row inversion driving of at least a specific number of row units can be performed.

According to the above, according to the present invention, it is possible to provide a display device and a method of driving the same that have higher display quality than before and improve viewing angle characteristics.

[Industrial availability]

The present invention is applicable to a display device that divides one pixel into a plurality of sub-pixels to improve the viewing angle characteristics, and a driving method thereof.

10‧‧‧Pixel forming department

10(i,j)‧‧‧Picture formation of the i-th column

10(i,j+1)‧‧‧Picture formation of the j+1th line of the i-th column

10(i+1,j)‧‧‧i+1 column jth pixel formation

10(i+1,j+1)‧‧‧i+1 column j+1 line pixel formation

11‧‧‧First Pixel Formation Department

11(i,j)‧‧‧1st pixel formation of the i-th column

11(i,j+1)‧‧‧1st column, the first pixel formation part of the j+1th line

11(i+1,j)‧‧‧1st column, the first pixel formation part of the jth row

11(i+1, j+1) ‧‧‧ the first sub-pixel formation part of the j+1th line of the i+1th column

12‧‧‧Second Pixel Formation Department

12(i,j)‧‧‧second sub-pixel formation of the i-th column

12(i, j+1) ‧‧‧ the second pixel formation part of the j+1th line

12(i+1,j)‧‧‧2nd pixel formation of the i-th column

12(i+1, j+1) ‧‧‧ the second pixel formation part of the j+1th line of the i+1th column

13b‧‧‧channel layer

100‧‧‧Display Department

200‧‧‧ display control circuit

300‧‧‧Source Driver

400‧‧‧gate driver

500‧‧‧CS driver (auxiliary capacitor line driver circuit)

CcsA‧‧‧1st auxiliary capacitor

CcsB‧‧‧2nd auxiliary capacitor

CcsC‧‧‧3rd auxiliary capacitor (adjusting capacitor)

Ccs1A‧‧‧1st auxiliary capacitor for bright pixels

Ccs1B‧‧‧Second auxiliary capacitor for bright pixels

Ccs2A‧‧‧1st auxiliary capacitor for dark pixels (3rd auxiliary capacitor)

Ccs2B‧‧‧Second auxiliary capacitor for dark pixels (4th auxiliary capacitor)

Cgd1‧‧‧1st adjustment capacitor

Cgd2‧‧‧2nd adjustment capacitor

Clc1‧‧‧1st liquid crystal capacitor

Clc2‧‧‧2nd LCD capacitor

COM‧‧‧ common electrode

CSL1‧‧‧1st auxiliary capacitor line

CSL2‧‧‧2nd auxiliary capacitor line

CSL3‧‧‧3rd auxiliary capacitor line

Epix1‧‧‧1st pixel electrode

Epix2‧‧‧2nd pixel electrode

GL‧‧‧ gate line (scanning signal line)

GLi‧‧‧第i column gate line

GLi+1‧‧‧i+1 column gate line

SLj‧‧‧j line source line

SLj+1‧‧‧j+1 line source line

SL‧‧‧Source line (video signal line)

T1‧‧‧1st thin film transistor (first switching element)

T2‧‧‧2nd thin film transistor (2nd switching element)

Fig. 1 is a block diagram showing the overall configuration of a liquid crystal display device according to a first embodiment of the present invention.

Fig. 2 is an equivalent circuit diagram showing a configuration of a pixel formation portion in the first embodiment.

Fig. 3 is a view showing the layout in the vicinity of the pixel formation portion in the first embodiment.

Fig. 4 is a signal waveform diagram for explaining the driving method in the first embodiment.

Fig. 5 is an equivalent circuit diagram showing a configuration of a pixel formation portion in a second embodiment of the present invention.

Fig. 6 is a signal waveform diagram for explaining the driving method in the second embodiment.

Fig. 7 is an equivalent circuit diagram showing a configuration of a pixel formation portion in a third embodiment of the present invention.

Figure 8 is a view for explaining the driving method in the third embodiment. Signal waveform diagram.

FIG. 9 is an equivalent circuit diagram showing a configuration of a pixel formation portion in a fourth embodiment of the present invention.

FIG. 10 is an equivalent circuit diagram showing a configuration of a pixel formation portion in a modification of the fourth embodiment.

Fig. 11 is a signal waveform diagram for explaining a driving method in a modification of the fourth embodiment.

FIG. 12 is an equivalent circuit diagram showing a configuration of a pixel formation portion in a fifth embodiment of the present invention.

Fig. 13 is a view showing the layout in the vicinity of the pixel formation portion in the fifth embodiment.

Fig. 14 is a signal waveform diagram for explaining the driving method in the fifth embodiment.

Fig. 15 is an equivalent circuit diagram showing a configuration of a pixel formation portion in a sixth embodiment of the present invention.

Fig. 16 is a view showing the layout in the vicinity of the pixel formation portion in the sixth embodiment.

Fig. 17 is a signal waveform diagram for explaining the driving method in the sixth embodiment.

Fig. 18 is a block diagram showing the overall configuration of a liquid crystal display device of a seventh embodiment of the present invention.

Fig. 19 is an equivalent circuit diagram showing a configuration of a pixel formation portion in the seventh embodiment.

Figure 20 is a view for explaining the driving method in the seventh embodiment. Signal waveform diagram.

Fig. 21 is an equivalent circuit diagram showing a configuration of a pixel formation portion in an eighth embodiment of the present invention.

Fig. 22 is a view showing the layout in the vicinity of the pixel formation portion in the eighth embodiment.

Fig. 23 is an equivalent circuit diagram showing a configuration of a pixel formation portion in a modification of the eighth embodiment.

Fig. 24 is a view showing the layout of the vicinity of the pixel formation portion in the modification of the eighth embodiment.

Fig. 25 is an equivalent circuit diagram showing a configuration of a pixel formation portion in a ninth embodiment of the present invention.

Fig. 26 is a view for explaining the layout of the thin film transistor in the ninth embodiment. (A) is a plan view showing the layout of a thin film transistor. (B) A-A line cross-sectional view of the system (A).

Fig. 27 is an equivalent circuit diagram showing the configuration of a pixel forming portion in the conventional liquid crystal display device.

10(i,j)‧‧‧Picture formation of the i-th column

10(i,j+1)‧‧‧Picture formation of the j+1th line of the i-th column

10(i+1,j)‧‧‧i+1 column jth pixel formation

10(i+1,j+1)‧‧‧i+1 column j+1 line pixel formation

11(i,j)‧‧‧1st pixel formation of the i-th column

11(i,j+1)‧‧‧1st column, the first pixel formation part of the j+1th line

11(i+1,j)‧‧‧1st column, the first pixel formation part of the jth row

11(i+1, j+1) ‧‧‧ the first sub-pixel formation part of the j+1th line of the i+1th column

12(i,j)‧‧‧second sub-pixel formation of the i-th column

12(i, j+1) ‧‧‧ the second pixel formation part of the j+1th line

12(i+1,j)‧‧‧2nd pixel formation of the i-th column

12(i+1, j+1) ‧‧‧ the second pixel formation part of the j+1th line of the i+1th column

CcsA‧‧‧1st auxiliary capacitor

CcsB‧‧‧2nd auxiliary capacitor

Clc1‧‧‧1st liquid crystal capacitor

Clc2‧‧‧2nd LCD capacitor

COM‧‧‧ common electrode

CSL1‧‧‧1st auxiliary capacitor line

CSL2‧‧‧2nd auxiliary capacitor line

Epix1‧‧‧1st pixel electrode

Epix2‧‧‧2nd pixel electrode

GLi‧‧‧第i column gate line

GLi+1‧‧‧i+1 column gate line

SLj‧‧‧j line source line

SLj+1‧‧‧j+1 line source line

T1‧‧‧1st thin film transistor (first switching element)

T2‧‧‧2nd thin film transistor (2nd switching element)

Claims (22)

A display device, characterized in that it is an active matrix type display device, and includes a plurality of image signal lines, a plurality of scanning signal lines crossing the plurality of image signal lines, corresponding to the plurality of image signal lines, and the foregoing a plurality of pixels arranged in a matrix in a plurality of scanning signal lines, and a common electrode disposed in the plurality of pixel forming portions in common, and at least a first specific number of image signals in a direction in which the scanning signal lines extend The display device further includes: a first auxiliary capacitance line and a second auxiliary capacitance line, which are disposed in a manner corresponding to each scanning signal line, and the potentials are different from each other, and the polarity is reversed. The potential changes at least after the selection period of the scanning signal line is completed; each pixel forming portion includes: a first pixel electrode and a second pixel electrode, each of which is given a potential corresponding to an image to be displayed; and a first display capacitor, The second pixel is formed between the first pixel electrode and the common electrode, and the second display capacitor is formed by the second pixel. Between the common electrode and the first switching element, the scanning signal line is connected to the control terminal, the video signal line is connected to the first conductive terminal, and the first pixel electrode is connected to the second conductive terminal. The second switching element is connected to the second pixel. The control signal is connected to the scanning signal line, and the image signal line is connected to the first conduction terminal, and is connected to the second signal. a terminal is connected to the second pixel electrode; and a first auxiliary capacitor is formed between one of the first auxiliary capacitance line and the second auxiliary capacitance line and the first pixel electrode; and a second auxiliary capacitor And being formed between the other of the first auxiliary capacitance line and the second auxiliary capacitance line and the first pixel electrode, and having a capacitance value smaller than the first auxiliary capacitance; and being connected to the first auxiliary capacitor The other one of the first auxiliary capacitance line and the second auxiliary capacitance line and the other of the first auxiliary capacitance line and the second auxiliary capacitance line to be connected to the second auxiliary capacitance are The scanning signal line extends in the direction in which the pixel formation portion of each of the first specific numbers is switched. The display device of claim 1, wherein the first specific number is 1. The display device according to claim 2, wherein the potential of the first auxiliary capacitance line is positively displayed when the pixel formation portion including the first auxiliary capacitance connected to the first auxiliary capacitance line is positively displayed, and corresponds to the pixel formation portion When the selection period of the scanning signal line is completed, the direction of the rising is changed, and when the negative polarity display is performed, the selection period of the scanning signal line corresponding to the pixel forming portion is changed and then decreases, and the second auxiliary capacitance line is changed. When the pixel formation portion including the first storage capacitor connected to the second storage capacitor line performs positive polarity display, the potential is changed in the rising direction after the selection period of the scanning signal line corresponding to the pixel formation portion is completed. When the negative polarity display is performed, the selection period of the scanning signal line corresponding to the pixel formation portion changes to a direction of decreasing. The display device according to claim 3, wherein the potential of the first auxiliary capacitance line and the second auxiliary capacitance line is changed in a selection period of each of the second specific number of the scanning signal lines of the second specific number . The display device according to claim 4, wherein the one of the first auxiliary capacitance line and the second auxiliary capacitance line to be connected to the first auxiliary capacitor is connected to the second auxiliary capacitor The other of the first auxiliary capacitance line and the second auxiliary capacitance line is exchanged for each of the second specific number of pixel formation portions in the direction in which the video signal line extends. The display device according to claim 4, wherein the first switching element of the pixel forming portion of the plurality of pixel forming portions adjacent to the direction in which the video signal line extends is the first conductive terminal of the second switching element And the first switching element of the other pixel forming portion of the plurality of pixel forming portions and the first conductive terminal of the second switching element are respectively connected to one of two adjacent image signal lines and The other. The display device according to claim 5, wherein the first switching element of the pixel forming portion of the plurality of pixel forming portions adjacent to the direction in which the video signal line extends is the first conductive terminal of the second switching element And the first switching element of the other pixel forming portion of the plurality of pixel forming portions and the first conductive terminal of the second switching element are respectively connected to one of two adjacent image signal lines and another One. The display device of claim 4, wherein the second specific number is 1. The display device of claim 5, wherein the second specific number is 1. The display device of claim 4, wherein the second specific number is a plural number. The display device of claim 5, wherein the second specific number is a plural number. The display device of claim 1, wherein each of the pixel forming portions further includes: a third auxiliary capacitor formed on the other of the first auxiliary capacitance line and the second auxiliary capacitance line and the second pixel electrode And a fourth auxiliary capacitor formed between the one of the first auxiliary capacitance line and the second auxiliary capacitance line and the second pixel electrode, and having a capacitance value smaller than the third auxiliary capacitance. The display device of claim 1, wherein each of the pixel forming portions further includes: a third auxiliary capacitor formed between the one of the first auxiliary capacitance line and the second auxiliary capacitance line and the second pixel electrode And a fourth auxiliary capacitor formed between the other of the first auxiliary capacitance line and the second auxiliary capacitance line and the second pixel electrode, and having a capacitance value smaller than the third auxiliary capacitance. The display device of claim 1, further comprising a storage capacitor line driving circuit that independently drives the first auxiliary capacitance line and the second pixel forming portion arranged in a direction in which the image signal line extends Auxiliary capacitor line. The display device of claim 1, further comprising a third auxiliary capacitance line, which is disposed corresponding to each of the scanning signal lines, and is provided with a fixed potential, and each of the pixel forming portions further includes an adjustment capacitor, the adjustment capacitor Formed between the third auxiliary capacitance line and the second pixel electrode, and is electrically The capacitance value is set such that the potential changes of the first pixel electrode and the second pixel electrode at the end of the selection period of the scanning signal line corresponding to the pixel formation portion are substantially equal to each other. The display device of claim 1, wherein each of the pixel formation portions further includes: a first adjustment capacitor formed between the scanning signal line and the first pixel electrode; and a second adjustment capacitor formed in the second display capacitor The scan signal line is interposed between the second pixel electrode; and the capacitance value of each of the first adjustment capacitor and the second adjustment capacitor is such that the scanning signal line corresponding to the pixel formation portion is selected. At the end, the potential changes of the first pixel electrode and the second pixel electrode are set to be substantially equal to each other. The display device according to claim 1, wherein the first conductive terminal of the second switching element or the first conductive terminal of the first switching element is connected to the image via the first switching element or the second switching element Signal line. The display device according to any one of claims 1 to 17, wherein each of the first switching element and the second switching element is a thin film transistor in which a channel layer is formed by an oxide semiconductor or a microcrystalline germanium. A driving method for driving a display device of an active matrix type, the display device comprising a plurality of image signal lines, a plurality of scanning signal lines crossing the plurality of image signal lines, corresponding to the plurality of scanning signal lines a plurality of pixels arranged in a matrix in the image signal line and the plurality of scanning signal lines, and are commonly provided in the plurality of pixels a common electrode of each of the pixel forming portions, and performing polarity inversion driving at a polarity of a potential of each of the first specific number of image signal lines at least in a direction in which the scanning signal line extends, and the driving method includes: potential control a step of giving a potential different from each other to the first auxiliary capacitance line and the second auxiliary capacitance line which are provided corresponding to the respective scanning signal lines, and at least after the selection period of the scanning signal line ends Each pixel forming portion includes: a first pixel electrode and a second pixel electrode, each of which is provided with a potential corresponding to an image to be displayed; and a first display capacitor formed on the first pixel electrode and The second display capacitor is formed between the second pixel electrode and the common electrode; the first switching element is connected to the scan signal line at the control terminal, and the image is connected to the first conductive terminal. a signal line connecting the first pixel electrode to the second conductive terminal; and a second switching element connecting the scanning signal line to the control terminal at the first conductive terminal Connected to the image signal line, the second pixel electrode is connected to the second conductive terminal; the first auxiliary capacitor is formed on one of the first auxiliary capacitance line and the second auxiliary capacitance line and the first pixel electrode And a second auxiliary capacitor formed between the other of the first auxiliary capacitance line and the second auxiliary capacitance line and the first pixel electrode; And the capacitance value is smaller than the first auxiliary capacitance; and the one of the first auxiliary capacitance line and the second auxiliary capacitance line to be connected to the first auxiliary capacitance should be connected to the second auxiliary capacitance The other of the first auxiliary capacitance line and the second auxiliary capacitance line of the target is exchanged for each of the first specific number of pixel formation portions in the direction in which the scanning signal line extends. The driving method of claim 19, wherein the first specific number is 1. The driving method of claim 20, wherein in the potential controlling step, the potential applied to the first auxiliary capacitance line is controlled as follows: a pixel forming portion including a first auxiliary capacitor connected to the first auxiliary capacitance line When the positive polarity display is performed, the selection period of the scanning signal line corresponding to the pixel formation portion is changed to the direction of the rise, and when the negative polarity display is performed, the selection period of the scanning signal line corresponding to the pixel formation portion is ended. The direction of the backward direction is changed, and the potential applied to the second auxiliary capacitance line is controlled as follows: when the pixel formation portion including the first auxiliary capacitance connected to the second auxiliary capacitance line performs positive polarity display, When the selection period of the scanning signal line corresponding to the pixel formation portion is changed, the direction of the change is changed, and when the negative polarity display is performed, the selection period of the scanning signal line corresponding to the pixel formation portion is changed to a direction of decreasing. The driving method of claim 21, wherein in the potential control step, the potential of the first auxiliary capacitance line and the second auxiliary capacitance line are controlled as follows: the scanning signal lines of the second specific number are selected The selection period for each of the second specific numbers changes.