TW201332053A - Substrate sustaining platform for plasma processing apparatus - Google Patents

Abstract

The present invention provides a substrate sustaining platform which is applicable to a plasma process apparatus and for carrying substrates. The said substrates are positioned above the substrate sustaining platform, and the substrate sustaining platform comprises: a first electrode connected with a radio-frequency power source of a first frequency to generate plasma; and an electrostatic sucking disk set above the first electrode, wherein the electrostatic sucking disk includes a first dielectric layer having one or more vacuum holes set therein, a second dielectric layer which is positioned above the first dielectric and has an electrode embedded therein to generate electrostatic sucking force, and a third dielectric layer which is implanted into the first dielectric layer and has a dielectric constant different from that of the first dielectric layer. The present invention also provides a plasma processing apparatus that includes the above-mentioned substrate sustaining platform. This invention can improve edge effects, and raise the homogeneity of processes.

Description

Slide table for plasma processing apparatus

The present invention relates to the field of semiconductor manufacturing, and more particularly to a stage for a plasma processing apparatus.

The edge effect of semiconductor process parts is a problem that plagues the semiconductor industry. The edge effect of the so-called semiconductor process component means that during the plasma processing, since the plasma is controlled by the electric field, the field strength at the edge of the upper and lower poles is affected by the edge condition, and a part of the electric field line is always bent, resulting in the edge portion of the electric field. The field strength is uneven, which in turn causes the plasma concentration of the portion to be uneven. In this case, there is also a circle of uneven processing around the produced semiconductor process member. This unevenness is more obvious when the RF electric field frequency is higher. When the RF frequency is greater than 60 MHz or even greater than 100 MHz, the degree of non-uniformity of the plasma concentration is difficult to be reused by other devices such as the edge of the electrostatic chuck. Ring to regulate.

Since the semiconductor process piece is circular, the larger the outer ring area, the poor uniformity of the various process steps at the edge portion will result in a significant drop in yield. Today, the 300 mm process is commonly used, and the edge effect of semiconductor process parts is even more significant.

Therefore, the industry needs to be able to simply and effectively improve edge effects and improve process uniformity.

In view of the above problems in the prior art, the present invention proposes a stage for a plasma processing apparatus capable of improving uniformity.

A first aspect of the invention provides a method for applying to a plasma processing apparatus And a substrate carrying a substrate, wherein the substrate is located above the stage, wherein the stage comprises: a first electrode connected to a radio frequency power source having a first frequency for generating a plasma, an electrostatic chuck, located above the first electrode, wherein the electrostatic chuck comprises: a first dielectric layer in which one or more vacuum voids are disposed; and a second dielectric layer located in the first dielectric Above the layer, an electrode for generating electrostatic attraction is embedded; a third dielectric layer is implanted in the first dielectric layer, wherein the third dielectric layer and the first dielectric layer have different dielectric constants.

Optionally, the third dielectric layer is implanted in the first dielectric layer corresponding to a lower portion of the central region of the substrate, wherein a dielectric constant of the third dielectric layer is smaller than the first dielectric layer Dielectric constant.

Optionally, the one or more vacuum voids are disposed in the first dielectric layer below the central region of the substrate.

Optionally, the one or more vacuum voids are respectively disposed on the first dielectric layer corresponding to the central region and the edge region of the substrate, and an intermediate region between the central region and the edge region in.

Optionally, the one or more vacuum voids corresponding to the central region of the substrate and the one or more vacuum voids corresponding to the intermediate region of the substrate are of the same volume.

Further, the one or more voids corresponding to the central region of the substrate are connected to the one or more voids corresponding to the intermediate portion of the substrate to be integrated.

Optionally, the volume of the one or more vacuum voids corresponding to the central region of the substrate is greater than the one or more corresponding to the intermediate region of the substrate The volume of the vacuum cavity.

Further, the one or more voids corresponding to the central region of the substrate are connected to the one or more voids corresponding to the intermediate portion of the substrate to be integrated.

Wherein, the first frequency is above 13 MHz.

A second aspect of the invention also provides a plasma processing apparatus comprising the stage provided by the first aspect of the invention.

Wherein, the first frequency is above 13 MHz.

The slide table provided by the present invention and the plasma processing apparatus including the same can easily and effectively improve the edge effect and improve the process uniformity.

Specific embodiments of the present invention will be described below with reference to the accompanying drawings.

The present invention changes the equivalent capacitance between the lower electrode and the lower surface of the substrate by providing one or more voids in the dielectric between the lower electrode and the substrate of the vacuum processing apparatus, and by configuration of different dielectrics. The dielectric constant, thereby further changing the size of the equivalent capacitance, to optimize the process uniformity of the substrate.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing the structure of a stage of a vacuum processing apparatus according to an embodiment of the present invention. In a specific embodiment to be described hereinafter, the vacuum processing apparatus is in particular an etching machine. As shown in FIG. 1, the present invention provides a stage 1 for carrying a substrate W applied to a plasma processing apparatus, wherein the substrate W is positioned above the stage 1. The stage 1 includes a first electrode 13 connected to a radio frequency power source 15 having a first frequency f. It should be noted that the upper portion of the etching machine chamber further includes a second electrode (not shown) parallel to the first electrode 13, and the two are combined to generate a plasma for the process, The substrate W is subjected to an etching process.

Wherein the first electrode 13 is made of an electrical conductor material, in particular, It can be made of metal aluminum.

An electrostatic chuck, located above the first electrode 13, includes a first dielectric layer 14 in which one or more vacuum voids are disposed. The present invention has different configurations for the above one or more vacuum voids according to different technical needs, which will be specifically described below.

A second dielectric layer 11 is located above the first dielectric layer 14 and is embedded with electrodes 12. The electrode 12 is an electrode film which is connected to a direct current power source (not shown) for generating electrostatic attraction to the substrate W.

A third dielectric layer 16 is implanted in the first dielectric layer 14, wherein the third dielectric layer 16 and the first dielectric layer 14 have different dielectric constants.

In order to explain the inventive mechanism of the present invention more concisely and conveniently, it is necessary to divide the substrate into regions. It should be noted that the zoning of the substrate in the following is not actually present, but the virtual division of the substrate for the convenience of the description of the present invention is not intended to limit the present invention. Fig. 2 is a schematic view showing the area division of a substrate of the present invention. As shown in Fig. 2, it shows a top view of a horizontally placed substrate which is disc-shaped, starting from the center of the disc-shaped substrate, and setting the circular portion in the central portion. For the central region C' of the substrate, the annular region located at the periphery of the central region C' is set as the intermediate region M' of the substrate, and the annular region located at the periphery of the intermediate region M' is set as the edge of the substrate. Area E'. Referring to FIG. 1, in the first dielectric layer 14 in the electrostatic chuck, a region corresponding to the central region C' of the substrate W is a central region C corresponding to the intermediate region M' of the substrate W. The area is the intermediate area M, and the area corresponding to the edge area E' of the substrate W is the edge area E. The intermediate region M is located between the central region C and the edge region E. Since the division of the above area is not actually present, the division of the above area may be arbitrarily adjusted according to technical needs, for example, The area corresponding to the substrate area where the etching rate is reduced to a certain extent is divided into edge areas, and is not necessarily divided according to the numerical range.

The original idea of the present invention is to change the edge electric field density of the semiconductor process member by changing the parasitic capacitance between the cavity and the upper electrode, and the edge effect of the semiconductor process component is improved. That is to say, the electric field at the edge of the semiconductor process piece can be redistributed by adjusting the parasitic capacitance between the plasma edge and the cavity. In general, there are three factors that affect the value of this parasitic capacitance, namely, the relative area of the edge of the upper electrode and the cavity, the distance between the edge of the upper electrode and the cavity, and the equivalent dielectric of the space between the plasma edge and the cavity. constant. Once the plasma processing chamber is fabricated, it is obvious that the relative area of the upper electrode edge to the cavity and the distance between them are fixed, and the relationship between the parasitic capacitance and the electric field distribution is complicated, and different RF energy inputs are also affected. This relationship, and considering the technical feasibility, it is difficult to pre-calculate and fabricate a vacuum reaction chamber having an appropriately sized parasitic capacitance.

Therefore, the only thing that is likely to change is the equivalent dielectric constant of the plasma to the cavity relative space, which is the equivalent dielectric constant of the first dielectric layer described above. The present invention is based on such considerations that the equivalent dielectric constant of the space is adjusted to achieve a suitable parasitic capacitance, such that the electric field is redistributed, thereby making the plasma processing effect of the semiconductor process piece uniform.

As shown in FIG. 1, in conjunction with FIG. 2, the third dielectric layer 16 is implanted in the first dielectric layer 14 corresponding to a lower portion of the central region of the substrate W, wherein the third dielectric layer 16 is The dielectric constant is less than the dielectric constant of the first dielectric layer 14.

The first electrode 13 and the substrate W are regarded as three equivalent capacitors Cc, Cm, and Ce according to the central region C, the intermediate region M, and the edge region E, respectively, wherein the first dielectric layer 14 serves as the equivalent capacitance. The medium, therefore, according to the capacitance formula: C = εS / 4πkd, where ε is the dielectric constant and d is the distance.

Thus, in the present embodiment, since the cavity H11 is disposed in the central region C of the first dielectric layer 14 below the central region where the etching rate is high, the dielectric in the central region C is made closer to the periphery thereof. The intermediate region M and the edge region E have less dielectric, that is, the dielectric constant of the equivalent capacitance Cc of the central region C is lowered, thereby causing the equivalent capacitance Cc to decrease, thereby further causing the radio frequency connected to the first electrode 13 The power source 15 is capable of reaching a reduction in the central region C of the substrate, thereby reducing the amount of plasma generated per unit time in the central region of the substrate, thereby reducing the activity of interaction between the generated plasma and the substrate, and ultimately reducing the substrate. The etch rate of the central region. Moreover, since the dielectric constant of the third dielectric layer 16 is smaller than the first dielectric layer 14, that is, the dielectric constant of the equivalent capacitance Cc of the central region C is further lowered, thereby optimizing the process uniformity of the substrate. .

Wherein the one or more vacuum voids may also be respectively disposed on the first dielectric layer corresponding to the central region and the edge region of the substrate, and an intermediate region between the central region and the edge region. in.

Optionally, the one or more vacuum voids disposed in a central region corresponding to the substrate are the same volume as the one or more vacuum voids disposed in an intermediate region corresponding to the substrate. Referring to FIG. 3, in the present embodiment, the volume of the cavity H21 is equal to the volume of the cavity H22, whereby the etching rate of the central region C' and the intermediate region M' of the substrate W can be lowered, so that the edge region E of the substrate W is The etch rate is phase-shifted to compensate for the edge effect of the substrate W.

The one or more holes H21 corresponding to the central region of the substrate are connected to the one or more holes H22 corresponding to the intermediate portion of the substrate to be integrated.

Optionally, the one or more of the central regions corresponding to the substrate are disposed The volume of the vacuum voids is greater than the volume of the one or more vacuum voids disposed in the intermediate region of the substrate. As shown in FIG. 4, in the present embodiment, the volume of the cavity H31 is larger than the volume of the cavity H32, so that the etching rate of the substrate W can be performed according to the central region C', the intermediate M', and the edge region E', respectively. Gradually adjust. Specifically, since the volume of the vacuum cavity H31 located in the central region C is the largest, the etching rate corresponding to the central region C' of the substrate W is lowered most. Secondly, since the volume of the vacuum cavity H32 located in the intermediate portion M is smaller than the vacuum cavity H31, the etching rate corresponding to the intermediate portion M' of the substrate W is also lowered, but it must be lower than the corresponding base. The etch rate of the central region C' of the sheet W. Again, since no vacuum cavity is provided in the edge region E corresponding to the edge region E' of the substrate W in this embodiment, the etching rate is not adjusted. Therefore, the above control makes the etching rate corresponding to the central region C' of the substrate W the lowest, and the etching rate corresponding to the intermediate portion M' of the substrate W is slightly higher than that of the central portion C' corresponding to the substrate W. The etch rate is the highest, and the etch rate corresponding to the edge region E' of the substrate W is the highest. The edge effect is compensated to further optimize the process uniformity.

The one or more voids H31 corresponding to the central region of the substrate are connected to the one or more voids H32 corresponding to the intermediate portion of the substrate to be integrated.

It should be noted that those skilled in the art can understand that the present invention further includes several variations to the foregoing embodiments. For example, one or more holes may be disposed at positions corresponding to the central area, the intermediate area, and the edge area of the substrate. And by arranging dielectric layers having different dielectric constants at corresponding positions in the central region, the intermediate region, and the edge region of the substrate, as long as the etch rate of the central region is the lowest, the intermediate region is second, and the edge region is the highest to etch the edge. The effect is compensated to achieve the object of the invention.

Further, the first frequency f is 13 MHz or more, preferably 60 MHz or more, or even 100 MHz.

Further, the first dielectric layer is cylindrical.

The present invention also provides a plasma processing apparatus including the aforementioned stage.

Further, the first frequency is above 13 MHz, preferably above 60 MHz, or even 100 MHz.

Further, the first dielectric layer is cylindrical.

The dielectric material to which the present invention is applied may be selected from the group consisting of quartz (Quarz), ceramic (Ceramic), and polytetrafluoroethylene (Tefflon). Among them, the quartz has a dielectric constant of 3.58, the polytetrafluoroethylene has a dielectric constant of 2.55, and the ceramic has a dielectric constant of 3. The present invention can be provided with the above-mentioned dielectric materials according to the size in different regions as needed. For example, a polytetrafluoroethylene having a minimum dielectric constant can be disposed in a central region, and quartz or ceramic can be disposed in other regions.

Referring to Fig. 5, the center of the substrate is taken as the origin, the diameter of the substrate is plotted on the horizontal axis, and the coordinate axis is determined as the Y axis. Wherein, S1 is an etch rate curve of the substrate obtained by applying the prior art carrier table, and it can be seen that the etching rate in the central region around the center of the circle is higher, and the etching rate is reduced in the middle region thereof. The edge region has the lowest etch rate, which necessarily has the defect of uniformity. S2 and S3 correspond to an etch rate curve of a substrate obtained by applying the stage provided by the present invention. Wherein, S2 only implements the invention corresponding to the central region of the substrate, and it can be seen that the etching rate of the central region is significantly reduced. S3 implements the invention for both the central region and the intermediate region of the substrate, and the etching rates of the central region and the intermediate region are all reduced. Thus, the advantages of the present invention are demonstrated, and the present invention can improve edge effects quickly and efficiently, and achieve process uniformity.

Although the content of the present invention has been described in detail through the above preferred embodiments However, it should be understood that the above description should not be taken as limiting the invention. Various modifications and alterations of the present invention will be apparent to those skilled in the art. Therefore, the scope of the invention should be limited by the scope of the appended claims.

1‧‧‧Slide

11‧‧‧Second dielectric layer

12‧‧‧ electrodes

13‧‧‧First electrode

14‧‧‧First dielectric layer

15‧‧‧RF power supply

16‧‧‧ Third dielectric layer

C‧‧‧Central area

C’‧‧‧Central Area

E‧‧‧Edge area

E’‧‧‧Edge area

H11‧‧‧ hollow

H21‧‧‧ hollow

H22‧‧‧ hollow

H31‧‧‧ hollow

H32‧‧‧ hollow

M‧‧‧Intermediate area

M’‧‧‧ intermediate area

S1‧‧‧etch rate curve

S2‧‧‧etch rate curve

S3‧‧‧etch rate curve

W‧‧‧ substrates

1 is a schematic view showing the structure of a stage of a vacuum processing apparatus according to a preferred embodiment of the present invention; FIG. 2 is a schematic view showing the area division of the substrate of the present invention; and FIG. 3 is a view of the vacuum processing apparatus of the first embodiment of the present invention. FIG. 4 is a schematic view showing the structure of a stage of a vacuum processing apparatus according to a second embodiment of the present invention; and FIG. 5 is a schematic view showing the effect of the invention.

1‧‧‧Slide

11‧‧‧Second dielectric layer

12‧‧‧ electrodes

13‧‧‧First electrode

14‧‧‧First dielectric layer

15‧‧‧RF power supply

16‧‧‧ Third dielectric layer

C‧‧‧Central area

E‧‧‧Edge area

H11‧‧‧ hollow

M‧‧‧Intermediate area

W‧‧‧ substrates

Claims (11)

A stage for a substrate for a plasma processing apparatus, wherein the substrate is located above the stage, the stage comprises: a first electrode connected to a radio frequency power source having a first frequency For generating a plasma; an electrostatic chuck located above the first electrode, wherein the electrostatic chuck comprises: a first dielectric layer in which one or more vacuum holes are disposed; and a second dielectric layer located at the first An electrode for generating electrostatic attraction is embedded above the dielectric layer, and a third dielectric layer is implanted in the first dielectric layer, wherein the third dielectric layer and the first dielectric layer have different dielectric constants. The stage according to claim 1, wherein the third dielectric layer is implanted in the first dielectric layer below the central region of the substrate, wherein the dielectric of the third dielectric layer The constant is less than the dielectric constant of the first dielectric layer. The stage of claim 2, wherein the one or more vacuum voids are disposed in the first dielectric layer below the central region of the substrate. The stage according to claim 2, wherein the one or more vacuum voids are respectively disposed in a central region and an edge region corresponding to the substrate, and in the middle between the central region and the edge region. In the first dielectric layer of the region. The stage of claim 4, wherein the one or more vacuum voids corresponding to a central region of the substrate and the one or more vacuum voids corresponding to an intermediate region of the substrate the same. The stage as claimed in claim 5, wherein the one or more voids corresponding to the central portion of the substrate are connected to the one or more voids corresponding to the intermediate portion of the substrate. The stage according to claim 4, wherein the volume of the one or more vacuum holes corresponding to the area in the center of the substrate is larger than the one or more vacuum holes corresponding to the intermediate portion of the substrate. volume of. The stage according to claim 7, wherein the one or more voids corresponding to the central region of the substrate are connected to the one or more voids corresponding to the intermediate portion of the substrate to be integrated. . The stage according to any one of claims 1 to 8, wherein the first frequency is 13 MHz or more. A plasma processing apparatus comprising the stage as described in any one of claims 1 to 8. The plasma processing apparatus of claim 10, wherein the first frequency is 13 MHz or more.