TW201329597A - Liquid crystal displays having pixels with embedded fringe field amplifiers - Google Patents

Abstract

A multi-domain liquid crystal display is disclosed. The display includes embedded fringe field amplifiers behind the color dots of the display. Specifically, the embedded fringe field amplifiers have a polarity that is different from the polarity of the color dot, that is located in front of the embedded fringe field amplifier. This difference in polarity enhances the fringe fields of the color dot or in some situations may create additional fringe fields. The enhanced fringe fields or additional fringe fiends enhances the performance of the display.

Description

Liquid crystal display having a pixel including a buried discrete field amplifier

The present invention relates to a liquid crystal display, and more particularly to a large pixel multi-region vertical alignment liquid crystal display that can be fabricated on a smooth substrate.

The liquid crystal display (LCD), which is used for the first time in simple monochrome displays such as computers and electronic watches, has become the most advantageous display technology. Liquid crystal displays are often used to replace the use of cathode ray tubes (CRTs) in computer displays and television displays. Various shortcomings of liquid crystal displays have been overcome to improve the quality of liquid crystal displays. For example, active matrix displays that widely replace passive matrix displays have reduced ghosting and improved resolution, color gradation, viewing angle, and contrast relative to passive matrix displays. (Contrast Ratio) and the effect of response time (Response Time).

However, the main drawback of conventional twisted nematic LCDs is the very narrow viewing angle and very low contrast. Even the perspective of the active matrix is narrower than the viewing angle of the cathode ray tube. Especially when the viewer directly views a high-quality image directly in front of the liquid crystal display, other high-quality images cannot be seen by other viewers beside the liquid crystal display. Multi-domain Vertical Alignment Liquid Crystal Display (MVA LCD) has been developed to improve the viewing angle and contrast of liquid crystal displays. Please refer to FIG. 1(a)-1(c) for showing the basic functions of a pixel of a vertical alignment liquid crystal display 100. For clarity of illustration, the liquid crystal display of Figure 1 uses only a single domain (Single Domain). Furthermore, for clarity of explanation, the liquid crystal display of FIGS. 1(a)-1(c) (and FIG. 2) is described in terms of gray scale operation.

The liquid crystal display 100 has a first polarizer 105, a first substrate 110, a first electrode 120, a first alignment layer 125, a plurality of liquid crystals 130, a second alignment layer 140, and a second electrode. 145, a second substrate 150 and a second polarizer 155. In general, the first substrate 110 and the second substrate 150 are made of transparent glass. The first electrode 120 and the second electrode 145 are made of a transparent conductive material such as Indium Tin Oxide (ITO). The first alignment layer 125 and the second alignment layer 140 are made of polyimide (PI) and are aligned perpendicularly to the liquid crystal 130 in a stationary state. In operation, a light source (not shown) emits light from a first polarizer 105 attached to the underlying substrate 110. The first polarizer 105 is generally polarized in a first direction, and the second polarizer 155 attached to the second substrate 150 is vertically polarized with the first polarizer 104. Therefore, the light from the light source does not penetrate the first polarizer 105 and the second polarizer 155 at the same time unless the polarization of the light is rotated by 90 degrees between the first polarizer 105 and the second polarizer 155. For the sake of clarity, many liquid crystals are not shown. In an actual display, the liquid crystal is rod like molecules having a diameter of about 5 angstroms (Angstrom, Å) and a length of about 20-25 angstroms. Therefore, there are more than 12 million liquid crystal molecules in one pixel, wherein the length, width and height of the pixels are 300 micrometers (micrometers), 120 micrometers, and 3 micrometers, respectively. Although not shown, many liquid crystal displays, especially active matrix liquid crystal displays, include a passivation layer on the bottom of the first electrode 120. The passivation layer serves as an insulating layer between the first electrode 120 and the device and conductor that may be formed on the substrate. The passivation layer is typically formed using tantalum nitride.

In Fig. 1, the liquid crystal 130 is vertically aligned. In the vertical alignment, the liquid crystal 130 does not divert the polarized aurora from the light source. Therefore, the light from the light source does not pass through the liquid crystal display 100, and provides a completely optical black state and a very high contrast for all colors and all cell gaps. (contrast ratio). Therefore, the multi-zone vertical alignment liquid crystal display provides a significant improvement in comparison with the conventional low contrast twisted nematic liquid crystal display. However, as shown in FIG. 1(b), when an electric field is applied between the first electrode 120 and the second electrode 145, the liquid crystal 130 is redirected to a tilted position. The liquid crystal in the tilted position turns the polarization of the polarized light from the first polarizer 105 by 90 degrees so that the light can pass through the second polarizer 155. And the slope is large Small, that is, controlling the amount of light passing through the liquid crystal display (such as the brightness of the pixels) is proportional to the electric field strength. In general, a single thin film transistor is used on each pixel. For color displays, however, individual thin film electro-crystal systems are used in each color component (typically, green and blue).

However, for viewers of different angles, the light passing through the liquid crystal display 120 is not the same. As shown in FIG. 1(c), the viewer 172 on the left side of the center will see a bright pixel because the side of the liquid crystal display 130 that is wide (light turning) faces the viewer 172. The centrally located viewer 174 will see gray pixels because the wide side of the liquid crystal display 130 is only partially facing the viewer 174. The viewer 176 located on the right side of the center will see the dark pixel because the wide side of the liquid crystal display 130 barely faces the viewer 176.

Multi-region vertical alignment liquid crystal displays (MVA LCDs) have been developed to improve the viewing angle of single-domain vertical alignment LCDs. Referring to FIG. 2, a pixel of a multi-region vertical alignment liquid crystal display (MVA LCDs) 200 is shown. The multi-zone vertical alignment liquid crystal display 200 includes a first polarizer 205, a first substrate 210, a first electrode 220, a first alignment layer 225, a plurality of liquid crystals 235, 237, a plurality of protrusions 260, and a second alignment. The layer 240, a second electrode 245, a second substrate 250, and a second polarizer 255. The liquid crystal 235 forms a first domain of pixels, and the liquid crystal 237 forms a second domain of pixels. When an electric field is applied between the first electrode 220 and the second electrode 245, the protrusion 260 causes the liquid crystal 235 to be tilted in a different direction with respect to the liquid crystal 237. Therefore, the center-left viewer will see that the left area (liquid crystal 235) appears black and the right area (liquid crystal 237) appears white. Viewers in the center will see two areas at the same time and appear gray. The center-right viewer will see the left area appear white and the right area appear black. However, because the individual pixels are small, all three viewers consider the pixels to be gray. As described above, the magnitude of the tilt of the liquid crystal is controlled by the magnitude of the electric field between the electrodes 220 and 245. The gray level perceived by the viewer is related to the tilt of the liquid crystal. Multi-zone vertical alignment LCDs can also be expanded to use four areas for liquid crystal orientation in one pixel It is divided into four main areas to provide a wide and symmetrical viewing angle in both the vertical and horizontal directions.

Therefore, a multi-region vertical alignment liquid crystal display that provides a wide and symmetrical viewing angle is very expensive, because of the difficulty in adding protrusions to the upper and lower substrates, and the difficulty in properly aligning the protrusions to the upper and lower substrates. In particular, a protrusion on the lower substrate must be placed in the center of the two protrusions of the upper substrate; any alignment between the upper and lower substrates will reduce the production yield. Other techniques that use physical properties on the substrate, such as ITO slits that have been used to replace or bond protrusions, are very expensive to manufacture. Furthermore, the protrusions and the indium tin oxide gap cannot transmit light, and thus reduce the contrast and contrast ratio of the multi-region vertical alignment liquid crystal display.

However, multi-region vertical alignment liquid crystal displays that do not require the use of physical features (e.g., protrusions or indium tin oxide gaps) on the substrate have been developed. In particular, the multi-region vertical alignment liquid crystal displays use discrete fields to form multiple regions. The difficulty of aligning the physical features of the top and bottom substrates will be eliminated without the need for physical features. Therefore, a multi-region vertical alignment liquid crystal display using discrete fields has higher yield and lower manufacturing cost than a multi-region vertical alignment liquid crystal display using physical features on a substrate.

Referring to Figures 3(a) and 3(b), there is shown a schematic diagram of a multi-region vertical alignment liquid crystal display (MVA LCD) 300 in accordance with the basic concepts of the present invention without the use of physical characteristics on the substrate. 3(a) and 3(b) show pixels 310, 320 and 330 between a first substrate 305 and a second substrate 355. A first polarizer 302 is adhered to the first substrate 305, and a second polarizer 357 is adhered to the second substrate 355. The pixel 310 includes a first electrode 311, a plurality of liquid crystals 312, 313, and a second electrode 315. The pixel 320 includes a first electrode 321, a plurality of liquid crystals 322, 323, and a second electrode 325. Similarly, the pixel 330 includes a first electrode 331, a plurality of liquid crystals 332, 333, and a second electrode 335. All electrodes are generally constructed using a transparent conductive material such as indium tin oxide (ITO). Furthermore, a first alignment layer 307 is overlying the electrodes on the first substrate 305. Similarly, a second alignment layer 352 is covered in the second Above the electrodes on the substrate 355. The two liquid crystal alignment layers 307 and 352 provide a vertical liquid crystal alignment. For the more detailed description below, electrodes 315, 325, and 335 are maintained at a common voltage V_Com. Therefore, for ease of fabrication, the electrodes 315, 325, and 335 are of a single structure (as shown in Figures 3(a) and 3(b)). The multi-zone vertical alignment liquid crystal display 300 uses alternating polarization to operate the pixels 310, 320, and 330. For example, if the polarization of pixels 310 and 330 is positive, then the polarization of pixel 320 is negative. Conversely, if the polarization of pixels 310 and 330 is negative, the polarization of pixel 320 is positive. In general, the polarization of each pixel is switched between frames, but alternately patterned patterns are maintained in each page frame. In Fig. 3(a), pixels 310, 320, and 330 are in an "OFF" state, that is, an electric field between the first and second electrodes is turned off. In the off state, some residual electric field may exist between the first and second substrates. However, in general, the residual electric field is too small to tilt the liquid crystal.

In FIG. 3(b), the pixels 310, 320, and 330 are in an "ON" state. In Fig. 3(b), "+" and "-" are used to represent the voltage polarity of the electrode. Therefore, the electrodes 311 and 331 have a positive voltage polarity, and the electrode 321 has a negative voltage polarity. The substrate 355 and the electrodes 315, 325, and 335 are maintained at a common voltage V_Com. The voltage polarity is defined with respect to the common voltage V_Com, wherein a positive polarity is higher than the common voltage V_Com, and a negative polarity is lower than the common voltage V_Com. The electric field 327 (indicated by the power line) between the electrodes 321 and 325 causes the liquid crystals 322 and 323 to tilt. In general, without protrusions or other physical properties, the tilt direction of the liquid crystal is not fixed by the liquid crystals in a vertical liquid crystal alignment layer 307 and 352. However, the discrete electric field at the edge of the pixel affects the tilt direction of the liquid crystal. For example, the electric field 327 between the electrodes 321 and 325 is vertically centered around the pixel 320, but is tilted to the left of the left half of the pixel and to the right of the right half of the pixel. Therefore, the discrete electric field between the electrodes 321 and 325 causes the liquid crystal 323 to tilt to the right to form a first region, and causes the liquid crystal 322 to tilt to the left to form a second region. Therefore, the pixel 320 is a multi-region pixel having a symmetric wide viewing angle.

Similarly, the electric field (not shown) between electrodes 311 and 315 has a discrete electric field that causes liquid crystal 313 to reposition and tilt to the right of the right side of pixel 312, also causing liquid crystal 312 to tilt to the pixel. 310 left to the left of the test. Similarly, the electric field (not shown) between electrodes 331 and 335 has a discrete electric field that causes liquid crystal 333 to reposition and tilt to the right of the right side of pixel 330, also causing liquid crystal 332 to tilt to the pixel. 330 left to the left of the test.

The alternating polarity of adjacent pixels amplifies the fringe field effect of each pixel. Therefore, by repeating the alternating polarity pattern between the pixels of each column (or the pixels of each column), a multi-region vertical alignment liquid crystal display can be achieved without physical properties. Furthermore, alternating polarity checkerboard patterns can be used to create four regions per pixel.

However, in general, the discrete field effect system is relatively small and weak. Therefore, when the pixels become larger, the discrete electric field at the edge of the pixel cannot be transmitted to all the liquid crystals in one pixel. Therefore, in the large pixel, the tilt direction of the liquid crystal far from the edge of the pixel is arbitrarily changed, and a multi-region pixel is not generated. In general, when the pixel becomes larger than 40-60 micrometers (micrometer, μm), the discrete field effect of the pixel does not affect the control liquid crystal tilt. Therefore, for large pixel liquid crystal displays, a novel pixel distinction method is used to achieve multi-region pixels. Especially for color liquid crystal displays, the pixels are distinguished by the color component. Each color component is controlled by a separate switching device such as a thin-film transistor (TFT). In general, the color components are red, green, and blue. According to the invention, the color component of a pixel is further distinguished by color dots.

The polarity of each pixel is switched between each successive page of the image to avoid degradation of image quality, and the quality of the image is reduced because the liquid crystal is distorted in the same direction in each page frame. However, if all of the switching elements are of the same polarity, the color point polarity pattern switching may cause other image quality problems such as flicker. In order to reduce flicker, switching elements (such as transistors) are arranged in a switching element drive mode, which includes positive and negative polarity. Furthermore, in order to reduce cross talk, the positive and negative polarities of the switching element are arranged in a fixed pattern which provides a more stable power distribution. Different switching element drive modes are used In an embodiment of the invention. There are three main switching element driving modes, which are switching element point inversion driving scheme, switching element row inversion driving scheme, and switching element row inversion driving mode. (switching element column inversion driving scheme). In the switching element dot inversion driving mode, the switching elements form a checkerboard pattern of alternating polarity. In the switching element column inversion driving mode, the switching elements in each column have the same polarity; however, one switching element in one column has opposite polarities with respect to the polarity of the switching elements of adjacent columns. In the switching element row inversion driving mode, the switching elements in each row have the same polarity; however, one switching element on one row has opposite polarities with respect to the polarity of the switching elements of adjacent rows. When the switching element dot inversion driving mode provides the most stable power distribution, the complexity of the switching element dot inversion driving mode and the additional cost are compared with the switching element column inversion driving mode and the switching element row inversion driving mode. It is not cost-effective. Therefore, when the switching element dot inversion driving mode is generally maintained in high performance applications, the switching element column inversion driving mode is used for the manufacture of liquid crystal displays for most low cost and low voltage applications.

The (new) pixels can include various key components that are configured to achieve a high quality, low cost display unit. For example, a pixel may include a color component, a color dot, a fringe field amplifying region (FFAR), a switching element, and a device component area. And associated dots. A display using these various components is described in the following patent document: US Patent No. "Large Pixel Multi-Domain Vertical Alignment Liquid Crystal Display Using Fringe Fields" U.S. Patent Application Serial No. 11/751,454, entitled "Pixels Using Associated Dot Polarity for Multi-Domain Vertical Alignment Liquid Crystal Displays", No. 7, 630, 033, Named "Pixels Having Polarity Extension Regions For Multi-Zone Vertical Alignment LCDs" U.S. Patent Application Serial No. 12/018,675, entitled "Multi-Domain Vertical Alignment Liquid Crystal Displays", and "Pixels having a Fringe Field for a Multi-Zone Vertical Alignment Liquid Crystal Display with a Cross-Position Discrete Field Magnification Area" Amplifying Regions for Multi-Domain Vertical Alignment Liquid Crystal Displays, Inc., U.S. Patent Application Serial No. 12/573,085, the disclosure of which is incorporated herein by reference.

This device component area contains areas occupying switching elements and/or storage capacitors, and this area is used to fabricate switching elements and/or storage capacitors. For clarity of illustration, a different device component area is defined by each switching element.

The associated point and the discrete field amplification region are electrically polarized regions and are not part of the color component. In many embodiments of the invention, the associated points cover the device component area. For these embodiments, the associated points are made by depositing an insulating layer over the switching elements and/or storage capacitors. Next, the associated points are formed by depositing an electrically conductive layer. This associated point is electrically connected to a particular switching element and/or other polarizing element (eg, a color point). The storage capacitor is electrically connected to a specific switching element and color dot electrodes to compensate and offset the liquid crystal cell during the switching-on or switching off process of the liquid crystal cell. The capacitance value on the change. Therefore, the storage capacitor is used to reduce the cross talk effect during the process of turning the cell on or off. A patterned mask is used when the associated point needs to form a patterned electrode. In general, a black matrix layer is attached to form a light shield for color points, switching elements, DCA, and associated points. In general, black matrix layers are black, however some displays use different colors to achieve a desired color pattern or shading. A color layer is attached to give the desired color to the color point. In general, the color layer is obtained by depositing a color filter layer on the corresponding ITO glass substrate. Specifically, a patterned color filter layer is deposited between the second substrate 355 and the second electrodes 315, 325, and 335, and the pattern corresponds to the color of the color point and the associated point. However, some displays may also place a patterned color filter layer on top or bottom of the following substrate 305: switching components, colors Electrode layer, associated point, or DCA.

In other embodiments of the invention, the associated point is an area that is independent of the switching element. Moreover, certain embodiments of the present invention have additional points of association that are not directly related to the switching elements. In general, the associated points include an active electrode layer such as indium tin oxide (ITO) or other conductive layer and are connected to a nearby color point or powered by other means. For opaque associated points, a black matrix layer can be attached to the bottom of the conductive layer to form an opaque area. In some embodiments of the invention, a black matrix can be fabricated on the indium tin oxide (ITO) glass substrate side to simplify the fabrication process. Additional points of association improve the effective use of the display area, thereby improving the aperture ratio and forming a plurality of liquid crystal domains within the color point. Certain embodiments of the present invention use association points to improve color performance. For example, a careful placement of associated points may allow the colors of nearby color points to be modified from useful color patterns.

Discrete field amplification regions (FFARs) are more versatile than associated points. In particular, the discrete field magnifying region may have a non-rectangular shape, although in general the overall shape of the magenta field magnified region may be divided into a rectangular shape group. Furthermore, the discrete field amplification region extends along one side of more than one color point. Moreover, in some embodiments of the invention, discrete field amplification regions may be used in place of associated points. In particular, in these embodiments, the discrete field magnified region not only covers the device component region, but also extends along more than one color dot side of the adjacent device component region.

In general, the color point, the device component area, and the associated dots are arranged in a lattice pattern and are spaced apart from each other by a horizontal dot pitch HDS and a vertical dot pitch VDS. When a discrete field amplification region is used in place of the associated point, portions of the discrete field amplification region are also adapted to the lattice pattern. In some displays, multiple horizontal dot pitches can be used with multiple vertical dot pitches. Each color point, associated point, and device component area has two adjacent components (eg, color point, associated point, or device component area) in a first dimension (eg, a vertical dimension), and in a second dimension ( For example, there are two adjacent components in the horizontal). In addition, two adjacent components may be aligned or offset. Each The color point has a color point height CDH and a color point width CDW. Similarly, each associated point has an associated point height ADH and an associated point width ADW. In addition, each device component area has a device component area height DCAH and a device component area width DCAW. In some displays, the color point, associated point, and device component area have the same size. However, in many displays, the color points, associated points, and device component areas can have different sizes or shapes. For example, in many displays, the height of the associated point is less than the height of the color point.

With the popularity of portable devices with higher performance, there is an increasing need to achieve higher pixel density in liquid crystal displays, because portable devices are generally more screens than liquid crystal displays for televisions or computer monitors. Close to the eyes of a user. However, the high pixel density requires a smaller pixel, which can result in a decrease in brightness because the size of many device components in a liquid crystal display cannot be reduced as much as the pixel size reduction. In addition, the distance between various device components in a pixel or color point will occupy a larger percentage of the surface area of the display. In addition, many mobile devices include touch screens for user input. The touch screen device can cause a liquid crystal display panel to touch the touch mura effect, which is caused by the physical disturbance of the liquid crystal. Touching the moiré effect means that the irregular pattern or area causes uneven screen uniformity. The physical disturbance of the liquid crystal can be caused by shaking, vibration, and pressing on the display. In particular, vertical alignment liquid crystal displays are very susceptible to touch moiré effects due to pressing on the display. In particular, pressing on a vertical alignment liquid crystal display can locally flatten the thickness of the liquid crystal and create an interference effect on the display. Accordingly, there is a need for a method or system for minimizing the spacing between various components to increase optical transmission, and a method or system for reducing the touch moiré effect in a vertical alignment liquid crystal display. .

Accordingly, the present invention provides a vertical alignment liquid crystal display having a higher pixel density and a reduced touch moiré effect. In particular, embodiments of the present invention use a novel pixel design with color points having buried polarity regions (EPR) for amplifying discrete fields, and discrete fields for enhancing multiple regions. Vertical alignment operation and faster recovery of the liquid crystal to its correct position. Moreover, embodiments of the present invention include buried discrete field amplifiers that are capable of amplifying discrete fields without the need for a wide area to achieve a high optical transmission. In addition, the optical transmittance of each embodiment of the present invention is increased, and higher brightness can be obtained while reducing the electric power consumption of the backlight unit.

For example, in accordance with some embodiments of the present invention, a pixel includes a first color component, a first switching element, and a buried discrete field amplifier. The first color component has a first color component first color point, and the first color component first color point is coupled to the first switching element. The first embedded discrete field amplifier is located after the first color point of the first color component. More specifically, the first edge of the first color component and the first edge of the first color point are located in front of the first embedded discrete field amplifier. The pixel also includes a second color component having a second color component first color point, the second color component first color point being coupled to a second switching element. The first color point has a first edge and a second edge, and the first edge and the second edge are located in front of the first embedded discrete field amplifier. In other embodiments of the invention, the first buried discrete field amplifier is for the first color component and a second buried discrete field amplifier is used with the second color component. Specifically, the second buried discrete field amplifier is located behind the first color point of the second color component. At least one first edge and a second edge of the first color point of the second color component are located in the second embedded discrete Field amplifier front.

In still other embodiments of the invention, the buried discrete field amplifier includes a vertical buried portion and a horizontal buried portion. For example, in some embodiments of the present invention, a pixel includes: a first color component having a first color component and a first color component; and a first switching component coupled to the first color component a first color point; and a first buried discrete field amplifier having a first vertical buried portion and a first horizontal buried portion. The first vertical embedding portion is located behind a first edge of the first color point of the first color component, and the first horizontal embedding portion is located behind a second edge of the first color point of the first component. The first buried discrete field amplifier can include additional horizontal buried portions and additional vertical buried portions. For example, in an embodiment of the present invention, the first embedded discrete field amplifier further includes a second vertical buried portion and a second horizontal embedded portion, wherein the second vertical embedded portion is located at the first One of the first color points is behind the third edge, and the second horizontal embedding portion is located behind the fourth edge of the first color point of the first color component.

The invention will be more fully understood from the following description and drawings.

As described above, the conventional vertical alignment liquid crystal display has a limited optical transmittance, and is highly susceptible to a moiré effect due to physical disturbance of the liquid crystal. However, vertical alignment liquid crystal displays in accordance with the principles of the present invention use buried discrete field amplifiers that achieve a higher aperture ratio to increase optical transmittance. In addition, the embedded discrete field amplifier enhances the multi-region vertical alignment operation and reduces the touch moiré effect by enhancing the lateral discrete field, which in turn helps to enhance multi-region vertical alignment operation and also helps to make the liquid crystal in a physical Return to its correct orientation after the disturbance. Therefore, the vertical alignment liquid crystal display according to the present invention has an improved optical transmittance and can quickly eliminate the touch moiré effect caused by the physical disturbance of the liquid crystal.

4(a) and 4(b) show different dot polarity patterns of a pixel design 410 (labeled 410+ and 410- as described below) in accordance with an embodiment of the present invention. In practice, one pixel will be in each An image frame is switched between a first dot polarity pattern and a second dot polarity pattern. For the sake of clarity, a dot pattern in which the first color point of the first color component has a positive polarity is referred to as a positive dot polarity pattern. In contrast, a dot polarity pattern in which the first color point of the first color component has a negative polarity is referred to as a negative dot polarity pattern. Specifically, in FIG. 4(a), the pixel design 410 has a positive dot polarity pattern (hence labeled 410+), and in FIG. 4(b), the pixel design 410 has a negative point. Polar pattern (hence labeled as 410-). Further, in various pixel designs, the polarity of each polarization component is represented by "+" for positive polarity or "-" for negative polarity.

The pixel design 410 has three color components CC_1, CC_2, and CC_3. Each of the three color components contains a color point. For the sake of clarity, the color points are represented as CD_X_Y, where X is a one-color component (from 1 to 3 in Figures 4(a)-4(b)), and Y is a color point number (in the figure) Y is always 1) in 4(a)-4(b). The pixel design 410 also includes a switching element (denoted as SE_1, SE_2, and SE_3) for each color component, and a device component area (denoted DCA_1, DCA_2, and DCA_3) for each color component. The switching elements SE_1, SE_2 and SE_3 are arranged in a row. The device component areas DCA_1, DCA_2, and DCA_3 surround the switching elements SE_1, SE_2, and SE_3, respectively.

The first color component CC_1 of the pixel design 410 has a color point CD_1_1. The color point CD_1_1 is horizontally aligned with the device component area DCA_1 and vertically spaced apart from the device component area DCA_1 by a vertical dot pitch VDS1. The switching element SE_1 is coupled to the electrode of the color point CD_1_1 to control the polarity of the color point CD_1_1. The color point CD_1_1 includes a buried polarity area EPR_1_1_1. For clarity, the buried polarity region is represented as EPR_X_Y_Z, where X is a one-color component, Y is a color point number, and the Z-series is in a buried polarity region in a color point. The buried polar regions can have different shapes. For example, in the pixel design 410, the buried polar region has a rectangular shape. However, other embodiments may have a square shape, a circular shape, a polygonal shape (eg, a quadrangle and a hexagon), or even other irregular shapes.

In general, polarity refers to the direction of polarity, which is generally marked as positive or negative. More specifically, the polarity also includes a polarity. The buried polar region may have the same polarity direction as the color point but have a different polarity. Further, the buried polar region may have a polarity different from that of the color point (ie, "polarity direction") (for example, the color point polarity is positive polarity, and the buried polarity region has negative polarity). Further, the buried polar region may have a neutral polarity. The invention Different embodiments use a variety of different novel techniques or combinations of novel techniques to form buried polar regions in color points. These techniques are described in detail below. In the embodiment of Figures 4(a) and 4(b), the color point has an opposite polarity to the buried polarity region located in the color point.

The second color component CC_2 of the pixel design 410 has a color point CD_2_1. The color point CD_2_1 is horizontally aligned with the device component area DCA_2 and vertically spaced apart from the device component area DCA_2 by a vertical dot pitch VDS1. The color point CD_2_1 is vertically aligned with the color point CD_1_1, and is horizontally spaced apart from the color point CD_1_1 by a horizontal dot pitch HDS1. The switching element SE_2 is coupled to the electrode of the color point CD_2_1 to control the polarity of the color point CD_2_1. The color point CD_2_1 includes a buried polarity area EPR_2_1_1.

The third color component CC_3 of the pixel design 410 has a color point CD_3_1. The color point CD_3_1 is horizontally aligned with the device component area DCA_3 and vertically spaced apart from the device component area DCA_3 by a vertical dot pitch VDS1. The color point CD_3_1 is vertically aligned with the color point CD_2_1, and is horizontally spaced apart from the color point CD_2_1 by a horizontal dot pitch HDS1. The switching element SE_3 is coupled to the electrode of the color point CD_3_1 to control the polarity of the color point CD_3_1. The color point CD_3_1 contains a buried polarity area EPR_3_1_1.

Use the "+" and "-" symbols to display the color point, the buried polarity area, and the polarity of the switching element. Therefore, in FIG. 4(a) in which the dot polarity pattern of the pixel design 410+ is displayed, the switching elements SE_1 and SE_3, the color points CD_1_1 and CD_3_1, and the buried polarity region EPR_2_1_1 have positive polarity. However, the switching element SE_2, the color point CD_2_1, and the buried polarity regions EPR_1_1_1 and EPR_3_1_1 have negative polarity.

5(a) and 5(b) illustrate a color point 500 in accordance with an embodiment of the present invention. The color point 500 includes a square shaped electrode 510 having a square shaped buried polarity region 512. Fig. 5(b) is a cross-sectional view of the color point 500 taken along the line A1-A1 shown in Fig. 5(a). As shown in FIG. 5(b), the buried polarity region 512 is formed by embedding the electrode 516 under one of the electrodes 510. The buried electrode 516 and the electrode 510 are separated by a passivation layer 514. The buried electrode 516 is electrically charged to create an electric field across the electrode 510. In most embodiments of the invention, electrode 510 and buried electrode 516 have opposite polar orientations. For example, when the electrode 510 has a positive polarity, the buried electrode 516 will have a negative polarity. However, in some embodiments of the invention, the buried electrode system is maintained at a common voltage V_com. The interaction of the electric field generated by the electrode 510 and the buried electrode 516 forms a lateral force, a lateral force Multi-zone vertical alignment operation can be enhanced and the liquid crystal can be redirected to its correct position more quickly after a physical disturbance.

Figure 5(c) illustrates another technique for forming a buried polar region that can be combined with a buried electrode. Specifically, in FIG. 5(c), a changed conductive regions 518 are formed in the electrodes 510 located in the buried polarity region 512. In one embodiment of the invention, the electrically conductive regions are altered to be heavily doped to reduce the conductivity of the electrically conductive regions. In other embodiments of the invention, the altered conductivity regions can be formed by etching portions of the conductor 510 and using, for example, an electroactive polymer (eg, polyacetylene, polythiophene, polypyrrole (PPY) A lower conductivity material such as polyaniline (PANI) and polystyrene), tantalum and aluminum gallium arsenide or a non-conductive material (for example, cerium oxide) is used to fill the regions. The electric field in the buried polar region is different from the electric field around the rest of the electrode 510 due to the different conductivity in the altered conductivity region.

In the embodiment of FIG. 5(c), the altered conductivity region 518 is made non-conductive such that the electric field in the buried polarity region 512 is primarily controlled by the buried electrode 516. The interaction of the electrodes 510 with the electric field generated by the buried electrode 516 creates a lateral force that enhances the multi-zone vertical alignment operation and also redirects the liquid crystal to its correct position more quickly after a physical disturbance.

Figures 6(a)-6(b) illustrate portions of a color point 600 in accordance with another embodiment of the present invention. The color point 600 includes a square shaped electrode 610 having a square shaped buried polarity region 612. However, electrode 610 does not extend into buried polarity region 612. In the embodiment of FIG. 6(a), electrode 610 is etched to form a void in buried polarity region 612. In other embodiments of the invention, the electrode system is formed with voids.

Fig. 6(b) is a cross-sectional view of the color point 600 taken along the line A1-A1 shown in Fig. 6(a). As shown in FIG. 6(b), the buried polarity region 612 is formed by embedding the electrode 616 under one of the electrodes 610. The buried electrode 616 and the electrode 610 are separated by a passivation layer 614. In the embodiment of FIG. 6(b), passivation layer 614 is etched to form a void in buried polarity region 612. In other embodiments of the invention, passivation layer 614 does not contain voids. The buried electrode 616 is electrically charged to create an electric field through one of the spaces in the electrode 610. In most embodiments of the invention, electrode 610 and buried electrode 616 have opposite polar orientations. For example, when the electrode 610 has a positive polarity, the buried electrode 616 will have a negative polarity. The interaction of the electric field generated by the electrode 610 and the buried electrode 616 forms a lateral force, and the lateral force enhances the multi-area vertical alignment operation, and is also The liquid crystal is redirected to its correct position more quickly after a physical disturbance.

As described above, an intrinsic fringe field can be used to form a multi-region. However, the essentially discrete field is only suitable for small color points. Therefore, for larger displays, the pixels are formed with color components that contain many color points. Each color component is controlled by a separate switching element (e.g., a thin-film transistor (TFT)). In general, the color components are red, green, and blue. According to the invention, the color components of a pixel are further divided into color points. Figures 7(a)-7(b) show one pixel design with multiple color points for each color component in accordance with the present invention, the colored dots including buried polar regions. Specifically, FIGS. 7(a) and 7(b) show different dot polarity patterns of a pixel design 710 (labeled as 710+ and 710- as described below), and the pixel design 710 is often used to have one. The switching element column is reversed in the display mode of the drive mode. In actual operation, a pixel will switch between a first dot polarity pattern and a second dot polarity pattern between each image frame. For the sake of clarity, a dot pattern in which the first color point of the first color component has a positive polarity is referred to as a positive dot polarity pattern. In contrast, a dot polarity pattern in which the first color point of the first color component has a negative polarity is referred to as a negative dot polarity pattern. Specifically, in FIG. 7(a), the pixel design 710 has a positive dot polarity pattern (hence labeled 710+), and in FIG. 7(b), the pixel design 710 has a negative point. Polar pattern (hence labeled as 710-). Further, in various pixel designs, the polarity of each polarization component is represented by "+" for positive polarity or "-" for negative polarity. However, in certain embodiments of the invention, certain conductors may be held at the common electrode V_com, thereby having a neutral polarity.

The pixel design 710 has three color components CC_1, CC_2, and CC_3 (not shown in Figures 7(a)-7(b)). Each of the three color components includes a two color point. For the sake of clarity, the color points are represented as CD_X_Y, where X is a one-color component (from 1 to 3 in Figures 7(a)-7(b)), and Y is a color point number (in the figure) 7(a)-7(b) is from 1 to 2). The pixel design 710 also includes a switching element (denoted as SE_1, SE_2, and SE_3) for each color component, and a discrete field amplification region (denoted as FFAR_1, FFAR_2, and FFAR_3) for each color component. The switching elements SE_1, SE_2 and SE_3 are arranged in a row. The device component area surrounding each of the switching elements is covered by a discrete field amplification area and is therefore not specifically labeled in Figures 7(a) and 7(b). The discrete field amplification regions FFAR_1, FFAR_2, and FFAR_3 are also arranged in a column, and will be described in detail in FIG. 7(c).

The first color component CC_1 of the pixel design 710 has two color points CD_1_1 and CD_1_2. color The dots CD_1_1 and CD_1_2 form a line and are spaced apart by a vertical dot pitch VDS1. In other words, the color points CD_1_1 and CD_1_2 are horizontally aligned and vertically spaced by the vertical dot pitch VDS1. Further, the color point CD_1_1 and the CD_1_2 are vertically shifted by the vertical dot offset VDO1, and the vertical dot offset VDO1 is equal to the vertical dot pitch VDS1 plus the color point height CDH. The switching element SE_1 is located between the color points CD_1_1 and CD_1_2 such that the color point CD_1_1 is located on a first side of the column switching element, and the color point CD_1_2 is located on a second side of the column switching element. The switching element SE_1 is coupled to the electrodes of the color points CD_1_1 and CD_1_2 to control the voltage polarity and voltage of the color points CD_1_1 and CD_1_2.

Each color point of the color component CC_1 includes a buried polarity region that minimizes any touch moiré effects in the color point. Specifically, the color points CD_1_1 and CD_1_2 respectively include buried polarity areas EPR_1_1 and EPR_1_2. As shown in FIG. 7(a), the buried polar regions EPR_1_1 and EPR_1_2 are respectively centered in the color points CD_1_1 and CD_1_2. In the pixel design 710, the buried polarity region is formed using the buried conductor technique shown in Figs. 6(a)-6(b). However, in order to reduce the complexity of the drawing, as in the general drawing of Fig. 5(a), the buried polar region is illustrated by a hatched square. However, other embodiments of the present invention may use other techniques to form the buried polarity region, may include multiple buried polarity regions, or may bias the buried polarity regions.

As described above, the polarity of the buried polarity region is different from the polarity of the color point. Therefore, the polarities of the buried polarity regions EPR_1_1 and EPR_1_2 are controlled by a polarity source different from the switching element SE_1 which controls the polarities of the color points CD_1_1 and CD_1_2. In some embodiments of the invention, a display includes a dedicated buried polarity region switching element to control the polarity of the buried polarity region (see Figure 7(d) for one such embodiment). Other embodiments of the invention may couple the buried polar regions to other elements of the pixel having a different polarity. For example, in some embodiments of the invention, the buried polarity regions EPR_1_1 and EPR_1_2 are coupled to discrete field amplification regions FFAR_1 as described below.

Similarly, the second color component CC_2 of the pixel design 710 has two color points CD_2_1 and CD_2_2. The color points CD_2_1 and CD_2_2 form a second line and are spaced apart by a vertical dot pitch VDS1. Therefore, the color points CD_2_1 and CD_2_2 are horizontally aligned and vertically spaced apart by the vertical dot pitch VDS1. The switching element SE_2 is located between the color points CD_2_1 and CD_2_2 such that the color point CD_2_1 is located on the first side of the column switching element, and the color point CD_2_2 is located on the second side of one of the column switching elements. The switching element SE_2 is coupled to the electrodes of the color points CD_2_1 and CD_2_2, To control the voltage polarity and voltage of the color points CD_2_1 and CD_2_2. The second color component CC_2 is vertically aligned with the first color component CC_1, and is spaced apart by a horizontal dot pitch HDS1 and the color component CC_1. Therefore, the color components CC_2 and CC_1 are horizontally shifted by a horizontal point offset HDD1, the horizontal point. The offset HDD1 is equal to the horizontal dot pitch HDS1 plus the color dot width CDW. Specifically, regarding the color point, the color point CD_2_1 and the color point CD_1_1 are vertically aligned and horizontally spaced by the horizontal dot pitch HDS1. Similarly, the color point CD_2_2 is vertically aligned with the color point CD_1_2 and horizontally spaced by the horizontal dot pitch HDS1. Therefore, the color point CD_1_1 and the color point CD_2_1 form a first column color point, and the color point CD_1_2 and the color point CD_2_2 form a second column color point. Like the color point CD_1_1 and the color point CD_1_2, the color point CD_2_1 and the color point CD_2_2 respectively include the buried polarity areas EPR_2_1 and EPR_2_2.

Similarly, the third color component CC_3 of the pixel design 710 has two color points CD_3_1 and CD_3_2. The color points CD_3_1 and CD_3_2 form a third line and are spaced apart by a vertical dot pitch VDS1. Therefore, the color points CD_3_1 and CD_3_2 are horizontally aligned and vertically spaced apart by the vertical dot pitch VDS1. The switching element SE_3 is located between the color points CD_3_1 and CD_3_2 such that the color point CD_3_1 is located on the first side of the column switching element, and the color point CD_3_2 is located on the second side of one of the column switching elements. The switching element SE_3 is coupled to the electrodes of the color points CD_3_1 and CD_3_2 to control the voltage polarity and voltage of the color points CD_3_1 and CD_3_2. The third color component CC_3 is vertically aligned with the second color component CC_2, and is spaced apart from the color component CC_2 by the horizontal dot pitch HDS1, so that the color components CC_3 and CC_2 are horizontally shifted by a horizontal dot offset amount HDO1. Specifically, with respect to the color point, the color point CD_3_1 and the color point CD_2_1 are vertically aligned and horizontally spaced by the horizontal dot pitch HDS1. Similarly, the color point CD_3_2 is vertically aligned with the color point CD_2_2 and horizontally spaced by the horizontal dot pitch HDS1. Therefore, the color point CD_3_1 is located on the first column color point, and the color point CD_3_2 is located on the second column color point. Like the color point CD_1_1 and the color point CD_1_2, the color point CD_3_1 and the color point CD_3_2 respectively include the buried polarity areas EPR_3_1 and EPR_3_2.

For the sake of clarity, the color points of the pixel design 710 are illustrated with color points having the same color point height CDH. However, certain embodiments of the invention may include color points having different color point heights. For example, in one embodiment of the present invention, which is a variant of the pixel design 710, the color point heights of the color points CD_1_1, CD_2_1, and CD_3_1 are smaller than the color point heights of the color points CD_1_2, CD_2_2, and CD_3_2. . Moreover, in many embodiments of the invention, the color points may have different shapes shape.

The pixel design 710 also includes discrete field amplification regions FFAR_1, FFAR_2, and FFAR_3. Figure 7(c) shows a more detailed view of one of the discrete field amplification regions FFAR_1 of the pixel design 710. For the sake of clarity, the discrete field amplification region FFAR_1 is conceptually divided into a vertical amplification portion VAP and a horizontal amplification portion HAP. In FIG. 7(c), the horizontal amplifying portion HAP is vertically centered on the vertical amplifying portion VAP and extends to the left side of the vertical amplifying portion VAP. The placement of the discrete field amplification region FFAR_1 can be more clearly explained by using the horizontal amplification portion and the vertical amplification portion. In most embodiments of the invention, the electrodes of the discrete field amplification region are formed from one continuous conductor. The horizontal amplifying portion HAP has a horizontal amplifying portion width HAP_W and a horizontal amplifying portion height HAP_H. Similarly, the vertical amplifying portion VAP has a vertical amplifying portion width VAP_W and a vertical amplifying portion height VAP_H. The discrete field amplification areas FFAR_2 and FFAR_3 have the same shape as the discrete field amplification area FFAR_1. In embodiments of the invention having different sized color points, the horizontal magnification portion HAP will be located between the color points rather than centered on the vertical magnification portion VAP.

As shown in FIG. 7(a), the discrete field amplification areas FFAR_1, FFAR_2, and FFAR_3 are placed between the color points of the pixel design 710. Specifically, the discrete field amplification area FFAR_1 is placed such that the horizontal amplification portion of the discrete field amplification area FFAR_1 is located between the color points CD_1_1 and CD_1_2, and is spaced apart from the color points CD_1_1 and CD_1_2 by a vertical discrete field amplification area spacing VFFARS. . The vertical amplification portion of the discrete field amplification area FFAR_1 is placed to the right of the color points CD_1_1 and CD_1_2, and is spaced apart from the color points CD_1_1 and CD_1_2 by a horizontal discrete field amplification area spacing HFFARS. Therefore, the discrete field amplification area FFAR_1 extends along the bottom and right sides of the color point CD_1_1 and along the top and right sides of the color point CD_1_2. In addition, the placement method also causes the vertical amplification portion of the discrete field amplification area FFAR_1 to be located between the color points CD_1_1 and CD_2_1 and between the color points CD_1_2 and CD_2_2.

Similarly, the discrete field amplification region FFAR_2 is placed such that the horizontal amplification portion of the discrete field amplification region FFAR_2 is located between the color points CD_2_1 and CD_2_2, and is spaced apart from the color points CD_2_1 and CD_2_2 by a vertical discrete field amplification region spacing VFFARS. The vertical amplification portion of the discrete field amplification region FFAR_2 is placed to the right of the color points CD_2_1 and CD_2_2, and is spaced apart from the color points CD_2_1 and CD_2_2 by a horizontal discrete field amplification region spacing HFFARS. Therefore, the discrete field amplification area FFAR_2 extends along the bottom and right sides of the color point CD_2_1 and along the top and right sides of the color point CD_2_2. This placement also enables the discrete field amplification area FFAR_2 The vertical enlargement portion is located between the color points CD_2_1 and CD_3_1 and between the color points CD_2_2 and CD_3_2.

The discrete field amplification area FFAR_3 is placed such that the horizontal amplification portion of the discrete field amplification area FFAR_3 is located between the color points CD_3_1 and CD_3_2, and is spaced apart from the color points CD_3_1 and CD_3_2 by a vertical discrete field amplification area spacing VFFARS. The vertical amplification portion of the discrete field amplification region FFAR_3 is placed to the right of the color points CD_3_1 and CD_3_2, and is spaced apart from the color points CD_3_1 and CD_3_2 by a horizontal discrete field amplification region spacing HFFARS. Therefore, the discrete field amplification area FFAR_3 extends along the bottom and right sides of the color point CD_3_1 and along the top and right sides of the color point CD_3_2.

Use the "+" and "-" symbols to display the color point, the discrete field amplification area, and the polarity of the switching element. Therefore, in FIG. 7(a) in which the dot polarity pattern of the pixel design 710+ is displayed, all the switching elements (ie, the switching elements SE_1, SE_2, and SE_3) and all the color points (ie, the color points CD_1_1, CD_1_2) , CD_2_1, CD_2_2, CD_3_1, and CD_3_2) have positive polarity. However, all of the discrete field amplification regions (ie, the discrete field amplification regions FFAR_1, FFAR_2, and FFAR_3) have a negative polarity. As noted above, the buried polar regions can have the same polarity direction (i.e., positive or negative) as the color dots but have a different polarity. Alternatively, the buried polar region may have a polarity other than the color point (ie, the polarity direction) (eg, the color point polarity is positive polarity and the buried polarity region has negative polarity). Additionally, the buried polar regions can have a neutral polarity. In a particular embodiment of the invention, each of the buried polar regions of the pixel design 710 has a polarity different from the color point. Therefore, for this embodiment, the buried polarity regions EPR_1_1, EPR_1_2, EPR_2_1, EPR_2_2, EPR_3_1, and EPR_3_2 will have a negative polarity in FIG. 7(a).

Figure 7(b) shows a pixel design 710 with a negative dot polarity pattern. For a negative dot polarity pattern, all switching elements (ie, switching elements SE_1, SE_2, and SE_3) and all color points (ie, color points CD_1_1, CD_1_2, CD_2_1, CD_2_2, CD_3_1, and CD_3_2) have negative polarity. However, all of the discrete field amplification regions (ie, the discrete field amplification regions FFAR_1, FFAR_2, and FFAR_3) have positive polarity. In a particular embodiment of the invention, each of the buried polar regions of the pixel design 710 has a polarity different from the color point, and the buried polar regions EPR_1_1, EPR_1_2, EPR_2_1, EPR_2_2, EPR_3_1, and EPR_3_2 are in FIG. 7(b). Lieutenant will have positive polarity.

If adjacent components have opposite polarities, the discrete fields in each color point will be amplified. The pixel design 710 utilizes discrete field amplification regions to enhance and stabilize the formation of multiple regions in the liquid crystal structure. One In general, the polarity of the polarization component is specified such that adjacent polarization components of a color point of a first polarity have a second polarity. For example, for the positive dot polarity pattern of the pixel design 710 (Fig. 7(a)), the color point CD_2_2 has a positive polarity. However, adjacent polarization components (discrete field amplification regions FFAR_2 and FFAR_1) have a negative polarity. Therefore, the discrete field of the color point CD_2_2 is amplified. Further, as described below, the polarity inversion mode is also performed at the display level, so that the color point of another pixel placed next to the color point CD_1_2 will have a negative polarity (see FIG. 7(d)).

Since all of the switching elements in pixel design 710 have the same polarity and the discrete field amplification regions require opposite polarities, the discrete field amplification region is comprised of an external polarity source (ie, one of the polar sources from a particular pixel of pixel design 710). )drive. Various sources of opposite polarity can be used in accordance with various embodiments of the present invention. For example, a particular discrete field amplification region switching element can be used, or a switching element having an opposite point polarity of a neighboring pixel can also be used to drive the discrete field amplification region. In the embodiment of Figures 7(a)-7(b), the discrete field amplification regions can also be driven using switching elements of adjacent pixels having opposite polarity. Thus, the pixel design 710 includes conductors to assist in coupling the discrete field amplification regions to switching elements in other pixels. Specifically, one of the current pixels 712 couples the electrodes of the discrete field amplification area FFAR_1 to the switching element SE_1 located above the current pixel (see FIGS. 7(d) and 7(e). ). The connection to the switching element is achieved via the electrode of the color point of the pixel above the current pixel. Similarly, one of the current pixels 714 couples the electrodes of the discrete field amplification region FFAR_2 to a switching element SE_2 located at one pixel above the current pixel (see Figure 7(d)). The connection to the switching element is achieved via the electrode of the color point of the pixel above the current pixel. A conductor 716 of a current pixel couples the electrodes of the discrete field amplification region FFAR_3 to a switching element SE_3 of one pixel above the current pixel (see FIGS. 7(d) and 7(e)). The connection to the switching element is achieved via the electrode of the color point of the pixel above the current pixel.

The connections are better shown in Figure 7(d), and Figure 7(d) shows a portion of a display 720 that uses the pixels P(0,0), P of the pixel design 710 ( 1,0), P(0,1), and P(1,1) and use a switching element column inversion driving mode. Display 720 can have thousands of columns with thousands of pixels on each column. The columns and rows will be successively arranged from the portion shown in Fig. 7(d) in the manner shown in Fig. 7(d). For the sake of clarity, the gate line and the source line for controlling the switching elements are omitted in FIG. 7(d). Furthermore, in order to better illustrate each pixel, the area of each pixel is shaded, and this shadow is used for illustration purposes only in FIG. 7(d) and does not have a functional meaning. The pixels of display 720 are arranged such that all pixels in a column have the same point polarity pattern (positive or negative), and each successive column should be in a positive dot polarity pattern and a negative dot polarity pattern. Alternate. Therefore, the pixels P(0,0) and P(1,0) in the first column (ie, column 0) have a positive dot polarity pattern, and the pixel P in the second column (ie, column 1) (0, 1) and P (1, 1) have a negative dot polarity pattern. However, in the next page box, the pixels will switch the dot polarity pattern. Therefore, in general, a pixel P(x, y) has a first dot polarity pattern when y is an even number and a second dot polarity pattern when y is an odd number. Inner conductors 712, 714, and 716 in pixel design 710 provide a polar to discrete field amplification region. Specifically, the discrete field amplification region of the first pixel receives voltage polarity and voltage magnitude from a second pixel. Specifically, the second pixel is a pixel located above the first pixel. For example, the electrode of the discrete field amplification region FFAR_1 of the pixel P(0,0) is coupled to the pixel P(0,1) via the electrode of the color point CD_1_2 of the pixel P(0,1). Element SE_1. Similarly, the electrodes of the discrete field amplification regions FFAR_2 and FFAR_3 of the pixel P(0,0) are respectively coupled to the pixel P(0,1) via the color points CD_2_2 and CD_3_2 of the pixel P(0,1). Switching elements SE_2 and SE_3.

Display 720 also includes a buried polarity area switching element EPR_SE_X_Y for each column buried polarity region. In Fig. 7(d), "X" indicates the column number of the pixel, and "Y" indicates the column number of the buried polarity region in one pixel. Therefore, the buried polar region switching elements EPR_SE_0_1 and EPR_SE_0_2 are used for the pixels in the column 0 (ie, the pixels P(0, 0) and the pixels P(1, 0)). Specifically, the buried polarity region switching element EPR_SE_0_1 is coupled to the buried polarity regions EPR_1_1, EPR_2_1, and EPR_3_1 of the pixel P(0, 0) and the buried polarity region EPR_1_1 of the pixel P(1, 0), EPR_2_1, and EPR_3_1. The buried polarity region switching element EPR_SE_0_2 is coupled to the buried polarity regions EPR_1_2, EPR_2_2, and EPR_3_2 of the pixel P(0,0) and the buried polarity regions EPR_1_2, EPR_2_2, and EPR_3_2 of the pixel P(1,0). . Similarly, the buried polar region switching elements EPR_SE_1_1 and EPR_SE_1_2 are used for the pixels in the column 1 (ie, the pixels P(0, 1) and the pixels P(1, 1)). Specifically, the buried polarity region switching element EPR_SE_1_1 is coupled to the buried polarity regions EPR_1_1, EPR_2_1, and EPR_3_1 of the pixel P(0, 1) and the buried polarity region EPR_1_1 of the pixel P(1, 1), EPR_2_1, and EPR_3_1. The buried polarity region switching element EPR_SE_1_2 is coupled to the buried polarity regions EPR_1_2, EPR_2_2, and EPR_3_2 of the pixel P(0,1) and the buried polarity regions EPR_1_2, EPR_2_2, and EPR_3_2 of the pixel P(1,1). . In general, A buried polarity area switching element has a different polarity than a switching element in a pixel corresponding to the buried polarity area switching element. Therefore, in FIG. 7(d), the buried polar region switching elements EPR_SE_0_1 and EPR_SE_0_2 will have a negative polarity. On the contrary, the buried polar region switching elements EPR_SE_1_1 and EPR_SE_1_2 will have positive polarity. In some embodiments of the invention, the buried polar area switching elements will be placed in a more balanced manner. For example, in one particular embodiment of the invention, one half of the buried polar area switching element is placed on the right side of the display and the other half of the buried polarity area switching element is placed on the left side of the display. In some embodiments of the invention, the number of buried polar region switching elements can be reduced by using a single buried polarity region switching element for each column of pixels. Specifically, the buried polarity area switching elements EPR_SE_0_1 and EPR_SE_0_2 are reduced to one buried polarity area switching element EPR_SE_0, and the buried polarity area switching element EPR_SE_0 is used for the pixels in the column 0 (ie, pixel P (0, 0) ) and pixels P(1,0)). The buried polarity region switching element EPR_SE_0 is coupled to the buried polarity regions EPR_1_1, EPR_2_1, EPR_3_1, EPR_1_2, EPR_2_2, and EPR_3_2 of the pixel P(0, 0) and the buried polar region of the pixel P(1, 0). EPR_1_1, EPR_2_1, EPR_3_1, EPR_1_2, EPR_2_2, and EPR_3_2. In addition, the buried polarity area switching elements EPR_SE_1_1 and EPR_SE_1_2 are reduced to one buried polarity area switching element EPR_SE_1, and the buried polarity area switching element EPR_SE_1 is used for the pixels in column 1 (ie, pixel P(0, 1) and Pixel P(1,1)). The buried polar region switching element EPR_SE_1 is coupled to the buried polar regions EPR_1_1, EPR_2_1, EPR_3_1, EPR_1_2, EPR_2_2, and EPR_3_2 of the pixel P(0, 1) and the buried polar region of the pixel P(1, 1). EPR_1_1, EPR_2_1, EPR_3_1, EPR_1_2, EPR_2_2, and EPR_3_2.

Since there is polarity switching on each column in display 720, if a color point has a first polarity, then any adjacent polarization components and buried polarity regions will have a second polarity. For example, the color point CD_3_2 of the pixel P(0,1) has a negative polarity, and the buried polarity region EPR_3_2 of the pixel P(0,1), the color point CD_3_1 of the pixel P(0,0), The discrete field amplification regions FFAR_2 and FFAR_3 of the prime P(0, 1) have positive polarity. In a particular embodiment of the invention, each color point has a width of one of 40 microns and a height of one of 60 microns. Each buried polar region has a width of one of 6 microns and a height of one of 6 microns. Each discrete field amplification region has a vertical magnification portion width of 5 microns, a vertical magnification portion height of 145 microns, a horizontal magnification portion width of 50 microns, and a horizontal magnification portion height of 5 microns. Horizontal point spacing HDS1 is 15 microns, vertical point spacing VDS1 The system is 25 micrometers, the horizontal discrete field amplification region spacing is HFFARS is 5 microns, and the vertical discrete field amplification region spacing VFFARS is 5 microns.

In another embodiment of the invention, a switching element of a neighboring pixel is used instead of having a buried polarity region switching element to bias the buried polar region. Figure 7(e) shows a portion of a display 730 that uses the pixels P(0,0), P(1,0), P(0,1), and P of the pixel design 710. 1,1) and use a switching element column inversion drive mode. Display 730 can have thousands of columns with thousands of pixels on each column. The columns and rows will be successively arranged from the portion shown in Fig. 7(e) in the manner shown in Fig. 7(e). For the sake of clarity, the gate lines and source lines for controlling the switching elements are omitted in Figure 7(e). Furthermore, in order to better illustrate each pixel, the area of each pixel is shaded. This shadow is used for illustration purposes only in Figure 7(e) and is not functional. Due to space constraints, the color point is labeled CDXY (cf. CD_X_Y) and the buried polarity region is labeled EPRXY (cf. to EPR_X_Y).

Since display 730 is very similar to display 720, only the differences are explained in detail. For example, the pixels of display 730 are arranged in the same manner as the pixels of display 720. In addition, the polarity of the color point, the switching element, and the discrete field amplification region are the same. Thus, as in display 720, in display 730, a pixel P(x, y) has a first dot polarity pattern when y is even and a second dot polarity pattern when y is odd. The main difference between display 720 and display 730 is that the polarity of the buried polarity region in display 730 is provided from the switching elements of adjacent pixels rather than from the dedicated buried polarity area switching elements used in display 720.

In the display 730, a first pixel is paired with a second pixel, and the buried polarity region of the first pixel is coupled to the switching element of the second pixel, and the second pixel is buried. The polar region is coupled to the switching element of the first pixel. Specifically, each pixel on the even column is paired with a pixel in an odd column above the even column. Therefore, in Fig. 7(e), the pixel P(0,0) is paired with the pixel P(0,1), and the pixel P(1,0) is paired with the pixel P(1,1). . In general, if Y is an even number, one pixel P(X, Y) is paired with one pixel P(X, Y+1). Conversely, if Y is an odd number, one pixel P(X, Y) is paired with pixel P(X, Y1).

As shown in FIG. 7(e), in the display 730, each buried polar region is coupled to the paired pixel by a conductor C_I_J_X_Y (labeled as CIJXY in FIG. 7(e) due to space constraints). A switching element, wherein I and J represent pixels containing a buried polar region (eg, pixel P (I, J)), X is a color component, and Y is a color point in a pixel (for example, a color point CD_X_Y (abbreviated as CDXY in Fig. 7(e)). For example, the conductor C0112 couples the buried polarity region EPR12 of the pixel P(0, 1) to the switching element SE_1 of the pixel P(0, 0). The conductors used to embed the polar regions are shown in dashed lines to indicate that the isotropic system is in a plane different from the color point. Typically, indium tin oxide is used to form a color point in a first plane, and a metal layer is used to form a conductor in a second plane.

As described above, in a pixel located on an odd column, a buried polarity region of a first pixel is coupled to a switching element of a pixel located below the first pixel. For example, the buried polarity region EPR_2_2 of the pixel P(0,1) (labeled as EPR22 in FIG. 7(e)) is coupled by the conductor C_0_1_2_2 (labeled as C0122 in FIG. 7(e)). Switching element SE_2 to pixel P(0,0). Similarly, the buried polarity region EPR_2_1 of the pixel P(0,1) (labeled EPR21 in FIG. 7(e)) is coupled to the conductor C_0_1_2_1 (labeled C0121 in FIG. 7(e)). Switching element SE_2 of pixel P(0,0). In general, when J is an odd number, a conductor C_I_J_X_Y couples the buried polarity region EPR_X_Y of one pixel P(I, J) to the switching element SE_X of the pixel P(I, J1).

In a pixel located on an even column, a buried polar region of a first pixel is coupled to a switching element of a pixel located above the first pixel. For example, the buried polarity region EPR_2_2 of the pixel P(0,0) (labeled as EPR22 in FIG. 7(e)) is coupled by the conductor C_0_0_2_2 (labeled as C0022 in FIG. 7(e)). Switching element SE_2 to pixel P(0,1). Similarly, the buried polarity region EPR_2_1 of the pixel P(0,0) (labeled EPR21 in FIG. 7(e)) is coupled to the conductor C_0_0_2_1 (labeled as C0021 in FIG. 7(e)). Switching element SE_2 of pixel P(0,1). In general, when J is an even number, a conductor C_I_J_X_Y couples the buried polarity region EPR_X_Y of one pixel P(I, J) to the switching element SE_X of the pixel P(I, J+1).

As noted above, in display 730, adjacent pixel columns have opposite polarities. Thus, by providing a polarity from the switching elements in adjacent pixels to the buried polarity region (as described above), the polarity of the buried polarity region is different from the polarity of the color point. This different polarity is used to enhance the discrete fields in the color point, thus enhancing multi-region vertical alignment operation and mitigating the touch moiré effect in display 730.

Figure 7(f) shows another embodiment of the invention in which the buried polar region receives polarity from the discrete field amplification region. Specifically, FIG. 7(f) shows a portion of a display 740 that uses pixels P(0,0), P(1,0), P(0,1) of the pixel design 710. ), and P(1,1) And use a switching element column inversion drive mode. Display 740 can have thousands of columns with thousands of pixels on each column. The columns and rows will be successively arranged from the portion shown in Fig. 7(f) in the manner shown in Fig. 7(f). For the sake of clarity, the gate lines and source lines for controlling the switching elements are omitted in Figure 7(f). Furthermore, in order to better illustrate each pixel, the area of each pixel is shaded, and this shadow is used for illustration purposes only in FIG. 7(f) and does not have a functional meaning. Due to space constraints, the color point is labeled CDXY (cf. CD_X_Y) and the buried polarity region is labeled EPRXY (cf. EPR_X_Y).

Since display 740 is very similar to display 720, only the differences are explained in detail. For example, the pixels of display 740 are arranged in the same manner as the pixels of display 720. In addition, the polarity of the color point, the switching element, and the discrete field amplification region are the same. Thus, as in display 720, in display 740, a pixel P(x,y) has a first dot polarity pattern when y is even and a second dot polarity pattern when y is odd. The main difference between display 720 and display 740 is that the polarity of the buried polarity region in display 740 is provided from the discrete field amplification region rather than from the dedicated buried polarity region switching element used in display 720.

Specifically, as shown in FIG. 7(f), in the display 740, each buried polar region is coupled to the nearest discrete field amplification region. Specifically, one of the pixels P(I, J) embedding the polar region EPR_X_Y is coupled to the discrete field amplification region by a conductor C_I_J_X_Y (labeled as CIJXY in FIG. 7(f) due to space limitation) FFAR_X, where I and J represent pixels (for example, pixels P(I, J)), X is a color component, and Y represents a color point in a pixel (for example, a color point CD_X_Y (in Figure 7 (f ) is abbreviated as CDXY)). For example, the conductor C0112 couples the buried polarity region EPR12 of the pixel P(0, 1) to the discrete field amplification region FFAR_1 of the pixel P(0, 1) (not specifically labeled in FIG. 7(f)) . The conductors used to embed the polar regions are shown in dashed lines to indicate that the isotropic system is in a plane different from the color point. Typically, indium tin oxide is used in a first plane to form color points and discrete field amplification regions, and a metal layer is used to form conductors in a second plane. Therefore, a pass (labeled V) is used to connect the discrete field amplification region to the conductor. In FIG. 7(f), the discrete field amplification region is coupled to one of the adjacent pixels, as described above with reference to FIG. 7(d). However, in other embodiments of the invention, the discrete field amplification region may use other methods (eg, dedicated discrete field amplification region switching elements) to receive polarity.

As described above, the discrete field amplification region has one polarity opposite to the color point. Therefore, borrow By providing a polarity from the discrete field amplification region to the buried polarity region, the polarity of the buried polarity region is different from the polarity of the color point. This different polarity is used to enhance the discrete fields in the color point, thus enhancing multi-region vertical alignment operation and reducing the touch moiré effect in display 740.

As noted above, it is desirable to have a higher pixel density in many applications. The higher the display pixel density, the smaller the pixels. The optical transmittance is proportional to the aperture ratio, which is the ratio of the total area of the color point to the area of the color component. In general, the higher the display pixel density, the smaller the aperture ratio. It is also necessary to increase the aperture ratio in a normal pixel density to increase the brightness of the display. Thus, in some embodiments of the invention, a high aperture ratio is achieved by combining buried electrodes with discrete field amplifiers. 8(a)-8(b) show a pixel design in which each color component has a plurality of color points, including a buried polarity region and a buried discrete field amplifier, in accordance with some embodiments of the present invention. Specifically, FIGS. 8(a) and 8(b) show different dot polarity patterns of a pixel design 810 (labeled as 810+ and 810- as described below), and the pixel design 810 is often used to have a switch. The component column is in the display of the reverse drive mode. In actual operation, a pixel will switch between a first dot polarity pattern and a second dot polarity pattern between each image frame.

Like the pixel design 710, the pixel design 810 has three color components CC_1, CC_2, and CC_3 (not shown in Figures 8(a)-8(b)). Each of the three color components includes a two color point. The pixel design 810 also includes a switching element (denoted as SE_1, SE_2, and SE_3) for each color component and a buried discrete field amplifier EFFA_1. The switching elements SE_1, SE_2, and SE_3 are arranged in a row. The color point of the pixel design 810, the buried polarity region, and the switching element are very similar to the pixel design 710. However, as described below, the formation of the buried polar regions in the pixel design 810 and the pixel design 710 are different from each other. In addition, the color components are placed closer to each other because the discrete field amplification regions in the pixel design 710 are not used in the pixel design 810.

The first color component CC_1 of the pixel design 810 has two color points CD_1_1 and CD_1_2. The color points CD_1_1 and CD_1_2 form a line and are spaced apart by a vertical dot pitch VDS1. In other words, the color points CD_1_1 and CD_1_2 are horizontally aligned and vertically spaced apart by the vertical dot pitch VDS1. Further, the color point CD_1_1 and the CD_1_2 are vertically shifted by the vertical dot offset VDO1, and the vertical dot offset VDO1 is equal to the vertical dot pitch VDS1 plus the color point height CDH. The switching element SE_1 is located between the color points CD_1_1 and CD_1_2 such that the color point CD_1_1 is located on a first side of the column switching element, and the color point CD_1_2 is located on a second side of the column switching element. The switching element SE_1 is coupled to the electrodes of the color points CD_1_1 and CD_1_2 to control the color point CD_1_1 and The voltage polarity and voltage of CD_1_2.

Each color point of color component CC_1 includes a buried polar region that will enhance the discrete field, thereby enhancing multi-region vertical alignment operation and minimizing any touch moiré effects in the color point. Specifically, the color points CD_1_1 and CD_1_2 respectively include buried polarity areas EPR_1_1 and EPR_1_2. As shown in FIG. 8(a), the buried polar regions EPR_1_1 and EPR_1_2 are respectively centered in the color points CD_1_1 and CD_1_2. In the pixel design 810, the buried conductor technique shown in Figures 6(a)-6(b) is extended and discretely used in the pixel design 710 (Figs. 7(a)-7(b)). The field amplification area is combined. Specifically, in the pixel design 810, a buried discrete field amplifier EFFA_1 is used for the entire pixel. The buried discrete field amplifier EFFA_1 will be explained below.

For the sake of clarity, the relative position of the various portions of a pixel design will be elucidated from the perspective of a user viewing a display held in a vertical position. Thus, for example, in Figure 8(a), the color point CD_1_1 is illustrated as being located above the switching element SE_1, and the color point CD_1_2 is illustrated as being located below the switching element SE_1. The color point CD_1_1 is located on the left side of the color point CD_2_1. On the contrary, the color point CD_3_1 is located on the right side of the color point CD_2_1. In addition, the buried discrete field amplifier is illustrated as being located behind the color point. Instead, the color point is illustrated as being located in front of the buried discrete field amplifier.

The second color component CC_2 of the pixel design 810 has two color points CD_2_1 and CD_2_2. The color points CD_2_1 and CD_2_2 form a second line and are spaced apart by a vertical dot pitch VDS1. Therefore, the color points CD_2_1 and CD_2_2 are horizontally aligned and vertically spaced apart by the vertical dot pitch VDS1. The switching element SE_2 is located between the color points CD_2_1 and CD_2_2 such that the color point CD_2_1 is located on the first side of the switching element column, and the color point CD_2_2 is located on the second side of one of the switching element columns. The switching element SE_2 is coupled to the electrodes of the color points CD_2_1 and CD_2_2 to control the voltage polarity and voltage of the color points CD_2_1 and CD_2_2. The second color component CC_2 is vertically aligned with the first color component CC_1, and is spaced apart by a horizontal dot pitch HDS1 and the color component CC_1. Therefore, the color components CC_2 and CC_1 are horizontally shifted by a horizontal point offset HDD1, the horizontal point. The offset HDD1 is equal to the horizontal dot pitch HDS1 plus the color dot width CDW. Specifically, regarding the color point, the color point CD_2_1 and the color point CD_1_1 are vertically aligned and horizontally spaced by the horizontal dot pitch HDS1. Similarly, the color point CD_2_2 is vertically aligned with the color point CD_1_2 and horizontally spaced by the horizontal dot pitch HDS1. Therefore, the color point CD_1_1 and the color point CD_2_1 form a first column color point, and the color point CD_1_2 and the color point CD_2_2 form a second column color point. And color point CD_1_1 and Like CD_1_2, the color points CD_2_1 and CD_2_2 respectively contain buried polar regions EPR_2_1 and EPR_2_2. The horizontal point spacing HDS1 of the pixel design 810 is significantly smaller than the horizontal point spacing HDS1 of the pixel design 710. Thus, the color point in the pixel design 810 can be larger than the color point in the pixel design 710 in the case of color components of the same size. Therefore, the aperture ratio of the pixel design 810 is larger than the aperture ratio of the pixel design 710.

Similarly, the third color component CC_3 of the pixel 810 has two color points CD_3_1 and CD_3_2. The color points CD_3_1 and CD_3_2 form a third line and are spaced apart by a vertical dot pitch VDS1. Therefore, the color points CD_3_1 and CD_3_2 are horizontally aligned and vertically spaced apart by the vertical dot pitch VDS1. The switching element SE_3 is located between the color points CD_3_1 and CD_3_2 such that the color point CD_3_1 is located on the first side of the column switching element, and the color point CD_3_2 is located on the second side of one of the column switching element columns. The switching element SE_3 is coupled to the electrodes of the color points CD_3_1 and CD_3_2 to control the voltage polarity and voltage of the color points CD_3_1 and CD_3_2. The third color component CC_3 is vertically aligned with the second color component CC_2, and is spaced apart from the color component CC_2 by the horizontal dot pitch HDS1, so that the color components CC_3 and CC_2 are horizontally shifted by a horizontal dot offset amount HDO1. Specifically, regarding the color point, the color point CD_3_1 and the color point CD_2_1 are vertically aligned and horizontally spaced by the horizontal dot pitch HDS1. Similarly, the color point CD_3_2 is vertically aligned with the color point CD_2_2 and horizontally spaced by the horizontal dot pitch HDS1. Therefore, the color point CD_3_1 is located on the first column color point, and the color point CD_3_2 is located on the second color point column. Like the color points CD_1_1 and CD_1_2, the color points CD_3_1 and CD_3_2 respectively contain the buried polarity areas EPR_3_1 and EPR_3_2.

For the sake of clarity, the color points of the pixel design 810 are illustrated with color points having the same color point height CDH. However, certain embodiments of the invention may include color points having different color point heights. For example, in one embodiment of the present invention, which is a variant of the pixel design 810, the color point heights of the color points CD_1_1, CD_2_1, and CD_3_1 are smaller than the color point heights of the color points CD_1_2, CD_2_2, and CD_3_2. . Moreover, in many embodiments of the invention, the color points can have different shapes.

In contrast to the pixel design 710, the pixel design 810 includes a buried discrete field amplifier EFFA_1 instead of a buried conductor that includes a discrete field amplification region and is located in the buried polarity region. In the pixel design 810, the embedded discrete field amplifier EFFA_1 is a buried conductor that is located behind the color point but extends beyond the color point on the left, right, top, and bottom of the color point. Therefore, the color point of the pixel design 810 is located in front of the buried discrete field amplifier EFFA_1. Specifically, buried The discrete field amplifier extends beyond the right edge of the color points CD_3_1 and CD_3_2 to a horizontal buried electrode extension distance HEEED1. Although not specifically shown in the figure, the buried discrete field amplifier EFFA_1 also extends beyond the left edge of the color points CD_1_1 and CD_1_2 to the horizontal buried electrode extension distance HEEED1. Similarly, in the pixel design 810, the buried discrete field amplifier EFFA_1 extends to a vertical buried electrode extension distance VEEED1 above the color points CD_1_1, CD_2_1, and CD_3_1, and also extends below the color points CD_1_2, CD_2_2, and CD_3_2.

Use the "+" and "-" symbols to display the color point, the embedded discrete field amplifier, and the polarity of the switching components. Therefore, in FIG. 8(a) in which the positive dot pattern of the pixel design 810+ is displayed, all the switching elements (ie, the switching elements SE_1, SE_2, and SE_3) and all the color points (ie, the color points CD_1_1, CD_1_2) , CD_2_1, CD_2_2, CD_3_1, and CD_3_2) have positive polarity. However, the buried discrete field amplifier EFFA_1 has a negative polarity. Therefore, the buried polar regions EPR_1_1, EPR_2_1, and EPR_3_1 also have a negative polarity (the polarity of the buried polar region is not shown in FIGS. 8(a) and 8(b) due to space limitations).

Figure 8(b) shows a pixel design 810 with a negative dot polarity pattern. For a negative dot polarity pattern, all switching elements (ie, switching elements SE_1, SE_2, and SE_3) and all color points (ie, color points CD_1_1, CD_1_2, CD_2_1, CD_2_2, CD_3_1, and CD_3_2) have negative polarity. However, the buried discrete field amplifier EFFA_1 has a positive polarity. Therefore, the buried polar regions EPR_1_1, EPR_2_1, and EPR_3_1 also have positive polarity.

The discrete fields in each color point are magnified because of the different voltages appearing near the edges of the color points. The pixel design 810 utilizes a buried discrete field amplifier to enhance and stabilize the formation of multiple region segments in the liquid crystal structure. Specifically, the edge of a color point is located in front of a portion of the buried discrete field amplifier EFFA_1. If the voltage on the buried discrete field amplifier EFFA_1 is different from the voltage at the color point, the overlapping of the color point and the buried discrete field amplifier EFFA_1 will amplify the discrete field of the color point. If the color point has the opposite polarity to the buried discrete field amplifier, the discrete field will be amplified to a greater extent. However, if the buried discrete field amplifier is maintained at a common voltage (ie, neutral polarity, see Figures 9(a)-9(c)), the discrete fields of the color points can be well magnified. In general, the polarity of the polarization component is specified such that a color point of a first polarity is located in front of a buried discrete field amplifier of a second polarity, and the buried discrete field amplifier of the second polarity extends beyond the color The edge of the point. For example, for the positive dot polarity pattern of the pixel design 810 (Fig. 8(a)), the color point CD_2_2 has a positive polarity. However, the buried discrete field amplifier EFFA_1 has a negative polarity. Therefore, the discrete field of the color point CD_2_2 is amplification.

Since all of the switching elements in the pixel design 810 have the same polarity and the buried discrete field amplifiers should have a different polarity, the discrete field amplifiers are derived from an external polar source (ie, one of the polar elements from the pixel design 810). Source) driver. Various sources of opposite polarity can be used in accordance with various embodiments of the present invention. For example, a particular buried discrete field amplifier switching element can be used or a buried pixel with a reverse polarity can be used to drive the buried discrete field amplifier. In the embodiment of Figures 8(a)-8(b), the discrete field amplification regions can also be driven using switching elements of adjacent pixels having opposite polarity. Thus, the pixel design 810 includes a conductor 812 to assist in coupling the discrete field amplification regions to the switching elements in other pixels. Specifically, a current pixel conductor 812 couples the buried discrete field amplifier to a switching element SE_1 located above one pixel of the current pixel (see FIG. 8(e)). The connection to the switching element is achieved via the electrode of the color point of the pixel above the current pixel. These connections are better shown in Figure 8(e), and Figure 8(e) shows a portion of the display 820 using the pixel design 810.

Figure 8(c) shows a cross section of the pixel design 810 taken along line AA (Fig. 8(b)), including color points CD_1_1, CD_2_1, CD_3_1, buried polarity regions EPR_1_1, EPR_2_1, and EPR_3_1, and embedding Discrete field amplifier EFFA_1. Figure 8(c) is used to illustrate the relative placement of color points and buried discrete field amplifiers. Thus, for clarity, certain layers and components that may be present in various embodiments of the invention are not shown in Figure 8(c). Moreover, other layers and components in the display using one of the pixel designs 810 may not be present in the area of the pixel design 820 shown in Figure 8(c). As shown in FIG. 8(c), one of the displays using the pixel design 820 includes a lower transparent substrate 821. A first passivation layer 823 is formed on the transparent substrate 821. Although not shown, a first metal layer is often formed on the substrate 821 and is typically covered by a first passivation layer 823. However, the first metal layer is not used in the portion of the pixel design 820 shown in Figure 8(c). Passivation layer 823 is made using a transparent passivation material (eg, dielectric layer SiNx). In general, a layer of transparent conductive material (eg, ITO, or ZnO (zinc oxide)) is formed over passivation layer 823 and etched to form buried discrete field amplifier EFFA_1. In some embodiments of the invention, a second metal layer can be formed over passivation layer 823. A second passivation layer 827 is formed over the buried discrete field amplifier EFFA_1 and also fills the gap left by the etch fabrication used to form the buried discrete field amplifier EFFA_1. A specific portion of the pixel design 820 shown in FIG. 8(c) includes buried polarity regions EPR_1_1, EPR_2_1, and EPR_3_1, and the buried polarity regions EPR_1_1, EPR_2_1, and EPR_3_1 are etched through. The color point is formed in the middle of the passivation layer 827. Therefore, the passivation layer 827 appears as a plurality of portions in FIG. 8(c). A color dot is formed on top of the passivation layer 827. Generally, the color point is formed by depositing a layer of a conductive material (for example, ITO or IZO) on the second passivation layer 827. Subsequently, the conductive layer is patterned and etched to form a color point. Therefore, as shown in FIG. 8(c), the color points CD_1_1, CD_2_1, and CD_3_1 are located on the top of the second passivation layer 827. Since the perspective view of Fig. 8(c) is taken at the place where the buried polar region is located, the color points CD_1_1, CD_2_1, and CD_3_1 appear as two separate portions in Fig. 8(c). However, the actual shape of the color point is a square shape having a square hole at the center as shown in Fig. 8(a). In some embodiments of the invention, a buried discrete field amplifier is formed on a transparent substrate 821.

Figure 8(d) shows a portion of display 840 having pixels P(0,0), P(1,0), P(0,1), and P(1) of pixel design 810. ,1). Display 840 uses a switching element column inversion drive mode. Display 840 can have thousands of columns with thousands of pixels on each column. The columns and rows will be successively arranged from the portion shown in Fig. 8(d) in the manner shown in Fig. 8(d). For the sake of clarity, the gate lines and source lines for controlling the switching elements are omitted in Figure 8(d). In display 840, the pixels on the same column are spaced apart by a horizontal pixel spacing HPS, and the pixels in each adjacent column are spaced apart by a vertical pixel spacing VPS. The pixels of display 840 are arranged such that all pixels in a column have the same dot pattern (positive or negative), and each successive column should be between a positive dot polarity pattern and a negative dot polarity pattern. alternately. Therefore, the pixels P(0,0) and P(1,0) in the first column (ie, column 0) have a positive dot polarity pattern, and the pixel P in the second column (ie, column 1) (0, 1) and P (1, 1) have a negative dot polarity pattern. However, in the next page box, the pixels will switch the dot polarity pattern. Therefore, in general, a pixel P(x, y) has a first dot polarity pattern when y is an even number and a second dot polarity pattern when y is an odd number. The inner conductor 812 in the pixel design 840 provides a polarity to buried discrete field amplifier. Specifically, a buried discrete field amplifier of a first pixel receives voltage polarity and voltage from a second pixel. More specifically, the second pixel is a pixel located above the first pixel. For example, the embedded discrete field amplifier EFFA_1 of the pixel P(0,0) is coupled to the switching element of the pixel P(0,1) via the electrode of the color point CD_1_2 of the pixel P(0,1). SE_1.

Alternatively, in another embodiment of the invention, a display can have embedded discrete field amplifier switching elements for each column of pixels. Similarly, the buried polar region switching element is used in Figure 7(d). However, only one buried discrete field amplifier switching element is required for each column of pixels.

Since there is polarity switching on each column in display 840, if a color point has a first polarity, the buried discrete field amplifier surrounding the color point will have a second polarity. For example, the color point CD_3_2 of the pixel P(0,0) has a positive polarity, and the buried discrete field amplifier EFFA_1 of the pixel P(0,0) has a negative polarity (from the pixel P(0,1) Switching element SE_1). In a particular embodiment of the invention, each color point has a width of one of 30 microns and a height of one of 35 microns. Each buried polar region has a width of one of 6 microns and a height of one of 6 microns. Each buried discrete field amplifier has a width of one of 105 microns and a height of one of 105 microns. The horizontal dot pitch HDS1 is 10 micrometers, the vertical dot pitch VDS1 is 30 micrometers, the horizontal buried electrode extends 6 micrometers, and the vertical buried electrode extends 6 micrometers. In addition, the horizontal pixel spacing HPS is 6 microns and the vertical pixel spacing VPS is 40 microns.

Figures 9(a) and 9(b) show different dot polarity patterns for a pixel design 910 (labeled 910+ and 910- as described above). The pixel design 910 is often used to have a switching element column inversion. Drive mode in the display. In actual operation, a pixel will switch between a first dot polarity pattern and a second dot polarity pattern between each image frame. The pixel design 910 is almost identical to the pixel design 810 and will not be described again, but only the differences. In particular, the pixel design 910 differs from the pixel design 810 in that the embedded discrete field amplifier EFFA_1 is polarized to a neutral polarity (as indicated by "="). Therefore, the conductor 812 for coupling the buried discrete field amplifier EFFA_1 to one of the adjacent pixel switching elements in the pixel design 810 is not present in the pixel design 910. In most embodiments of the invention, the neutral polarity is obtained from a common voltage V_Com.

As described above, the use of neutral polarity on the buried discrete field amplifier EFFA_1 magnifies the discrete fields of color points. Therefore, the pixel design 910 will also have a good multi-area segmentation performance and can be used to form the display in the same manner as the pixel design 810. For example, FIG. 9(c) shows a portion of display 920 having pixels P(0,0), P(1,0), P(0,1) of pixel design 910, And P(1,1). Display 920 uses a switching element column inversion drive mode. Display 920 can have thousands of columns with thousands of pixels on each column. In display 920, the pixels on the same column are spaced apart by a horizontal pixel spacing HPS, and the pixels in adjacent columns are spaced apart by a vertical pixel spacing VPS. The columns and rows will be successively arranged from the portion shown in Fig. 9(c) in the manner shown in Fig. 9(c). For the sake of clarity, the gate lines and source lines for controlling the switching elements are omitted in Figure 9(c). The pixels of display 920 are arranged such that all pixels in one column have the same The point polarity pattern (positive or negative), and each successive column should alternate between a positive dot polarity pattern and a negative dot polarity pattern. Therefore, the pixels P(0,0) and P(1,0) in the first column (ie, column 0) have a positive dot polarity pattern, and the pixel P in the second column (ie, column 1) (0, 1) and P (1, 1) have a negative dot polarity pattern. However, in the next page box, the pixels will switch the dot polarity pattern. Therefore, in general, a pixel P(x, y) has a first dot polarity pattern when y is an even number and a second dot polarity pattern when y is an odd number.

One benefit of using a neutral polarity on the buried discrete field amplifier EFFA_1 is that the polarity of the color points located in front of the buried discrete field amplifier can have different polarities. For example, Figures 10(a) and 10(b) show different dot polarity patterns for a pixel design 1010 (labeled 1010+ and 1010- as described above). The pixel design 1010 is often used to have a switch. In the display of the component dot inversion driving mode and the switching element row inversion driving mode. In actual operation, a pixel will switch between a first dot polarity pattern and a second dot polarity pattern between each image frame. The pixel design 1010 is almost identical to the pixel design 910 and will not be described again, but only the differences. Specifically, the pixel design 1010 is different from the pixel design 910 in that the polarity of the switching element SE_2, the color point CD_2_1, and the color point CD_2_2 is negative for a positive point polarity and positive for a negative point polarity. of.

Therefore, in FIG. 10(a) in which the dot polarity pattern of the pixel design 1010+ is displayed, the switching elements SE_1 and SE_3, the color points CD_1_1, CD_1_2, CD_3_1, and CD_3_2 have positive polarity. However, the switching element SE_2, the color points CD_2_1 and CD_2_2 have a negative polarity. The buried discrete field amplifier EFFA_1 has a neutral polarity. Figure 10(b) shows a pixel design 1010 with a negative dot polarity pattern. For the negative dot polarity pattern, the switching elements SE_1 and SE_3, the color points CD_1_1, CD_1_2, CD_3_1, and CD_3_2 have negative polarity. However, the switching element SE_2, the color points CD_2_1 and CD_2_2 have positive polarity. The buried discrete field amplifier EFFA_1 has a neutral polarity.

Figure 10 (c) shows a portion of display 1020 having pixels of pixel design 1010 P(0,0), P(1,0), P(0,1), and P(1). ,1). Display 1020 uses a switching element dot inversion drive mode. Display 1020 can have thousands of columns with thousands of pixels on each column. In display 1020, the pixels on the same column are spaced apart by a horizontal pixel spacing HPS, and the pixels in adjacent columns are spaced apart by a vertical pixel spacing VPS. The columns and rows will be successively arranged from the portion shown in Fig. 10(c) in the manner shown in Fig. 10(c). For the sake of clarity, in Figure 10(c) The gate lines and source lines for controlling the switching elements are omitted. In the display 1020, the pixels are arranged such that the pixels located in one column alternately have a dot polarity pattern (positive or negative), and the pixels in one row are also at the positive dot polarity pattern and the negative point. The polarity patterns alternate between each other. Therefore, the pixels P(0, 0) and P(1, 1) have a positive dot polarity pattern, and the pixels P(0, 1) and P(1, 0) have a negative dot polarity pattern. However, in the next page box, the pixels will switch the dot polarity pattern. Therefore, in general, a pixel P(x, y) has a first dot polarity pattern when x+y is even, and a second dot polarity pattern when x+y is odd.

The pixel design 1010 can also be used in a display that uses a switching element row inversion driving mode. Figure 10 (d) shows a portion of the display 1030, which has pixels of the pixel design 1010 P(0,0), P(1,0), P(0,1), and P(1). ,1). Display 1030 can have thousands of columns with thousands of pixels on each column. In display 1030, the pixels on the same column are spaced apart by a horizontal pixel spacing HPS, and the pixels in adjacent columns are spaced apart by a vertical pixel spacing VPS. The columns and rows will be successively arranged from the portion shown in Fig. 10(d) in the manner shown in Fig. 10(d). For the sake of clarity, the gate lines and source lines for controlling the switching elements are omitted in FIG. 10(d). In display 1030, the pixels are arranged such that pixels located in a column alternately have a dot polarity pattern (positive or negative), and pixels located in one row have the same dot polarity pattern. Therefore, the pixels P(0, 0) and P(0, 1) have a positive dot polarity pattern, and the pixels P(1, 0) and P(1, 1) have a negative dot polarity pattern. However, in the next page box, the pixels will switch the dot polarity pattern. Therefore, in general, a pixel P(x, y) has a first dot polarity pattern when x is an even number and a second dot polarity pattern when x is an odd number.

In many portable LCD applications, there is a need to reduce power consumption to save battery life. 11(a) and 11(b) show a pixel design in which each color component has a plurality of color points, including a buried polar region and a plurality of buried discrete fields, in accordance with some embodiments of the present invention. Amplifier. Specifically, FIGS. 11(a) and 11(b) show different dot polarity patterns of a pixel design 1110 (labeled as 1110+ and 1110- as described below), and the pixel design 1110 is often used to have a switch. The component column is in the display of the reverse drive mode. In actual operation, a pixel will switch between a first dot polarity pattern and a second dot polarity pattern between each image frame.

Like the pixel design 810, the pixel design 1110 has three color components CC_1, CC_2, and CC_3 (not shown in Figures 11(a)-11(b)). Each of the three color components includes a two color point. The pixel design 1110 also includes a switching element for each color component (represented as SE_1, SE_2 and SE_3) and include a buried discrete field amplifier (denoted EFFA_1, EFFA_2, and EFFA_3) for each color component. The switching elements SE_1, SE_2 and SE_3 are arranged in a row. The buried discrete field amplifiers EFFA_1, EFFA_2, and EFFA_3 are also arranged in a column. The color point of the pixel design 1110, the buried polarity region, and the switching elements are very similar to the pixel design 810. However, as described below, the pixel design 1110 is different from the formation of the buried polarity regions in the pixel design 810.

The first color component CC_1 of the pixel design 1110 has two color points CD_1_1 and CD_1_2. The color points CD_1_1 and CD_1_2 form a line and are spaced apart by a vertical dot pitch VDS1. In other words, the color points CD_1_1 and CD_1_2 are horizontally aligned and vertically spaced apart by the vertical dot pitch VDS1. Further, the color point CD_1_1 and the CD_1_2 are vertically shifted by the vertical dot offset VDO1, and the vertical dot offset VDO1 is equal to the vertical dot pitch VDS1 plus the color point height CDH. The switching element SE_1 is located between the color points CD_1_1 and CD_1_2 such that the color point CD_1_1 is located on a first side of the column switching element, and the color point CD_1_2 is located on a second side of the column switching element. The switching element SE_1 is coupled to the electrodes of the color points CD_1_1 and CD_1_2 to control the voltage polarity and voltage of the color points CD_1_1 and CD_1_2.

Each color point of the color component CD_1_1 includes a buried polar region, and the buried polar region enhances the discrete field, thereby enhancing the multi-region vertical alignment operation and minimizing any touch moiré effects in the color point. Specifically, the color points CD_1_1 and CD_1_2 respectively include buried polarity areas EPR_1_1 and EPR_1_2. As shown in FIG. 11(a), the buried polar regions EPR_1_1 and EPR_1_2 are respectively centered in the color points CD_1_1 and CD_1_2. In the pixel design 1110, the buried conductor technique shown in Figures 6(a)-6(b) is extended and discrete with the pixel design 710 (Figs. 7(a)-7(b)). The field amplification area is combined. Specifically, in the pixel design 1110, a buried discrete field amplifier is used for each color component.

For the sake of clarity, the relative position of the various portions of a pixel design will be elucidated from the perspective of a user viewing a display held in a vertical position. Thus, for example, in Figure 11(a), the color point CD_1_1 is illustrated as being located above the switching element SE_1, and the color point CD_1_2 is illustrated as being located below the switching element SE_1. The color point CD_1_1 is located on the left side of the color point CD_2_1. On the contrary, the color point CD_3_1 is located on the right side of the color point CD_2_1. In addition, the buried discrete field amplifier is illustrated as being located behind the color point. Instead, the color point is illustrated as being located in front of the buried discrete field amplifier.

The second color component CC_2 of the pixel design 1110 has two color points CD_2_1 and CD_2_2. The color points CD_2_1 and CD_2_2 form a second line and are spaced apart by a vertical dot pitch VDS1. Therefore, the color points CD_2_1 and CD_1_2 are horizontally aligned and vertically spaced apart by the vertical dot pitch VDS1. The switching element SE_2 is located between the color points CD_2_1 and CD_2_2 such that the color point CD_2_1 is located on the first side of the column switching element, and the color point CD_2_2 is located on the second side of one of the column switching elements. The switching element SE_2 is coupled to the electrodes of the color points CD_2_1 and CD_2_2 to control the voltage polarity and voltage of the color points CD_2_1 and CD_2_2. The second color component CC_2 is vertically aligned with the first color component CC_1, and is spaced apart by a horizontal dot pitch HDS1 and the color component CC_1. Therefore, the color components CC_2 and CC_1 are horizontally shifted by a horizontal point offset HDD1, the horizontal point. The offset HDD1 is equal to the horizontal dot pitch HDS1 plus the color dot width CDW. Specifically, regarding the color point, the color point CD_2_1 and the color point CD_1_1 are vertically aligned and horizontally spaced by the horizontal dot pitch HDS1. Similarly, the color point CD_2_2 is vertically aligned with the color point CD_2_1 and horizontally spaced by the horizontal dot pitch HDS1. Therefore, the color point CD_1_1 and the color point CD_2_1 form a first column color point, and the color point CD_1_2 and the color point CD_2_2 form a second column color point. Like the color points CD_1_1 and CD_1_2, the color points CD_2_1 and CD_2_2 respectively contain the buried polar regions EPR_2_1 and EPR_2_2.

Similarly, the third color component CC_3 of the pixel 1110 has two color points CD_3_1 and CD_3_2. The color points CD_3_1 and CD_3_2 form a third line and are spaced apart by a vertical dot pitch VDS1. Therefore, the color points CD_3_1 and CD_3_2 are horizontally aligned and vertically spaced apart by the vertical dot pitch VDS1. The switching element SE_3 is located between the color points CD_3_1 and CD_3_2 such that the color point CD_3_1 is located on the first side of the column switching element, and the color point CD_3_2 is located on the second side of one of the column switching elements. The switching element SE_3 is coupled to the electrodes of the color points CD_3_1 and CD_3_2 to control the voltage polarity and voltage of the color points CD_3_1 and CD_3_2. The third color component CC_3 is vertically aligned with the second color component CC_2, and is spaced apart from the color component CC_2 by the horizontal dot pitch HDS1, so that the color components CC_3 and CC_2 are horizontally shifted by a horizontal dot offset amount HDO1. Specifically, regarding the color point, the color point CD_3_1 and the color point CD_2_1 are vertically aligned and horizontally spaced by the horizontal dot pitch HDS1. Similarly, the color point CD_3_2 is vertically aligned with the color point CD_2_2 and horizontally spaced by the horizontal dot pitch HDS1. Therefore, the color point CD_3_1 is located on the first column color point, and the color point CD_3_2 is located on the second column color point. Like the color points CD_1_1 and CD_1_2, the color points CD_3_1 and CD_3_2 respectively contain the buried polarity areas EPR_3_1 and EPR_3_2.

For the sake of clarity, the color points of the pixel design 1110 are exemplified by color points having the same color point height CDH. However, certain embodiments of the invention may include color points having different color point heights. For example, in one embodiment of the present invention, which is a variant of the pixel design 1110, the color point heights of the color points CD_1_1, CD_2_1, and CD_3_1 are smaller than the color point heights of the color points CD_1_2, CD_2_2, and CD_3_2. . Moreover, in many embodiments of the invention, the color points can have different shapes.

In contrast to the pixel design 710, the pixel design 1110 includes a buried discrete field amplifier EFFA rather than a buried conductor that includes a discrete field amplification region and is located in the buried polarity region. In particular, pixel design 1110 includes buried discrete field amplifiers EFFA_1, EFFA_2, and EFFA_3. As shown in FIG. 11(a), the buried discrete field amplifiers EFFA_1, EFFA_2, and EFFA_3 are placed behind the color point of the pixel design 1110. Specifically, the buried discrete field amplifier EFFA_1 is placed such that the color point CD_1_1 and the color point CD_1_2 and the switching element SE_1 are located in front of the buried discrete field amplifier EFFA_1. However, the buried discrete field amplifier EFFA_1 extends beyond the left and right sides of the color points CD_1_1 and CD_1_2 to a horizontal buried electrode extension distance HEEED1. Similarly, the buried discrete field amplifier EFFA_1 extends beyond the top of the color point CD_1_1 and the bottom of the color point CD_1_2 to a vertical buried electrode extension distance VEEED1. Therefore, the edges of the color points CD_1_1 and CD_1_2 are located in front of the portion of the buried discrete field amplifier EFFA_1. Similarly, the buried discrete field amplifier EFFA_2 is placed such that the color point CD_2_1 and the color point CD_2_2 and the switching element SE_2 are located in front of the buried discrete field amplifier EFFA_2. However, the buried discrete field amplifier EFFA_2 extends beyond the left and right sides of the color points CD_2_1 and CD_2_2 to a horizontal buried electrode extension distance HEEED1. Similarly, the buried discrete field amplifier EFFA_2 extends beyond the top of the color point CD_2_1 and the bottom of the color point CD_2_2 to a vertical buried electrode extension distance VEEED1. Therefore, the edges of the color points CD_2_1 and CD_2_2 are located in front of the portion of the buried discrete field amplifier EFFA_2. In addition, the buried discrete field amplifier EFFA_2 is vertically aligned with the buried discrete field amplifier EFFA_1 and spaced apart from the buried discrete field amplifier EFFA_1 by a horizontal buried electrode pitch HEES1.

Similarly, the buried discrete field amplifier EFFA_3 is placed such that the color point CD_3_1 and the color point CD_3_2 and the switching element SE_3 are located in front of the buried discrete field amplifier EFFA_3. However, the buried discrete field amplifier EFFA_3 extends beyond the left and right sides of the color points CD_3_1 and CD_3_2 to a horizontal buried electrode extension distance HEEED1. Similarly, buried discrete field amplifier EFFA_3 Extending beyond the top of the color point CD_3_1 and the bottom of the color point CD_3_2 to a vertical buried electrode extension distance VEEED1. Therefore, the edges of the color points CD_3_1 and CD_3_2 are located in front of the portion of the buried discrete field amplifier EFFA_3. In addition, the buried discrete field amplifier EFFA_3 is vertically aligned with the buried discrete field amplifier EFFA_2 and spaced apart from the buried discrete field amplifier EFFA_2 by a horizontal buried electrode pitch HEES1. An electrode 1116 is used to couple the buried discrete field amplifier EFFA_1 to a voltage source.

Use the "+" and "-" symbols to display the color point, the embedded discrete field amplifier, and the polarity of the switching components. Therefore, in Fig. 11(a) in which the dot pattern of the pixel design 1110+ is displayed, all the switching elements (i.e., switching elements SE_1, SE_2, and SE_3) and all the color points (i.e., color points CD_1_1, CD_1_2) , CD_2_1, CD_2_2, CD_3_1, and CD_3_2) have positive polarity. However, the buried discrete field amplifiers EFFA_1, EFFA_2, and EFFA_3 have negative polarity. Therefore, the buried polar regions EPR_1_1, EPR_2_1, and EPR_3_1 also have a negative polarity (the polarity of the buried polar region is not shown in FIGS. 11(a) and 11(b) due to space limitations).

Figure 11 (b) shows a pixel design 1110 with a negative dot polarity pattern. For a negative dot polarity pattern, all switching elements (ie, switching elements SE_1, SE_2, and SE_3) and all color points (ie, color points CD_1_1, CD_1_2, CD_2_1, CD_2_2, CD_3_1, and 3_2) have negative polarity. However, the buried discrete field amplifiers EFFA_1, EFFA_2, and EFFA_3 have positive polarity. Therefore, the buried polar regions EPR_1_1, EPR_2_1, and EPR_3_1 also have positive polarity.

The discrete fields in each color point are magnified because of the different voltages near the edges of the color points. The pixel design 1110 utilizes a buried discrete field amplifier to enhance and stabilize the formation of multiple regions in the liquid crystal structure. Specifically, the edge of a color point is located in front of a portion of a buried discrete field amplifier. When the voltage across the buried discrete field amplifier EFFA_1 is different from the voltage at the color point, the overlap of the color point and the buried discrete field amplifier amplifies the discrete field of the color point. If the color point has the opposite polarity to the buried discrete field amplifier, the discrete field will be amplified to a greater extent. However, if the buried discrete field amplifier is maintained at a common voltage (ie, neutral polarity), the discrete fields of the color points can be well magnified. In general, the polarity of the polarization component is specified such that a color point of a first polarity is in front of a buried discrete field amplifier of a second polarity, and the buried discrete field amplifier of the second polarity extends beyond the color point. The edge. For example, for the positive dot polarity pattern of the pixel design 1110 (Fig. 11(a)), the color point CD_2_2 has a positive polarity. However, the buried discrete field amplifier EFFA_2 has a negative polarity. Therefore, the discrete field of the color point CD_2_2 is amplified.

Since all of the switching elements in the pixel design 1110 have the same polarity and the buried discrete field amplifier should have a different polarity, the discrete field amplifier is comprised of an external polar source (ie, one of the specific pixels from the pixel design 1110). Polar source) drive. Various sources of opposite polarity can be used in accordance with various embodiments of the present invention. For example, a particular buried discrete field amplifier switching element can be used or a buried pixel with a reverse polarity can be used to drive the buried discrete field amplifier. In the embodiment of Figures 11(a)-11(b), the discrete field amplification regions can also be driven using switching elements of adjacent pixels having opposite polarity. Thus, the pixel design 1110 includes conductors 1112, 1114, and 1116 to assist in coupling the discrete field amplification regions to the switching elements in other pixels. An electrode 1112 is used to couple the buried discrete field amplifier EFFA_1 to a voltage source. In general, in the switching element column inversion driving mode display, the electrode 1112 is coupled to a color point CD_1_2 located at a pixel above the current pixel (see FIG. 11(d)). An electrode 1114 is used to couple the buried discrete field amplifier EFFA_2 to a voltage source. In general, in the switching element column inversion driving mode display, the electrode 1114 is coupled to a color point CD_2_2 located at a pixel above the current pixel (see FIG. 11(d)). An electrode 1116 is used to couple the buried discrete field amplifier EFFA_1 to a voltage source. In general, in the switching element column inversion driving mode display, the electrode 1116 is coupled to a color point CD_3_2 located at a pixel above the current pixel (see FIG. 11(d)).

Figure 11 (c) shows a cross section of the pixel design 1110 taken along line AA (Figure 11 (b)), including color points CD_1_1, CD_2_1, CD_3_1, buried polarity regions EPR_1_1, EPR_2_1, and EPR_3_1, and embedding Discrete field amplifiers EFFA_1, EFFA_2, and EFFA_3. Figure 11 (c) is used to illustrate the relative placement of color points and buried discrete field amplifiers. Thus, for clarity, certain layers and components that may be present in various embodiments of the invention are not shown in Figure 11(c). In addition, other layers and components in the display using one of the pixel design 1110 may not be present in the region of the pixel design 1110 shown in Figure 11(c). As shown in FIG. 11(c), one of the displays using the pixel design 1110 includes a lower transparent substrate 1121. A first passivation layer 1123 is formed on the transparent substrate 1121. Although not shown, a first metal layer is often formed on the substrate 1121 and is typically covered by the first passivation layer 1123. However, the first metal layer is not used in the portion of the pixel design 1110 shown in Fig. 11(c). Passivation layer 1123 is made using a transparent passivation material (eg, dielectric layer SiNx). In general, a layer of transparent conductive material (eg, ITO, or ZnO) is formed over passivation layer 1123 and etched to form buried discrete field amplifiers EFFA_1, EFFA_2, and EFFA_3. In some embodiments of the invention, a second metal layer can be formed over passivation layer 1123. a second passivation layer 1127 is formed over the buried discrete field amplifier EFFA_1 and also fills the gap left by the etch fabrication used to form the buried discrete field amplifiers EFFA_1, EFFA_2, and EFFA_3. A specific portion of the pixel design 1110 shown in FIG. 11(c) includes buried polarity regions EPR_1_1, EPR_2_1, and EPR_3_1, and the buried polarity regions EPR_1_1, EPR_2_1, and EPR_3_1 are etched through the middle of the color point and the passivation layer 1127. And formed. Therefore, in FIG. 11(c), the passivation layer 1127 appears as a plurality of portions. A color dot is formed on top of the passivation layer 1127. Generally, the color point is formed by depositing a layer of a conductive material (for example, ITO or IZO) on the second passivation layer 1127. Subsequently, the conductive layer is patterned and etched to form a color point. Therefore, as shown in FIG. 11(c), the color points CD_1_1, CD_2_1, and CD_3_1 are located on the top of the second passivation layer 1127. Since the perspective view of Fig. 11(c) is taken at the place where the buried polar region is located, the color points CD_1_1, CD_2_1, and CD_3_1 appear as two separate portions in Fig. 11(c). However, the actual shape of the color point is a square shape having a square hole at the center as shown in Fig. 11(a). In some embodiments of the invention, a buried discrete field amplifier is formed on a transparent substrate 1121.

Figure 11 (d) shows a portion of the display 1140 having the pixels P10, 0, P(0, 1) ,1). Display 1140 uses a switching element column inversion drive mode. Display 1140 can have thousands of columns with thousands of pixels on each column. The columns and rows will be successively arranged from the portion shown in Fig. 11(d) in the manner shown in Fig. 11(d). For the sake of clarity, the gate lines and source lines for controlling the switching elements are omitted in FIG. 11(d). In display 1140, the pixels on the same column are spaced apart by a horizontal pixel spacing HPS, and the pixels in adjacent columns are spaced apart by a vertical pixel spacing VPS. The pixels of display 1140 are arranged such that all pixels in a column have the same point polarity pattern (positive or negative), and each successive column should be between a positive dot polarity pattern and a negative dot polarity pattern. alternately. Therefore, the pixels P(0,0) and P(1,0) in the first column (ie, column 0) have a positive dot polarity pattern, and the pixel P in the second column (ie, column 1) (0, 1) and P (1, 1) have a negative dot polarity pattern. However, in the next page box, the pixels will switch the dot polarity pattern. Therefore, in general, a pixel P(x, y) has a first dot polarity pattern when y is an even number and a second dot polarity pattern when y is an odd number. The inner conductor 1112 of the pixel design 1110 provides a polarity to buried discrete field amplifier. Specifically, a buried discrete field amplifier of a first pixel receives voltage polarity and voltage from a second pixel. More specifically, the second pixel is a pixel located above the first pixel. For example, pixel P (0, 0) The embedded discrete field amplifier EFFA_1 is coupled to the switching element SE_1 of the pixel P(0, 1) via the electrode of the color point CD_1_2 of the pixel P(0, 1).

Alternatively, in another embodiment of the invention, a display can have embedded discrete field amplifier switching elements for each column of pixels. Similarly, the buried polar region switching element is used in Figure 7(d). However, only one buried discrete field amplifier switching element is required for each column of pixels.

Since there is polarity switching on each column in display 1140, if a color point has a first polarity, the buried discrete field amplifier surrounding the color point will have a second polarity. For example, the color point CD_3_2 of the pixel P(0,0) has a positive polarity, and the buried discrete field amplifier EFFA_1 of the pixel P(0,0) has a negative polarity (from the pixel P(0,1) Switching element SE_1). In a particular embodiment of the invention, each color point has a width of one of 30 microns and a height of one of 35 microns. Each buried polar region has a width of one of 6 microns and a height of one of 6 microns. Each buried discrete field amplifier has a width of one of 105 microns and a height of one of 105 microns. The horizontal dot pitch HDS1 is 10 micrometers, the vertical dot pitch VDS1 is 30 micrometers, the horizontal buried electrode extends 6 micrometers, and the vertical buried electrode extends 6 micrometers. In addition, the horizontal pixel spacing HPS is micrometers and the vertical pixel spacing VPS is micrometers.

The pixel design 1110 can be easily modified for use with a display having a switching element row inversion driving mode and a switching element dot inversion driving mode. Figures 11(e) and 11(f) show different dot polarity patterns for a pixel design 1120 (labeled 1120+ and 1120-). In actual operation, a pixel will switch between a first dot polarity pattern and a second dot polarity pattern between each image frame. The pixel design 1120 is almost identical to the pixel design 1110, so it will not be described again, but only the differences. Specifically, the pixel design 1120 is different from the pixel design 1110 in that the polarity of the switching element SE_2, the color point CD_2_1, and the color point CD_2_2 is negative for a positive point polarity and positive for a negative point polarity. of. Furthermore, the polarity of the buried discrete field amplifier EFFA_2 is positive for positive point polarities and negative for negative point polarities.

Therefore, in FIG. 11(e) in which the dot polarity pattern of the pixel design 1120+ is displayed, the switching elements SE_1 and SE_3, the color points CD_1_1, CD_1_2, CD_3_1, and CD_3_2, and the buried discrete field amplifier EFFA_2 have positive electrodes. Sex. However, the switching element SE_2, the color points CD_2_1 and CD_2_2, and the buried discrete field amplifiers EFFA_1 and EFFA_3 have negative polarity. Figure 11 (f) shows a pixel design 1120 having a negative dot polarity pattern. For negative dot polarity patterns, switching elements SE_1 and SE_3, color points CD_1_1, CD_1_2, CD_3_1, and CD_3_2, And the buried discrete field amplifier EFFA_2 has a negative polarity. However, the switching element SE_2, the color points CD_2_1 and CD_2_2, and the buried discrete field amplifiers EFFA_1 and EFFA_3 have positive polarity. The pixel design 1120 can also be modified to use a neutral polarity for the buried discrete field amplifier.

In addition to the polarity change, the electrodes 1112, 1114, and 1116 can also be modified as compared to the pixel design 1110. In general, in the switching element dot inversion driving mode display, the electrode 1112 is coupled to a color point CD_1_2 located at a pixel above the current pixel (see FIG. 11(g)). However, in the switching element row inversion driving mode display, the electrode 1112 is coupled to the color point CD_2_1 of the current pixel (see FIG. 11(h)). However, in other embodiments of the present invention, in the switching element row inversion driving mode display, the electrode 1112 is coupled to a color point CD_3_2 located at one of the left pixels of the current pixel. In general, in the switching element dot inversion driving mode display, the electrode 1114 is coupled to a color point CD_2_2 located at a pixel above the current pixel (see FIG. 11(g)). However, in the switching element row inversion driving mode display, the electrode 1114 is coupled to the color point CD_3_1 of the current pixel (see FIG. 11(h)). However, in other embodiments of the present invention, in the switching element row inversion driving mode display, the electrode 1114 is coupled to the color point CD_1_2 of one pixel located at the upper left of the current pixel. In general, in the switching element dot inversion driving mode display, the electrode 1116 is coupled to a color point CD_3_2 located at a pixel above the current pixel (see FIG. 11(g)). However, in the switching element row inversion driving mode display, the electrode 1116 is coupled to the color point CD_1_1 of one pixel on the right side of the current pixel (see FIG. 11(h)). However, in other embodiments of the present invention using a switching element row inversion driving mode display, the electrode 1116 is coupled to a color point CD_2_2 located at a pixel on the upper left of the current pixel.

Figure 11 (g) shows a portion of the display 1160, which has pixels of the pixel design 1120 P(0,0), P(1,0), P(0,1), and P(1). ,1). Display 1160 uses a switching element dot inversion drive mode. Display 1160 can have thousands of columns with thousands of pixels on each column. In display 1160, the pixels on the same column are spaced apart by a horizontal pixel spacing HPS, and the pixels in adjacent columns are spaced apart by a vertical pixel spacing VPS. The columns and rows will be successively arranged from the portion shown in Fig. 11(g) in the manner shown in Fig. 11(g). For the sake of clarity, the gate lines and source lines for controlling the switching elements are omitted in FIG. 11(g). In the display 1160, the pixels are arranged such that the pixels located in one column alternately have a dot polarity pattern (positive or negative), and the pixels in one row are also at a positive dot polarity pattern and a negative point. The polarity patterns alternate between each other. Therefore, the pixels P(0,0) and P(1,1) have a positive dot polarity pattern, and the pixels P(0,1) and P(1,0) have Negative point polarity pattern. However, in the next page box, the pixels will switch the dot polarity pattern. Therefore, in general, a pixel P(x, y) has a first dot polarity pattern when x+y is even, and a second dot polarity pattern when x+y is odd.

The pixel design 1120 can also be used in a display that uses a switching element row inversion driving mode. Figure 11 (h) shows a portion of the display 1180 having the pixels P (0, 0), P (1, 0), P (0, 1), and P (1) of the pixel design 1120. ,1). Display 1180 can have thousands of columns with thousands of pixels on each column. In display 1180, the pixels on the same column are spaced apart by a horizontal pixel spacing HPS, and the pixels in adjacent columns are spaced apart by a vertical pixel spacing VPS. The columns and rows will be successively arranged from the portion shown in Fig. 11(h) in the manner shown in Fig. 11(h). For the sake of clarity, the gate lines and source lines for controlling the switching elements are omitted in FIG. 11(h). In the display 1180, the pixels are arranged such that the pixels located in one column alternately have a dot polarity pattern (positive or negative), and the pixels located in one row have the same dot polarity pattern. Therefore, the pixels P(0, 0) and P(0, 1) have a positive dot polarity pattern, and the pixels P(1, 0) and P(1, 1) have a negative dot polarity pattern. However, in the next page box, the pixels will switch the dot polarity pattern. Therefore, in general, a pixel P(x, y) has a first dot polarity pattern when x is an even number and a second dot polarity pattern when x is an odd number.

The use of buried discrete field amplifiers is not limited to pixel designs with buried polar regions. Moreover, many embodiments of the present invention use a plurality of buried discrete field amplifiers one pixel. For example, Figures 12(a) and 12(b) show different dot polarity patterns for a pixel design 1210 (labeled 1210+ and 1210-), and the pixel design 1210 includes three buried discrete field amplifiers but Does not contain buried polar regions located in the color point. The pixel design 1210 is often used in displays having a switching element dot inversion driving mode or a switching element row inversion driving mode. In actual operation, a pixel will switch between a first dot polarity pattern and a second dot polarity pattern between each image frame.

The pixel design 1210 has three color components CC_1, CC_2, and CC_3 (not shown in Figures 12(a)-11(b)). Each of the three color components includes a two color point. For the sake of clarity, the color points are represented as CD_X_Y, where X is a one-color component (from 1 to 3 in Figures 12(a)-12(b)), and Y is a color point number (in the figure) 12(a)-12(b) is from 1 to 2). The pixel design 1210 also includes a switching element (denoted as SE_1, SE_2, and SE_3) for each color component and a buried discrete field amplifier (denoted EFFA_1, EFFA_2, and EFFA_3) for each color component. The switching elements SE_1, SE_2 and SE_3 are arranged in a row. Embedded discrete field The EFFA_1, EFFA_2, and EFFA_3 are also arranged in a row.

The first color component CC_1 of the pixel design 1210 has two color points CD_1_1 and CD_1_2. The color points CD_1_1 and CD_1_2 form a line and are spaced apart by a vertical dot pitch VDS1. In other words, the color points CD_1_1 and CD_1_2 are horizontally aligned and vertically spaced by the vertical dot pitch VDS1. Further, the color point CD_1_1 and the CD_1_2 are vertically shifted by the vertical dot offset VDO1, and the vertical dot offset VDO1 is equal to the vertical dot pitch VDS1 plus the color point height CDH. The switching element SE_1 is located above the color point CD_1_1. The switching element SE_1 is coupled to the electrodes of the color points CD_1_1 and CD_1_2 to control the voltage polarity and voltage of the color points CD_1_1 and CD_1_2.

Similarly, the second color component CC_2 of the pixel design 1210 has two color points CD_2_1 and CD_2_2. The color points CD_2_1 and CD_2_2 form a second line and are spaced apart by a vertical dot pitch VDS1. Therefore, the color points CD_2_1 and CD_2_2 are horizontally aligned and vertically spaced apart by the vertical dot pitch VDS1. The switching element SE_2 is located above the color point CD_2_1. The switching element SE_2 is coupled to the electrodes of the color points CD_2_1 and CD_2_2 to control the voltage polarity and voltage of the color points CD_2_1 and CD_2_2. The second color component CC_2 is vertically aligned with the first color component CC_1, and is spaced apart by a horizontal dot pitch HDS1 and the color component CC_1. Therefore, the color components CC_2 and CC_1 are horizontally shifted by a horizontal point offset HDD1, the horizontal point. The offset HDD1 is equal to the horizontal dot pitch HDS1 plus the color dot width CDW. Specifically, regarding the color point, the color point CD_2_1 and the color point CD_1_1 are vertically aligned and horizontally spaced by the horizontal dot pitch HDS1. Similarly, the color point CD_2_2 is vertically aligned with the color point CD_2_1 and horizontally spaced by the horizontal dot pitch HDS1. Therefore, the color point CD_1_1 and the color point CD_2_1 form a first column color point, and the color point CD_1_2 and the color point CD_2_2 form a second column color point.

Similarly, the third color component CC_3 of the pixel 1210 has two color points CD_3_1 and CD_3_2. The color points CD_3_1 and CD_3_2 form a third line and are spaced apart by a vertical dot pitch VDS1. Therefore, the color points CD_3_1 and CD_3_2 are horizontally aligned and vertically spaced apart by the vertical dot pitch VDS1. The switching element SE_3 is located above the color point CD_3_1. The switching element SE_3 is coupled to the electrodes of the color points CD_3_1 and CD_3_2 to control the voltage polarity and voltage of the color points CD_3_1 and CD_3_2. The third color component CC_3 is vertically aligned with the second color component CC_2, and is spaced apart from the color component CC_2 by the horizontal dot pitch HDS1, so that the color components CC_3 and CC_2 are horizontally shifted by a horizontal dot offset amount HDO1. Specifically, regarding the color point, the color point CD_3_1 and the color point CD_2_1 are vertically aligned and horizontally spaced by the horizontal dot pitch HDS1. open. Similarly, the color point CD_3_2 is vertically aligned with the color point CD_2_2 and horizontally spaced by the horizontal dot pitch HDS1. Therefore, the color point CD_3_1 is located on the first column color point, and the color point CD_3_2 is located on the second column color point.

For the sake of clarity, the various color points of the pixel design 1210 are illustrated with color points having the same color point height CDH. However, certain embodiments of the invention may include color points having different color point heights. For example, in one embodiment of the present invention, which is a variant of the pixel design 1210, the color point heights of the color points CD_1_1, CD_2_1, and CD_3_1 are smaller than the color point heights of the color points CD_1_2, CD_2_2, and CD_3_2. . Moreover, in many embodiments of the invention, the color points can have different shapes.

The pixel design 1210 also includes embedded discrete field amplifiers EFFA_1, EFFA_2, and EFFA_3. As shown in FIG. 12(a), the buried discrete field amplifiers EFFA_1, EFFA_2, and EFFA_3 are placed behind the color point of the pixel design 1210. Specifically, the buried discrete field amplifier EFFA_1 is placed such that the color point CD_1_1 and the color point CD_1_2 and the switching element SE_1 are located in front of the buried discrete field amplifier EFFA_1. However, the buried discrete field amplifier EFFA_1 extends beyond the left and right sides of the color points CD_1_1 and CD_1_2 to a horizontal buried electrode extension distance HEEED1. Similarly, the buried discrete field amplifier EFFA_1 extends beyond the top of the switching element SE_1 and the bottom of the color point CD_1_2 to a vertical buried electrode extension distance VEEED1. Therefore, the edges of the color points CD_1_1 and CD_1_2 are located in front of the portion of the buried discrete field amplifier EFFA_1. An electrode 1212 is used to couple the buried discrete field amplifier EFFA_1 to a voltage source. In general, in the switching element dot inversion driving mode display, the electrode 1212 is coupled to a color point CD_1_2 located at a pixel above the current pixel (see FIG. 12(c)). However, in the switching element row inversion driving mode display, the electrode 1212 is coupled to a color point CD_3_2 located at the upper left of the current pixel (see FIG. 12(d), pixel P(1, 0)). .

Similarly, the buried discrete field amplifier EFFA_2 is placed such that the color point CD_2_1 and the color point CD_2_2 and the switching element SE_2 are located in front of the buried discrete field amplifier EFFA_2. However, the buried discrete field amplifier EFFA_2 extends beyond the left and right sides of the color points CD_2_1 and CD_2_2 to a horizontal buried electrode extension distance HEEED1. Similarly, the buried discrete field amplifier EFFA_2 extends beyond the top of the switching element SE_2 and the bottom of the color point CD_2_2 to a vertical buried electrode extension distance VEEED1. Therefore, the edges of the color points CD_2_1 and CD_2_2 are located in front of the portion of the buried discrete field amplifier EFFA_2. In addition, the buried discrete field amplifier EFFA_2 is embedded and buried The field amplifier EFFA_1 is vertically aligned and spaced apart from the buried discrete field amplifier EFFA_1 by a horizontal buried electrode pitch HEES1. An electrode 1214 is used to couple the buried discrete field amplifier EFFA_1 to a voltage source. In general, in the switching element dot inversion driving mode display, the electrode 1214 is coupled to a color point CD_2_2 located at a pixel above the current pixel (see FIG. 12(c)). However, in the switching element row inversion driving mode display, the electrode 1214 is coupled to the color point CD_1_2 of one pixel above the current pixel (see FIG. 12(d), pixel P(1, 0)).

Similarly, the buried discrete field amplifier EFFA_3 is placed such that the color point CD_3_1 and the color point CD_3_2 and the switching element SE_3 are located in front of the buried discrete field amplifier EFFA_3. However, the buried discrete field amplifier EFFA_3 extends beyond the left and right sides of the color points CD_3_1 and CD_3_2 to a horizontal buried electrode extension distance HEEED1. Similarly, the buried discrete field amplifier EFFA_3 extends beyond the top of the switching element SE_3 and the bottom of the color point CD_3_2 to a vertical buried electrode extension distance VEEED1. Therefore, the edges of the color points CD_3_1 and CD_3_2 are located in front of the portion of the buried discrete field amplifier EFFA_3. In addition, the buried discrete field amplifier EFFA_3 is vertically aligned with the buried discrete field amplifier EFFA_2 and spaced apart from the buried discrete field amplifier EFFA_2 by a horizontal buried electrode pitch HEES1. An electrode 1216 is used to couple the buried discrete field amplifier EFFA_1 to a voltage source. In general, in the switching element dot inversion driving mode display, the electrode 1216 is coupled to a color point CD_3_2 located at a pixel above the current pixel (see FIG. 12(c)). However, in the switching element row inversion driving mode display, the electrode 1216 is coupled to the color point CD_2_2 of one pixel above the current pixel (see FIG. 12(d), pixel P(1, 0)).

Use the "+" and "-" symbols to display the color point, the embedded discrete field amplifier, and the polarity of the switching components. Therefore, in FIG. 12(a) in which the dot polarity pattern of the pixel design 1210+ is displayed, the switching elements SE_1 and SE_3, the color points CD_1_1, CD_1_2, CD_3_1, and CD_3_2, and the buried discrete field amplifier EFFA_2 have positive electrodes. Sex. However, the switching element SE_2, the color points CD_2_1 and CD_2_2, and the buried discrete field amplifiers EFFA_1 and EFFA_3 have negative polarity. Figure 12(b) shows a pixel design 1210 with a negative dot polarity pattern. For the negative dot polarity pattern, the switching elements SE_1 and SE_3, the color points CD_1_1, CD_1_2, CD_3_1, and CD_3_2, and the buried discrete field amplifier EFFA_2 have negative polarity. However, the switching element SE_2, the color points CD_2_1 and CD_2_2, and the buried discrete field amplifiers EFFA_1 and EFFA_3 have positive polarity. Other embodiments of the invention may use a neutral polarity for the buried discrete field amplifiers EFFA_1, EFFA_2, and EFFA_3. For example, in a particular embodiment of the invention, the embedding The field amplifiers EFFA_1, EFFA_2, and EFFA_3 are coupled to a common voltage V_com.

Figure 12 (c) shows a portion of display 1220 having pixels of pixel design 1010 P(0,0), P(1,0), P(0,1), and P(1). ,1). Display 1220 uses a switching element dot inversion drive mode. Display 1220 can have thousands of columns with thousands of pixels on each column. In display 1220, the pixels on the same column are spaced apart by a horizontal pixel spacing HPS, and the pixels in adjacent columns are spaced apart by a vertical pixel spacing VPS. The columns and rows will be successively arranged from the portion shown in Fig. 12(c) in the manner shown in Fig. 12(c). For the sake of clarity, the gate lines and source lines for controlling the switching elements are omitted in Figure 12(c). In the display 1220, the pixels are arranged such that the pixels located in one column alternately have a dot polarity pattern (positive or negative), and the pixels in one row are also in a positive dot polarity pattern and a negative point. The polarity patterns alternate between each other. Therefore, the pixels P(0, 0) and P(1, 1) have a positive dot polarity pattern, and the pixels P(0, 1) and P(1, 0) have a negative dot polarity pattern. However, in the next page box, the pixels will switch the dot polarity pattern. Therefore, in general, a pixel P(x, y) has a first dot polarity pattern when x+y is even, and a second dot polarity pattern when x+y is odd.

The pixel design 1210 can also be used in a display that uses a switching element row inversion driving mode. Figure 12 (d) shows a portion of display 1230 having the pixels P10 (0, 0), P (1, 0), P (0, 1), and P (1) of pixel design 1210. ,1). Display 1230 can have thousands of columns with thousands of pixels on each column. In display 1230, the pixels on the same column are spaced apart by a horizontal pixel spacing HPS, and the pixels in adjacent columns are spaced apart by a vertical pixel spacing VPS. The columns and rows will be successively arranged from the portion shown in Fig. 12(d) in the manner shown in Fig. 12(d). For the sake of clarity, the gate lines and source lines for controlling the switching elements are omitted in Figure 12(d). In display 1230, the pixels are arranged such that pixels located in a column alternately have a dot polarity pattern (positive or negative), and pixels located in one row have the same dot polarity pattern. Therefore, the pixels P(0, 0) and P(0, 1) have a positive dot polarity pattern, and the pixels P(1, 0) and P(1, 1) have a negative dot polarity pattern. However, in the next page box, the pixels will switch the dot polarity pattern. Therefore, in general, a pixel P(x, y) has a first dot polarity pattern when x is an even number and a second dot polarity pattern when x is an odd number.

Figures 13(a) and 13(b) show different dot polarity patterns for a pixel design 1310 (labeled 1310+ and 1310-), and the pixel design 1310 can be used with a display having a switching element column inversion driving mode. use. The layout of the pixel design 1310 is the same as the pixel design 1210, so it will not be given To repeat. However, the polarity of the buried discrete field amplifier EFFA_2, the switching element SE_2, and the color points CD_2_1 and CD_2_2 in the pixel design 1310 is reversed compared to the pixel design 1210. Therefore, in FIG. 13(a) in which the dot polarity pattern of the pixel design 1310+ is displayed, the switching elements SE_1, SE_2, and SE_3, the color points CD_1_1, CD_1_2, CD_2_1, CD_2_2, CD_3_1, and CD_3_2 have positive polarity. However, the buried discrete field amplifiers EFFA_1, EFFA_2, and EFFA_3 have negative polarity. Figure 13 (b) shows a pixel design 1310 having a negative dot polarity pattern. For the negative dot polarity pattern, the switching elements SE_1, SE_2, and SE_3, the color points CD_1_1, CD_1_2, CD_2_1, CD_2_2, CD_3_1, and CD_3_2 have negative polarity. However, the buried discrete field amplifiers EFFA_1, EFFA_2, and EFFA_3 have positive polarity. In other embodiments of the invention, the buried discrete field amplifiers EFFA_1, EFFA_2, and EFFA_3 have a neutral polarity.

Figure 13 (c) shows a portion of the display 1320, which has pixels of the pixel design 1310 P(0,0), P(1,0), P(0,1), and P(1). ,1). Display 1320 uses a switching element column inversion drive mode. Display 1320 can have thousands of columns with thousands of pixels on each column. In display 1320, the pixels on the same column are spaced apart by a horizontal pixel spacing HPS, and the pixels in adjacent columns are spaced apart by a vertical pixel spacing VPS. The columns and rows will be successively arranged from the portion shown in Fig. 13(c) in the manner shown in Fig. 13(c). For the sake of clarity, the gate lines and source lines for controlling the switching elements are omitted in FIG. 13(c). The pixels of display 1320 are arranged such that all pixels in a column have the same point polarity pattern (positive or negative), and each successive column should be between a positive dot polarity pattern and a negative dot polarity pattern. alternately. Therefore, the pixels P(0,0) and P(1,0) in the first column (ie, column 0) have a positive dot polarity pattern, and the pixel P in the second column (ie, column 1) (0, 1) and P (1, 1) have a negative dot polarity pattern. However, in the next page box, the pixels will switch the dot polarity pattern. Therefore, in general, a pixel P(x, y) has a first dot polarity pattern when y is an even number and a second dot polarity pattern when y is an odd number.

One of the disadvantages of including a buried discrete field amplifier is that additional energy is required to bias the buried discrete field amplifier. This additional energy requirement is proportional to the size of the buried discrete field amplifier. Thus, many embodiments of the present invention use a buried discrete field amplifier having a smaller area instead of a rectangular buried discrete field amplifier. Since the buried discrete field amplifier is used to amplify the discrete field at the edge of the color point, the portion of the discrete field amplifier that is buried to maximize the discrete field is near the edge of the color point. Therefore, the buried discrete field amplifier can be removed behind the middle of the color point Part of it. Thus, for example, one embodiment of the present invention replaces the rectangular buried discrete field amplifier shown above with the buried discrete field amplifier shown in FIG.

Figure 14 shows a buried discrete field amplifier 1400. For the sake of clarity, the buried discrete field amplifier 1400 is conceptually divided into a vertical buried portion and a horizontal buried portion. Specifically, the buried discrete field amplifier 1400 includes two vertical buried portions VEP_1 and VEP_2 and three horizontal buried portions HEP_1, HEP_2, and HEP_3. The position of the vertical embedding portion and the horizontal embedding portion will be described for the case where the buried discrete field amplifier 1400 is used instead of the buried discrete field amplifier EFFA_1 of the pixel design 13(a). The vertical embedding portion VEP_1 is located behind the right edges of the color points CD_1_1 and CD_1_2 (Fig. 13(a)). The vertical embedding portion VEP_2 is located behind the left edges of the color points CD_1_1 and CD_1_2 (Fig. 13(a)). The horizontal embedding portion HEP_1 is located behind the bottom edge of the color point CD_1_2; the horizontal embedding portion HEP_2 is located at the upper edge of the color point CD_1_2 and behind the lower edge of the color point CD_1_1; and the horizontal embedding portion HEP_3 is located above the color point CD_1_1 Behind the edge. As shown in FIG. 14, the horizontal embedding portion HEP_2 is wider than the horizontal embedding portions HEP_1 and HEP_3. The extra width of the horizontal buried portion HEP_2 is used for two purposes. First, the reason why the horizontal embedding portion HEP_2 is wider is because it is located behind the upper edge of the color point CD_1_2 and the lower edge of the color point CD_1_1 to enlarge the discrete fields of the color points CD_1_1 and CD_1_2. Secondly, the horizontal embedding portion HEP_2 can be used as a storage capacitor for one of the color points CD_1_1 and CD_1_2. The larger the area, the larger the charge storage capacity. In a particular embodiment of the invention, the color point CD_1_1 has a width (horizontal) of 28 microns and a length (vertical) of 30 microns, and the color point CD_1_2 has a width of 28 microns and a height of 30 microns, horizontally buried The portion HEP_1 has a width of one micron and a height of three micrometers; the horizontal embedding portion HEP_2 has a width of one of 28 micrometers and a height of one micrometer; the horizontal embedding portion HEP_3 has one width of 15 micrometers and one of three micrometers. The height; the vertical embedding portion VEP_1 has a width of one micrometer and a height of 95 micrometers; and the vertical embedding portion VEP_2 has a width of one micrometer and one height of 80 micrometers.

Another advantage of using a buried discrete field amplifier that extends only along the edges of the color point is that the buried discrete field amplifier does not need to be formed using a transparent conductive material. Thus, a non-transparent material (eg, a metal layer) for other components of the display (eg, switching elements, source lines, and data lines) can be used to form the buried discrete field amplifier 1400 (and other buried as described below) Set the discrete field amplifier). Thus, embodiments of the invention can be made using a single ITO layer rather than a two ITO layer. Reducing the number of layers reduces the manufacturing cost of a display due to the number of manufacturing steps and the mask The number will decrease.

As noted above, in some embodiments of the invention, the layers used to form the buried discrete field amplifier are also used in a switching element. Thus, for these embodiments, the buried discrete field amplifier does not extend to the switching element. Figure 15 shows a buried discrete field amplifier 1500 that does not extend to the switching element. For the sake of clarity, the buried discrete field amplifier 1500 is conceptually divided into a vertical buried portion and a horizontal buried portion. Specifically, the buried discrete field amplifier 1500 includes two vertical buried portions VEP_1 and VEP_2, three horizontal buried portions HEP_1, HEP_2, and HEP_3, and an optional fourth horizontal buried portion HEP_4. The position of the vertical embedding portion and the horizontal embedding portion will be described for the case where the buried discrete field amplifier 1500 is used instead of the buried discrete field amplifier EFFA_1 of the pixel design 13(a). The vertical embedding portion VEP_1 is located behind the right edges of the color points CD_1_1 and CD_1_2 (Fig. 13(a)). The vertical embedding portion VEP_2 is located behind the left edge of the color point CD_1_2 and behind one of the left edges of the color point CD_1_1 (Fig. 13(a)). Specifically, the vertical embedding portion VEP_2 does not extend to the position where the switching element SE_1 at the upper left corner of the color point CD_1_1 is positioned. The horizontal embedding portion HEP_1 is located behind the bottom edge of the color point CD_1_2; the horizontal embedding portion HEP_2 is located at the upper edge of the color point CD_1_2 and behind the lower edge of the color point CD_1_1; and the horizontal embedding portion HEP_3 is located above the color point CD_1_1 Behind one of the edges. Specifically, the horizontal embedding portion HEP_3 does not extend to the position where the switching element SE_1 at the upper left corner of the color point CD_1_1 is positioned. The horizontal embedding portion HEP_2 of the buried discrete field amplifier 1500 is wider than the horizontal embedding portions HEP_1 and HEP_3, as described above with respect to the horizontal embedding portion HEP_3 in which the discrete field amplifier 1400 is buried. The buried discrete field amplifier 1500 is shown with an optional horizontal buried portion HEP_4 that extends a small distance to the right from the right edge of the vertical buried portion VEP_1. The horizontal embedding portion HEP_4 is vertically centered on the horizontal embedding portion HEP_2. The horizontal buried portion HEP_4 is for coupling a first buried discrete field amplifier to a second buried discrete field amplifier located on the right side of the first buried discrete field amplifier. Therefore, the horizontal buried portion HEP_4 is used only when the first buried discrete field amplifier and the second buried discrete field amplifier have the same polarity. For example, in a pixel that uses a neutral polarity for a buried discrete field amplifier, including the horizontal buried portion HEP_4 will easily provide a neutral polarity for all buried discrete field amplifiers. In a particular embodiment of the invention, the color point CD_1_1 has a width (horizontal) of 28 microns and a length (vertical) of 30 microns, and the color point CD_1_2 has a width of 28 microns and a height of 30 microns, horizontally buried The portion HEP_1 has a width of 28 microns and a height of 3 microns; the horizontal buried portion HEP_2 has 28 microns One of the width and one height of 5 microns; the horizontal embedding portion HEP_3 has a width of one of 15 microns and a height of one of three microns; the horizontal embedding portion HEP_4 has a width of one of 15 microns and a height of 12 microns; the vertical embedding portion VEP_1 has a width of one micron and a height of 95 micrometers; and the vertical embedding portion VEP_2 has a width of one micron and a height of one of 80 micrometers.

In addition to amplifying discrete fields, buried discrete field amplifiers can also be used to improve cell gap uniformity and reduce the liquid crystal effects of other components of the display (eg, photo spacers). 16 shows a buried discrete field amplifier 1600 in accordance with another embodiment of the present invention. The buried discrete field amplifier 1600 also improves cell gap uniformity and reduces the effect of the optical spacer on the liquid crystal. For the sake of clarity, the buried discrete field amplifier 1600 is conceptually divided into a vertical buried portion and a horizontal buried portion. Specifically, the buried discrete field amplifier 1600 includes four vertical buried portions VEP_1, VEP_2, VEP_3, and VEP_4 and four horizontal buried portions HEP_1, HEP_2, HEP_3, and HEP_4. The position of the vertical embedding portion and the horizontal embedding portion will be described for the case where the buried discrete field amplifier 1600 is used instead of the buried discrete field amplifier EFFA_1 of the pixel design 13(a). The vertical embedding portion VEP_1 is located behind the right edge of the color point CD_1_2 (Fig. 13(a)). The vertical embedding portion VEP_2 is located behind the left edge of the color point CD_1_2 (Fig. 13(a)). The vertical embedding portion VEP_3 is located behind the right edge of the color point CD_1_1 (Fig. 13(a)). The vertical embedding portion VEP_4 is located behind the left edge of the color point CD_1_1 (Fig. 13(a)). The horizontal embedding portion HEP_1 is located behind the bottom edge of the color point CD_1_2 and also slightly extends to the right side of the vertical embedding portion VEP_1 and slightly extends to the left side of the vertical embedding portion VEP_2. The extension of the horizontal embedding portion HEP_1 beyond the portions of the vertical embedding portions VEP_1 and VEP_2 improves the cell gap uniformity. The horizontal embedding portion HEP_2 is located at the upper edge of the color point CD_1_2 and behind the lower edge of the color point CD_1_1. The horizontal embedding portion HEP_2 extends to the left side of the vertical embedding portions VEP_2 and VEP_4 to improve cell gap uniformity. The horizontal embedding portion HEP_3 is located behind one of the upper edges of the color point CD_1_1. Specifically, the horizontal embedding portion HEP_3 does not extend to the position where the switching element SE_1 at the upper left corner of the color point CD_1_1 is positioned. The horizontal embedding portion HEP_4 is included to improve cell gap uniformity, and extends to the left side of the vertical embedding portion VEP_4 and is aligned approximately perpendicularly to the horizontal embedding portion HEP_3. The horizontal embedding portion HEP_2 of the buried discrete field amplifier 1600 is wider than the horizontal embedding portions HEP_1, HEP_3, and HEP_4, as described above with respect to the horizontal embedding portion HEP_2 in which the discrete field amplifier 1400 is buried. In a particular embodiment of the invention, the color point CD_1_1 has a width (horizontal) of 28 microns and a length (vertical) of 30 microns, and the color point CD_1_2 has a width of 28 microns and a thickness of 30 microns. A height, horizontal embedding portion HEP_1 has a width of one of 32 microns and a height of one micron; the horizontal embedding portion HEP_2 has a width of one of 32 microns and a height of 5 microns; the horizontal embedding portion HEP_3 has a width of 15 microns. And a height of one micron; the horizontal embedding portion HEP_4 has a width of one of 15 micrometers and a height of one micrometer; the vertical embedding portion VEP_1 has a width of one micron and a height of 28 micrometers; the vertical embedding portion VEP_2 has 3 One of the micrometers and one of the heights of 28 microns; the vertical embedding portion VEP_3 has a width of one micron and one of 28 micrometers; the vertical embedding portion VEP_4 has a width of one micron and one height of 28 micrometers.

The above pixel design can also be modified for use in a transflective display that provides better performance in a bright environment (eg, outdoors on a clear day). In accordance with some embodiments of the present invention, a subset of color points is made using a reflective material rather than a transparent material. Figure 17 shows a pixel design 1710, which is designed for a transflective display. The pixel design 1710 is almost identical to the pixel design 1210. Therefore, only the differences will be explained. Specifically, in the pixel design 1210, the color points CD_1_1, CD_2_2, and CD_3_1 are formed as reflective color points, as indicated by hatching in the color points CD_1_1, CD_2_2, and CD_3_1. Reflective dots use a reflective material (eg, aluminum) rather than a transparent material. Other color points, switching elements, and buried polarity regions (including the polarity of the polarization components) are the same as the pixel design 1210. Thus, the pixel design 1710 can be used in the various displays described above using the pixel design 1210. In other embodiments of the invention, a different subset of color points is selected as a reflective color point. For example, the color points CD_1_2, CD_2_1, and the color point CD_3_2 may be reflective color dots, and the color points CD_1_1, CD_2_2, and CD_3_1 may be transmissive color points. In general, reflective color dots should be evenly dispersed throughout the display to provide uniform performance in the display. Similarly, the other pixel designs described above can also be modified to use reflective color points.

Figure 18 illustrates a transflective color dot 1800 in accordance with one embodiment of the present invention. A transflective color dot can be used in place of a normal transmissive color point to convert a conventional transmissive display into a transflective display. Thus, the transflective color points described herein can be used to modify any of the above pixel designs. Specifically, the transflective color point 1800 includes two rectangular transmissive portions TP_1 and TP_2 which are spaced apart by a reflecting portion RP_1. For the sake of clarity, the reflections RP_1 are drawn using shading. The transmissive portion is made using a transparent conductive material such as ITO. The reflective portion is made using a reflective conductive material such as aluminum. In some embodiments of the invention, the transparent portions TP_1 and TP_2 and the reflective portion RP_1 have the same size. In other embodiments of the invention, the reflecting portion RP_1 is larger than the transparent portions TP_1 and TP_2. In other embodiments of the invention, other transflective color dots are used. In general, a half transflective color dot will have one or more transparent portions and one or more reflective portions. The area ratio of the transparent portion to the reflective portion is usually between 3:1 and 1:1. In general, when the ambient light is bright (for example, in an outdoor environment during the day), the higher the ratio of the reflective areas, the better the performance.

Other modifications can be made to displays that use reflective color dots or transflective color points to improve the performance of the display. For example, the color filter above the reflective color point and the reflective portion of the transflective color point can be reduced, because the reflected light passes through the filter color twice (once on the way to the reflective color point) , once on the way back to the viewer of the display). For example, in one embodiment of the invention, the thickness of the color filter above a reflective color point is only one-half the thickness of the color filter above a transmissive color point. In other embodiments of the invention, the color filter (or the reflective portion of the transflective color point) above the reflective color point is reduced by more than 50% to improve brightness.

In various embodiments of the present invention, a novel structure and method for producing a multi-region vertical alignment liquid crystal display without the use of physical features on the substrate has been described. The various embodiments of the present invention are not intended to limit the scope of the present invention to the specific embodiments. For example, in the context of the present disclosure, those skilled in the art can define other pixel definitions, buried polar regions, buried discrete field amplifiers, field reduction layers, insulating layers, passivation layers, conductive layers, voids, and dots. Polarity pattern, pixel design, color component, polar extension region, polarity, discrete field, electrode, substrate, film, color point, reflective color point, transflective color point, etc., and are used in accordance with the principles of the present invention These alternative features result in a method or system. Accordingly, the invention is limited only by the scope of the following claims.

302‧‧‧First polarizer

305‧‧‧First substrate

307‧‧‧First alignment layer

310‧‧‧ pixels

311‧‧‧First electrode

312‧‧‧LCD

313‧‧‧LCD

315‧‧‧second electrode

320‧‧‧ pixels

321‧‧‧first electrode

322‧‧‧LCD

323‧‧‧LCD

325‧‧‧second electrode

327‧‧‧ electric field

330‧‧‧ pixels

331‧‧‧First electrode

332‧‧‧LCD

333‧‧‧LCD

335‧‧‧second electrode

352‧‧‧Second alignment layer

355‧‧‧second substrate

357‧‧‧Second polarizer

410‧‧‧ pixel design

500‧‧‧ color point

510‧‧‧electrode

512‧‧‧ buried polar area

514‧‧‧ Passivation layer

516‧‧‧ embedded electrode

518‧‧‧Change the conductivity area

600‧‧‧ color point

610‧‧‧electrode

612‧‧‧ Buried polar area

614‧‧‧ Passivation layer

616‧‧‧ buried electrode

710‧‧‧ pixel design

712‧‧‧Conductor

714‧‧‧Conductor

716‧‧‧Conductor

720‧‧‧ display

730‧‧‧ display

740‧‧‧ display

810‧‧‧ pixel design

812‧‧‧Conductor

820‧‧‧ display

821‧‧‧Transparent substrate

823‧‧‧ Passivation layer

827‧‧‧ Passivation layer

840‧‧‧ display

910‧‧ ‧ pixel design

920‧‧‧ display

1010‧‧‧ pixel design

1020‧‧‧ display

1030‧‧‧ display

1110‧‧‧ pixel design

1112‧‧‧Electrode

1114‧‧‧electrode

1116‧‧‧electrode

1121‧‧‧Transparent substrate

1123‧‧‧ Passivation layer

1127‧‧‧ Passivation layer

1140‧‧‧ display

1160‧‧‧ display

1210‧‧‧ pixel design

1214‧‧‧electrode

1216‧‧‧ electrodes

1220‧‧‧ display

1230‧‧‧ display

1310‧‧‧ pixel design

1320‧‧‧ display

1400‧‧‧ embedded discrete field amplifier

1500‧‧‧ embedded discrete field amplifier

1600‧‧‧ embedded discrete field amplifier

1710‧‧‧ pixel design

1800‧‧‧ color point

CC_1‧‧‧ color component

CC_2‧‧‧ color component

CC_3‧‧‧ color component

CD_1_1‧‧‧ color point

CD_1_2‧‧‧ color point

CD_1_3‧‧‧ color point

CD_2_1‧‧‧ color point

CD_2_2‧‧‧ color point

CD_2_3‧‧‧ color point

CD_3_1‧‧‧ color point

CD_3_2‧‧‧ color point

CDH‧‧‧ color point height

CDW‧‧‧ color point width

DCA_1‧‧‧ device component area

DCA_2‧‧‧ device component area

DCA_3‧‧‧ device component area

EPR_1_1‧‧‧ buried polar area

EPR_1_2‧‧‧ buried polar area

EPR_2_1‧‧‧ buried polar area

EPR_2_2‧‧‧ buried polar area

EPR_3_1‧‧‧ buried polar area

EPR_3_2‧‧‧ buried polar area

EPR_SE_0_1‧‧‧ Buried Polar Area Switching Element

EPR_SE_0_2‧‧‧ Buried Polar Area Switching Element

EPR_SE_1_1‧‧‧ Buried Polar Area Switching Element

EPR_SE_1_2‧‧‧ Buried Polar Region Switching Element

FFAR_1‧‧‧Discrete field magnification area

FFAR_2‧‧‧Discrete field magnification area

FFAR_3‧‧‧Discrete field magnification area

HAP‧‧‧Horizontal Zoom Department

HAP_H‧‧‧Horizontal magnification

HAP_W‧‧‧ horizontal magnification

HDO1‧‧‧ horizontal point offset

HDS1‧‧‧ horizontal point spacing

HFFARS‧‧‧ horizontal discrete field amplification area spacing

HPS‧‧‧ horizontal pixel spacing

SE_1‧‧‧Switching components

SE_2‧‧‧Switching element

SE_3‧‧‧Switching components

VDO1‧‧‧ vertical point offset

VDS1‧‧‧ vertical point spacing

VFFARS‧‧‧Vertical discrete field amplification area spacing

VPS‧‧‧ vertical pixel spacing

1(a)-1(c) are three diagrams of one of the pixels of a conventional single-region vertical alignment liquid crystal display.

Figure 2 is an illustration of one of the pixels of a conventional multi-region vertical alignment liquid crystal display.

3(a)-3(b) illustrate a multi-area vertical distribution according to an embodiment of the present invention To the liquid crystal display.

4(a)-4(b) illustrate a pixel design in accordance with an embodiment of the present invention.

Figures 5(a)-5(c) illustrate a color point in accordance with an embodiment of the present invention.

6(a)-6(b) illustrate a color point in accordance with an embodiment of the present invention.

7(a)-7(c) illustrate a pixel design in accordance with an embodiment of the present invention.

Figure 7 (d) illustrates a portion of a display in accordance with an embodiment of the present invention.

Figure 7 (e) illustrates a portion of a display in accordance with an embodiment of the present invention.

Figure 7 (f) illustrates a portion of a display in accordance with an embodiment of the present invention.

8(a)-8(c) illustrate a pixel design in accordance with an embodiment of the present invention.

Figure 8 (d) illustrates a portion of a display in accordance with an embodiment of the present invention.

Figures 9(a)-9(b) illustrate a pixel design in accordance with an embodiment of the present invention.

Figure 9 (c) illustrates a portion of a display in accordance with an embodiment of the present invention.

Figures 10(a)-10(b) illustrate a pixel design in accordance with an embodiment of the present invention.

Figure 10 (c) illustrates a portion of a display in accordance with an embodiment of the present invention.

Figure 10 (d) illustrates a portion of a display in accordance with an embodiment of the present invention.

11(a)-11(c) illustrate a pixel design in accordance with an embodiment of the present invention.

Figure 11 (d) illustrates a portion of a display in accordance with an embodiment of the present invention.

11(e)-11(f) illustrate a pixel design in accordance with an embodiment of the present invention.

Figure 11 (g) illustrates a portion of a display in accordance with an embodiment of the present invention.

Figure 11 (h) illustrates a portion of a display in accordance with an embodiment of the present invention.

12(a)-12(b) illustrate a pixel design in accordance with an embodiment of the present invention.

Figure 12 (c) illustrates a portion of a display in accordance with an embodiment of the present invention.

Figure 12 (d) illustrates a portion of a display in accordance with an embodiment of the present invention.

Figures 13(a)-13(b) illustrate a pixel design in accordance with an embodiment of the present invention.

Figure 13 (c) illustrates a portion of a display in accordance with an embodiment of the present invention.

Figure 14 illustrates a buried discrete field amplifier.

Figure 15 illustrates a buried discrete field amplifier.

Figure 16 illustrates a buried discrete field amplifier.

Figure 17 illustrates a transflective pixel design in accordance with one embodiment of the present invention.

Figure 18 illustrates a transflective color dot in accordance with one embodiment of the present invention.

810‧‧‧ pixel design

CD_1_1‧‧‧ color point

CD_1_2‧‧‧ color point

CD_2_1‧‧‧ color point

CD_2_2‧‧‧ color point

CD_3_1‧‧‧ color point

CD_3_1‧‧‧ color point

CDH‧‧‧ color point height

CDW‧‧‧ color point width

EFFA_1‧‧‧ embedded discrete field amplifier

EPR_1_1‧‧‧ buried polar area

EPR_2_1‧‧‧ buried polar area

EPR_3_1‧‧‧ buried polar area

HDO1‧‧‧ horizontal point offset

HDS1‧‧‧ horizontal point spacing

VDO1‧‧‧ vertical point offset

VDS1‧‧‧ vertical point spacing

Claims (29)

A pixel for a display, comprising: a first color component having a first color component first color point; a first switching component coupled to the first color component first color point; a buried discrete field amplifier located after the first color point of the first color component, wherein at least a first edge and a second edge of the first color component of the first color component are located in front of the first embedded discrete field amplifier . According to the pixel of claim 1, the method further includes: a second color component having a second color component, wherein the second color component has at least a first edge of the first color point and a second edge is located in front of the first buried discrete field amplifier; and a second switching element is coupled to the first color component first color point. According to the pixel of claim 2, the method further includes: a third color component having a first color point of the third color component, wherein the third color component has at least a first edge of the first color point and a second edge is located in front of the second buried discrete field amplifier; and a third switching element is coupled to the first color point of the third color component. The pixel according to claim 3, wherein the first switching element, the second switching element, and the third switching element have a first polarity direction. The pixel of claim 4, wherein the first buried discrete field amplifier has a neutral polarity. The pixel according to claim 4, wherein the first buried discrete field amplifier has a second polarity direction. According to the pixels described in item 3 of the patent application, Wherein the first switching element and the third switching element have a first polarity direction; and wherein the second switching element has a second polarity direction. The pixel according to claim 7, wherein the first buried discrete field amplifier has a neutral polarity. The pixel of claim 2, wherein the first color component further comprises a first color component, a second color point, the first color component, the second color point being coupled to the first switching component, wherein At least one first edge and a second edge of the second color point of the first color component are located in front of the first buried discrete field amplifier. The pixel according to claim 9, wherein the first color component is located above the first switching element, and the first color component is located below the first switching component. . The pixel according to claim 9, wherein the first color component is located between the first switching element and the second color point of the first color component. The pixel according to claim 9 , wherein the first color component is a transparent color dot, and the first color component second color dot is a reflective color dot. The pixel according to claim 9 , wherein the second color component further comprises a second color component, the second color point is coupled to the second switching component, wherein the second color component is coupled to the second switching component, wherein The at least one first edge and the second edge of the second color component second color point are located in front of the first buried discrete field amplifier. According to the pixel of claim 13, the method further includes: a third color component having a third color component, a first color point, and a third color a second color point of the component, wherein the at least one first edge and the second edge of the first color point of the third color component are located in front of the first embedded discrete field amplifier, and wherein the third color component is the second color point The at least one first edge and the second edge are located in front of the first embedded discrete field amplifier, wherein: a third switching component is coupled to the third color component first color point and the third color component The second color point. The pixel according to claim 14, wherein the first color component first color point, the second color component first color point, and the third color component first color point form a first column color point . The pixel according to claim 15, wherein the first color component second color dot, the second color component second color dot, and the third color component second color dot form a second column color dot . The pixel according to claim 16, wherein the first switching element, the second switching element, and the third switching element are located between the first column color point and the second column color point. The pixel according to claim 17, wherein the first switching element, the second switching element, and the third switching element are located in front of the first buried discrete field amplifier. The pixel according to claim 14, wherein the first color component is a reflective color dot; wherein the second color component is a reflective color dot; The first color point of the third color component is a reflective color point. The pixel according to claim 19, wherein the second color point of the first color component is a transparent color point; The first color point of the second color component is a transparent color point; and wherein the second color component is a transparent color point. The pixel according to claim 14, wherein the first color component is a semi-transflective color point; wherein the second color component is a half transflective a color point; and wherein the first color point of the third color component is a semi-transflective color point. The pixel according to claim 21, wherein the second color point of the first color component is a semi-transflective color point; wherein the first color component is half transflective a color point; and wherein the third color component is a half transflective color point. The pixel according to claim 14, wherein the first switching element, the second switching element, and the third switching element have a first polarity direction. The pixel according to claim 23, wherein the first buried discrete field amplifier has a neutral polarity. The pixel according to claim 23, wherein the first buried discrete field amplifier has a second polarity direction. The pixel according to claim 14, wherein the first switching element and the third switching element have a first polarity direction; and wherein the second switching element has a second polarity direction. The pixel according to claim 26, wherein the first buried discrete field amplifier has a neutral polarity. The pixel according to claim 1, wherein the first color component is a semi-transparent color point. The pixel according to claim 1, wherein the first embedded discrete field amplifier is made of a transparent material.