TW201329570A - Liquid crystal displays having pixels with embedded fringe field amplifiers - Google Patents
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本發明係關於一種液晶顯示器,特別是指一種可以平滑型基板製造的大畫素多區域垂直配向液晶顯示器。 The present invention relates to a liquid crystal display, and more particularly to a large pixel multi-region vertical alignment liquid crystal display that can be fabricated on a smooth substrate.
初次使用在如計算機與電子錶的簡單單色顯示器的液晶顯示器(Liquid Crystal Display,LCD),係已變成最優勢的顯示科技。液晶顯示器係經常用來取代陰極射線管(Cathode Ray Tube,CRT)在電腦顯示與電視顯示上的應用。液晶顯示器的各種缺點已經被克服以改善液晶顯示器的品質。舉例來說,廣泛地取代被動矩陣顯示器的主動矩陣顯示器,係相對於被動矩陣顯示器具有降低鬼影(Ghosting)且改善解析度(Resolution)、色階(Color Gradation)、視角(Viewing Angle)、對比(Contrast Ratio)以及反應時間(Response Time)的成效。 The liquid crystal display (LCD), which is used for the first time in simple monochrome displays such as computers and electronic watches, has become the most advantageous display technology. Liquid crystal displays are often used to replace the use of cathode ray tubes (CRTs) in computer displays and television displays. Various shortcomings of liquid crystal displays have been overcome to improve the quality of liquid crystal displays. For example, active matrix displays that widely replace passive matrix displays have reduced ghosting and improved resolution, color gradation, viewing angle, and contrast relative to passive matrix displays. (Contrast Ratio) and the effect of response time (Response Time).
然而,傳統扭轉向列液晶顯示器(Twisted Nematic LCD)的主要缺點係為非常窄的視角以及非常低的對比。甚至連主動式矩陣的視角更窄於陰極射線管的視角。尤其是當觀看者直接地在液晶顯示器前面收看一高畫質影像時,在液晶顯示器側旁的其他觀看者則無法看到此一高畫質影像。多區域垂直配向液晶顯示器(Multi-domain Vertical Alignment Liquid Crystal Display,MVA LCD)係被發展來改善液晶顯示器的視角以及對比。請參考圖1(a)-1(c),係表示一垂直配向液晶顯示器100的畫素基本功能。為了清楚地解說,圖1的液晶顯示器係僅使用單一區域(Single Domain)。再者,為了清楚地解說,圖1(a)-1(c)(以及圖2)的液晶顯示器係依據灰階操作來敘述。 However, the main drawback of conventional twisted nematic LCDs is the very narrow viewing angle and very low contrast. Even the perspective of the active matrix is narrower than the viewing angle of the cathode ray tube. Especially when the viewer directly views a high-quality image directly in front of the liquid crystal display, other high-quality images cannot be seen by other viewers beside the liquid crystal display. Multi-domain Vertical Alignment Liquid Crystal Display (MVA LCD) has been developed to improve the viewing angle and contrast of liquid crystal displays. Please refer to FIG. 1(a)-1(c) for showing the basic functions of a pixel of a vertical alignment liquid crystal display 100. For clarity of illustration, the liquid crystal display of Figure 1 uses only a single domain (Single Domain). Furthermore, for clarity of explanation, the liquid crystal display of FIGS. 1(a)-1(c) (and FIG. 2) is described in terms of gray scale operation.
液晶顯示器100具有一第一偏光片105、一第一基板110、一第一電極120、一第一配向層125、多個液晶130、一第二配向層140、一第二電極145、一第二基板150以及一第二偏光片155。一般而言,第一基板110與第二基板150係由透明玻璃所製成。第一電極120與第二電極145係由如 氧化銦錫(Indium Tin Oxide,ITO)之透明導電材質所製成。第一配向層125與第二配向層140係由聚醯亞氨(Polyimide,PI)所製成,且與在靜止態之液晶130垂直地配向。在操作時,一光源(圖未示)係從貼附在第一基板110之在下面的第一偏光片105射出光線。第一偏光片105係通常在一第一方向偏振,且貼附在第二基板150的第二偏光片155係與第一偏光片104垂直地偏振。因此,從光源而來的光線並不會同時穿透第一偏光片105與第二光偏光片155,除非光線的偏振在第一偏光片105與第二偏光片155之間旋轉90度。為了清楚說明,並未顯示很多的液晶。在實際的顯示器中,液晶係為棒狀分子(rod like molecules),其直徑大約為5埃(Angstrom,Å),長度大約20-25埃。因此,在一畫素中有超過一千兩百萬的液晶分子,其中畫素的長、寬、高分別為300微米(micrometer,μm)、120微米、3微米。儘管圖未示出,然而許多液晶顯示器(尤其係主動矩陣式液晶顯示器)於第一電極120之底部上包含一鈍化層(passivation layer)。鈍化層係於第一電極120與可能形成於基板上之裝置及導體之間用作一絕緣層。鈍化層通常係使用氮化矽形成。 The liquid crystal display 100 has a first polarizer 105, a first substrate 110, a first electrode 120, a first alignment layer 125, a plurality of liquid crystals 130, a second alignment layer 140, a second electrode 145, and a first Two substrates 150 and a second polarizer 155. In general, the first substrate 110 and the second substrate 150 are made of transparent glass. The first electrode 120 and the second electrode 145 are Indium Tin Oxide (ITO) made of transparent conductive material. The first alignment layer 125 and the second alignment layer 140 are made of polyimide (PI) and are aligned perpendicularly to the liquid crystal 130 in a stationary state. In operation, a light source (not shown) emits light from a first polarizer 105 attached to the underlying substrate 110. The first polarizer 105 is generally polarized in a first direction, and the second polarizer 155 attached to the second substrate 150 is vertically polarized with the first polarizer 104. Therefore, the light from the light source does not penetrate the first polarizer 105 and the second polarizer 155 at the same time unless the polarization of the light is rotated by 90 degrees between the first polarizer 105 and the second polarizer 155. For the sake of clarity, many liquid crystals are not shown. In an actual display, the liquid crystal is rod like molecules having a diameter of about 5 angstroms (Angstrom, Å) and a length of about 20-25 angstroms. Therefore, there are more than 12 million liquid crystal molecules in one pixel, wherein the length, width and height of the pixels are 300 micrometers (micrometers), 120 micrometers, and 3 micrometers, respectively. Although not shown, many liquid crystal displays, especially active matrix liquid crystal displays, include a passivation layer on the bottom of the first electrode 120. The passivation layer serves as an insulating layer between the first electrode 120 and the device and conductor that may be formed on the substrate. The passivation layer is typically formed using tantalum nitride.
在圖1中,液晶130係為垂直配向。在垂直配向中,液晶130並不會將從光源的偏振極光轉向。因此,從光源來的光線並不會穿過液晶顯示器100,且對所有顏色及所有間隙晶胞(cell gap)而言,提供一個完全地光學暗態(optical black state)及非常高的的對比(contrast ratio)。因此,多區域垂直配向液晶顯示器相對傳統的低對比之扭轉式向列型液晶顯示器而言,係在對比上提供一個顯著的改善。然而,如圖1(b)所示,當在第一電極120與第二電極145之間加入一個電場(electric field)時,液晶130即重新定向到一傾斜位置(tilted position)。在傾斜位置的液晶係將從第一偏光片105而來的偏振光線之偏振轉向90度,以致光線可以穿過第二偏光片155。而傾斜的大小,即控制光線穿過液晶顯示器的多寡(如畫素的亮度),係與電場強度成正比。一般而言,單一個薄膜電晶體,係用在每一個畫素上。然而對彩色顯示器而言,各別的薄膜電晶體係用在每一色分量(color component,典型地為、綠及藍)。 In Fig. 1, the liquid crystal 130 is vertically aligned. In the vertical alignment, the liquid crystal 130 does not divert the polarized aurora from the light source. Therefore, the light from the light source does not pass through the liquid crystal display 100, and provides a completely optical black state and a very high contrast for all colors and all cell gaps. (contrast ratio). Therefore, the multi-zone vertical alignment liquid crystal display provides a significant improvement in comparison with the conventional low contrast twisted nematic liquid crystal display. However, as shown in FIG. 1(b), when an electric field is applied between the first electrode 120 and the second electrode 145, the liquid crystal 130 is redirected to a tilted position. The liquid crystal in the tilted position turns the polarization of the polarized light from the first polarizer 105 by 90 degrees so that the light can pass through the second polarizer 155. The size of the tilt, that is, the amount of light that passes through the liquid crystal display (such as the brightness of the pixels), is proportional to the electric field strength. In general, a single thin film transistor is used on each pixel. For color displays, however, individual thin film electro-crystal systems are used in each color component (typically, green and blue).
然而,對不同角度的觀看者而言,光線通過液晶顯示器120並不是相同的。如圖1(c)所示,在中央左邊的觀看者172會看到亮畫素(bright pixel), 因為液晶顯示器130寬闊(光線轉向)的一側係面對觀看者172。位在中央的觀看者174會看到灰畫素(gray pixel),因為液晶顯示器130寬闊的一側係僅部分地面對觀看者174。而位在中央右側的觀看者176會看到暗畫素(dark pixel),因為液晶顯示器130寬闊的一側幾乎沒有面對觀看者176。 However, for viewers of different angles, the light passing through the liquid crystal display 120 is not the same. As shown in Figure 1(c), the viewer 172 on the left side of the center will see bright pixels. Because the side of the liquid crystal display 130 that is wide (light turning) faces the viewer 172. The centrally located viewer 174 will see gray pixels because the wide side of the liquid crystal display 130 is only partially facing the viewer 174. The viewer 176 located on the right side of the center will see the dark pixel because the wide side of the liquid crystal display 130 barely faces the viewer 176.
多區域垂直配向液晶顯示器(MVA LCDs)係被發展來改善單區域垂直配向液晶顯示器(single-domain vertical alignment LCD)的視角問題。請參考圖2,係表示一多區域垂直配向液晶顯示器(MVA LCDs)200的畫素。多區域垂直配向液晶顯示器200係包括一第一偏光片205、一第一基板210、一第一電極220、一第一配向層225、若干液晶235、237、若干突起物260、一第二配向層240、一第二電極245、一第二基板250以及一第二偏光片255。液晶235係形成畫素的第一區域(first domain),而液晶237則形成畫素的第二區域(second domain)。當在第一電極220與第二電極245之間施加一電場時,突起物260會導致液晶235相對液晶237而傾斜一不同的方向。因此,中央偏左的觀看者會看到左邊區域(液晶235)呈現黑色(black)而右邊區域(液晶237)呈現白色(white)。在中央的觀看者則會同時看到兩個區域而呈現灰色。中央偏右的觀看者則會看到左邊區域呈現白色而右邊區域呈現黑色。然而,因為個別單獨的畫素很小,因此三個觀看者都認為畫素是灰色的。如上所述,液晶的傾斜的大小,係由在電極220與245之間的電場大小所控制。觀看者所感知的灰階係與液晶傾斜大小相關聯。多區域垂直配向液晶顯示器也可以擴大到使用四個區域,以便在一畫素中的液晶方向被區分為四個主區域,以提供同時在垂直與水平方向上之寬大且對稱的視角。 Multi-region vertical alignment liquid crystal displays (MVA LCDs) have been developed to improve the viewing angle of single-domain vertical alignment LCDs. Referring to FIG. 2, a pixel of a multi-region vertical alignment liquid crystal display (MVA LCDs) 200 is shown. The multi-zone vertical alignment liquid crystal display 200 includes a first polarizer 205, a first substrate 210, a first electrode 220, a first alignment layer 225, a plurality of liquid crystals 235, 237, a plurality of protrusions 260, and a second alignment. The layer 240, a second electrode 245, a second substrate 250, and a second polarizer 255. The liquid crystal 235 forms a first domain of pixels, and the liquid crystal 237 forms a second domain of pixels. When an electric field is applied between the first electrode 220 and the second electrode 245, the protrusion 260 causes the liquid crystal 235 to be tilted in a different direction with respect to the liquid crystal 237. Therefore, the center-left viewer will see that the left area (liquid crystal 235) appears black and the right area (liquid crystal 237) appears white. Viewers in the center will see two areas at the same time and appear gray. The center-right viewer will see the left area appear white and the right area appear black. However, because the individual pixels are small, all three viewers consider the pixels to be gray. As described above, the magnitude of the tilt of the liquid crystal is controlled by the magnitude of the electric field between the electrodes 220 and 245. The gray level perceived by the viewer is related to the tilt of the liquid crystal. The multi-zone vertical alignment liquid crystal display can also be expanded to use four regions so that the liquid crystal direction in one pixel is divided into four main regions to provide a wide and symmetrical viewing angle in both the vertical and horizontal directions.
因此,提供寬大且對稱之視角的多區域垂直配向液晶顯示器,成本卻非常高,因為將突起物增加到上、下基板的困難,以及將突起物正確地配向到上、下基板的困難。尤其是在下基板的一突起物必須設置在上基板的二突起物中央;任何在上、下基板之間的配向,都將會降低生產良率。其他在基板上使用物理特性的技術,如已用來取代或結合突起物使用之氧化銦錫間隙(ITO slits),係在製造上非常昂貴。再者,突起物與氧化銦錫間隙無法傳輸光線,也因此降低多區域垂直配向液晶顯示器的亮度及對比度(contrast ratio)。 Therefore, a multi-region vertical alignment liquid crystal display that provides a wide and symmetrical viewing angle is very expensive, because of the difficulty in adding protrusions to the upper and lower substrates, and the difficulty in properly aligning the protrusions to the upper and lower substrates. In particular, a protrusion on the lower substrate must be placed in the center of the two protrusions of the upper substrate; any alignment between the upper and lower substrates will reduce the production yield. Other techniques that use physical properties on the substrate, such as ITO slits that have been used to replace or bond protrusions, are very expensive to manufacture. Furthermore, the protrusions and the indium tin oxide gap cannot transmit light, and thus reduce the contrast and contrast ratio of the multi-region vertical alignment liquid crystal display.
然而,已開發出無需在基板上使用物理特徵(例如,突起物或氧化銦錫間隙)之多區域垂直配向液晶顯示器。具體而言,該等多區域垂直配向液晶顯示器係使用離散場來形成多區域。在無需物理特徵之情況下,將消除對頂部基板及底部基板之物理特徵進行配向之困難。因此,使用離散場之多區域垂直配向液晶顯示器較在基板上使用物理特徵之多區域垂直配向液晶顯示器具有更高之良率且製造成本更低。 However, multi-region vertical alignment liquid crystal displays that do not require the use of physical features (e.g., protrusions or indium tin oxide gaps) on the substrate have been developed. In particular, the multi-region vertical alignment liquid crystal displays use discrete fields to form multiple regions. The difficulty of aligning the physical features of the top and bottom substrates will be eliminated without the need for physical features. Therefore, a multi-region vertical alignment liquid crystal display using discrete fields has higher yield and lower manufacturing cost than a multi-region vertical alignment liquid crystal display using physical features on a substrate.
請參考圖3(a)及圖3(b),係表示依據本發明基本概念,無須在基板上使用物理特性,以產生一多區域垂直配向液晶顯示器(MVA LCD)300的示意圖。而圖3(a)及圖3(b)係顯示出在一第一基板305與一第二基板355之間,具有畫素310、320及330。一第一偏光片302係黏貼到第一基板305,且一第二偏光片357係黏貼到第二基板355。畫素310包含有一第一電極311、若干液晶312、313以及一第二電極315。畫素320包含有一第一電極321、若干液晶322、323以及一第二電極325。相似地,畫素330包含有一第一電極331、若干液晶332、333以及一第二電極335。所有電極一般地架構係使用如氧化銦錫(ITO)之透明導電材質。再者,一第一配向層307係覆蓋在第一基板305上的電極之上。相似地,一第二配向層352係覆蓋在第二基板355上的電極之上。二液晶配向層307及352係提供一垂直液晶配向。為了下列的更加詳細敘述,電極315、325及335係維持在一共同電壓(common voltage)V_Com。因此,為了容易製造,電極315、325及335係為一單一結構(如圖3(a)及圖3(b)所示)。多區域垂直配向液晶顯示器300係使用交替偏振以操作畫素310、320及330。舉例來說,若畫素310與330之偏振為正(positive)的話,則畫素320的偏振為負(negative)。相反地,若畫素310與330之偏振為負(negative)的話,則畫素320的偏振為正(positive)。一般來說,每一畫素的偏振係在頁框(frames)間切換,但交替偏振的圖案(pattern)係維持在每一頁框中。在圖3(a)中,畫素310、320及330係在「關閉(OFF)」狀態,意即關閉在第一與第二電極之間的電場(electric field)。在關閉狀態下,某些殘餘電場可能存在第一與第二基板之間。然而,一般而言,殘餘電場太小而無法使液晶傾斜。 Referring to Figures 3(a) and 3(b), there is shown a schematic diagram of a multi-region vertical alignment liquid crystal display (MVA LCD) 300 in accordance with the basic concepts of the present invention without the use of physical characteristics on the substrate. 3(a) and 3(b) show pixels 310, 320 and 330 between a first substrate 305 and a second substrate 355. A first polarizer 302 is adhered to the first substrate 305, and a second polarizer 357 is adhered to the second substrate 355. The pixel 310 includes a first electrode 311, a plurality of liquid crystals 312, 313, and a second electrode 315. The pixel 320 includes a first electrode 321, a plurality of liquid crystals 322, 323, and a second electrode 325. Similarly, the pixel 330 includes a first electrode 331, a plurality of liquid crystals 332, 333, and a second electrode 335. All electrodes are generally constructed using a transparent conductive material such as indium tin oxide (ITO). Furthermore, a first alignment layer 307 is overlying the electrodes on the first substrate 305. Similarly, a second alignment layer 352 overlies the electrodes on the second substrate 355. The two liquid crystal alignment layers 307 and 352 provide a vertical liquid crystal alignment. For the more detailed description below, electrodes 315, 325, and 335 are maintained at a common voltage V_Com. Therefore, for ease of fabrication, the electrodes 315, 325, and 335 are of a single structure (as shown in Figures 3(a) and 3(b)). The multi-zone vertical alignment liquid crystal display 300 uses alternating polarization to operate the pixels 310, 320, and 330. For example, if the polarization of pixels 310 and 330 is positive, then the polarization of pixel 320 is negative. Conversely, if the polarization of pixels 310 and 330 is negative, the polarization of pixel 320 is positive. In general, the polarization of each pixel is switched between frames, but alternately patterned patterns are maintained in each page frame. In Fig. 3(a), pixels 310, 320, and 330 are in an "OFF" state, that is, an electric field between the first and second electrodes is turned off. In the off state, some residual electric field may exist between the first and second substrates. However, in general, the residual electric field is too small to tilt the liquid crystal.
在圖3(b)中,畫素310、320及330係處在「開啟(ON)」狀態。而圖3(b)係使用「+」及「-」代表電極的電壓極性(voltage polarity)。因此,電極311 及331具有正電壓極性,而電極321具有負電壓極性。基板355與電極315、325及335係保持在共同電壓V_Com。電壓極性係相對共同電壓V_Com來定義,其中一正極性係其電壓高於共同電壓V_Com,一負極性係其電壓低於共同電壓V_Com。在電極321與325之間的電場327(以電力線表示)係造成液晶322與323傾斜。一般而言,沒有突起物或其他物理特性,液晶的傾斜方向不會被在一垂直的液晶配向層307與352之液晶所固定。然而,在畫素邊緣的離散電場會影響到液晶的傾斜方向。舉例來說,在電極321與325之間的電場327,係垂直圍繞畫素320中心,但傾斜到畫素左半部的左邊,以及傾斜到畫素右半部的右邊。因此,在電極321與325之間的離散電場係造成液晶323傾斜到右邊而形成一第一區域,且造成液晶322傾斜到左邊而形成一第二區域。因此,畫素320係為具有對稱寬視角的多區域畫素。 In FIG. 3(b), the pixels 310, 320, and 330 are in an "ON" state. In Fig. 3(b), "+" and "-" are used to represent the voltage polarity of the electrode. Therefore, the electrode 311 And 331 has a positive voltage polarity, and electrode 321 has a negative voltage polarity. The substrate 355 and the electrodes 315, 325, and 335 are maintained at a common voltage V_Com. The voltage polarity is defined with respect to the common voltage V_Com, wherein a positive polarity is higher than the common voltage V_Com, and a negative polarity is lower than the common voltage V_Com. The electric field 327 (indicated by the power line) between the electrodes 321 and 325 causes the liquid crystals 322 and 323 to tilt. In general, without protrusions or other physical properties, the tilt direction of the liquid crystal is not fixed by the liquid crystals in a vertical liquid crystal alignment layer 307 and 352. However, the discrete electric field at the edge of the pixel affects the tilt direction of the liquid crystal. For example, the electric field 327 between the electrodes 321 and 325 is vertically centered around the pixel 320, but is tilted to the left of the left half of the pixel and to the right of the right half of the pixel. Therefore, the discrete electric field between the electrodes 321 and 325 causes the liquid crystal 323 to tilt to the right to form a first region, and causes the liquid crystal 322 to tilt to the left to form a second region. Therefore, the pixel 320 is a multi-region pixel having a symmetric wide viewing angle.
相似地,在電極311與315之間的電場(圖未示)係具有離散電場,此離散電場係造成液晶313重新定位,且傾斜到畫素312右側的右邊,也造成液晶312傾斜到畫素310左測的左邊。相似地,在電極331與335之間的電場(圖未示)係具有離散電場,此離散電場係造成液晶333重新定位,且傾斜到畫素330右側的右邊,也造成液晶332傾斜到畫素330左測的左邊。 Similarly, the electric field (not shown) between electrodes 311 and 315 has a discrete electric field that causes liquid crystal 313 to reposition and tilt to the right of the right side of pixel 312, also causing liquid crystal 312 to tilt to the pixel. 310 left to the left of the test. Similarly, the electric field (not shown) between electrodes 331 and 335 has a discrete electric field that causes liquid crystal 333 to reposition and tilt to the right of the right side of pixel 330, also causing liquid crystal 332 to tilt to the pixel. 330 left to the left of the test.
鄰近畫素的交替極性係放大每一畫素離散場效(fringe field effect)。因此,藉由在每列的畫素(或每欄的畫素)之間重覆交替極性圖案,即可無須物理特性而達到一多區域垂直配向液晶顯示器。再者,可以使用交替極性棋盤圖案,以在每一畫素產生四個區域。 The alternating polarity of adjacent pixels amplifies the fringe field effect of each pixel. Therefore, by repeating the alternating polarity pattern between the pixels of each column (or the pixels of each column), a multi-region vertical alignment liquid crystal display can be achieved without physical properties. Furthermore, alternating polarity checkerboard patterns can be used to create four regions per pixel.
然而,一般而言,離散場效係相對地小且微弱。所以,當畫素變較大時,在畫素邊緣的離散電場係無法傳遞到在一畫素中的所有液晶。因此,在大畫素中,對於遠離畫素邊緣之液晶的傾斜方向係隨意變化,且不會產生一多區域畫素。一般而言,當畫素變得大於40-60微米(micrometer,μm)時,畫素的離散場效係不會影響控制液晶傾斜。故,對大畫素液晶顯示器而言,使用一新穎的畫素區分方法來達到多區域畫素。尤其是對彩色液晶顯示器而言,畫素係區分成色分量。每一色分量係由如薄膜電晶體(thin-film transistor,TFT)的一個別的切換裝置所控制。一般而言,色分量係為紅色、綠色及藍色。依據本發明,一畫素的色分量係進一步區分成色 點(color dots)。 However, in general, the discrete field effect system is relatively small and weak. Therefore, when the pixels become larger, the discrete electric field at the edge of the pixel cannot be transmitted to all the liquid crystals in one pixel. Therefore, in the large pixel, the tilt direction of the liquid crystal far from the edge of the pixel is arbitrarily changed, and a multi-region pixel is not generated. In general, when the pixel becomes larger than 40-60 micrometers (micrometer, μm), the discrete field effect of the pixel does not affect the control liquid crystal tilt. Therefore, for large pixel liquid crystal displays, a novel pixel distinction method is used to achieve multi-region pixels. Especially for color liquid crystal displays, the pixels are distinguished by the color component. Each color component is controlled by a separate switching device such as a thin-film transistor (TFT). In general, the color components are red, green, and blue. According to the present invention, the color component of a pixel is further differentiated into color Color dots.
每一畫素的極性係在影像的之每一連續頁框之間做切換,以避免圖像品質的降低,而圖像品質的降低係因為在每一頁框中液晶在相同方向扭曲。然而,若是所有的切換元件係為相同極性者,則色點極性圖案切換係可能造成其他如閃爍(flicker)之圖像品質問題。為了降低閃爍,切換元件(如電晶體)係配置在一切換元件驅動模式中,此機制包括正、負極性。再者,為了降低串影(cross talk),切換元件的正、負極性係被配置在一固定圖案中,此固定圖案係提供一更穩定的配電。不同的切換元件驅動模式係使用在本發明的實施例中。有三個主要的切換元件驅動模式,係為切換元件點反轉驅動模式(switching element point inversion driving scheme)、切換元件列反轉驅動模式(switching element row inversion driving scheme)以及切換元件行反轉驅動模式(switching element column inversion driving scheme)。在切換元件點反轉驅動模式中,切換元件係形成一交替極性的棋盤圖案。在切換元件列反轉驅動模式中,在每一列的切換元件具有相同極性;然而,在一列上的一切換元件相對於鄰近列之切換元件的極性而具有相反極性。在切換元件行反轉驅動模式中,在每一行的切換元件具有相同極性;然而,在一行上的一切換元件相對於鄰近行之切換元件的極性而具有相反極性。當切換元件點反轉驅動模式提供最穩定的配電時,切換元件點反轉驅動模式的複雜性與額外的成本,相比較切換元件列反轉驅動模式與切換元件行反轉驅動模式而言,是不划算的。因此,當切換元件點反轉驅動模式通常保持在高性能應用時,對於大部分低成本與低電壓應用之液晶顯示器的製造,係使用切換元件列反轉驅動模式。 The polarity of each pixel is switched between each successive page of the image to avoid degradation of image quality, and the quality of the image is reduced because the liquid crystal is distorted in the same direction in each page frame. However, if all of the switching elements are of the same polarity, the color point polarity pattern switching may cause other image quality problems such as flicker. In order to reduce flicker, switching elements (such as transistors) are arranged in a switching element drive mode, which includes positive and negative polarity. Furthermore, in order to reduce cross talk, the positive and negative polarities of the switching element are arranged in a fixed pattern which provides a more stable power distribution. Different switching element drive modes are used in embodiments of the present invention. There are three main switching element driving modes, which are switching element point inversion driving scheme, switching element row inversion driving scheme, and switching element row inversion driving mode. (switching element column inversion driving scheme). In the switching element dot inversion driving mode, the switching elements form a checkerboard pattern of alternating polarity. In the switching element column inversion driving mode, the switching elements in each column have the same polarity; however, one switching element in one column has opposite polarities with respect to the polarity of the switching elements of adjacent columns. In the switching element row inversion driving mode, the switching elements in each row have the same polarity; however, one switching element on one row has opposite polarities with respect to the polarity of the switching elements of adjacent rows. When the switching element dot inversion driving mode provides the most stable power distribution, the complexity of the switching element dot inversion driving mode and the additional cost are compared with the switching element column inversion driving mode and the switching element row inversion driving mode. It is not cost-effective. Therefore, when the switching element dot inversion driving mode is generally maintained in high performance applications, the switching element column inversion driving mode is used for the manufacture of liquid crystal displays for most low cost and low voltage applications.
(新)畫素可包含各種關鍵組件(key component),該等關鍵組件被設置成用以達成高品質、低成本顯示單元。舉例而言,畫素可包含色分量(color component)、色點(color dot)、離散場放大區域(fringe field amplifying region,FFAR)、切換元件(switching element)、裝置組件區域(device component area)、及關聯點(associated dot)。使用該等各種組件之顯示器闡述於以下專利文獻中:名稱為「使用離散場之大畫素多區域垂直配向液晶顯示器(Large Pixel Multi-Domain Vertical Alignment Liquid Crystal Display Using Fringe Fields)」之美國專利第7,630,033號、名稱為「用於多區域垂 直配向液晶顯示器之使用關聯點極性之畫素(Pixels Using Associated Dot Polarity for Multi-Domain Vertical Alignment Liquid Crystal Displays)」之美國專利申請案第11/751,454號、名稱為「用於多區域垂直配向液晶顯示器之具有極性延伸區域之畫素(Pixels Having Polarity Extension Regions For Multi-Domain Vertical Alignment Liquid Crystal Displays)」之美國專利申請案第12/018,675號、以及名稱為「用於多區域垂直配向液晶顯示器且具有跨位面離散場放大區域之畫素(Pixels having Fringe Field Amplifying Regions for Multi-Domain Vertical Alignment Liquid Crystal Displays)」之美國專利申請案第12/573,085號,該等專利文獻以引用方式併入本文中。 The (new) pixels can include various key components that are configured to achieve a high quality, low cost display unit. For example, a pixel may include a color component, a color dot, a fringe field amplifying region (FFAR), a switching element, and a device component area. And associated dots. A display using these various components is described in the following patent document: US Patent No. "Large Pixel Multi-Domain Vertical Alignment Liquid Crystal Display Using Fringe Fields" 7,630,033, the name is "for multi-regional vertical U.S. Patent Application Serial No. 11/751,454, entitled "Pixels Using Associated Dot Polarity for Multi-Domain Vertical Alignment Liquid Crystal Displays", entitled "Multi-region Vertical Alignment Liquid Crystals" U.S. Patent Application Serial No. 12/018,675, entitled "Pixels Having Polarity Extension Regions For Multi-Domain Vertical Alignment Liquid Crystal Displays", and "For Multi-Zone Vertical Alignment Liquid Crystal Displays" U.S. Patent Application Serial No. 12/573,085, the entire disclosure of which is incorporated herein by reference. in.
此裝置元件區域係包含佔用切換元件及/或儲存電容的區域,而且此區域係被用來製造切換元件及/或儲存電容。為了清楚說明,一不同的裝置元件區域係由每一切換元件所界定。 This device component area contains areas occupying switching elements and/or storage capacitors, and this area is used to fabricate switching elements and/or storage capacitors. For clarity of illustration, a different device component area is defined by each switching element.
關聯點與離散場放大區域係為電性偏振區域(electrically polarized area),而並未是色分量的一部分。在本發明許多的實施例中,關聯點係覆蓋裝置元件區域。對這些實施例而言,關聯點係由將一絕緣層沉積覆蓋在切換元件及/或儲存電容上所製成。接著,藉由沉積一電性導電層以形成所述的關聯點。此關聯點係電性地連接到特定的切換元件及/或其他偏振元件(例如色點)。儲存電容係電性地連接到特定的切換元件及色點電極(color dot electrodes),以在液晶盒打開(switching-on)或是關掉(switching off)的過程期間補償並抵銷在液晶盒上的電容值變化。因此,儲存電容係用來在液晶盒打開或是關掉的過程期間減低串影效應(cross talk effect)。一圖案化光罩(patterning mask)係使用在當關聯點需要形成圖案化電極(patterned electrode)之時。一般而言,係附加一黑色矩陣層(black matrix layer)以形成對色點、切換元件、DCA及關聯點的一光屏蔽(light shield)。一般而言,黑色矩陣層係為黑色的,然而某些顯示器使用不同顏色來達成一所需之顏色圖案或陰影(shading)。附加一顏色層以給予色點所需之顏色。一般而言,顏色層係藉由在對應之ITO玻璃基板上沈積一濾色層(color filter layer)而獲得。具體而言,在第二基板355與第二電極315、325、及335之間沈積一圖案化濾色層,且其圖案對應於色點及關聯點之顏色。然而,某些顯示器亦可在第一基板305上將一圖案化濾色層放置於下列之頂部上或底下:切換元件、色 點之電極層、關聯點、或DCA。 The associated point and the discrete field amplification region are electrically polarized regions and are not part of the color component. In many embodiments of the invention, the associated points cover the device component area. For these embodiments, the associated points are made by depositing an insulating layer over the switching elements and/or storage capacitors. Next, the associated points are formed by depositing an electrically conductive layer. This associated point is electrically connected to a particular switching element and/or other polarizing element (eg, a color point). The storage capacitor is electrically connected to a specific switching element and color dot electrodes to compensate and offset the liquid crystal cell during the switching-on or switching off process of the liquid crystal cell. The capacitance value on the change. Therefore, the storage capacitor is used to reduce the cross talk effect during the process of turning the cell on or off. A patterned mask is used when the associated point needs to form a patterned electrode. In general, a black matrix layer is attached to form a light shield for color points, switching elements, DCA, and associated points. In general, black matrix layers are black, however some displays use different colors to achieve a desired color pattern or shading. A color layer is attached to give the desired color to the color point. In general, the color layer is obtained by depositing a color filter layer on the corresponding ITO glass substrate. Specifically, a patterned color filter layer is deposited between the second substrate 355 and the second electrodes 315, 325, and 335, and the pattern corresponds to the color of the color point and the associated point. However, some displays may also place a patterned color filter layer on top or bottom of the following substrate 305: switching components, colors Electrode layer, associated point, or DCA.
在本發明其他實施例中,關聯點係為與切換元間相互獨立的一區域。再者,本發明的某些實施例具有額外的關聯點,此等關聯點並不直接地與切換元件相關。一般而言,關聯點係包括如氧化銦錫(ITO)或其他導電層的一主動電極層(active electrode layer),且連接到一附近的色點或者是以其他手段供電。對不透明的關聯點而言,一黑色矩陣層可以被附加在導電層的底部上,以形成不透明區域(opaque area)。在本發明某些實施例中,黑色矩陣可以被製造在氧化銦錫(ITO)玻璃基板側上,以簡化製程(fabrication process)。額外的關聯點係改善顯示區域有效的使用,藉以改善開口率(aperture ratio)且在色點內形成多個液晶區域(liquid crystal domains)。本發明的某些實施例使用關聯點以改善色彩表現。舉例來說,關聯點的小心佈局(careful placement)可以允許附近色點的顏色從有用的色彩圖案進行修飾。 In other embodiments of the invention, the associated point is an area that is independent of the switching element. Moreover, certain embodiments of the present invention have additional points of association that are not directly related to the switching elements. In general, the associated points include an active electrode layer such as indium tin oxide (ITO) or other conductive layer and are connected to a nearby color point or powered by other means. For opaque associated points, a black matrix layer can be attached to the bottom of the conductive layer to form an opaque area. In some embodiments of the invention, a black matrix can be fabricated on the indium tin oxide (ITO) glass substrate side to simplify the fabrication process. Additional points of association improve the effective use of the display area, thereby improving the aperture ratio and forming a plurality of liquid crystal domains within the color point. Certain embodiments of the present invention use association points to improve color performance. For example, a careful placement of associated points may allow the colors of nearby color points to be modified from useful color patterns.
離散場放大區域(FFARs)係比關聯點更加多功能。特別是,離散場放大區域係可以具有非矩形形狀,雖然一般來說璃散場放大區域的整體形狀可以被劃分成一矩形形狀組。再者,離散場放大區域係沿著多於一色點的一側而延伸。而且,在本發明某些實施例中,離散場放大區域可以被用來取代關聯點。尤其是,在這些實施例中,離散場放大區域不僅覆蓋裝置元件區域,而且沿著多於鄰近裝置元件區域之色點一側而延伸。 Discrete field amplification regions (FFARs) are more versatile than associated points. In particular, the discrete field magnifying region may have a non-rectangular shape, although in general the overall shape of the magenta field magnified region may be divided into a rectangular shape group. Furthermore, the discrete field amplification region extends along one side of more than one color point. Moreover, in some embodiments of the invention, discrete field amplification regions may be used in place of associated points. In particular, in these embodiments, the discrete field magnified region not only covers the device component region, but also extends along more than one color dot side of the adjacent device component region.
一般而言,色點、裝置組件區域、及關聯點係排列成一格狀圖案,且以一水平點間距HDS及一垂直點間距VDS而彼此間隔開。當使用離散場放大區域來取代關聯點時,離散場放大區域之部分亦適配於格狀圖案中。在某些顯示器中,可使用多個垂直點間距多個水平點間距。每一色點、關聯點、及裝置組件區域在一第一維度(例如,垂直維度)中具有二相鄰組件(例如,色點、關聯點、或裝置組件區域),且在一第二維度(例如,為水平的)中具有二相鄰組件。此外,二相鄰組件可係為配向的或偏移的。每一色點具有一色點高度CDH及一色點寬度CDW。相似地,每一關聯點具有一關聯點高度ADH及一關聯點寬度ADW。此外,每一裝置組件區域具有一裝置組件區域高度DCAH以及一裝置組件區域寬度DCAW。在某些顯示器中,色點、關聯點、及裝置組件區 域具有相同尺寸。然而,在許多顯示器中,色點、關聯點、及裝置組件區域可具有不同尺寸或形狀。舉例而言,在許多顯示器中,關聯點之高度小於色點之高度。 In general, the color point, the device component area, and the associated dots are arranged in a lattice pattern and are spaced apart from each other by a horizontal dot pitch HDS and a vertical dot pitch VDS. When a discrete field amplification region is used in place of the associated point, portions of the discrete field amplification region are also adapted to the lattice pattern. In some displays, multiple horizontal dot pitches can be used with multiple vertical dot pitches. Each color point, associated point, and device component area has two adjacent components (eg, color point, associated point, or device component area) in a first dimension (eg, a vertical dimension), and in a second dimension ( For example, there are two adjacent components in the horizontal). In addition, two adjacent components may be aligned or offset. Each color point has a color point height CDH and a color point width CDW. Similarly, each associated point has an associated point height ADH and an associated point width ADW. In addition, each device component area has a device component area height DCAH and a device component area width DCAW. In some displays, color points, associated points, and device component areas Domains have the same size. However, in many displays, the color points, associated points, and device component areas can have different sizes or shapes. For example, in many displays, the height of the associated point is less than the height of the color point.
隨著具有更高效能之可攜式裝置之流行,越來越需要在液晶顯示器中達成更高之畫素密度,乃因可攜式裝置通常較用於電視機或電腦顯示器之液晶顯示器螢幕更靠近一使用者之眼睛。然而,高畫素密度需要更小之畫素,而此可導致亮度降低,乃因液晶顯示器中之許多裝置組件之尺寸無法與畫素尺寸減小量同等地減小。此外,畫素或色點中各種裝置組件間之間距會在顯示器之表面積中佔據一更大百分比。此外,許多行動裝置包含供使用者輸入之觸控螢幕。觸控螢幕裝置可使一液晶顯示器面板出現觸碰雲紋效應(touch mura effect),該觸碰雲紋效應係起因於液晶之物理擾動。觸碰雲紋效應係指不規則圖案或區域造成不均一之螢幕均勻性。液晶之物理擾動可係由搖動(shaking)、震動(vibration)、及在顯示器上之按壓所造成。特別是,垂直配向液晶顯示器非常容易因在顯示器上之按壓而造成觸碰雲紋效應。尤其是,在一垂直配向液晶顯示器上之按壓可使液晶厚度局部地變平,且在顯示器上形成一干擾效應。因此,需要一種用於使各種組件間之間距最小化之方法或系統以提高光學透射率(optical transmission),且需要一種用於降低一垂直配向液晶顯示器中之觸碰雲紋效應之方法或系統。 With the popularity of portable devices with higher performance, there is an increasing need to achieve higher pixel density in liquid crystal displays, because portable devices are generally more screens than liquid crystal displays for televisions or computer monitors. Close to the eyes of a user. However, the high pixel density requires a smaller pixel, which can result in a decrease in brightness because the size of many device components in a liquid crystal display cannot be reduced as much as the pixel size reduction. In addition, the distance between various device components in a pixel or color point will occupy a larger percentage of the surface area of the display. In addition, many mobile devices include touch screens for user input. The touch screen device can cause a liquid crystal display panel to touch the touch mura effect, which is caused by the physical disturbance of the liquid crystal. Touching the moiré effect means that the irregular pattern or area causes uneven screen uniformity. The physical disturbance of the liquid crystal can be caused by shaking, vibration, and pressing on the display. In particular, vertical alignment liquid crystal displays are very susceptible to touch moiré effects due to pressing on the display. In particular, pressing on a vertical alignment liquid crystal display can locally flatten the thickness of the liquid crystal and create an interference effect on the display. Accordingly, there is a need for a method or system for minimizing the spacing between various components to increase optical transmission, and a method or system for reducing the touch moiré effect in a vertical alignment liquid crystal display. .
因此,本發明提供一種垂直配向液晶顯示器,該垂直配向液晶顯示器具有更高之畫素密度及降低之觸碰雲紋效應。具體而言,本發明之各實施例係使用具有色點之新穎畫素設計,該等色點具有用於放大離散場之埋置極性區域(embedded polarity regions,EPR),離散場可增強多區域垂直配向操作,且亦更快地將液晶恢復至其正確位置。此外,本發明之各實施例包含埋置離 散場放大器,該等埋置離散場放大器無需廣闊之區域便能夠放大離散場,俾獲得一高的光學透射率。此外,本發明之各實施例之光學透射率增大,俾可獲得更高之亮度、同時可降低背光單元之電功率消耗。 Accordingly, the present invention provides a vertical alignment liquid crystal display having a higher pixel density and a reduced touch moiré effect. In particular, embodiments of the present invention use a novel pixel design with color points having buried polarity regions (EPR) for amplifying discrete fields, and discrete fields for enhancing multiple regions. Vertical alignment operation and faster recovery of the liquid crystal to its correct position. Moreover, various embodiments of the invention include embedding With a field-of-flight amplifier, these buried discrete-field amplifiers can amplify discrete fields without the need for a wide area, and achieve a high optical transmittance. In addition, the optical transmittance of each embodiment of the present invention is increased, and higher brightness can be obtained while reducing the electric power consumption of the backlight unit.
舉例而言,依據本發明之某些實施例,一畫素包含一第一色分量、一第一切換元件及一埋置離散場放大器。該第一色分量具有一第一色分量第一色點,該第一色分量第一色點係耦接至該第一切換元件。該第一埋置離散場放大器係位於該第一色分量第一色點後面。更具體而言,該第一色分量第一色點之一第一邊緣及一第二邊緣係位於該第一埋置離散場放大器前面。該畫素亦包含一第二色分量,該第二色分量具有一第二色分量第一色點,該第二色分量第一色點係耦接至一第二切換元件。該第二色分量第一色點具有一第一邊緣及一第二邊緣,該第一邊緣及該第二邊緣係位於該第一埋置離散場放大器前面。在本發明之其他實施例中,該第一埋置離散場放大器係用於該第一色分量,且一第二埋置離散場放大器係與該第二色分量一起使用。具體而言,該第二埋置離散場放大器係位於該第二色分量第一色點後面。該第二色分量第一色點之至少一第一邊緣及一第二邊緣係位於該第二埋置離散場放大器前面。 For example, in accordance with some embodiments of the present invention, a pixel includes a first color component, a first switching element, and a buried discrete field amplifier. The first color component has a first color component first color point, and the first color component first color point is coupled to the first switching element. The first embedded discrete field amplifier is located after the first color point of the first color component. More specifically, the first edge of the first color component and the first edge of the first color point are located in front of the first embedded discrete field amplifier. The pixel also includes a second color component having a second color component first color point, the second color component first color point being coupled to a second switching element. The first color point has a first edge and a second edge, and the first edge and the second edge are located in front of the first embedded discrete field amplifier. In other embodiments of the invention, the first buried discrete field amplifier is for the first color component and a second buried discrete field amplifier is used with the second color component. Specifically, the second buried discrete field amplifier is located behind the first color point of the second color component. At least one first edge and a second edge of the first color point of the second color component are located in front of the second buried discrete field amplifier.
在本發明之再一些實施例中,埋置離散場放大器包含垂直埋置部及水平埋置部。舉例而言,在本發明之某些實施例中,一畫素包含:一第一色分量,具有一第一色分量第一色點;一第一切換元件,耦接至該第一色分量第一色點;以及一第一埋置離散場放大器,具有一第一垂直埋置部及一第一水平埋置部。該第一垂直埋置部係位於該第一色分量第一色點之一第一邊緣後面,且該第一水平埋置部係位於該第一分量第一色點之一第二邊緣後面。該第一埋置離散場放大器可包含額外之水平埋置部及額外之垂直埋置部。舉例而言,在本發明之一實施例中,該第一埋置離散場放大器亦包含一第二垂直埋置部及一第二水平埋置部,該第二垂直埋置部係位於該第一色分量第一色點之一第三邊緣後面,該第 二水平埋置部係位於該第一色分量第一色點之一第四邊緣後面。 In still other embodiments of the invention, the buried discrete field amplifier includes a vertical buried portion and a horizontal buried portion. For example, in some embodiments of the present invention, a pixel includes: a first color component having a first color component and a first color component; and a first switching component coupled to the first color component a first color point; and a first buried discrete field amplifier having a first vertical buried portion and a first horizontal buried portion. The first vertical embedding portion is located behind a first edge of the first color point of the first color component, and the first horizontal embedding portion is located behind a second edge of the first color point of the first component. The first buried discrete field amplifier can include additional horizontal buried portions and additional vertical buried portions. For example, in an embodiment of the present invention, the first embedded discrete field amplifier further includes a second vertical buried portion and a second horizontal embedded portion, wherein the second vertical embedded portion is located at the first One color component, one of the first color points, behind the third edge, the first The two horizontal embedding portion is located behind a fourth edge of the first color point of the first color component.
藉由以下說明與圖式,將會更全面地理解本發明。 The invention will be more fully understood from the following description and drawings.
如上所述,習知垂直配向液晶顯示器具有有限之光學透射率,且極易因液晶受到物理擾動而造成觸碰雲紋效應。然而,依據本發明原理之垂直配向液晶顯示器係使用埋置離散場放大器,此等埋置離散場放大器能達成更高之開口率(aperture ratio)以增大光學透射率。此外,埋置離散場放大器會增強多區域垂直配向操作,並藉由增強橫向離散場來降低觸碰雲紋效應,進而有助於增強多區域垂直配向操作並亦有助於使液晶在一物理擾動之後恢復至其正確定向。因此,依據本發明之垂直配向液晶顯示器具有提高之光學透射率,並可迅速地消除由液晶之物理擾動所造成之觸碰雲紋效應。 As described above, the conventional vertical alignment liquid crystal display has a limited optical transmittance, and is highly susceptible to a moiré effect due to physical disturbance of the liquid crystal. However, vertical alignment liquid crystal displays in accordance with the principles of the present invention use buried discrete field amplifiers that achieve a higher aperture ratio to increase optical transmittance. In addition, the embedded discrete field amplifier enhances the multi-region vertical alignment operation and reduces the touch moiré effect by enhancing the lateral discrete field, which in turn helps to enhance multi-region vertical alignment operation and also helps to make the liquid crystal in a physical Return to its correct orientation after the disturbance. Therefore, the vertical alignment liquid crystal display according to the present invention has an improved optical transmittance and can quickly eliminate the touch moiré effect caused by the physical disturbance of the liquid crystal.
圖4(a)及圖4(b)顯示依據本發明一實施例之一畫素設計410(如下所述被標示為410+及410-)之不同點極性圖案。在實際操作中,一畫素將在每一影像頁框(image frame)之間在一第一點極性圖案與一第二點極性圖案之間切換。為清楚起見,將其中第一色分量之第一色點具有一正極性之點極性圖案稱為正的點極性圖案。相反,將其中第一色分量之第一色點具有一負極性之點極性圖案稱為負的點極性圖案。具體而言,在圖4(a)中,畫素設計410具有一正的點極性圖案(因此被標示為410+),且在圖4(b)中,畫素設計410具有一負的點極性圖案(因此被標示為410-)。此外,在各種畫素設計中,每一偏極化組件之極性係以「+」表示正極性,或以「-」表示負極性。 4(a) and 4(b) show different dot polarity patterns of a pixel design 410 (labeled 410+ and 410- as described below) in accordance with an embodiment of the present invention. In actual operation, a pixel will switch between a first dot polarity pattern and a second dot polarity pattern between each image frame. For the sake of clarity, a dot pattern in which the first color point of the first color component has a positive polarity is referred to as a positive dot polarity pattern. In contrast, a dot polarity pattern in which the first color point of the first color component has a negative polarity is referred to as a negative dot polarity pattern. Specifically, in FIG. 4(a), the pixel design 410 has a positive dot polarity pattern (hence labeled 410+), and in FIG. 4(b), the pixel design 410 has a negative point. Polar pattern (hence labeled as 410-). Further, in various pixel designs, the polarity of each polarization component is represented by "+" for positive polarity or "-" for negative polarity.
畫素設計410具有三個色分量CC_1、CC_2及CC_3。該三個色分量其中每一者包含一個色點。為清楚起見,該等色點被表示成CD_X_Y,其中X係為一色分量(在圖4(a)-4(b)中係從1至3),且Y係為一色點編號(在圖4(a)-4(b)中Y始終為1)。畫素設計410亦針對每一色分量包含一切換元件(被表示為SE_1、SE_2及SE_3),且針對每一色分量包含一裝置組件區域(被表示為DCA_1、DCA_2、及DCA_3)。切換元件SE_1、SE_2及SE_3係排列成一列。裝置組件區域DCA_1、DCA_2、及DCA_3係分別圍繞切換元件SE_1、SE_2及SE_3。 The pixel design 410 has three color components CC_1, CC_2, and CC_3. Each of the three color components contains a color point. For the sake of clarity, the color points are represented as CD_X_Y, where X is a one-color component (from 1 to 3 in Figures 4(a)-4(b)), and Y is a color point number (in the figure) Y is always 1) in 4(a)-4(b). The pixel design 410 also includes a switching element (denoted as SE_1, SE_2, and SE_3) for each color component, and a device component area (denoted DCA_1, DCA_2, and DCA_3) for each color component. The switching elements SE_1, SE_2 and SE_3 are arranged in a row. The device component areas DCA_1, DCA_2, and DCA_3 surround the switching elements SE_1, SE_2, and SE_3, respectively.
畫素設計410之第一色分量CC_1具有一個色點CD_1_1。色點CD_1_1係與裝置組件區域DCA_1水平地配向,並以一垂直點間距VDS1與裝置組件區域DCA_1垂直地間隔開。切換元件SE_1係耦接至色點CD_1_1之電極,以控制色點CD_1_1之極性。色點CD_1_1包含一埋置極性區域EPR_1_1_1。為清楚起見,埋置極性區域被表示成EPR_X_Y_Z,其中X係為一色分量,Y係為一色點編號,且Z係列舉位於一色點中之埋置極性區域。埋置極性區域可具有不同形狀。舉例而言,在畫素設計410中,埋置極性區域具有一矩形形狀。然而,其他實施例可具有正方形形狀、圓形形狀、多邊形形狀(例如,四邊形及六邊形)、或甚至其他不規則形狀。 The first color component CC_1 of the pixel design 410 has a color point CD_1_1. The color point CD_1_1 is horizontally aligned with the device component area DCA_1 and vertically spaced apart from the device component area DCA_1 by a vertical dot pitch VDS1. The switching element SE_1 is coupled to the electrode of the color point CD_1_1 to control the polarity of the color point CD_1_1. The color point CD_1_1 includes a buried polarity area EPR_1_1_1. For clarity, the buried polarity region is represented as EPR_X_Y_Z, where X is a one-color component, Y is a color point number, and the Z-series is in a buried polarity region in a color point. The buried polar regions can have different shapes. For example, in the pixel design 410, the buried polar region has a rectangular shape. However, other embodiments may have a square shape, a circular shape, a polygonal shape (eg, a quadrangle and a hexagon), or even other irregular shapes.
一般而言,極性係指極性方向,其通常被標記為正的或負的。更具體而言,極性亦包含一極性大小。埋置極性區域可具有與色點相同之極性方向但具有一不同之極性大小。此外,埋置極性區域可具有不同於色點之極性(即,「極性方向」)(例如,色點極性為正極性,而埋置極性區域具有負極性)。此外,埋置極性區域可具有中性極性(neutral polarity)。本發明之不同實施例係使用各種不同之新穎技術或新穎技術之組合以在色點中形成埋置極性區域。以下將詳細闡述該等技術。在圖4(a)及圖4(b)之實施例中,色點與位於色點中之埋置極性區域具有相反之極性。 In general, polarity refers to the direction of polarity, which is generally marked as positive or negative. More specifically, the polarity also includes a polarity. The buried polar region may have the same polarity direction as the color point but have a different polarity. Further, the buried polar region may have a polarity different from that of the color point (ie, "polarity direction") (for example, the color point polarity is positive polarity, and the buried polarity region has negative polarity). Further, the buried polar region may have a neutral polarity. Different embodiments of the invention use a variety of different novel techniques or combinations of novel techniques to form buried polar regions in color points. These techniques are described in detail below. In the embodiment of Figures 4(a) and 4(b), the color point has an opposite polarity to the buried polarity region located in the color point.
畫素設計410之第二色分量CC_2具有一個色點CD_2_1。色點CD_2_1係與裝置組件區域DCA_2水平地配向,並以垂直點間距VDS1與裝置組件區域DCA_2垂直地間隔開。色點CD_2_1係與色點CD_1_1垂直地配向,並以一水平點間距HDS1與色點CD_1_1水平地間隔開。切換元件SE_2係耦接至色點CD_2_1之電極,以控制色點CD_2_1之極性。色點CD_2_1包含一埋置極性區域EPR_2_1_1。 The second color component CC_2 of the pixel design 410 has a color point CD_2_1. The color point CD_2_1 is horizontally aligned with the device component area DCA_2 and vertically spaced apart from the device component area DCA_2 by a vertical dot pitch VDS1. The color point CD_2_1 is vertically aligned with the color point CD_1_1, and is horizontally spaced apart from the color point CD_1_1 by a horizontal dot pitch HDS1. The switching element SE_2 is coupled to the electrode of the color point CD_2_1 to control the polarity of the color point CD_2_1. The color point CD_2_1 includes a buried polarity area EPR_2_1_1.
畫素設計410之第三色分量CC_3具有一個色點CD_3_1。色點CD_3_1係與裝置組件區域DCA_3水平地配向,並以垂直點間距VDS1與裝置組件區域DCA_3垂直地間隔開。色點CD_3_1係與色點CD_2_1垂直地配向,並以一水平點間距HDS1與色點CD_2_1水平地間隔開。切換元件SE_3係耦接至色點CD_3_1之電極,以控制色點CD_3_1之極性。色點CD_3_1包含一埋置極性區域EPR_3_1_1。 The third color component CC_3 of the pixel design 410 has a color point CD_3_1. The color point CD_3_1 is horizontally aligned with the device component area DCA_3 and vertically spaced apart from the device component area DCA_3 by a vertical dot pitch VDS1. The color point CD_3_1 is vertically aligned with the color point CD_2_1, and is horizontally spaced apart from the color point CD_2_1 by a horizontal dot pitch HDS1. The switching element SE_3 is coupled to the electrode of the color point CD_3_1 to control the polarity of the color point CD_3_1. The color point CD_3_1 contains a buried polarity area EPR_3_1_1.
使用「+」及「-」符號來顯示色點、埋置極性區域、及切換元件之極 性。因此,在其中顯示畫素設計410+之正的點極性圖案之圖4(a)中,切換元件SE_1及SE_3、色點CD_1_1及CD_3_1、以及埋置極性區域EPR_2_1_1具有正極性。然而,切換元件SE_2、色點CD_2_1、及埋置極性區域EPR_1_1_1及EPR_3_1_1具有負極性。 Use the "+" and "-" symbols to display color points, buried polarity areas, and poles of switching components Sex. Therefore, in FIG. 4(a) in which the dot polarity pattern of the pixel design 410+ is displayed, the switching elements SE_1 and SE_3, the color points CD_1_1 and CD_3_1, and the buried polarity region EPR_2_1_1 have positive polarity. However, the switching element SE_2, the color point CD_2_1, and the buried polarity regions EPR_1_1_1 and EPR_3_1_1 have negative polarity.
圖5(a)及圖5(b)例示依據本發明一實施例之一色點500。色點500包含一正方形形狀之電極510,該正方形形狀之電極510具有一正方形形狀之埋置極性區域512。圖5(b)係為沿圖5(a)所示A1-A1切線截取之色點500之剖視圖。如圖5(b)所示,埋置極性區域512係由位於電極510下麵之一埋置電極516所形成。埋置電極516與電極510係由一鈍化層514間隔開。埋置電極516係帶電的,以產生穿過電極510之一電場。在本發明之大多數實施例中,電極510與埋置電極516具有相反之極性方向。舉例而言,當電極510具有正極性時,埋置電極516將具有一負極性。然而,在本發明之某些實施例中,埋置電極係被保持於一共同電壓V_com。電極510與埋置電極516所產生電場之交互作用會形成橫向力(lateral force),橫向力可增強多區域垂直配向操作,且亦在一物理擾動之後更快地將液晶重新定向至其正確位置。 5(a) and 5(b) illustrate a color point 500 in accordance with an embodiment of the present invention. The color point 500 includes a square shaped electrode 510 having a square shaped buried polarity region 512. Fig. 5(b) is a cross-sectional view of the color point 500 taken along the line A1-A1 shown in Fig. 5(a). As shown in FIG. 5(b), the buried polarity region 512 is formed by embedding the electrode 516 under one of the electrodes 510. The buried electrode 516 and the electrode 510 are separated by a passivation layer 514. The buried electrode 516 is electrically charged to create an electric field across the electrode 510. In most embodiments of the invention, electrode 510 and buried electrode 516 have opposite polar orientations. For example, when the electrode 510 has a positive polarity, the buried electrode 516 will have a negative polarity. However, in some embodiments of the invention, the buried electrode system is maintained at a common voltage V_com. The interaction of the electric field generated by the electrode 510 and the buried electrode 516 creates a lateral force that enhances the multi-zone vertical alignment operation and also redirects the liquid crystal to its correct position more quickly after a physical disturbance. .
圖5(c)例示可與埋置電極相組合之另一種用於形成埋置極性區域之技術。具體而言,在圖5(c)中,在位於埋置極性區域512內之電極510中形成一改變導電性區域(changed conductivity regions)518。在本發明之一實施例中,改變導電性區域受到重摻雜,以降低改變該等導電性區域之導電性。在本發明之其他實施例中,該等改變導電性區域可藉由如下方式形成:蝕刻導體510之某些部分並使用例如電活性聚合物(例如,聚乙炔、聚噻吩、聚吡咯(PPY)、聚苯胺(PANI)、及聚苯乙烯)、矽鍺及砷化鋁鎵等較低導電性材料或一非導電性材料(例如,二氧化矽)來填充該等區域。由於改變導電性區域中具有不同之導電性,埋置極性區域中之電場不同於電極510之其餘部分周圍之電場。 Figure 5(c) illustrates another technique for forming a buried polar region that can be combined with a buried electrode. Specifically, in FIG. 5(c), a changed conductive regions 518 are formed in the electrodes 510 located in the buried polarity region 512. In one embodiment of the invention, the electrically conductive regions are altered to be heavily doped to reduce the conductivity of the electrically conductive regions. In other embodiments of the invention, the altered conductivity regions can be formed by etching portions of the conductor 510 and using, for example, an electroactive polymer (eg, polyacetylene, polythiophene, polypyrrole (PPY) A lower conductivity material such as polyaniline (PANI) and polystyrene), tantalum and aluminum gallium arsenide or a non-conductive material (for example, cerium oxide) is used to fill the regions. The electric field in the buried polar region is different from the electric field around the rest of the electrode 510 due to the different conductivity in the altered conductivity region.
在圖5(c)之實施例中,改變導電性區域518係被製成非導電性的,俾使埋置極性區域512中之電場主要受埋置電極516控制。電極510與埋置電極516所產生電場之交互作用會形成橫向力,橫向力可增強多區域垂直配向操作,且亦在一物理擾動之後更快地將液晶重新定向至其正確位置。 In the embodiment of FIG. 5(c), the altered conductivity region 518 is made non-conductive such that the electric field in the buried polarity region 512 is primarily controlled by the buried electrode 516. The interaction of the electrodes 510 with the electric field generated by the buried electrode 516 creates a lateral force that enhances the multi-zone vertical alignment operation and also redirects the liquid crystal to its correct position more quickly after a physical disturbance.
圖6(a)-6(b)例示依據本發明另一實施例之一色點600之部分。色點600包含一正方形形狀之電極610,該正方形形狀之電極610具有一正方形形狀之埋置極性區域612。然而,電極610未延伸至埋置極性區域612中。在圖6(a)之實施例中,電極610被蝕刻,以在埋置極性區域612中形成一空隙。在本發明之其他實施例中,電極係形成有空隙。 Figures 6(a)-6(b) illustrate portions of a color point 600 in accordance with another embodiment of the present invention. The color point 600 includes a square shaped electrode 610 having a square shaped buried polarity region 612. However, electrode 610 does not extend into buried polarity region 612. In the embodiment of FIG. 6(a), electrode 610 is etched to form a void in buried polarity region 612. In other embodiments of the invention, the electrode system is formed with voids.
圖6(b)係為沿圖6(a)所示A1-A1切線截取之色點600之剖視圖。如圖6(b)所示,埋置極性區域612係由位於電極610下麵之一埋置電極616所形成。埋置電極616與電極610係由一鈍化層614間隔開。在圖6(b)之實施例中,鈍化層614被蝕刻,以在埋置極性區域612中形成一空隙。在本發明之其他實施例中,鈍化層614不包含空隙。埋置電極616係帶電的,以產生穿過電極610中之空隙之一電場。在本發明之大多數實施例中,電極610與埋置電極616具有相反之極性方向。舉例而言,當電極610具有正極性時,埋置電極616將具有一負極性。電極610與埋置電極616所產生電場之交互作用會形成橫向力,橫向力可增強多區域垂直配向操作,且亦在一物理擾動之後更快地將液晶重新定向至其正確位置。 Fig. 6(b) is a cross-sectional view of the color point 600 taken along the line A1-A1 shown in Fig. 6(a). As shown in FIG. 6(b), the buried polarity region 612 is formed by embedding the electrode 616 under one of the electrodes 610. The buried electrode 616 and the electrode 610 are separated by a passivation layer 614. In the embodiment of FIG. 6(b), passivation layer 614 is etched to form a void in buried polarity region 612. In other embodiments of the invention, passivation layer 614 does not contain voids. The buried electrode 616 is electrically charged to create an electric field through one of the spaces in the electrode 610. In most embodiments of the invention, electrode 610 and buried electrode 616 have opposite polar orientations. For example, when the electrode 610 has a positive polarity, the buried electrode 616 will have a negative polarity. The interaction of the electrodes 610 with the electric field generated by the buried electrode 616 creates a lateral force that enhances the multi-zone vertical alignment operation and also redirects the liquid crystal to its correct position more quickly after a physical disturbance.
如上所述,可使用本質離散場(intrinsic fringe field)來形成多區域。然而,本質離散場僅適用於小色點。因此,對於較大之顯示器,畫素係形成有包含許多色點之色分量。每一色分量係由一單獨之切換元件(例如,一薄膜電晶體(thin-film transistor,TFT))控制。一般而言,色分量係為紅色、綠色及藍色。依據本發明,一畫素之各色分量被進一步劃分成色點。圖7(a)-7(b)顯示依據本發明其中每一色分量具有多個色點之一畫素設計,該等色點包含埋置極性區域。具體而言,圖7(a)及圖7(b)顯示一畫素設計710(如下所述被標示為710+及710-)之不同點極性圖案,畫素設計710係常常用於具有一切換元件列反轉驅動模式之顯示器中。在實際操作中,一畫素將在每一影像頁框之間在一第一點極性圖案與一第二點極性圖案之間切換。為清楚起見,將其中第一色分量之第一色點具有一正極性之點極性圖案稱為正的點極性圖案。相反,將其中第一色分量之第一色點具有一負極性之點極性圖案稱為負的點極性圖案。具體而言,在圖7(a)中,畫素設計710具有一正的點極性圖案(因此被標示為710+),且在圖7(b)中,畫素設計710具有一負的點極性圖案(因此被標示為710-)。此外,在各種畫素設 計中,每一偏極化組件之極性係以「+」表示正極性,或以「-」表示負極性。然而,在本發明之某些實施例中,某些導體可被保持於共同電極V_com,進而具有一中性極性。 As described above, an intrinsic fringe field can be used to form a multi-region. However, the essentially discrete field is only suitable for small color points. Therefore, for larger displays, the pixels are formed with color components that contain many color points. Each color component is controlled by a separate switching element (e.g., a thin-film transistor (TFT)). In general, the color components are red, green, and blue. According to the invention, the color components of a pixel are further divided into color points. Figures 7(a)-7(b) show one pixel design with multiple color points for each color component in accordance with the present invention, the colored dots including buried polar regions. Specifically, FIGS. 7(a) and 7(b) show different dot polarity patterns of a pixel design 710 (labeled as 710+ and 710- as described below), and the pixel design 710 is often used to have one. The switching element column is reversed in the display mode of the drive mode. In actual operation, a pixel will switch between a first dot polarity pattern and a second dot polarity pattern between each image frame. For the sake of clarity, a dot pattern in which the first color point of the first color component has a positive polarity is referred to as a positive dot polarity pattern. In contrast, a dot polarity pattern in which the first color point of the first color component has a negative polarity is referred to as a negative dot polarity pattern. Specifically, in FIG. 7(a), the pixel design 710 has a positive dot polarity pattern (hence labeled 710+), and in FIG. 7(b), the pixel design 710 has a negative point. Polar pattern (hence labeled as 710-). In addition, in various pixel settings In the calculation, the polarity of each polarization component is represented by "+" for positive polarity or "-" for negative polarity. However, in certain embodiments of the invention, certain conductors may be held at the common electrode V_com, thereby having a neutral polarity.
畫素設計710具有三個色分量CC_1、CC_2及CC_3(在圖7(a)-7(b)中未標示出)。該三個色分量其中每一者包含二色點。為清楚起見,該等色點被表示成CD_X_Y,其中X係為一色分量(在圖7(a)-7(b)中係從1至3),且Y係為一色點編號(在圖7(a)-7(b)中係從1至2)。畫素設計710亦針對每一色分量包含一切換元件(被表示為SE_1、SE_2及SE_3),且針對每一色分量包含一離散場放大區域(被表示為FFAR_1、FFAR_2、及FFAR_3)。切換元件SE_1、SE_2及SE_3係排列成一列。圍繞各該切換元件之裝置組件區域係由離散場放大區域覆蓋,且因此在圖7(a)及圖7(b)中未具體標示出。離散場放大區域FFAR_1、FFAR_2、及FFAR_3亦排列成一列,且將在圖7(c)中對其進行詳細闡述。 The pixel design 710 has three color components CC_1, CC_2, and CC_3 (not shown in Figures 7(a)-7(b)). Each of the three color components includes a two color point. For the sake of clarity, the color points are represented as CD_X_Y, where X is a one-color component (from 1 to 3 in Figures 7(a)-7(b)), and Y is a color point number (in the figure) 7(a)-7(b) is from 1 to 2). The pixel design 710 also includes a switching element (denoted as SE_1, SE_2, and SE_3) for each color component, and a discrete field amplification region (denoted as FFAR_1, FFAR_2, and FFAR_3) for each color component. The switching elements SE_1, SE_2 and SE_3 are arranged in a row. The device component area surrounding each of the switching elements is covered by a discrete field amplification area and is therefore not specifically labeled in Figures 7(a) and 7(b). The discrete field amplification regions FFAR_1, FFAR_2, and FFAR_3 are also arranged in a row, and will be described in detail in FIG. 7(c).
畫素設計710之第一色分量CC_1具有二色點CD_1_1及CD_1_2。色點CD_1_1與CD_1_2形成一行,並以一垂直點間距VDS1間隔開。換言之,色點CD_1_1與CD_1_2係水平地配向並由垂直點間距VDS1垂直地間隔開。此外,色點CD_1_1與CD_1_2係垂直地錯開垂直點偏移量VDO1,垂直點偏移量VDO1係等於垂直點間距VDS1加上色點高度CDH。切換元件SE_1係位於色點CD_1_1與CD_1_2之間,俾使色點CD_1_1位於該列切換元件之一第一側,而色點CD_1_2位於該列切換元件之一第二側。切換元件SE_1係耦接至色點CD_1_1及CD_1_2之電極,以控制色點CD_1_1及CD_1_2之電壓極性及電壓大小。 The first color component CC_1 of the pixel design 710 has two color points CD_1_1 and CD_1_2. The color points CD_1_1 and CD_1_2 form a line and are spaced apart by a vertical dot pitch VDS1. In other words, the color points CD_1_1 and CD_1_2 are horizontally aligned and vertically spaced by the vertical dot pitch VDS1. Further, the color point CD_1_1 and the CD_1_2 are vertically shifted by the vertical dot offset VDO1, and the vertical dot offset VDO1 is equal to the vertical dot pitch VDS1 plus the color point height CDH. The switching element SE_1 is located between the color points CD_1_1 and CD_1_2 such that the color point CD_1_1 is located on a first side of the column switching element, and the color point CD_1_2 is located on a second side of the column switching element. The switching element SE_1 is coupled to the electrodes of the color points CD_1_1 and CD_1_2 to control the voltage polarity and voltage of the color points CD_1_1 and CD_1_2.
色分量CC_1之每一色點包含一埋置極性區域,該埋置極性區域會將色點中之任何觸碰雲紋效應最小化。具體而言,色點CD_1_1及CD_1_2分別包含埋置極性區域EPR_1_1及EPR_1_2。如圖7(a)所示,埋置極性區域EPR_1_1及EPR_1_2係分別居中於色點CD_1_1及CD_1_2中。在畫素設計710中,係使用圖6(a)-6(b)所示埋置導體技術來形成埋置極性區域。然而,為降低附圖之複雜性,如在圖5(a)中一般,以一陰影正方形來例示埋置極性區域。然而,本發明之其他實施例可使用其他技術來形成埋置極性區域,可包含多個埋置極性區域,或者可使埋置極性區域偏置。 Each color point of the color component CC_1 includes a buried polarity region that minimizes any touch moiré effects in the color point. Specifically, the color points CD_1_1 and CD_1_2 respectively include buried polarity areas EPR_1_1 and EPR_1_2. As shown in FIG. 7(a), the buried polar regions EPR_1_1 and EPR_1_2 are respectively centered in the color points CD_1_1 and CD_1_2. In the pixel design 710, the buried polarity region is formed using the buried conductor technique shown in Figs. 6(a)-6(b). However, in order to reduce the complexity of the drawing, as in the general drawing of Fig. 5(a), the buried polar region is illustrated by a hatched square. However, other embodiments of the present invention may use other techniques to form the buried polarity region, may include multiple buried polarity regions, or may bias the buried polarity regions.
如上所述,埋置極性區域之極性不同於色點之極性。因此,埋置極性區域EPR_1_1及EPR_1_2之極性係由一不同於切換元件SE_1(其控制色點CD_1_1及CD_1_2之極性)之極性源所控制。在本發明之某些實施例中,一顯示器包含專用埋置極性區域切換元件來控制埋置極性區域之極性(一個此類實施例參見圖7(d))。本發明之其他實施例可將埋置極性區域耦接至畫素之具有一不同極性之其他元件。舉例而言,在本發明之某些實施例中,埋置極性區域EPR_1_1及EPR_1_2係耦接至以下所述之離散場放大區域FFAR_1。 As described above, the polarity of the buried polarity region is different from the polarity of the color point. Therefore, the polarities of the buried polarity regions EPR_1_1 and EPR_1_2 are controlled by a polarity source different from the switching element SE_1 which controls the polarities of the color points CD_1_1 and CD_1_2. In some embodiments of the invention, a display includes a dedicated buried polarity region switching element to control the polarity of the buried polarity region (see Figure 7(d) for one such embodiment). Other embodiments of the invention may couple the buried polar regions to other elements of the pixel having a different polarity. For example, in some embodiments of the invention, the buried polarity regions EPR_1_1 and EPR_1_2 are coupled to discrete field amplification regions FFAR_1 as described below.
相似地,畫素設計710之第二色分量CC_2具有二色點CD_2_1及CD_2_2。色點CD_2_1與CD_2_2形成一第二行,並以一垂直點間距VDS1間隔開。因此,色點CD_2_1與CD_2_2係水平地配向並以垂直點間距VDS1垂直地間隔開。切換元件SE_2係位於色點CD_2_1與CD_2_2之間,俾使色點CD_2_1位於該列切換元件之第一側,而色點CD_2_2位於該列切換元件之一第二側。切換元件SE_2係耦接至色點CD_2_1及CD_2_2之電極,以控制色點CD_2_1及CD_2_2之電壓極性及電壓大小。第二色分量CC_2係與第一色分量CC_1垂直地配向,並以一水平點間距HDS1與色分量CC_1間隔開,因此色分量CC_2與CC_1係水平地錯開一水平點偏移量HDO1,水平點偏移量HDO1係等於水平點間距HDS1加上色點寬度CDW。具體關於色點而言,色點CD_2_1與色點CD_1_1係垂直地配向並以水平點間距HDS1水平地間隔開。相似地,色點CD_2_2與色點CD_1_2係垂直地配向並以水平點間距HDS1水平地間隔開。因此,色點CD_1_1與色點CD_2_1形成一第一列色點,且色點CD_1_2與色點CD_2_2形成一第二列色點。與色點CD_1_1及色點CD_1_2一樣,色點CD_2_1及色點CD_2_2分別包含埋置極性區域EPR_2_1及EPR_2_2。 Similarly, the second color component CC_2 of the pixel design 710 has two color points CD_2_1 and CD_2_2. The color points CD_2_1 and CD_2_2 form a second line and are spaced apart by a vertical dot pitch VDS1. Therefore, the color points CD_2_1 and CD_2_2 are horizontally aligned and vertically spaced apart by the vertical dot pitch VDS1. The switching element SE_2 is located between the color points CD_2_1 and CD_2_2 such that the color point CD_2_1 is located on the first side of the column switching element, and the color point CD_2_2 is located on the second side of one of the column switching elements. The switching element SE_2 is coupled to the electrodes of the color points CD_2_1 and CD_2_2 to control the voltage polarity and voltage of the color points CD_2_1 and CD_2_2. The second color component CC_2 is vertically aligned with the first color component CC_1, and is spaced apart by a horizontal dot pitch HDS1 and the color component CC_1. Therefore, the color components CC_2 and CC_1 are horizontally shifted by a horizontal point offset HDD1, the horizontal point. The offset HDD1 is equal to the horizontal dot pitch HDS1 plus the color dot width CDW. Specifically, regarding the color point, the color point CD_2_1 and the color point CD_1_1 are vertically aligned and horizontally spaced by the horizontal dot pitch HDS1. Similarly, the color point CD_2_2 is vertically aligned with the color point CD_1_2 and horizontally spaced by the horizontal dot pitch HDS1. Therefore, the color point CD_1_1 and the color point CD_2_1 form a first column color point, and the color point CD_1_2 and the color point CD_2_2 form a second column color point. Like the color point CD_1_1 and the color point CD_1_2, the color point CD_2_1 and the color point CD_2_2 respectively include the buried polarity areas EPR_2_1 and EPR_2_2.
相似地,畫素設計710之第三色分量CC_3具有二色點CD_3_1及CD_3_2。色點CD_3_1與CD_3_2形成一第三行,並以一垂直點間距VDS1間隔開。因此,色點CD_3_1與CD_3_2係水平地配向並以垂直點間距VDS1垂直地間隔開。切換元件SE_3係位於色點CD_3_1與CD_3_2之間,俾使色點CD_3_1位於該列切換元件之第一側,而色點CD_3_2位於該列切換元件之一第二側。切換元件SE_3係耦接至色點CD_3_1及CD_3_2之電極, 以控制色點CD_3_1及CD_3_2之電壓極性及電壓大小。第三色分量CC_3係與第二色分量CC_2垂直地配向,並以水平點間距HDS1與色分量CC_2間隔開,因此色分量CC_3與CC_2係水平地錯開一水平點偏移量HDO1。具體關於色點而言,色點CD_3_1與色點CD_2_1係垂直地配向且以水平點間距HDS1水平地間隔開。相似地,色點CD_3_2與色點CD_2_2係垂直地配向並以水平點間距HDS1水平地間隔開。因此,色點CD_3_1係位於第一列色點上,且色點CD_3_2係位於第二列色點上。與色點CD_1_1及色點CD_1_2一樣,色點CD_3_1及色點CD_3_2分別包含埋置極性區域EPR_3_1及EPR_3_2。 Similarly, the third color component CC_3 of the pixel design 710 has two color points CD_3_1 and CD_3_2. The color points CD_3_1 and CD_3_2 form a third line and are spaced apart by a vertical dot pitch VDS1. Therefore, the color points CD_3_1 and CD_3_2 are horizontally aligned and vertically spaced apart by the vertical dot pitch VDS1. The switching element SE_3 is located between the color points CD_3_1 and CD_3_2 such that the color point CD_3_1 is located on the first side of the column switching element, and the color point CD_3_2 is located on the second side of one of the column switching elements. The switching element SE_3 is coupled to the electrodes of the color points CD_3_1 and CD_3_2. To control the voltage polarity and voltage of the color points CD_3_1 and CD_3_2. The third color component CC_3 is vertically aligned with the second color component CC_2, and is spaced apart from the color component CC_2 by the horizontal dot pitch HDS1, so that the color components CC_3 and CC_2 are horizontally shifted by a horizontal dot offset amount HDO1. Specifically, with respect to the color point, the color point CD_3_1 and the color point CD_2_1 are vertically aligned and horizontally spaced by the horizontal dot pitch HDS1. Similarly, the color point CD_3_2 is vertically aligned with the color point CD_2_2 and horizontally spaced by the horizontal dot pitch HDS1. Therefore, the color point CD_3_1 is located on the first column color point, and the color point CD_3_2 is located on the second column color point. Like the color point CD_1_1 and the color point CD_1_2, the color point CD_3_1 and the color point CD_3_2 respectively include the buried polarity areas EPR_3_1 and EPR_3_2.
為清楚起見,以具有相同色點高度CDH之色點來例示畫素設計710之各色點。然而,本發明之某些實施例可包含具有不同色點高度之色點。舉例而言,在本發明之一實施例(其為畫素設計710之一變體)中,色點CD_1_1、CD_2_1、及CD_3_1之色點高度小於色點CD_1_2、CD_2_2、及CD_3_2之色點高度。此外,在本發明之許多實施例中,色點可具有不同形狀。 For the sake of clarity, the color points of the pixel design 710 are illustrated with color points having the same color point height CDH. However, certain embodiments of the invention may include color points having different color point heights. For example, in one embodiment of the present invention, which is a variant of the pixel design 710, the color point heights of the color points CD_1_1, CD_2_1, and CD_3_1 are smaller than the color point heights of the color points CD_1_2, CD_2_2, and CD_3_2. . Moreover, in many embodiments of the invention, the color points can have different shapes.
畫素設計710亦包含離散場放大區域FFAR_1、FFAR_2、及FFAR_3。圖7(c)顯示畫素設計710之離散場放大區域FFAR_1之一更詳細視圖。為清楚起見,將離散場放大區域FFAR_1在概念上劃分成一垂直放大部VAP與一水平放大部HAP。在圖7(c)中,水平放大部HAP係垂直地居中於垂直放大部VAP上並向垂直放大部VAP左側延伸。藉由使用水平放大部及垂直放大部,能夠更清楚地說明離散場放大區域FFAR_1之放置。在本發明之大多數實施例中,離散場放大區域之電極係由一個連續導體形成。水平放大部HAP具有一水平放大部寬度HAP_W及一水平放大部高度HAP_H。相似地,垂直放大部VAP具有一垂直放大部寬度VAP_W及一垂直放大部高度VAP_H。離散場放大區域FFAR_2及FFAR_3具有與離散場放大區域FFAR_1相同之形狀。在具有不同大小色點之本發明實施例中,水平放大部HAP將位於各色點之間而非居中於垂直放大部VAP上。 The pixel design 710 also includes discrete field amplification regions FFAR_1, FFAR_2, and FFAR_3. Figure 7(c) shows a more detailed view of one of the discrete field amplification regions FFAR_1 of the pixel design 710. For the sake of clarity, the discrete field amplification region FFAR_1 is conceptually divided into a vertical amplification portion VAP and a horizontal amplification portion HAP. In FIG. 7(c), the horizontal amplifying portion HAP is vertically centered on the vertical amplifying portion VAP and extends to the left side of the vertical amplifying portion VAP. The placement of the discrete field amplification region FFAR_1 can be more clearly explained by using the horizontal amplification portion and the vertical amplification portion. In most embodiments of the invention, the electrodes of the discrete field amplification region are formed from one continuous conductor. The horizontal amplifying portion HAP has a horizontal amplifying portion width HAP_W and a horizontal amplifying portion height HAP_H. Similarly, the vertical amplifying portion VAP has a vertical amplifying portion width VAP_W and a vertical amplifying portion height VAP_H. The discrete field amplification areas FFAR_2 and FFAR_3 have the same shape as the discrete field amplification area FFAR_1. In embodiments of the invention having different sized color points, the horizontal magnification portion HAP will be located between the color points rather than centered on the vertical magnification portion VAP.
如圖7(a)所示,離散場放大區域FFAR_1、FFAR_2、及FFAR_3係被放置於畫素設計710之各色點之間。具體而言,離散場放大區域FFAR_1係被放置成使離散場放大區域FFAR_1之水平放大部位於色點CD_1_1與 CD_1_2之間,並以一垂直離散場放大區域間距VFFARS與色點CD_1_1及CD_1_2間隔開。離散場放大區域FFAR_1之垂直放大部係被放置於色點CD_1_1及CD_1_2之右側,並以一水平離散場放大區域間距HFFARS與色點CD_1_1及CD_1_2間隔開。因此,離散場放大區域FFAR_1係沿色點CD_1_1之底部及右側以及沿色點CD_1_2之頂部及右側延伸。此外,此種放置方式亦使離散場放大區域FFAR_1之垂直放大部位於色點CD_1_1與CD_2_1之間及色點CD_1_2與CD_2_2之間。 As shown in FIG. 7(a), the discrete field amplification areas FFAR_1, FFAR_2, and FFAR_3 are placed between the color points of the pixel design 710. Specifically, the discrete field amplification area FFAR_1 is placed such that the horizontal amplification portion of the discrete field amplification area FFAR_1 is located at the color point CD_1_1 and Between CD_1_2, and a vertical discrete field amplification area spacing VFFARS is spaced apart from color points CD_1_1 and CD_1_2. The vertical amplification portion of the discrete field amplification area FFAR_1 is placed to the right of the color points CD_1_1 and CD_1_2, and is spaced apart from the color points CD_1_1 and CD_1_2 by a horizontal discrete field amplification area spacing HFFARS. Therefore, the discrete field amplification area FFAR_1 extends along the bottom and right sides of the color point CD_1_1 and along the top and right sides of the color point CD_1_2. In addition, the placement method also causes the vertical amplification portion of the discrete field amplification area FFAR_1 to be located between the color points CD_1_1 and CD_2_1 and between the color points CD_1_2 and CD_2_2.
相似地,離散場放大區域FFAR_2係被放置成使離散場放大區域FFAR_2之水平放大部位於色點CD_2_1與CD_2_2之間,並以一垂直離散場放大區域間距VFFARS與色點CD_2_1及CD_2_2間隔開。離散場放大區域FFAR_2之垂直放大部係被放置於色點CD_2_1及CD_2_2之右側,並以一水平離散場放大區域間距HFFARS與色點CD_2_1及CD_2_2間隔開。因此,離散場放大區域FFAR_2係沿色點CD_2_1之底部及右側以及沿色點CD_2_2之頂部及右側延伸。此種放置方式亦使離散場放大區域FFAR_2之垂直放大部位於色點CD_2_1與CD_3_1之間及色點CD_2_2與CD_3_2之間。 Similarly, the discrete field amplification region FFAR_2 is placed such that the horizontal amplification portion of the discrete field amplification region FFAR_2 is located between the color points CD_2_1 and CD_2_2, and is spaced apart from the color points CD_2_1 and CD_2_2 by a vertical discrete field amplification region spacing VFFARS. The vertical amplification portion of the discrete field amplification region FFAR_2 is placed to the right of the color points CD_2_1 and CD_2_2, and is spaced apart from the color points CD_2_1 and CD_2_2 by a horizontal discrete field amplification region spacing HFFARS. Therefore, the discrete field amplification area FFAR_2 extends along the bottom and right sides of the color point CD_2_1 and along the top and right sides of the color point CD_2_2. This placement also causes the vertical amplification of the discrete field amplification region FFAR_2 to be between the color points CD_2_1 and CD_3_1 and between the color points CD_2_2 and CD_3_2.
離散場放大區域FFAR_3係被放置成使離散場放大區域FFAR_3之水平放大部位於色點CD_3_1與CD_3_2之間,並以一垂直離散場放大區域間距VFFARS與色點CD_3_1及CD_3_2間隔開。離散場放大區域FFAR_3之垂直放大部係被放置於色點CD_3_1及CD_3_2之右側,並以一水平離散場放大區域間距HFFARS與色點CD_3_1及CD_3_2間隔開。因此,離散場放大區域FFAR_3係沿色點CD_3_1之底部及右側以及沿色點CD_3_2之頂部及右側延伸。 The discrete field amplification area FFAR_3 is placed such that the horizontal amplification portion of the discrete field amplification area FFAR_3 is located between the color points CD_3_1 and CD_3_2, and is spaced apart from the color points CD_3_1 and CD_3_2 by a vertical discrete field amplification area spacing VFFARS. The vertical amplification portion of the discrete field amplification region FFAR_3 is placed to the right of the color points CD_3_1 and CD_3_2, and is spaced apart from the color points CD_3_1 and CD_3_2 by a horizontal discrete field amplification region spacing HFFARS. Therefore, the discrete field amplification area FFAR_3 extends along the bottom and right sides of the color point CD_3_1 and along the top and right sides of the color point CD_3_2.
使用「+」及「-」符號來顯示色點、離散場放大區域、及切換元件之極性。因此,在其中顯示畫素設計710+之正的點極性圖案之圖7(a)中,所有切換元件(即,切換元件SE_1、SE_2及SE_3)及所有色點(即,色點CD_1_1、CD_1_2、CD_2_1、CD_2_2、CD_3_1、及CD_3_2)具有正極性。然而,所有離散場放大區域(即,離散場放大區域FFAR_1、FFAR_2、及FFAR_3)具有負極性。如上所述,埋置極性區域可具有與色點相同之極性方向(即,正的或負的)但具有一不同之極性大小。作為另一選擇,埋置 極性區域可具有不同於色點之極性(即,極性方向)(例如,色點極性為正極性,而埋置極性區域具有負極性)。此外,埋置極性區域可具有中性極性。在本發明之一特定實施例中,畫素設計710之各埋置極性區域具有不同於色點之極性。因此,對於此實施例,埋置極性區域EPR_1_1、EPR_1_2、EPR_2_1、EPR_2_2、EPR_3_1、及EPR_3_2在圖7(a)中將具有負極性。 Use the "+" and "-" symbols to display the color point, the discrete field amplification area, and the polarity of the switching element. Therefore, in FIG. 7(a) in which the dot polarity pattern of the pixel design 710+ is displayed, all the switching elements (ie, the switching elements SE_1, SE_2, and SE_3) and all the color points (ie, the color points CD_1_1, CD_1_2) , CD_2_1, CD_2_2, CD_3_1, and CD_3_2) have positive polarity. However, all of the discrete field amplification regions (ie, the discrete field amplification regions FFAR_1, FFAR_2, and FFAR_3) have a negative polarity. As noted above, the buried polar regions can have the same polarity direction (i.e., positive or negative) as the color dots but have a different polarity. As another option, embed The polar regions may have a polarity different from the color point (ie, the polarity direction) (eg, the color point polarity is positive polarity and the buried polarity region has negative polarity). Additionally, the buried polar regions can have a neutral polarity. In a particular embodiment of the invention, each of the buried polar regions of the pixel design 710 has a polarity different from the color point. Therefore, for this embodiment, the buried polarity regions EPR_1_1, EPR_1_2, EPR_2_1, EPR_2_2, EPR_3_1, and EPR_3_2 will have a negative polarity in FIG. 7(a).
圖7(b)顯示具有負的點極性圖案之畫素設計710。對於負的點極性圖案,所有切換元件(即,切換元件SE_1、SE_2及SE_3)及所有色點(即,色點CD_1_1、CD_1_2、CD_2_1、CD_2_2、CD_3_1、及CD_3_2)具有負極性。然而,所有離散場放大區域(即,離散場放大區域FFAR_1、FFAR_2、及FFAR_3)具有正極性。在本發明之特定實施例中,畫素設計710之各埋置極性區域具有不同於色點之極性,且埋置極性區域EPR_1_1、EPR_1_2、EPR_2_1、EPR_2_2、EPR_3_1、及EPR_3_2在圖7(b)中將具有正極性。 Figure 7(b) shows a pixel design 710 with a negative dot polarity pattern. For a negative dot polarity pattern, all switching elements (ie, switching elements SE_1, SE_2, and SE_3) and all color points (ie, color points CD_1_1, CD_1_2, CD_2_1, CD_2_2, CD_3_1, and CD_3_2) have negative polarity. However, all of the discrete field amplification regions (ie, the discrete field amplification regions FFAR_1, FFAR_2, and FFAR_3) have positive polarity. In a particular embodiment of the invention, each of the buried polar regions of the pixel design 710 has a polarity different from the color point, and the buried polar regions EPR_1_1, EPR_1_2, EPR_2_1, EPR_2_2, EPR_3_1, and EPR_3_2 are in FIG. 7(b). Lieutenant will have positive polarity.
若鄰近組件具有相反極性,則每一色點中之離散場會被放大。畫素設計710利用離散場放大區域來增強並穩定液晶結構中之多區域之形成。一般而言,偏極化組件之極性被指定成使一第一極性之一色點之相鄰偏極化組件具有第二極性。舉例而言,對於畫素設計710(圖7(a))之正的點極性圖案,色點CD_2_2具有正極性。然而,相鄰之偏極化組件(離散場放大區域FFAR_2及FFAR_1)具有負極性。因此,色點CD_2_2之離散場被放大。此外,如下所述,亦在顯示器層階執行極性反轉模式,俾使緊鄰色點CD_1_2放置之另一畫素之色點將具有負極性(參見圖7(d))。 If adjacent components have opposite polarities, the discrete fields in each color point will be amplified. The pixel design 710 utilizes discrete field amplification regions to enhance and stabilize the formation of multiple regions in the liquid crystal structure. In general, the polarity of the polarization component is specified such that adjacent polarization components of a color point of a first polarity have a second polarity. For example, for the positive dot polarity pattern of the pixel design 710 (Fig. 7(a)), the color point CD_2_2 has a positive polarity. However, adjacent polarization components (discrete field amplification regions FFAR_2 and FFAR_1) have a negative polarity. Therefore, the discrete field of the color point CD_2_2 is amplified. Further, as described below, the polarity inversion mode is also performed at the display level, so that the color point of another pixel placed next to the color point CD_1_2 will have a negative polarity (see FIG. 7(d)).
因畫素設計710中之所有切換元件具有相同極性且離散場放大區域需要相反極性,故離散場放大區域係由一外部極性源(即,來自畫素設計710之特定畫素外之一極性源)驅動。可依據本發明之不同實施例來使用各種相反極性源。舉例而言,可使用特定的離散場放大區域切換元件、或亦可使用鄰近畫素之具有一相反點極性之切換元件來驅動離散場放大區域。在圖7(a)-7(b)之實施例中,亦可使用鄰近畫素之具有一相反點極性之切換元件來驅動離散場放大區域。因此,畫素設計710包含用以幫助離散場放大區域耦接至其他畫素中之切換元件之導體。具體而言,一當前畫素之一導體712會將離散場放大區域FFAR_1之電極耦接至位於當前畫素上方之一畫素之切換元件SE_1(參見圖7(d)及圖7(e))。與切換元件之連接將經由位於當 前畫素上方之畫素之色點之電極達成。相似地,一當前畫素之一導體714會將離散場放大區域FFAR_2之電極耦接至位於當前畫素上方之一畫素之切換元件SE_2(參見圖7(d))。與切換元件之連接將經由位於當前畫素上方之畫素之色點之電極達成。一當前畫素之一導體716會將離散場放大區域FFAR_3之電極耦接至位於當前畫素上方之一畫素之切換元件SE_3(參見圖7(d)及圖7(e))。與切換元件之連接將經由位於當前畫素上方之畫素之色點之電極達成。 Since all of the switching elements in pixel design 710 have the same polarity and the discrete field amplification regions require opposite polarities, the discrete field amplification region is comprised of an external polarity source (ie, one of the polar sources from a particular pixel of pixel design 710). )drive. Various sources of opposite polarity can be used in accordance with various embodiments of the present invention. For example, a particular discrete field amplification region switching element can be used, or a switching element having an opposite point polarity of a neighboring pixel can also be used to drive the discrete field amplification region. In the embodiment of Figures 7(a)-7(b), the discrete field amplification regions can also be driven using switching elements of adjacent pixels having opposite polarity. Thus, the pixel design 710 includes conductors to assist in coupling the discrete field amplification regions to switching elements in other pixels. Specifically, one of the current pixels 712 couples the electrodes of the discrete field amplification area FFAR_1 to the switching element SE_1 located above the current pixel (see FIGS. 7(d) and 7(e). ). The connection to the switching element will be via The electrode of the color point of the pixel above the front pixel is achieved. Similarly, one of the current pixels 714 couples the electrodes of the discrete field amplification region FFAR_2 to a switching element SE_2 located at one pixel above the current pixel (see Figure 7(d)). The connection to the switching element is achieved via the electrode of the color point of the pixel above the current pixel. A conductor 716 of a current pixel couples the electrodes of the discrete field amplification region FFAR_3 to a switching element SE_3 of one pixel above the current pixel (see FIGS. 7(d) and 7(e)). The connection to the switching element is achieved via the electrode of the color point of the pixel above the current pixel.
該等連接更佳地顯示於圖7(d)中,圖7(d)示出一顯示器720之一部分,顯示器720之該部分使用畫素設計710之畫素P(0,0)、P(1,0)、P(0,1)、及P(1,1)並使用一切換元件列反轉驅動模式。顯示器720可具有數千列,且每一列上具有數千畫素。列與行將以圖7(d)所示之方式從圖7(d)所示之部分連續排列。為清楚起見,在圖7(d)中省略了用於控制切換元件之閘極線(gate line)及源極線(source line)。此外,為更佳地例示每一畫素,將每一畫素之區域陰影化,此陰影在圖7(d)中僅用於例示目的,並不具有功能意義。顯示器720之畫素被設置成使位於一列中之所有畫素皆具有相同之點極性圖案(正的或負的),且每一連續列應在正的點極性圖案與負的點極性圖案之間交替。因此,第一列(即,列0)中之畫素P(0,0)及P(1,0)具有正的點極性圖案,且第二列(即,列1)中之畫素P(0,1)及P(1,1)具有負的點極性圖案。然而,在下一頁框中,畫素將切換點極性圖案。因此,一般而言,一畫素P(x,y)在y為偶數時具有一第一點極性圖案,而在y為奇數時具有一第二點極性圖案。畫素設計710中之內部導體712、714、及716提供極性至離散場放大區域。具體而言,一第一畫素之離散場放大區域係自一第二畫素接收電壓極性及電壓大小。具體而言,該第二畫素係位於該第一畫素上方之畫素。舉例而言,畫素P(0,0)之離散場放大區域FFAR_1之電極係經由畫素P(0,1)之色點CD_1_2之電極而耦接至畫素P(0,1)之切換元件SE_1。相似地,畫素P(0,0)之離散場放大區域FFAR_2及FFAR_3之電極分別經由畫素P(0,1)之色點CD_2_2及CD_3_2而耦接至畫素P(0,1)之切換元件SE_2及SE_3。 The connections are better shown in Figure 7(d), and Figure 7(d) shows a portion of a display 720 that uses the pixels P(0,0), P of the pixel design 710 ( 1,0), P(0,1), and P(1,1) and use a switching element column inversion driving mode. Display 720 can have thousands of columns with thousands of pixels on each column. The columns and rows will be successively arranged from the portion shown in Fig. 7(d) in the manner shown in Fig. 7(d). For the sake of clarity, the gate line and the source line for controlling the switching elements are omitted in FIG. 7(d). Furthermore, in order to better illustrate each pixel, the area of each pixel is shaded, and this shadow is used for illustration purposes only in FIG. 7(d) and does not have a functional meaning. The pixels of display 720 are arranged such that all pixels in a column have the same point polarity pattern (positive or negative), and each successive column should be in a positive dot polarity pattern and a negative dot polarity pattern. Alternate. Therefore, the pixels P(0,0) and P(1,0) in the first column (ie, column 0) have a positive dot polarity pattern, and the pixel P in the second column (ie, column 1) (0, 1) and P (1, 1) have a negative dot polarity pattern. However, in the next page box, the pixels will switch the dot polarity pattern. Therefore, in general, a pixel P(x, y) has a first dot polarity pattern when y is an even number and a second dot polarity pattern when y is an odd number. Inner conductors 712, 714, and 716 in pixel design 710 provide a polar to discrete field amplification region. Specifically, the discrete field amplification region of the first pixel receives voltage polarity and voltage magnitude from a second pixel. Specifically, the second pixel is a pixel located above the first pixel. For example, the electrode of the discrete field amplification region FFAR_1 of the pixel P(0,0) is coupled to the pixel P(0,1) via the electrode of the color point CD_1_2 of the pixel P(0,1). Element SE_1. Similarly, the electrodes of the discrete field amplification regions FFAR_2 and FFAR_3 of the pixel P(0,0) are respectively coupled to the pixel P(0,1) via the color points CD_2_2 and CD_3_2 of the pixel P(0,1). Switching elements SE_2 and SE_3.
顯示器720亦針對每一列埋置極性區域包含埋置極性區域切換元件EPR_SE_X_Y。在圖7(d)中,「X」係表示畫素之列編號,且「Y」係表示一 畫素中之埋置極性區域之列編號。因此,埋置極性區域切換元件EPR_SE_0_1及EPR_SE_0_2係用於列0中之畫素(即,畫素P(0,0)及畫素P(1,0))。具體而言,埋置極性區域切換元件EPR_SE_0_1係耦接至畫素P(0,0)之埋置極性區域EPR_1_1、EPR_2_1、及EPR_3_1以及畫素P(1,0)之埋置極性區域EPR_1_1、EPR_2_1、及EPR_3_1。埋置極性區域切換元件EPR_SE_0_2係耦接至畫素P(0,0)之埋置極性區域EPR_1_2、EPR_2_2、及EPR_3_2以及畫素P(1,0)之埋置極性區域EPR_1_2、EPR_2_2、及EPR_3_2。同樣地,埋置極性區域切換元件EPR_SE_1_1及EPR_SE_1_2係用於列1中之畫素(即,畫素P(0,1)及畫素P(1,1))。具體而言,埋置極性區域切換元件EPR_SE_1_1係耦接至畫素P(0,1)之埋置極性區域EPR_1_1、EPR_2_1、及EPR_3_1以及畫素P(1,1)之埋置極性區域EPR_1_1、EPR_2_1、及EPR_3_1。埋置極性區域切換元件EPR_SE_1_2係耦接至畫素P(0,1)之埋置極性區域EPR_1_2、EPR_2_2、及EPR_3_2以及畫素P(1,1)之埋置極性區域EPR_1_2、EPR_2_2、及EPR_3_2。一般而言,一埋置極性區域切換元件相較於與該埋置極性區域切換元件相對應之畫素中之切換元件具有不同極性。因此,在圖7(d)中,埋置極性區域切換元件EPR_SE_0_1及EPR_SE_0_2將具有負極性。相反,埋置極性區域切換元件EPR_SE_1_1及EPR_SE_1_2將具有正極性。在本發明之某些實施例中,將以一更平衡之方式放置埋置極性區域切換元件。舉例而言,在本發明之一特定實施例中,埋置極性區域切換元件之一半係被放置於顯示器之右側,且埋置極性區域切換元件之另一半係被放置於顯示器之左側。在本發明之某些實施例中,可藉由對於每一列畫素使用單一埋置極性區域切換元件來減少埋置極性區域切換元件之數目。具體而言,埋置極性區域切換元件EPR_SE_0_1及EPR_SE_0_2減少至一個埋置極性區域切換元件EPR_SE_0,埋置極性區域切換元件EPR_SE_0係用於列0中之畫素(即,畫素P(0,0)及畫素P(1,0))。埋置極性區域切換元件EPR_SE_0係耦接至畫素P(0,0)之埋置極性區域EPR_1_1、EPR_2_1、EPR_3_1、EPR_1_2、EPR_2_2、及EPR_3_2以及畫素P(1,0)之埋置極性區域EPR_1_1、EPR_2_1、EPR_3_1、EPR_1_2、EPR_2_2、及EPR_3_2。此外,埋置極性區域切換元件EPR_SE_1_1及EPR_SE_1_2減少至一個埋置極性區域切換 元件EPR_SE_1,埋置極性區域切換元件EPR_SE_1係用於列1中之畫素(即,畫素P(0,1)及畫素P(1,1))。埋置極性區域切換元件EPR_SE_1係耦接至畫素P(0,1)之埋置極性區域EPR_1_1、EPR_2_1、EPR_3_1、EPR_1_2、EPR_2_2、及EPR_3_2以及畫素P(1,1)之埋置極性區域EPR_1_1、EPR_2_1、EPR_3_1、EPR_1_2、EPR_2_2、及EPR_3_2。 Display 720 also includes a buried polarity area switching element EPR_SE_X_Y for each column buried polarity region. In Fig. 7(d), "X" indicates the column number of the pixel, and "Y" indicates one. The number of the buried polar region in the pixel. Therefore, the buried polar region switching elements EPR_SE_0_1 and EPR_SE_0_2 are used for the pixels in the column 0 (ie, the pixels P(0, 0) and the pixels P(1, 0)). Specifically, the buried polarity region switching element EPR_SE_0_1 is coupled to the buried polarity regions EPR_1_1, EPR_2_1, and EPR_3_1 of the pixel P(0, 0) and the buried polarity region EPR_1_1 of the pixel P(1, 0), EPR_2_1, and EPR_3_1. The buried polarity region switching element EPR_SE_0_2 is coupled to the buried polarity regions EPR_1_2, EPR_2_2, and EPR_3_2 of the pixel P(0,0) and the buried polarity regions EPR_1_2, EPR_2_2, and EPR_3_2 of the pixel P(1,0). . Similarly, the buried polar region switching elements EPR_SE_1_1 and EPR_SE_1_2 are used for the pixels in the column 1 (ie, the pixels P(0, 1) and the pixels P(1, 1)). Specifically, the buried polarity region switching element EPR_SE_1_1 is coupled to the buried polarity regions EPR_1_1, EPR_2_1, and EPR_3_1 of the pixel P(0, 1) and the buried polarity region EPR_1_1 of the pixel P(1, 1), EPR_2_1, and EPR_3_1. The buried polarity region switching element EPR_SE_1_2 is coupled to the buried polarity regions EPR_1_2, EPR_2_2, and EPR_3_2 of the pixel P(0,1) and the buried polarity regions EPR_1_2, EPR_2_2, and EPR_3_2 of the pixel P(1,1). . In general, a buried polarity area switching element has a different polarity than a switching element in a pixel corresponding to the buried polarity area switching element. Therefore, in FIG. 7(d), the buried polar region switching elements EPR_SE_0_1 and EPR_SE_0_2 will have a negative polarity. On the contrary, the buried polar region switching elements EPR_SE_1_1 and EPR_SE_1_2 will have positive polarity. In some embodiments of the invention, the buried polar area switching elements will be placed in a more balanced manner. For example, in one particular embodiment of the invention, one half of the buried polar area switching element is placed on the right side of the display and the other half of the buried polarity area switching element is placed on the left side of the display. In some embodiments of the invention, the number of buried polar region switching elements can be reduced by using a single buried polarity region switching element for each column of pixels. Specifically, the buried polarity area switching elements EPR_SE_0_1 and EPR_SE_0_2 are reduced to one buried polarity area switching element EPR_SE_0, and the buried polarity area switching element EPR_SE_0 is used for the pixels in the column 0 (ie, pixel P (0, 0) ) and pixels P(1,0)). The buried polarity region switching element EPR_SE_0 is coupled to the buried polarity regions EPR_1_1, EPR_2_1, EPR_3_1, EPR_1_2, EPR_2_2, and EPR_3_2 of the pixel P(0, 0) and the buried polar region of the pixel P(1, 0). EPR_1_1, EPR_2_1, EPR_3_1, EPR_1_2, EPR_2_2, and EPR_3_2. In addition, the buried polarity area switching elements EPR_SE_1_1 and EPR_SE_1_2 are reduced to one buried polarity area switching The element EPR_SE_1, the buried polarity area switching element EPR_SE_1 is used for the pixels in the column 1 (ie, the pixels P(0, 1) and the pixels P(1, 1)). The buried polar region switching element EPR_SE_1 is coupled to the buried polar regions EPR_1_1, EPR_2_1, EPR_3_1, EPR_1_2, EPR_2_2, and EPR_3_2 of the pixel P(0, 1) and the buried polar region of the pixel P(1, 1). EPR_1_1, EPR_2_1, EPR_3_1, EPR_1_2, EPR_2_2, and EPR_3_2.
由於在顯示器720中每一列上存在極性切換,若一色點具有第一極性,則任何相鄰之偏極化組件及埋置極性區域將具有第二極性。舉例而言,畫素P(0,1)之色點CD_3_2具有負極性,而畫素P(0,1)之埋置極性區域EPR_3_2、畫素P(0,0)之色點CD_3_1、畫素P(0,1)之離散場放大區域FFAR_2及FFAR_3具有正極性。在本發明之一特定實施例中,每一色點具有40微米之一寬度及60微米之一高度。每一埋置極性區域具有6微米之一寬度及6微米之一高度。每一離散場放大區域具有5微米之一垂直放大部寬度、145微米之一垂直放大部高度、50微米之一水平放大部寬度、5微米之一水平放大部高度。水平點間距HDS1係為15微米,垂直點間距VDS1係為25微米、水平離散場放大區域間距HFFARS係為5微米,且垂直離散場放大區域間距VFFARS係為5微米。 Since there is polarity switching on each column in display 720, if a color point has a first polarity, then any adjacent polarization components and buried polarity regions will have a second polarity. For example, the color point CD_3_2 of the pixel P(0,1) has a negative polarity, and the buried polarity region EPR_3_2 of the pixel P(0,1), the color point CD_3_1 of the pixel P(0,0), The discrete field amplification regions FFAR_2 and FFAR_3 of the prime P(0, 1) have positive polarity. In a particular embodiment of the invention, each color point has a width of one of 40 microns and a height of one of 60 microns. Each buried polar region has a width of one of 6 microns and a height of one of 6 microns. Each discrete field amplification region has a vertical magnification portion width of 5 microns, a vertical magnification portion height of 145 microns, a horizontal magnification portion width of 50 microns, and a horizontal magnification portion height of 5 microns. The horizontal point spacing HDS1 is 15 microns, the vertical point spacing VDS1 is 25 microns, the horizontal discrete field amplification area spacing is HFFARS is 5 microns, and the vertical discrete field amplification area spacing VFFARS is 5 microns.
在本發明之另一實施例中,使用鄰近畫素之切換元件而非具有使用埋置極性區域切換元件來使埋置極性區域偏極化。圖7(e)示出一顯示器730之一部分,顯示器730之該部分使用畫素設計710之畫素P(0,0)、P(1,0)、P(0,1)、及P(1,1)並使用一切換元件列反轉驅動模式。顯示器730可具有數千列,且每一列上具有數千畫素。列與行將以圖7(e)所示之方式從圖7(e)所示之部分連續排列。為清楚起見,在圖7(e)中省略了用於控制切換元件之閘極線及源極線。此外,為更佳地例示每一畫素,將每一畫素之區域陰影化,此陰影在圖7(e)中僅用於例示目的,並不具有功能意義。由於空間限制,色點被標示成CDXY(對照於CD_X_Y)且埋置極性區域被標示成EPRXY(對照於EPR_X_Y)。 In another embodiment of the invention, a switching element of a neighboring pixel is used instead of having a buried polarity region switching element to bias the buried polar region. Figure 7(e) shows a portion of a display 730 that uses the pixels P(0,0), P(1,0), P(0,1), and P of the pixel design 710. 1,1) and use a switching element column inversion drive mode. Display 730 can have thousands of columns with thousands of pixels on each column. The columns and rows will be successively arranged from the portion shown in Fig. 7(e) in the manner shown in Fig. 7(e). For the sake of clarity, the gate lines and source lines for controlling the switching elements are omitted in Figure 7(e). Furthermore, in order to better illustrate each pixel, the area of each pixel is shaded. This shadow is used for illustration purposes only in Figure 7(e) and is not functional. Due to space constraints, the color point is labeled CDXY (cf. CD_X_Y) and the buried polarity region is labeled EPRXY (cf. to EPR_X_Y).
因顯示器730與顯示器720非常相似,故僅詳細闡述其不同之處。舉例而言,顯示器730之畫素係以與顯示器720之畫素相同之方式排列。此外,色點、切換元件、及離散場放大區域之極性係為相同的。因此,與在顯示器720中一樣,在顯示器730中,一畫素P(x,y)在y為偶數時具有一 第一點極性圖案,而在y為奇數時具有一第二點極性圖案。顯示器720與顯示器730間之主要差異在於,顯示器730中之埋置極性區域之極性係自鄰近像素之切換元件提供,而非自顯示器720中所使用之專用埋置極性區域切換元件提供。 Since display 730 is very similar to display 720, only the differences are explained in detail. For example, the pixels of display 730 are arranged in the same manner as the pixels of display 720. In addition, the polarity of the color point, the switching element, and the discrete field amplification region are the same. Thus, as in display 720, in display 730, a pixel P(x, y) has one when y is even. The first point of polarity pattern, and when y is odd, has a second point polarity pattern. The main difference between display 720 and display 730 is that the polarity of the buried polarity region in display 730 is provided from the switching elements of adjacent pixels rather than from the dedicated buried polarity area switching elements used in display 720.
在顯示器730中,一第一畫素與一第二畫素配對,俾使該第一畫素之埋置極性區域耦接至該第二畫素之切換元件,且該第二畫素之埋置極性區域耦接至該第一畫素之切換元件。具體而言,偶數列上之各畫素與位於偶數列上方之奇數列中之畫素配對。因此,在圖7(e)中,畫素P(0,0)係與畫素P(0,1)配對,且畫素P(1,0)係與畫素P(1,1)配對。一般而言,若Y為偶數,則一畫素P(X,Y)與一畫素P(X,Y+1)配對。相反,若Y為奇數,則一畫素P(X,Y)與畫素P(X,1)配對。 In the display 730, a first pixel is paired with a second pixel, and the buried polarity region of the first pixel is coupled to the switching element of the second pixel, and the second pixel is buried. The polar region is coupled to the switching element of the first pixel. Specifically, each pixel on the even column is paired with a pixel in an odd column above the even column. Therefore, in Fig. 7(e), the pixel P(0,0) is paired with the pixel P(0,1), and the pixel P(1,0) is paired with the pixel P(1,1). . In general, if Y is an even number, one pixel P(X, Y) is paired with one pixel P(X, Y+1). Conversely, if Y is an odd number, then one pixel P(X, Y) and pixel P (X, 1) Pairing.
如圖7(e)所示,在顯示器730中,每一埋置極性區域係藉由一導體C_I_J_X_Y(由於空間限制,在圖7(e)中標示為CIJXY)而耦接至配對畫素之一切換元件,其中I、J係表示包含埋置極性區域之畫素(例如,畫素P(I,J)),X係為色分量,且Y係表示畫素中之色點(例如,色點CD_X_Y(在圖7(e)中被縮寫為CDXY))。舉例而言,導體C0112將畫素P(0,1)之埋置極性區域EPR12耦接至畫素P(0,0)之切換元件SE_1。用虛線顯示用於埋置極性區域之導體,以表明該等導體係位於一不同於色點之平面。通常,在一第一平面中使用氧化銦錫形成色點,且在一第二平面中使用一金屬層形成導體。 As shown in FIG. 7(e), in the display 730, each buried polar region is coupled to the paired pixel by a conductor C_I_J_X_Y (labeled as CIJXY in FIG. 7(e) due to space constraints). A switching element, wherein I, J denotes a pixel including a buried polar region (for example, pixel P(I, J)), X is a color component, and Y represents a color point in a pixel (for example, The color point CD_X_Y (abbreviated as CDXY in Fig. 7(e)). For example, the conductor C0112 couples the buried polarity region EPR12 of the pixel P(0, 1) to the switching element SE_1 of the pixel P(0, 0). The conductors used to embed the polar regions are shown in dashed lines to indicate that the isotropic system is in a plane different from the color point. Typically, indium tin oxide is used to form a color point in a first plane, and a metal layer is used to form a conductor in a second plane.
如上所述,在位於奇數列上之畫素中,一第一畫素之埋置極性區域係耦接至位於該第一畫素下方之畫素之切換元件。舉例而言,畫素P(0,1)之埋置極性區域EPR_2_2(在圖7(e)中標示為EPR22)係藉由導體C_0_1_2_2(在圖7(e)中標示為C0122)而耦接至畫素P(0,0)之切換元件SE_2。相似地,畫素P(0,1)之埋置極性區域EPR_2_1(在圖7(e)中標示為EPR21)係藉由導體C_0_1_2_1(在圖7(e)中標示為C0121)而耦接至畫素P(0,0)之切換元件SE_2。一般而言,當J為一奇數時,一導體C_I_J_X_Y將一畫素P(I,J)之埋置極性區域EPR_X_Y耦接至畫素P(I,J1)之切換元件SE_X。 As described above, in a pixel located on an odd column, a buried polarity region of a first pixel is coupled to a switching element of a pixel located below the first pixel. For example, the buried polarity region EPR_2_2 of the pixel P(0,1) (labeled as EPR22 in FIG. 7(e)) is coupled by the conductor C_0_1_2_2 (labeled as C0122 in FIG. 7(e)). Switching element SE_2 to pixel P(0,0). Similarly, the buried polarity region EPR_2_1 of the pixel P(0,1) (labeled EPR21 in FIG. 7(e)) is coupled to the conductor C_0_1_2_1 (labeled C0121 in FIG. 7(e)). Switching element SE_2 of pixel P(0,0). In general, when J is an odd number, a conductor C_I_J_X_Y couples the buried polarity region EPR_X_Y of one pixel P(I, J) to the switching element SE_X of the pixel P(I, J1).
在位於偶數列上之畫素中,一第一畫素之埋置極性區域係耦接至位於該第一畫素上方之畫素之切換元件。舉例而言,畫素P(0,0)之埋置極性區 域EPR_2_2(在圖7(e)中標示為EPR22)係藉由導體C_0_0_2_2(在圖7(e)中標示為C0022)而耦接至畫素P(0,1)之切換元件SE_2。相似地,畫素P(0,0)之埋置極性區域EPR_2_1(在圖7(e)中標示為EPR21)係藉由導體C_0_0_2_1(在圖7(e)中標示為C0021)而耦接至畫素P(0,1)之切換元件SE_2。一般而言,當J為一偶數時,一導體C_I_J_X_Y將一畫素P(I,J)之埋置極性區域EPR_X_Y耦接至畫素P(I,J+1)之切換元件SE_X。 In a pixel located on an even column, a buried polar region of a first pixel is coupled to a switching element of a pixel located above the first pixel. For example, the buried polar region of pixel P(0,0) The field EPR_2_2 (labeled EPR22 in Fig. 7(e)) is coupled to the switching element SE_2 of the pixel P(0, 1) by the conductor C_0_0_2_2 (labeled C0022 in Fig. 7(e)). Similarly, the buried polarity region EPR_2_1 of the pixel P(0,0) (labeled EPR21 in FIG. 7(e)) is coupled to the conductor C_0_0_2_1 (labeled as C0021 in FIG. 7(e)). Switching element SE_2 of pixel P(0,1). In general, when J is an even number, a conductor C_I_J_X_Y couples the buried polarity region EPR_X_Y of one pixel P(I, J) to the switching element SE_X of the pixel P(I, J+1).
如上所述,在顯示器730中,鄰近之畫素列具有相反極性。因此,藉由自鄰近列之畫素中之切換元件提供極性至埋置極性區域(如上所述),會使埋置極性區域之極性不同於色點之極性。此不同之極性用於增強色點中之離散場,因此增強多區域垂直配向操作並減輕顯示器730中之觸碰雲紋效應。 As noted above, in display 730, adjacent pixel columns have opposite polarities. Thus, by providing a polarity from the switching elements in adjacent pixels to the buried polarity region (as described above), the polarity of the buried polarity region is different from the polarity of the color point. This different polarity is used to enhance the discrete fields in the color point, thus enhancing multi-region vertical alignment operation and mitigating the touch moiré effect in display 730.
圖7(f)顯示本發明之另一實施例,其中埋置極性區域係自離散場放大區域接收極性。具體而言,圖7(f)示出一顯示器740之一部分,顯示器740之該部分係使用畫素設計710之畫素P(0,0)、P(1,0)、P(0,1)、及P(1,1)並使用一切換元件列反轉驅動模式。顯示器740可具有數千列,且每一列上具有數千畫素。列與行將以圖7(f)所示之方式從圖7(f)所示之部分連續排列。為清楚起見,在圖7(f)中省略了用於控制切換元件之閘極線及源極線。此外,為更佳地例示每一畫素,將每一畫素之區域陰影化,此陰影在圖7(f)中僅用於例示目的,並不具有功能意義。由於空間限制,色點被標示成CDXY(對照於CD_X_Y),且埋置極性區域被標示成EPRXY(對照於EPR_X_Y)。 Figure 7(f) shows another embodiment of the invention in which the buried polar region receives polarity from the discrete field amplification region. Specifically, FIG. 7(f) shows a portion of a display 740 that uses pixels P(0,0), P(1,0), P(0,1) of the pixel design 710. ) and P(1,1) and use a switching element column inversion driving mode. Display 740 can have thousands of columns with thousands of pixels on each column. The columns and rows will be successively arranged from the portion shown in Fig. 7(f) in the manner shown in Fig. 7(f). For the sake of clarity, the gate lines and source lines for controlling the switching elements are omitted in Figure 7(f). Furthermore, in order to better illustrate each pixel, the area of each pixel is shaded, and this shadow is used for illustration purposes only in FIG. 7(f) and does not have a functional meaning. Due to space constraints, the color point is labeled CDXY (cf. CD_X_Y) and the buried polarity region is labeled EPRXY (cf. EPR_X_Y).
因顯示器740與顯示器720非常相似,故僅詳細闡述其不同之處。舉例而言,顯示器740之畫素係以與顯示器720之畫素相同之方式排列。此外,色點、切換元件、及離散場放大區域之極性係為相同的。因此,與在顯示器720中一樣,在顯示器740中,一畫素P(x,y)在y為偶數時具有一第一點極性圖案,而在y為奇數時具有一第二點極性圖案。顯示器720與顯示器740間之主要差異在於,顯示器740中之埋置極性區域之極性係自離散場放大區域提供,而非自顯示器720中所使用之專用埋置極性區域切換元件提供。 Since display 740 is very similar to display 720, only the differences are explained in detail. For example, the pixels of display 740 are arranged in the same manner as the pixels of display 720. In addition, the polarity of the color point, the switching element, and the discrete field amplification region are the same. Thus, as in display 720, in display 740, a pixel P(x,y) has a first dot polarity pattern when y is even and a second dot polarity pattern when y is odd. The main difference between display 720 and display 740 is that the polarity of the buried polarity region in display 740 is provided from the discrete field amplification region rather than from the dedicated buried polarity region switching element used in display 720.
具體而言,如圖7(f)所示,在顯示器740中,每一埋置極性區域係耦接 至最近之離散場放大區域。具體而言,一畫素P(I,J)之一埋置極性區域EPR_X_Y係藉由一導體C_I_J_X_Y(由於空間限制,在圖7(f)中標示為CIJXY)而耦接至離散場放大區域FFAR_X,其中I、J係表示畫素(例如,畫素P(I,J)),X係為色分量,Y係表示畫素中之色點(例如,色點CD_X_Y(在圖7(f)中被縮寫為CDXY))。舉例而言,導體C0112將畫素P(0,1)之埋置極性區域EPR12耦接至畫素P(0,1)之離散場放大區域FFAR_1(在圖7(f)中未具體標示)。用虛線顯示用於埋置極性區域之導體,以表明該等導體係位於一不同於色點之平面。通常,在一第一平面中使用氧化銦錫形成色點及離散場放大區域,且在一第二平面中使用一金屬層形成導體。因此,使用一通路(via,標示為V)來將離散場放大區域連接至導體。在圖7(f)中,離散場放大區域係耦接至一相鄰畫素之一切換元件,如上文參照圖7(d)所述。然而,在本發明之其他實施例中,離散場放大區域可使用其他方法(例如,專用離散場放大區域切換元件)來接收極性。 Specifically, as shown in FIG. 7(f), in the display 740, each buried polar region is coupled To the nearest discrete field magnification area. Specifically, one of the pixels P(I, J) embedding the polar region EPR_X_Y is coupled to the discrete field amplification region by a conductor C_I_J_X_Y (labeled as CIJXY in FIG. 7(f) due to space limitation) FFAR_X, where I and J represent pixels (for example, pixels P(I, J)), X is a color component, and Y represents a color point in a pixel (for example, a color point CD_X_Y (in Figure 7 (f ) is abbreviated as CDXY)). For example, the conductor C0112 couples the buried polarity region EPR12 of the pixel P(0, 1) to the discrete field amplification region FFAR_1 of the pixel P(0, 1) (not specifically labeled in FIG. 7(f)) . The conductors used to embed the polar regions are shown in dashed lines to indicate that the isotropic system is in a plane different from the color point. Typically, indium tin oxide is used in a first plane to form color points and discrete field amplification regions, and a metal layer is used to form conductors in a second plane. Therefore, a pass (labeled V) is used to connect the discrete field amplification region to the conductor. In FIG. 7(f), the discrete field amplification region is coupled to one of the adjacent pixels, as described above with reference to FIG. 7(d). However, in other embodiments of the invention, the discrete field amplification region may use other methods (eg, dedicated discrete field amplification region switching elements) to receive polarity.
如上所述,離散場放大區域具有相較於色點相反之一極性。因此,藉由自離散場放大區域提供極性至埋置極性區域,會使埋置極性區域之極性不同於色點之極性。此不同之極性用於增強色點中之離散場,因此增強多區域垂直配向操作並降低顯示器740中之觸碰雲紋效應。 As described above, the discrete field amplification region has one polarity opposite to the color point. Therefore, by providing a polarity from the discrete field amplification region to the buried polarity region, the polarity of the buried polarity region is different from the polarity of the color point. This different polarity is used to enhance the discrete fields in the color point, thus enhancing multi-region vertical alignment operation and reducing the touch moiré effect in display 740.
如上所述,在許多應用中期望具有一更高之畫素密度。顯示器畫素密度愈高,其中之畫素愈小。光學透射率係正比於開口率(aperture ratio),開口率係為色點總面積對色分量面積之比率。一般而言,顯示器畫素密度愈高,其中之開口率愈小。亦需要在一正常畫素密度中增大開口率,以提高顯示器之亮度。因此,在本發明之某些實施例中,一高開口率係藉由組合埋置電極與離散場放大器而達成。圖8(a)-8(b)顯示依據本發明某些實施例其中每一色分量具有多個色點之一畫素設計,該畫素設計包含埋置極性區域及一埋置離散場放大器。具體而言,圖8(a)及圖8(b)顯示一畫素設計810(如下所述被標示為810+及810-)之不同點極性圖案,畫素設計810常常用於具有一切換元件列反轉驅動模式之顯示器中。在實際操作中,一畫素將在每一影像頁框之間在一第一點極性圖案與一第二點極性圖案之間切換。 As noted above, it is desirable to have a higher pixel density in many applications. The higher the display pixel density, the smaller the pixels. The optical transmittance is proportional to the aperture ratio, which is the ratio of the total area of the color point to the area of the color component. In general, the higher the display pixel density, the smaller the aperture ratio. It is also necessary to increase the aperture ratio in a normal pixel density to increase the brightness of the display. Thus, in some embodiments of the invention, a high aperture ratio is achieved by combining buried electrodes with discrete field amplifiers. 8(a)-8(b) show a pixel design in which each color component has a plurality of color points, including a buried polarity region and a buried discrete field amplifier, in accordance with some embodiments of the present invention. Specifically, FIGS. 8(a) and 8(b) show different dot polarity patterns of a pixel design 810 (labeled as 810+ and 810- as described below), and the pixel design 810 is often used to have a switch. The component column is in the display of the reverse drive mode. In actual operation, a pixel will switch between a first dot polarity pattern and a second dot polarity pattern between each image frame.
與畫素設計710一樣,畫素設計810具有三個色分量CC_1、CC_2及CC_3(在圖8(a)-8(b)中未標示出)。該三個色分量其中每一者包含二色點。 畫素設計810亦針對每一色分量包含一切換元件(被表示為SE_1、SE_2及SE_3)以及包含一埋置離散場放大器EFFA_1。切換元件SE_1、SE_2、及SE_3係排列成一列。畫素設計810之色點、埋置極性區域、及切換元件係與畫素設計710非常相似。然而,如下所述,畫素設計810與畫素設計710中之埋置極性區域之形成彼此不同。此外,各色分量被放置得彼此更靠近,乃因於畫素設計810中未使用畫素設計710中之離散場放大區域。 Like the pixel design 710, the pixel design 810 has three color components CC_1, CC_2, and CC_3 (not shown in Figures 8(a)-8(b)). Each of the three color components includes a two color point. The pixel design 810 also includes a switching element (denoted as SE_1, SE_2, and SE_3) for each color component and a buried discrete field amplifier EFFA_1. The switching elements SE_1, SE_2, and SE_3 are arranged in a row. The color point of the pixel design 810, the buried polarity region, and the switching element are very similar to the pixel design 710. However, as described below, the formation of the buried polar regions in the pixel design 810 and the pixel design 710 are different from each other. In addition, the color components are placed closer to each other because the discrete field amplification regions in the pixel design 710 are not used in the pixel design 810.
畫素設計810之第一色分量CC_1具有二色點CD_1_1及CD_1_2。色點CD_1_1與CD_1_2形成一行,並以一垂直點間距VDS1間隔開。換言之,色點CD_1_1與CD_1_2係水平地配向且以垂直點間距VDS1垂直地間隔開。此外,色點CD_1_1與CD_1_2係垂直地錯開垂直點偏移量VDO1,垂直點偏移量VDO1係等於垂直點間距VDS1加上色點高度CDH。切換元件SE_1係位於色點CD_1_1與CD_1_2之間,俾使色點CD_1_1位於該列切換元件之一第一側,而色點CD_1_2位於該列切換元件之一第二側。切換元件SE_1係耦接至色點CD_1_1及CD_1_2之電極,以控制色點CD_1_1及CD_1_2之電壓極性及電壓大小。 The first color component CC_1 of the pixel design 810 has two color points CD_1_1 and CD_1_2. The color points CD_1_1 and CD_1_2 form a line and are spaced apart by a vertical dot pitch VDS1. In other words, the color points CD_1_1 and CD_1_2 are horizontally aligned and vertically spaced apart by the vertical dot pitch VDS1. Further, the color point CD_1_1 and the CD_1_2 are vertically shifted by the vertical dot offset VDO1, and the vertical dot offset VDO1 is equal to the vertical dot pitch VDS1 plus the color point height CDH. The switching element SE_1 is located between the color points CD_1_1 and CD_1_2 such that the color point CD_1_1 is located on a first side of the column switching element, and the color point CD_1_2 is located on a second side of the column switching element. The switching element SE_1 is coupled to the electrodes of the color points CD_1_1 and CD_1_2 to control the voltage polarity and voltage of the color points CD_1_1 and CD_1_2.
色分量CC_1之每一色點包含一埋置極性區域,埋置極性區域將增強離散場,因此增強多區域垂直配向操作並將色點中之任何觸碰雲紋效應最小化。具體而言,色點CD_1_1及CD_1_2分別包含埋置極性區域EPR_1_1及EPR_1_2。如圖8(a)所示,埋置極性區域EPR_1_1及EPR_1_2係分別居中於色點CD_1_1及CD_1_2中。在畫素設計810中,圖6(a)-6(b)中所示埋置導體技術被擴展,並與畫素設計710(圖7(a)-7(b))中所使用之離散場放大區域相結合。具體而言,在畫素設計810中,一埋置離散場放大器EFFA_1係用於整個畫素。以下將闡述埋置離散場放大器EFFA_1。 Each color point of color component CC_1 includes a buried polar region that will enhance the discrete field, thereby enhancing multi-region vertical alignment operation and minimizing any touch moiré effects in the color point. Specifically, the color points CD_1_1 and CD_1_2 respectively include buried polarity areas EPR_1_1 and EPR_1_2. As shown in FIG. 8(a), the buried polar regions EPR_1_1 and EPR_1_2 are respectively centered in the color points CD_1_1 and CD_1_2. In the pixel design 810, the buried conductor technique shown in Figures 6(a)-6(b) is extended and discretely used in the pixel design 710 (Figs. 7(a)-7(b)). The field amplification area is combined. Specifically, in the pixel design 810, a buried discrete field amplifier EFFA_1 is used for the entire pixel. The buried discrete field amplifier EFFA_1 will be explained below.
為清楚起見,將從一使用者觀察一被保持於一垂直位置之顯示器之角度來闡述一畫素設計之各個部分之相對位置。因此,舉例而言,在圖8(a)中,色點CD_1_1係被闡述成位於切換元件SE_1上方,且色點CD_1_2係被闡述成位於切換元件SE_1下方。色點CD_1_1係位於色點CD_2_1左側,相反,色點CD_3_1係位於色點CD_2_1右側。此外,埋置離散場放大器係被闡述成位於色點後面。相反,色點係被闡述成位於埋置離散場放大器前面。 For the sake of clarity, the relative position of the various portions of a pixel design will be elucidated from the perspective of a user viewing a display held in a vertical position. Thus, for example, in Figure 8(a), the color point CD_1_1 is illustrated as being located above the switching element SE_1, and the color point CD_1_2 is illustrated as being located below the switching element SE_1. The color point CD_1_1 is located on the left side of the color point CD_2_1. On the contrary, the color point CD_3_1 is located on the right side of the color point CD_2_1. In addition, the buried discrete field amplifier is illustrated as being located behind the color point. Instead, the color point is illustrated as being located in front of the buried discrete field amplifier.
畫素設計810之第二色分量CC_2具有二色點CD_2_1及CD_2_2。色點CD_2_1與CD_2_2形成一第二行,並以一垂直點間距VDS1間隔開。因此,色點CD_2_1與CD_2_2係水平地配向並以垂直點間距VDS1垂直地間隔開。切換元件SE_2係位於色點CD_2_1與CD_2_2之間,俾使色點CD_2_1位於切換元件列之第一側,而色點CD_2_2位於切換元件列之一第二側。切換元件SE_2係耦接至色點CD_2_1及CD_2_2之電極,以控制色點CD_2_1及CD_2_2之電壓極性及電壓大小。第二色分量CC_2係與第一色分量CC_1垂直地配向,並以一水平點間距HDS1與色分量CC_1間隔開,因此色分量CC_2與CC_1係水平地錯開一水平點偏移量HDO1,水平點偏移量HDO1係等於水平點間距HDS1加上色點寬度CDW。具體關於色點而言,色點CD_2_1與色點CD_1_1係垂直地配向並以水平點間距HDS1水平地間隔開。相似地,色點CD_2_2與色點CD_1_2係垂直地配向並以水平點間距HDS1水平地間隔開。因此,色點CD_1_1與色點CD_2_1形成一第一列色點,且色點CD_1_2與色點CD_2_2形成一第二列色點。與色點CD_1_1及CD_1_2一樣,色點CD_2_1及CD_2_2分別包含埋置極性區域EPR_2_1及EPR_2_2。畫素設計810之水平點間距HDS1顯著小於畫素設計710之水平點間距HDS1。因此,在具有相同大小之色分量之情況下,畫素設計810中之色點之尺寸可大於畫素設計710中之色點之尺寸。因此畫素設計810之開口率大於畫素設計710之開口率。 The second color component CC_2 of the pixel design 810 has two color points CD_2_1 and CD_2_2. The color points CD_2_1 and CD_2_2 form a second line and are spaced apart by a vertical dot pitch VDS1. Therefore, the color points CD_2_1 and CD_2_2 are horizontally aligned and vertically spaced apart by the vertical dot pitch VDS1. The switching element SE_2 is located between the color points CD_2_1 and CD_2_2 such that the color point CD_2_1 is located on the first side of the switching element column, and the color point CD_2_2 is located on the second side of one of the switching element columns. The switching element SE_2 is coupled to the electrodes of the color points CD_2_1 and CD_2_2 to control the voltage polarity and voltage of the color points CD_2_1 and CD_2_2. The second color component CC_2 is vertically aligned with the first color component CC_1, and is spaced apart by a horizontal dot pitch HDS1 and the color component CC_1. Therefore, the color components CC_2 and CC_1 are horizontally shifted by a horizontal point offset HDD1, the horizontal point. The offset HDD1 is equal to the horizontal dot pitch HDS1 plus the color dot width CDW. Specifically, regarding the color point, the color point CD_2_1 and the color point CD_1_1 are vertically aligned and horizontally spaced by the horizontal dot pitch HDS1. Similarly, the color point CD_2_2 is vertically aligned with the color point CD_1_2 and horizontally spaced by the horizontal dot pitch HDS1. Therefore, the color point CD_1_1 and the color point CD_2_1 form a first column color point, and the color point CD_1_2 and the color point CD_2_2 form a second column color point. Like the color points CD_1_1 and CD_1_2, the color points CD_2_1 and CD_2_2 respectively contain the buried polar regions EPR_2_1 and EPR_2_2. The horizontal point spacing HDS1 of the pixel design 810 is significantly smaller than the horizontal point spacing HDS1 of the pixel design 710. Thus, the color point in the pixel design 810 can be larger than the color point in the pixel design 710 in the case of color components of the same size. Therefore, the aperture ratio of the pixel design 810 is larger than the aperture ratio of the pixel design 710.
相似地,畫素810之第三色分量CC_3具有二色點CD_3_1及CD_3_2。色點CD_3_1與CD_3_2形成一第三行,並以一垂直點間距VDS1間隔開。因此,色點CD_3_1與CD_3_2係水平地配向並以垂直點間距VDS1垂直地間隔開。切換元件SE_3係位於色點CD_3_1與CD_3_2之間,俾使色點CD_3_1位於該列切換元件之第一側,而色點CD_3_2位於該列切換元件列之一第二側。切換元件SE_3係耦接至色點CD_3_1及CD_3_2之電極,以控制色點CD_3_1及CD_3_2之電壓極性及電壓大小。第三色分量CC_3係與第二色分量CC_2垂直地配向,並以水平點間距HDS1與色分量CC_2間隔開,因此色分量CC_3與CC_2係水平地錯開一水平點偏移量HDO1。具體關於色點而言,色點CD_3_1與色點CD_2_1係垂直地配向並以水平點間距HDS1水平地間隔開。相似地,色點CD_3_2與色點CD_2_2垂直地配向 並以水平點間距HDS1水平地間隔開。因此,色點CD_3_1係位於第一列色點上,且色點CD_3_2係位於第二色點列上。與色點CD_1_1及CD_1_2一樣,色點CD_3_1及CD_3_2分別包含埋置極性區域EPD_3_1及EPR_3_2。 Similarly, the third color component CC_3 of the pixel 810 has two color points CD_3_1 and CD_3_2. The color points CD_3_1 and CD_3_2 form a third line and are spaced apart by a vertical dot pitch VDS1. Therefore, the color points CD_3_1 and CD_3_2 are horizontally aligned and vertically spaced apart by the vertical dot pitch VDS1. The switching element SE_3 is located between the color points CD_3_1 and CD_3_2 such that the color point CD_3_1 is located on the first side of the column switching element, and the color point CD_3_2 is located on the second side of one of the column switching element columns. The switching element SE_3 is coupled to the electrodes of the color points CD_3_1 and CD_3_2 to control the voltage polarity and voltage of the color points CD_3_1 and CD_3_2. The third color component CC_3 is vertically aligned with the second color component CC_2, and is spaced apart from the color component CC_2 by the horizontal dot pitch HDS1, so that the color components CC_3 and CC_2 are horizontally shifted by a horizontal dot offset amount HDO1. Specifically, regarding the color point, the color point CD_3_1 and the color point CD_2_1 are vertically aligned and horizontally spaced by the horizontal dot pitch HDS1. Similarly, the color point CD_3_2 is vertically aligned with the color point CD_2_2 And horizontally spaced by the horizontal point spacing HDS1. Therefore, the color point CD_3_1 is located on the first column color point, and the color point CD_3_2 is located on the second color point column. Like the color points CD_1_1 and CD_1_2, the color points CD_3_1 and CD_3_2 respectively contain the buried polarity areas EPD_3_1 and EPR_3_2.
為清楚起見,以具有相同色點高度CDH之色點來例示畫素設計810之各色點。然而,本發明之某些實施例可包含具有不同色點高度之色點。舉例而言,在本發明之一實施例(其為畫素設計810之一變體)中,色點CD_1_1、CD_2_1、及CD_3_1之色點高度小於色點CD_1_2、CD_2_2、及CD_3_2之色點高度。此外,在本發明之許多實施例中,色點可具有不同形狀。 For the sake of clarity, the color points of the pixel design 810 are illustrated with color points having the same color point height CDH. However, certain embodiments of the invention may include color points having different color point heights. For example, in one embodiment of the present invention, which is a variant of the pixel design 810, the color point heights of the color points CD_1_1, CD_2_1, and CD_3_1 are smaller than the color point heights of the color points CD_1_2, CD_2_2, and CD_3_2. . Moreover, in many embodiments of the invention, the color points can have different shapes.
相較於畫素設計710,畫素設計810包含一埋置離散場放大器EFFA_1而非包含離散場放大區域以及位於埋置極性區域中之埋置導體。在畫素設計810中,埋置離散場放大器EFFA_1係為一埋置導體,該埋置導體係位於色點後面,但在色點之左側、右側、上方、及下方延伸超過色點。因此,畫素設計810之色點係位於埋置離散場放大器EFFA_1前面。具體而言,埋置離散場放大器延伸超過色點CD_3_1及CD_3_2之右邊緣達一水平埋置電極延伸距離HEEED1。儘管圖中未具體標示,然而埋置離散場放大器EFFA_1亦延伸超過色點CD_1_1及CD_1_2之左邊緣達水平埋置電極延伸距離HEEED1。相似地,在畫素設計810中,埋置離散場放大器EFFA_1延伸至色點CD_1_1、CD_2_1、及CD_3_1上方一垂直埋置電極延伸距離VEEED1,且亦延伸於色點CD_1_2、CD_2_2、及CD_3_2下方。 In contrast to the pixel design 710, the pixel design 810 includes a buried discrete field amplifier EFFA_1 instead of a buried conductor that includes a discrete field amplification region and is located in the buried polarity region. In the pixel design 810, the embedded discrete field amplifier EFFA_1 is a buried conductor that is located behind the color point but extends beyond the color point on the left, right, top, and bottom of the color point. Therefore, the color point of the pixel design 810 is located in front of the buried discrete field amplifier EFFA_1. Specifically, the buried discrete field amplifier extends beyond the right edge of the color points CD_3_1 and CD_3_2 to a horizontal buried electrode extension distance HEEED1. Although not specifically shown in the figure, the buried discrete field amplifier EFFA_1 also extends beyond the left edge of the color points CD_1_1 and CD_1_2 to the horizontal buried electrode extension distance HEEED1. Similarly, in the pixel design 810, the buried discrete field amplifier EFFA_1 extends to a vertical buried electrode extension distance VEEED1 above the color points CD_1_1, CD_2_1, and CD_3_1, and also extends below the color points CD_1_2, CD_2_2, and CD_3_2.
使用「+」及「-」符號來顯示色點、埋置離散場放大器、及切換元件之極性。因此,在其中顯示畫素設計810+之正的點極性圖案之圖8(a)中,所有切換元件(即,切換元件SE_1、SE_2及SE_3)及所有色點(即,色點CD_1_1、CD_1_2、CD_2_1、CD_2_2、CD_3_1、及CD_3_2)具有正極性。然而,埋置離散場放大器EFFA_1具有負極性。因此,埋置極性區域EPR_1_1、EPR_2_1、及EPR_3_1亦具有負極性(由於空間限制,在圖8(a)及圖8(b)中未表示埋置極性區域之極性)。 Use the "+" and "-" symbols to display the color point, the embedded discrete field amplifier, and the polarity of the switching components. Therefore, in FIG. 8(a) in which the positive dot pattern of the pixel design 810+ is displayed, all the switching elements (ie, the switching elements SE_1, SE_2, and SE_3) and all the color points (ie, the color points CD_1_1, CD_1_2) , CD_2_1, CD_2_2, CD_3_1, and CD_3_2) have positive polarity. However, the buried discrete field amplifier EFFA_1 has a negative polarity. Therefore, the buried polar regions EPR_1_1, EPR_2_1, and EPR_3_1 also have a negative polarity (the polarity of the buried polar region is not shown in FIGS. 8(a) and 8(b) due to space limitations).
圖8(b)顯示具有負的點極性圖案之畫素設計810。對於負的點極性圖案,所有切換元件(即,切換元件SE_1、SE_2及SE_3)及所有色點(即,色點CD_1_1、CD_1_2、CD_2_1、CD_2_2、CD_3_1、及CD_3_2)具有負 極性。然而,埋置離散場放大器EFFA_1具有正極性。因此,埋置極性區域EPR_1_1、EPR_2_1、及EPR_3_1亦具有正極性。 Figure 8(b) shows a pixel design 810 with a negative dot polarity pattern. For a negative dot polarity pattern, all switching elements (ie, switching elements SE_1, SE_2, and SE_3) and all color points (ie, color points CD_1_1, CD_1_2, CD_2_1, CD_2_2, CD_3_1, and CD_3_2) have negative polarity. However, the buried discrete field amplifier EFFA_1 has a positive polarity. Therefore, the buried polar regions EPR_1_1, EPR_2_1, and EPR_3_1 also have positive polarity.
每一色點中之離散場被放大,乃因色點之邊緣附近呈現不同電壓。畫素設計810利用埋置離散場放大器來增強並穩定液晶結構中之多區域分割之形成。具體而言,一色點之邊緣係位於埋置離散場放大器EFFA_1之一部分前面。若埋置離散場放大器EFFA_1上之電壓不同於色點之電壓,則色點與埋置離散場放大器EFFA_1之交疊放置會放大色點之離散場。若色點與埋置離散場放大器具有相反極性,則會更大程度地放大離散場。然而,若埋置離散場放大器係被保持於共同電壓(即,中性極性,參見圖9(a)-9(c)),亦可良好地放大色點之離散場。一般而言,偏極化組件之極性係被指定成使一第一極性之一色點位於一第二極性之一埋置離散場放大器前面,該第二極性之埋置離散場放大器延伸超過該色點之邊緣。舉例而言,對於畫素設計810(圖8(a))之正的點極性圖案,色點CD_2_2具有正極性。然而,埋置離散場放大器EFFA_1具有一負極性。因此,色點CD_2_2之離散場被放大。 The discrete fields in each color point are magnified because of the different voltages appearing near the edges of the color points. The pixel design 810 utilizes a buried discrete field amplifier to enhance and stabilize the formation of multiple region segments in the liquid crystal structure. Specifically, the edge of a color point is located in front of a portion of the buried discrete field amplifier EFFA_1. If the voltage on the buried discrete field amplifier EFFA_1 is different from the voltage at the color point, the overlapping of the color point and the buried discrete field amplifier EFFA_1 will amplify the discrete field of the color point. If the color point has the opposite polarity to the buried discrete field amplifier, the discrete field will be amplified to a greater extent. However, if the buried discrete field amplifier is maintained at a common voltage (ie, neutral polarity, see Figures 9(a)-9(c)), the discrete fields of the color points can be well magnified. In general, the polarity of the polarization component is specified such that a color point of a first polarity is located in front of a buried discrete field amplifier of a second polarity, and the buried discrete field amplifier of the second polarity extends beyond the color The edge of the point. For example, for the positive dot polarity pattern of the pixel design 810 (Fig. 8(a)), the color point CD_2_2 has a positive polarity. However, the buried discrete field amplifier EFFA_1 has a negative polarity. Therefore, the discrete field of the color point CD_2_2 is amplified.
因畫素設計810中所有切換元件具有相同極性且埋置離散場放大器應具有一不同極性,故離散場放大器係由一外部極性源(即,來自畫素設計810之特定畫素外之一極性源)驅動。可依據本發明之不同實施例來使用各種相反極性源。舉例而言,可使用特定的埋置離散場放大器切換元件或亦可使用鄰近畫素之具有一相反點極性之切換元件來驅動埋置離散場放大器。在圖8(a)-8(b)之實施例中,亦可使用鄰近畫素之具有一相反點極性之切換元件來驅動離散場放大區域。因此,畫素設計810包含一導體812以幫助離散場放大區域耦接至其他畫素中之切換元件。具體而言,一當前畫素之導體812會將埋置離散場放大器耦接至位於當前畫素上方之一畫素之切換元件SE_1(參見圖8(e))。與切換元件之連接將經由位於當前畫素上方之畫素之色點之電極達成。該等連接更佳地顯示於圖8(e)中,圖8(e)顯示使用畫素設計810之顯示器820之一部分。 Since all of the switching elements in the pixel design 810 have the same polarity and the buried discrete field amplifiers should have a different polarity, the discrete field amplifiers are derived from an external polar source (ie, one of the polar elements from the pixel design 810). Source) driver. Various sources of opposite polarity can be used in accordance with various embodiments of the present invention. For example, a particular buried discrete field amplifier switching element can be used or a buried pixel with a reverse polarity can be used to drive the buried discrete field amplifier. In the embodiment of Figures 8(a)-8(b), the discrete field amplification regions can also be driven using switching elements of adjacent pixels having opposite polarity. Thus, the pixel design 810 includes a conductor 812 to assist in coupling the discrete field amplification regions to the switching elements in other pixels. Specifically, a current pixel conductor 812 couples the buried discrete field amplifier to a switching element SE_1 located above one pixel of the current pixel (see FIG. 8(e)). The connection to the switching element is achieved via the electrode of the color point of the pixel above the current pixel. These connections are better shown in Figure 8(e), and Figure 8(e) shows a portion of the display 820 using the pixel design 810.
圖8(c)顯示沿A-A線(圖8(b))截取之畫素設計810之橫截面,其包含色點CD_1_1、CD_2_1、CD_3_1、埋置極性區域EPR_1_1、EPR_2_1、及EPR_3_1、以及埋置離散場放大器EFFA_1。圖8(c)係用以說明色點與埋 置離散場放大器之相對放置。因此,為清楚起見,可能存在於本發明各實施例中之某些層及組件未顯示於圖8(c)中。此外,使用畫素設計810之一顯示器中之其他層及組件可能不存在於圖8(c)所示畫素設計820之區域中。如圖8(c)所示,使用畫素設計820之一顯示器包含一下層透明基板821。透明基板821上形成有一第一鈍化層823。儘管圖未示出,然而一第一金屬層常常形成於基板821上且通常由第一鈍化層823覆蓋。然而,第一金屬層未用於圖8(c)所示畫素設計820之部分中。鈍化層823係使用一透明鈍化材料(例如,介電層SiNx)製成。一般而言,一層透明導電材料(例如ITO、或ZnO(氧化鋅))係形成於鈍化層823之上並被蝕刻以形成埋置離散場放大器EFFA_1。在本發明之某些實施例中,可在鈍化層823上形成一第二金屬層。一第二鈍化層827係形成於埋置離散場放大器EFFA_1之上且亦填充由用於形成埋置離散場放大器EFFA_1之蝕刻製造所留下之間隙。圖8(c)所示畫素設計820之特定部分包含埋置極性區域EPR_1_1、EPR_2_1、及EPR_3_1,埋置極性區域EPR_1_1、EPR_2_1、及EPR_3_1係藉由蝕刻穿過色點及鈍化層827之中間而形成。因此,鈍化層827在圖8(c)中顯現為多個部分。色點係形成於鈍化層827之頂部上。通常,色點係藉由在第二鈍化層827上沈積一層導電材料(例如,ITO或IZO)而形成。隨後,圖案化並蝕刻導電層以形成色點。因此,如圖8(c)所示,色點CD_1_1、CD_2_1、及CD_3_1係位於第二鈍化層827之頂部上。因圖8(c)之透視圖係於埋置極性區域所在之處截取,故色點CD_1_1、CD_2_1、及CD_3_1在圖8(c)中係顯現為二分開之部分。然而,色點之實際形狀係為一正方形形狀,該正方形形狀於中心處具有一正方形孔,如圖8(a)所示。在本發明之某些實施例中,埋置離散場放大器係形成於透明基板821上。 Figure 8(c) shows a cross section of the pixel design 810 taken along line AA (Fig. 8(b)), including color points CD_1_1, CD_2_1, CD_3_1, buried polarity regions EPR_1_1, EPR_2_1, and EPR_3_1, and embedding Discrete field amplifier EFFA_1. Figure 8 (c) is used to illustrate the color point and bury Place the relative placement of the discrete field amplifiers. Thus, for clarity, certain layers and components that may be present in various embodiments of the invention are not shown in Figure 8(c). Moreover, other layers and components in the display using one of the pixel designs 810 may not be present in the area of the pixel design 820 shown in Figure 8(c). As shown in FIG. 8(c), one of the displays using the pixel design 820 includes a lower transparent substrate 821. A first passivation layer 823 is formed on the transparent substrate 821. Although not shown, a first metal layer is often formed on the substrate 821 and is typically covered by a first passivation layer 823. However, the first metal layer is not used in the portion of the pixel design 820 shown in Figure 8(c). Passivation layer 823 is made using a transparent passivation material (eg, dielectric layer SiNx). In general, a layer of transparent conductive material (eg, ITO, or ZnO (zinc oxide)) is formed over passivation layer 823 and etched to form buried discrete field amplifier EFFA_1. In some embodiments of the invention, a second metal layer can be formed over passivation layer 823. A second passivation layer 827 is formed over the buried discrete field amplifier EFFA_1 and also fills the gap left by the etch fabrication used to form the buried discrete field amplifier EFFA_1. A specific portion of the pixel design 820 shown in FIG. 8(c) includes buried polarity regions EPR_1_1, EPR_2_1, and EPR_3_1, and the buried polarity regions EPR_1_1, EPR_2_1, and EPR_3_1 are etched through the middle of the color point and the passivation layer 827. And formed. Therefore, the passivation layer 827 appears as a plurality of portions in FIG. 8(c). A color dot is formed on top of the passivation layer 827. Generally, the color point is formed by depositing a layer of a conductive material (for example, ITO or IZO) on the second passivation layer 827. Subsequently, the conductive layer is patterned and etched to form a color point. Therefore, as shown in FIG. 8(c), the color points CD_1_1, CD_2_1, and CD_3_1 are located on the top of the second passivation layer 827. Since the perspective view of Fig. 8(c) is taken at the place where the buried polar region is located, the color points CD_1_1, CD_2_1, and CD_3_1 appear as two separate portions in Fig. 8(c). However, the actual shape of the color point is a square shape having a square hole at the center as shown in Fig. 8(a). In some embodiments of the invention, a buried discrete field amplifier is formed on a transparent substrate 821.
圖8(d)示出顯示器840之一部分,顯示器840之該部分具有畫素設計810之畫素P(0,0)、P(1,0)、P(0,1)、及P(1,1)。顯示器840係使用一切換元件列反轉驅動模式。顯示器840可具有數千列,且每一列上具有數千畫素。列與行將以圖8(d)所示之方式從圖8(d)所示之部分連續排列。為清楚起見,在圖8(d)中省略了用於控制切換元件之閘極線及源極線。在顯示器840中,同一列上之畫素係以一水平畫素間距HPS間隔開,且各鄰近列中之畫素係以一垂直畫素間距VPS間隔開。顯示器840之畫素被設置成使 位於一列中之所有畫素具有相同之點極性圖案(正的或負的),且每一連續列應在正的點極性圖案與負的點極性圖案之間交替。因此,第一列(即,列0)中之畫素P(0,0)及P(1,0)具有正的點極性圖案,且第二列(即,列1)中之畫素P(0,1)及P(1,1)具有負的點極性圖案。然而,在下一頁框中,畫素將切換點極性圖案。因此,一般而言,一畫素P(x,y)在y為偶數時具有一第一點極性圖案,而在y為奇數時具有一第二點極性圖案。畫素設計840中之內部導體812提供極性至埋置離散場放大器。具體而言,一第一畫素之埋置離散場放大器係自一第二畫素接收電壓極性及電壓大小。更具體而言,該第二畫素係為位於該第一畫素上方之畫素。舉例而言,畫素P(0,0)之埋置離散場放大器EFFA_1係經由畫素P(0,1)之色點CD_1_2之電極而耦接至畫素P(0,1)之切換元件SE_1。 Figure 8(d) shows a portion of display 840 having pixels P(0,0), P(1,0), P(0,1), and P(1) of pixel design 810. ,1). Display 840 uses a switching element column inversion drive mode. Display 840 can have thousands of columns with thousands of pixels on each column. The columns and rows will be successively arranged from the portion shown in Fig. 8(d) in the manner shown in Fig. 8(d). For the sake of clarity, the gate lines and source lines for controlling the switching elements are omitted in Figure 8(d). In display 840, the pixels on the same column are spaced apart by a horizontal pixel spacing HPS, and the pixels in each adjacent column are spaced apart by a vertical pixel spacing VPS. The pixels of the display 840 are set such that All pixels in one column have the same point polarity pattern (positive or negative), and each successive column should alternate between a positive dot polarity pattern and a negative dot polarity pattern. Therefore, the pixels P(0,0) and P(1,0) in the first column (ie, column 0) have a positive dot polarity pattern, and the pixel P in the second column (ie, column 1) (0, 1) and P (1, 1) have a negative dot polarity pattern. However, in the next page box, the pixels will switch the dot polarity pattern. Therefore, in general, a pixel P(x, y) has a first dot polarity pattern when y is an even number and a second dot polarity pattern when y is an odd number. The inner conductor 812 in the pixel design 840 provides a polarity to buried discrete field amplifier. Specifically, a buried discrete field amplifier of a first pixel receives voltage polarity and voltage from a second pixel. More specifically, the second pixel is a pixel located above the first pixel. For example, the embedded discrete field amplifier EFFA_1 of the pixel P(0,0) is coupled to the switching element of the pixel P(0,1) via the electrode of the color point CD_1_2 of the pixel P(0,1). SE_1.
作為另一選擇,在本發明之另一實施例中,一顯示器可針對每一列畫素具有埋置離散場放大器切換元件。相似地,埋置極性區域切換元件係用於圖7(d)中。然而,每一列畫素僅需要一個埋置離散場放大器切換元件。 Alternatively, in another embodiment of the invention, a display can have embedded discrete field amplifier switching elements for each column of pixels. Similarly, the buried polar region switching element is used in Figure 7(d). However, only one buried discrete field amplifier switching element is required for each column of pixels.
由於在顯示器840中每一列上存在極性切換,故若一色點具有第一極性,則圍繞該色點之埋置離散場放大器將具有第二極性。舉例而言,畫素P(0,0)之色點CD_3_2具有正極性,而畫素P(0,0)之埋置離散場放大器EFFA_1具有負極性(來自畫素P(0,1)之切換元件SE_1)。在本發明之一特定實施例中,每一色點具有30微米之一寬度及35微米之一高度。每一埋置極性區域具有6微米之一寬度及6微米之一高度。每一埋置離散場放大器具有105微米之一寬度及105微米之一高度。水平點間距HDS1係為10微米,垂直點間距VDS1係為30微米,水平埋置電極延伸距離係為6微米,且垂直埋置電極延伸距離係為6微米。此外,水平畫素間距HPS係為6微米,且垂直畫素間距VPS係為40微米。 Since there is polarity switching on each column in display 840, if a color point has a first polarity, the buried discrete field amplifier surrounding the color point will have a second polarity. For example, the color point CD_3_2 of the pixel P(0,0) has a positive polarity, and the buried discrete field amplifier EFFA_1 of the pixel P(0,0) has a negative polarity (from the pixel P(0,1) Switching element SE_1). In a particular embodiment of the invention, each color point has a width of one of 30 microns and a height of one of 35 microns. Each buried polar region has a width of one of 6 microns and a height of one of 6 microns. Each buried discrete field amplifier has a width of one of 105 microns and a height of one of 105 microns. The horizontal dot pitch HDS1 is 10 micrometers, the vertical dot pitch VDS1 is 30 micrometers, the horizontal buried electrode extends 6 micrometers, and the vertical buried electrode extends 6 micrometers. In addition, the horizontal pixel spacing HPS is 6 microns and the vertical pixel spacing VPS is 40 microns.
圖9(a)及圖9(b)顯示一畫素設計910(如上所述被標示為910+及910-)之不同點極性圖案,畫素設計910常常用於具有一切換元件列反轉驅動模式之顯示器中。在實際操作中,一畫素將在每一影像頁框之間在一第一點極性圖案與一第二點極性圖案之間切換。畫素設計910幾乎完全相同於畫素設計810,因此不再予以贅述,而僅闡述其不同之處。具體而言,畫素設計910與畫素設計810之不同之處在於,埋置離散場放大器EFFA_1係被偏 極化成一中性極性(如「=」所表示)。因此,在畫素設計810中用於將埋置離散場放大器EFFA_1耦接至一鄰近畫素之一切換元件之導體812不存在於畫素設計910中。在本發明之大多數實施例中,中性極性係自共同電壓V_Com獲得。 Figures 9(a) and 9(b) show different dot polarity patterns for a pixel design 910 (labeled 910+ and 910- as described above). The pixel design 910 is often used to have a switching element column inversion. Drive mode in the display. In actual operation, a pixel will switch between a first dot polarity pattern and a second dot polarity pattern between each image frame. The pixel design 910 is almost identical to the pixel design 810 and will not be described again, but only the differences. Specifically, the difference between the pixel design 910 and the pixel design 810 is that the embedded discrete field amplifier EFFA_1 is biased. Polarize to a neutral polarity (as indicated by "="). Therefore, the conductor 812 for coupling the buried discrete field amplifier EFFA_1 to one of the adjacent pixel switching elements in the pixel design 810 is not present in the pixel design 910. In most embodiments of the invention, the neutral polarity is obtained from a common voltage V_Com.
如上所述,在埋置離散場放大器EFFA_1上使用中性極性會放大色點之離散場。因此,畫素設計910亦會具有良好之多區域分割效能,且可用於以與畫素設計810相同之方式形成顯示器。舉例而言,圖9(c)示出顯示器920之一部分,顯示器920之該部分具有畫素設計910之畫素P(0,0)、P(1,0)、P(0,1)、及P(1,1)。顯示器920使用一切換元件列反轉驅動模式。顯示器920可具有數千列,且每一列上具有數千畫素。在顯示器920中,同一列上之畫素係以一水平畫素間距HPS間隔開,且鄰近列中之畫素係以一垂直畫素間距VPS間隔開。列與行將以圖9(c)所示之方式從圖9(c)所示之部分連續排列。為清楚起見,在圖9(c)中省略了用於控制切換元件之閘極線及源極線。顯示器920之畫素被設置成使位於一列中之所有畫素具有相同之點極性圖案(正的或負的),且每一連續列應在正的點極性圖案與負的點極性圖案之間交替。因此,第一列(即,列0)中之畫素P(0,0)及P(1,0)具有正的點極性圖案,且第二列(即,列1)中之畫素P(0,1)及P(1,1)具有負的點極性圖案。然而,在下一頁框中,畫素將切換點極性圖案。因此,一般而言,一畫素P(x,y)在y為偶數時具有一第一點極性圖案,而在y為奇數時具有一第二點極性圖案。 As described above, the use of neutral polarity on the buried discrete field amplifier EFFA_1 magnifies the discrete fields of color points. Therefore, the pixel design 910 will also have a good multi-area segmentation performance and can be used to form the display in the same manner as the pixel design 810. For example, FIG. 9(c) shows a portion of display 920 having pixels P(0,0), P(1,0), P(0,1) of pixel design 910, And P(1,1). Display 920 uses a switching element column inversion drive mode. Display 920 can have thousands of columns with thousands of pixels on each column. In display 920, the pixels on the same column are spaced apart by a horizontal pixel spacing HPS, and the pixels in adjacent columns are spaced apart by a vertical pixel spacing VPS. The columns and rows will be successively arranged from the portion shown in Fig. 9(c) in the manner shown in Fig. 9(c). For the sake of clarity, the gate lines and source lines for controlling the switching elements are omitted in Figure 9(c). The pixels of display 920 are arranged such that all pixels in a column have the same point polarity pattern (positive or negative), and each successive column should be between a positive dot polarity pattern and a negative dot polarity pattern. alternately. Therefore, the pixels P(0,0) and P(1,0) in the first column (ie, column 0) have a positive dot polarity pattern, and the pixel P in the second column (ie, column 1) (0, 1) and P (1, 1) have a negative dot polarity pattern. However, in the next page box, the pixels will switch the dot polarity pattern. Therefore, in general, a pixel P(x, y) has a first dot polarity pattern when y is an even number and a second dot polarity pattern when y is an odd number.
在埋置離散場放大器EFFA_1上使用中性極性之一有益效果係為:位於埋置離散場放大器前面之色點之極性可具有不同極性。舉例而言,圖10(a)及圖10(b)顯示一畫素設計1010(如上所述被標示為1010+及1010-)之不同點極性圖案,畫素設計1010常常用於具有一切換元件點反轉驅動模式及切換元件行反轉驅動模式之顯示器中。在實際操作中,一畫素將在每一影像頁框之間在一第一點極性圖案與一第二點極性圖案之間切換。畫素設計1010幾乎完全相同於畫素設計910,因此不再予以贅述,而僅闡述其不同之處。具體而言,畫素設計1010與畫素設計910之不同之處在於,切換元件SE_2、色點CD_2_1、色點CD_2_2之極性對於正的點極性係為負的且對於負的點極性係為正的。 One benefit of using a neutral polarity on the buried discrete field amplifier EFFA_1 is that the polarity of the color points located in front of the buried discrete field amplifier can have different polarities. For example, Figures 10(a) and 10(b) show different dot polarity patterns for a pixel design 1010 (labeled 1010+ and 1010- as described above). The pixel design 1010 is often used to have a switch. In the display of the component dot inversion driving mode and the switching element row inversion driving mode. In actual operation, a pixel will switch between a first dot polarity pattern and a second dot polarity pattern between each image frame. The pixel design 1010 is almost identical to the pixel design 910 and will not be described again, but only the differences. Specifically, the pixel design 1010 is different from the pixel design 910 in that the polarity of the switching element SE_2, the color point CD_2_1, and the color point CD_2_2 is negative for a positive point polarity and positive for a negative point polarity. of.
因此,在其中顯示畫素設計1010+之正的點極性圖案之圖10(a)中,切換元件SE_1及SE_3、色點CD_1_1、CD_1_2、CD_3_1、及CD_3_2具有正極性。然而,切換元件SE_2、色點CD_2_1及CD_2_2具有負極性。埋置離散場放大器EFFA_1具有中性極性。圖10(b)顯示具有負的點極性圖案之畫素設計1010。對於負的點極性圖案,切換元件SE_1及SE_3、色點CD_1_1、CD_1_2、CD_3_1、及CD_3_2具有負極性。然而,切換元件SE_2、色點CD_2_1及CD_2_2具有正極性。埋置離散場放大器EFFA_1具有中性極性。 Therefore, in FIG. 10(a) in which the dot polarity pattern of the pixel design 1010+ is displayed, the switching elements SE_1 and SE_3, the color points CD_1_1, CD_1_2, CD_3_1, and CD_3_2 have positive polarity. However, the switching element SE_2, the color points CD_2_1 and CD_2_2 have a negative polarity. The buried discrete field amplifier EFFA_1 has a neutral polarity. Figure 10(b) shows a pixel design 1010 with a negative dot polarity pattern. For the negative dot polarity pattern, the switching elements SE_1 and SE_3, the color points CD_1_1, CD_1_2, CD_3_1, and CD_3_2 have negative polarity. However, the switching element SE_2, the color points CD_2_1 and CD_2_2 have positive polarity. The buried discrete field amplifier EFFA_1 has a neutral polarity.
圖10(c)示出顯示器1020之一部分,顯示器1020之該部分具有畫素設計1010之畫素P(0,0)、P(1,0)、P(0,1)、及P(1,1)。顯示器1020使用一切換元件點反轉驅動模式。顯示器1020可具有數千列,且每一列上具有數千畫素。在顯示器1020中,同一列上之畫素係以一水平畫素間距HPS間隔開,且鄰近列中之畫素係以一垂直畫素間距VPS間隔開。列與行將以圖10(c)所示之方式從圖10(c)所示之部分連續排列。為清楚起見,在圖10(c)中省略了用於控制切換元件之閘極線及源極線。在顯示器1020中,畫素係被設置成使位於一列中之畫素交替地具有點極性圖案(正的或負的),且位於一行中之畫素亦在正的點極性圖案與負的點極性圖案之間交替。因此,畫素P(0,0)及P(1,1)具有正的點極性圖案,且畫素P(0,1)及P(1,0)具有負的點極性圖案。然而,在下一頁框中,畫素將切換點極性圖案。因此,一般而言,一畫素P(x,y)在x+y為偶數時具有一第一點極性圖案,而在x+y為奇數時具有一第二點極性圖案。 Figure 10 (c) shows a portion of display 1020 having pixels of pixel design 1010 P(0,0), P(1,0), P(0,1), and P(1). ,1). Display 1020 uses a switching element dot inversion drive mode. Display 1020 can have thousands of columns with thousands of pixels on each column. In display 1020, the pixels on the same column are spaced apart by a horizontal pixel spacing HPS, and the pixels in adjacent columns are spaced apart by a vertical pixel spacing VPS. The columns and rows will be successively arranged from the portion shown in Fig. 10(c) in the manner shown in Fig. 10(c). For the sake of clarity, the gate lines and source lines for controlling the switching elements are omitted in FIG. 10(c). In the display 1020, the pixels are arranged such that the pixels located in one column alternately have a dot polarity pattern (positive or negative), and the pixels in one row are also at the positive dot polarity pattern and the negative point. The polarity patterns alternate between each other. Therefore, the pixels P(0, 0) and P(1, 1) have a positive dot polarity pattern, and the pixels P(0, 1) and P(1, 0) have a negative dot polarity pattern. However, in the next page box, the pixels will switch the dot polarity pattern. Therefore, in general, a pixel P(x, y) has a first dot polarity pattern when x+y is even, and a second dot polarity pattern when x+y is odd.
畫素設計1010亦可用於使用切換元件行反轉驅動模式之顯示器中。圖10(d)示出顯示器1030之一部分,顯示器1030之該部分具有畫素設計1010之畫素P(0,0)、P(1,0)、P(0,1)、及P(1,1)。顯示器1030可具有數千列,且每一列上具有數千畫素。在顯示器1030中,同一列上之畫素係以一水平畫素間距HPS間隔開,且鄰近列中之畫素係以一垂直畫素間距VPS間隔開。列與行將以圖10(d)所示之方式從圖10(d)所示之部分連續排列。為清楚起見,在圖10(d)中省略了用於控制切換元件之閘極線及源極線。在顯示器1030中,畫素係被設置成使位於一列中之畫素交替地具有點極性圖案(正的或負的),且位於一行中之畫素具有相同之點極性圖案。因此,畫素P(0, 0)及P(0,1)具有正的點極性圖案,且畫素P(1,0)及P(1,1)具有負的點極性圖案。然而,在下一頁框中,畫素將切換點極性圖案。因此,一般而言,一畫素P(x,y)在x為偶數時具有一第一點極性圖案,而在x為奇數時具有一第二點極性圖案。 The pixel design 1010 can also be used in a display that uses a switching element row inversion driving mode. Figure 10 (d) shows a portion of the display 1030, which has pixels of the pixel design 1010 P(0,0), P(1,0), P(0,1), and P(1). ,1). Display 1030 can have thousands of columns with thousands of pixels on each column. In display 1030, the pixels on the same column are spaced apart by a horizontal pixel spacing HPS, and the pixels in adjacent columns are spaced apart by a vertical pixel spacing VPS. The columns and rows will be successively arranged from the portion shown in Fig. 10(d) in the manner shown in Fig. 10(d). For the sake of clarity, the gate lines and source lines for controlling the switching elements are omitted in FIG. 10(d). In display 1030, the pixels are arranged such that pixels located in a column alternately have a dot polarity pattern (positive or negative), and pixels located in one row have the same dot polarity pattern. Therefore, the pixel P (0, 0) and P(0,1) have a positive dot polarity pattern, and the pixels P(1,0) and P(1,1) have a negative dot polarity pattern. However, in the next page box, the pixels will switch the dot polarity pattern. Therefore, in general, a pixel P(x, y) has a first dot polarity pattern when x is an even number and a second dot polarity pattern when x is an odd number.
在許多可攜式液晶顯示器應用中,需要降低功耗來節省電池壽命。圖11(a)及圖11(b)顯示依據本發明某些實施例其中每一色分量具有多個色點之一畫素設計,該畫素設計包含埋置極性區域及多個埋置離散場放大器。具體而言,圖11(a)及圖11(b)顯示一畫素設計1110(如下所述被標示為1110+及1110-)之不同點極性圖案,畫素設計1110常常用於具有一切換元件列反轉驅動模式之顯示器中。在實際操作中,一畫素將在每一影像頁框之間在一第一點極性圖案與一第二點極性圖案之間切換。 In many portable LCD applications, there is a need to reduce power consumption to save battery life. 11(a) and 11(b) show a pixel design in which each color component has a plurality of color points, including a buried polar region and a plurality of buried discrete fields, in accordance with some embodiments of the present invention. Amplifier. Specifically, FIGS. 11(a) and 11(b) show different dot polarity patterns of a pixel design 1110 (labeled as 1110+ and 1110- as described below), and the pixel design 1110 is often used to have a switch. The component column is in the display of the reverse drive mode. In actual operation, a pixel will switch between a first dot polarity pattern and a second dot polarity pattern between each image frame.
與畫素設計810一樣,畫素設計1110具有三個色分量CC_1、CC_2及CC_3(在圖11(a)-11(b)中未標示出)。該三個色分量其中每一者包含二色點。畫素設計1110亦針對每一色分量包含一切換元件(被表示為SE_1、SE_2及SE_3)且針對每一色分量包含一埋置離散場放大器(被表示為EFFA_1、EFFA_2、及EFFA_3)。切換元件SE_1、SE_2及SE_3係排列成一列。埋置離散場放大器EFFA_1、EFFA_2、及EFFA_3亦排列成一列。畫素設計1110之色點、埋置極性區域、及切換元件與畫素設計810非常相似。然而,如下所述,畫素設計1110與畫素設計810中之埋置極性區域之形成不同。 Like the pixel design 810, the pixel design 1110 has three color components CC_1, CC_2, and CC_3 (not shown in Figures 11(a)-11(b)). Each of the three color components includes a two color point. The pixel design 1110 also includes a switching element (denoted as SE_1, SE_2, and SE_3) for each color component and a buried discrete field amplifier (denoted EFFA_1, EFFA_2, and EFFA_3) for each color component. The switching elements SE_1, SE_2 and SE_3 are arranged in a row. The buried discrete field amplifiers EFFA_1, EFFA_2, and EFFA_3 are also arranged in a column. The color point of the pixel design 1110, the buried polarity region, and the switching elements are very similar to the pixel design 810. However, as described below, the pixel design 1110 is different from the formation of the buried polarity regions in the pixel design 810.
畫素設計1110之第一色分量CC_1具有二色點CD_1_1及CD_1_2。色點CD_1_1與CD_1_2形成一行,並以一垂直點間距VDS1間隔開。換言之,色點CD_1_1與CD_1_2係水平地配向並以垂直點間距VDS1垂直地間隔開。此外,色點CD_1_1與CD_1_2係垂直地錯開垂直點偏移量VDO1,垂直點偏移量VDO1係等於垂直點間距VDS1加上色點高度CDH。切換元件SE_1係位於色點CD_1_1與CD_1_2之間,俾使色點CD_1_1位於該列切換元件之一第一側,而色點CD_1_2位於該列切換元件之一第二側。切換元件SE_1係耦接至色點CD_1_1及CD_1_2之電極,以控制色點CD_1_1及CD_1_2之電壓極性及電壓大小。 The first color component CC_1 of the pixel design 1110 has two color points CD_1_1 and CD_1_2. The color points CD_1_1 and CD_1_2 form a line and are spaced apart by a vertical dot pitch VDS1. In other words, the color points CD_1_1 and CD_1_2 are horizontally aligned and vertically spaced apart by the vertical dot pitch VDS1. Further, the color point CD_1_1 and the CD_1_2 are vertically shifted by the vertical dot offset VDO1, and the vertical dot offset VDO1 is equal to the vertical dot pitch VDS1 plus the color point height CDH. The switching element SE_1 is located between the color points CD_1_1 and CD_1_2 such that the color point CD_1_1 is located on a first side of the column switching element, and the color point CD_1_2 is located on a second side of the column switching element. The switching element SE_1 is coupled to the electrodes of the color points CD_1_1 and CD_1_2 to control the voltage polarity and voltage of the color points CD_1_1 and CD_1_2.
色分量CD_1_1之每一色點包含一埋置極性區域,埋置極性區域會增強 離散場,因此增強多區域垂直配向操作並將色點中之任何觸碰雲紋效應最小化。具體而言,色點CD_1_1及CD_1_2分別包含埋置極性區域EPR_1_1及EPR_1_2。如圖11(a)所示,埋置極性區域EPR_1_1及EPR_1_2係分別居中於色點CD_1_1及CD_1_2中。在畫素設計1110中,圖6(a)-6(b)中所示埋置導體技術被擴展,並與畫素設計710(圖7(a)-7(b))中所使用之離散場放大區域相結合。具體而言,在畫素設計1110中,係針對每一色分量使用一埋置離散場放大器。 Each color point of the color component CD_1_1 includes a buried polarity region, and the buried polarity region is enhanced. The discrete field, thus enhancing the multi-region vertical alignment operation and minimizing any touch moiré effects in the color point. Specifically, the color points CD_1_1 and CD_1_2 respectively include buried polarity areas EPR_1_1 and EPR_1_2. As shown in FIG. 11(a), the buried polar regions EPR_1_1 and EPR_1_2 are respectively centered in the color points CD_1_1 and CD_1_2. In the pixel design 1110, the buried conductor technique shown in Figures 6(a)-6(b) is extended and discrete with the pixel design 710 (Figs. 7(a)-7(b)). The field amplification area is combined. Specifically, in the pixel design 1110, a buried discrete field amplifier is used for each color component.
為清楚起見,將從一使用者觀察一被保持於一垂直位置之顯示器之角度來闡述一畫素設計之各個部分之相對位置。因此,舉例而言,在圖11(a)中,色點CD_1_1係被闡述成位於切換元件SE_1上方,且色點CD_1_2係被闡述成位於切換元件SE_1下方。色點CD_1_1係位於色點CD_2_1左側,相反,色點CD_3_1係位於色點CD_2_1右側。此外,埋置離散場放大器係被闡述成位於色點後面。相反,色點係被闡述成位於埋置離散場放大器前面。 For the sake of clarity, the relative position of the various portions of a pixel design will be elucidated from the perspective of a user viewing a display held in a vertical position. Thus, for example, in Figure 11(a), the color point CD_1_1 is illustrated as being located above the switching element SE_1, and the color point CD_1_2 is illustrated as being located below the switching element SE_1. The color point CD_1_1 is located on the left side of the color point CD_2_1. On the contrary, the color point CD_3_1 is located on the right side of the color point CD_2_1. In addition, the buried discrete field amplifier is illustrated as being located behind the color point. Instead, the color point is illustrated as being located in front of the buried discrete field amplifier.
畫素設計1110之第二色分量CC_2具有二色點CD_2_1及CD_2_2。色點CD_2_1與CD_2_2形成一第二行,並以一垂直點間距VDS1間隔開。因此,色點CD_2_1與CD_1_2係水平地配向並以垂直點間距VDS1垂直地間隔開。切換元件SE_2係位於色點CD_2_1與CD_2_2之間,俾使色點CD_2_1位於該列切換元件之第一側,而色點CD_2_2位於該列切換元件之一第二側。切換元件SE_2係耦接至色點CD_2_1及CD_2_2之電極,以控制色點CD_2_1及CD_2_2之電壓極性及電壓大小。第二色分量CC_2係與第一色分量CC_1垂直地配向,並以一水平點間距HDS1與色分量CC_1間隔開,因此色分量CC_2與CC_1係水平地錯開一水平點偏移量HDO1,水平點偏移量HDO1係等於水平點間距HDS1加上色點寬度CDW。具體關於色點而言,色點CD_2_1與色點CD_1_1係垂直地配向並以水平點間距HDS1水平地間隔開。相似地,色點CD_2_2與色點CD_2_1係垂直地配向並以水平點間距HDS1水平地間隔開。因此,色點CD_1_1與色點CD_2_1形成一第一列色點,且色點CD_1_2與色點CD_2_2形成一第二列色點。與色點CD_1_1及CD_1_2一樣,色點CD_2_1及CD_2_2分別包含埋置極性區域EPR_2_1及EPR_2_2。 The second color component CC_2 of the pixel design 1110 has two color points CD_2_1 and CD_2_2. The color points CD_2_1 and CD_2_2 form a second line and are spaced apart by a vertical dot pitch VDS1. Therefore, the color points CD_2_1 and CD_1_2 are horizontally aligned and vertically spaced apart by the vertical dot pitch VDS1. The switching element SE_2 is located between the color points CD_2_1 and CD_2_2 such that the color point CD_2_1 is located on the first side of the column switching element, and the color point CD_2_2 is located on the second side of one of the column switching elements. The switching element SE_2 is coupled to the electrodes of the color points CD_2_1 and CD_2_2 to control the voltage polarity and voltage of the color points CD_2_1 and CD_2_2. The second color component CC_2 is vertically aligned with the first color component CC_1, and is spaced apart by a horizontal dot pitch HDS1 and the color component CC_1. Therefore, the color components CC_2 and CC_1 are horizontally shifted by a horizontal point offset HDD1, the horizontal point. The offset HDD1 is equal to the horizontal dot pitch HDS1 plus the color dot width CDW. Specifically, regarding the color point, the color point CD_2_1 and the color point CD_1_1 are vertically aligned and horizontally spaced by the horizontal dot pitch HDS1. Similarly, the color point CD_2_2 is vertically aligned with the color point CD_2_1 and horizontally spaced by the horizontal dot pitch HDS1. Therefore, the color point CD_1_1 and the color point CD_2_1 form a first column color point, and the color point CD_1_2 and the color point CD_2_2 form a second column color point. Like the color points CD_1_1 and CD_1_2, the color points CD_2_1 and CD_2_2 respectively contain the buried polar regions EPR_2_1 and EPR_2_2.
相似地,畫素1110之第三色分量CC_3具有二色點CD_3_1及CD_3_2。色點CD_3_1與CD_3_2形成一第三行,並以一垂直點間距VDS1間隔開。因此,色點CD_3_1與CD_3_2係水平地配向並以垂直點間距VDS1垂直地間隔開。切換元件SE_3係位於色點CD_3_1與CD_3_2之間,俾使色點CD_3_1位於該列切換元件之第一側,而色點CD_3_2位於該列切換元件之一第二側。切換元件SE_3係耦接至色點CD_3_1及CD_3_2之電極,以控制色點CD_3_1及CD_3_2之電壓極性及電壓大小。第三色分量CC_3係與第二色分量CC_2垂直地配向,並以水平點間距HDS1與色分量CC_2間隔開,因此色分量CC_3與CC_2係水平地錯開一水平點偏移量HDO1。具體關於色點而言,色點CD_3_1與色點CD_2_1係垂直地配向並以水平點間距HDS1水平地間隔開。相似地,色點CD_3_2與色點CD_2_2係垂直地配向並以水平點間距HDS1水平地間隔開。因此,色點CD_3_1係位於第一列色點上,且色點CD_3_2係位於第二列色點上。與色點CD_1_1及CD_1_2一樣,色點CD_3_1及CD_3_2分別包含埋置極性區域EPR_3_1及EPR_3_2。 Similarly, the third color component CC_3 of the pixel 1110 has two color points CD_3_1 and CD_3_2. The color points CD_3_1 and CD_3_2 form a third line and are spaced apart by a vertical dot pitch VDS1. Therefore, the color points CD_3_1 and CD_3_2 are horizontally aligned and vertically spaced apart by the vertical dot pitch VDS1. The switching element SE_3 is located between the color points CD_3_1 and CD_3_2 such that the color point CD_3_1 is located on the first side of the column switching element, and the color point CD_3_2 is located on the second side of one of the column switching elements. The switching element SE_3 is coupled to the electrodes of the color points CD_3_1 and CD_3_2 to control the voltage polarity and voltage of the color points CD_3_1 and CD_3_2. The third color component CC_3 is vertically aligned with the second color component CC_2, and is spaced apart from the color component CC_2 by the horizontal dot pitch HDS1, so that the color components CC_3 and CC_2 are horizontally shifted by a horizontal dot offset amount HDO1. Specifically, regarding the color point, the color point CD_3_1 and the color point CD_2_1 are vertically aligned and horizontally spaced by the horizontal dot pitch HDS1. Similarly, the color point CD_3_2 is vertically aligned with the color point CD_2_2 and horizontally spaced by the horizontal dot pitch HDS1. Therefore, the color point CD_3_1 is located on the first column color point, and the color point CD_3_2 is located on the second column color point. Like the color points CD_1_1 and CD_1_2, the color points CD_3_1 and CD_3_2 respectively contain the buried polarity areas EPR_3_1 and EPR_3_2.
為清楚起見,以具有相同色點高度CDH之色點來例示畫素設計1110之各色點。然而,本發明之某些實施例可包含具有不同色點高度之色點。舉例而言,在本發明之一實施例(其為畫素設計1110之一變體)中,色點CD_1_1、CD_2_1、及CD_3_1之色點高度小於色點CD_1_2、CD_2_2、及CD_3_2之色點高度。此外,在本發明之許多實施例中,色點可具有不同形狀。 For the sake of clarity, the color points of the pixel design 1110 are exemplified by color points having the same color point height CDH. However, certain embodiments of the invention may include color points having different color point heights. For example, in one embodiment of the present invention, which is a variant of the pixel design 1110, the color point heights of the color points CD_1_1, CD_2_1, and CD_3_1 are smaller than the color point heights of the color points CD_1_2, CD_2_2, and CD_3_2. . Moreover, in many embodiments of the invention, the color points can have different shapes.
相較於畫素設計710,畫素設計1110包含埋置離散場放大器EFFA而非包含離散場放大區域及位於埋置極性區域中之埋置導體。具體而言,畫素設計1110包含埋置離散場放大器EFFA_1、EFFA_2、及EFFA_3。如圖11(a)所示,埋置離散場放大器EFFA_1、EFFA_2、及EFFA_3係被放置於畫素設計1110之色點後面。具體而言,埋置離散場放大器EFFA_1係被放置成使色點CD_1_1及色點CD_1_2及切換元件SE_1位於埋置離散場放大器EFFA_1前面。然而,埋置離散場放大器EFFA_1延伸超過色點CD_1_1及CD_1_2之左側及右側達一水平埋置電極延伸距離HEEED1。相似地,埋置離散場放大器EFFA_1延伸超過色點CD_1_1之頂部及色點CD_1_2之底部達一垂直埋置電極延伸距離VEEED1。因此,色點CD_1_1及CD_1_2 之邊緣係位於埋置離散場放大器EFFA_1之部分前面。相似地,埋置離散場放大器EFFA_2係被放置成使色點CD_2_1及色點CD_2_2及切換元件SE_2位於埋置離散場放大器EFFA_2前面。然而,埋置離散場放大器EFFA_2延伸超過色點CD_2_1以及CD_2_2之左側及右側達一水平埋置電極延伸距離HEEED1。相似地,埋置離散場放大器EFFA_2延伸超過色點CD_2_1之頂部及色點CD_2_2之底部達一垂直埋置電極延伸距離VEEED1。因此,色點CD_2_1及CD_2_2之邊緣係位於埋置離散場放大器EFFA_2之部分前面。此外,埋置離散場放大器EFFA_2係與埋置離散場放大器EFFA_1垂直地配向,並以一水平埋置電極間距HEES1與埋置離散場放大器EFFA_1間隔開。 In contrast to the pixel design 710, the pixel design 1110 includes a buried discrete field amplifier EFFA rather than a buried conductor that includes a discrete field amplification region and is located in the buried polarity region. In particular, pixel design 1110 includes buried discrete field amplifiers EFFA_1, EFFA_2, and EFFA_3. As shown in FIG. 11(a), the buried discrete field amplifiers EFFA_1, EFFA_2, and EFFA_3 are placed behind the color point of the pixel design 1110. Specifically, the buried discrete field amplifier EFFA_1 is placed such that the color point CD_1_1 and the color point CD_1_2 and the switching element SE_1 are located in front of the buried discrete field amplifier EFFA_1. However, the buried discrete field amplifier EFFA_1 extends beyond the left and right sides of the color points CD_1_1 and CD_1_2 to a horizontal buried electrode extension distance HEEED1. Similarly, the buried discrete field amplifier EFFA_1 extends beyond the top of the color point CD_1_1 and the bottom of the color point CD_1_2 to a vertical buried electrode extension distance VEEED1. Therefore, the color points CD_1_1 and CD_1_2 The edge is located in front of the portion of the buried discrete field amplifier EFFA_1. Similarly, the buried discrete field amplifier EFFA_2 is placed such that the color point CD_2_1 and the color point CD_2_2 and the switching element SE_2 are located in front of the buried discrete field amplifier EFFA_2. However, the buried discrete field amplifier EFFA_2 extends beyond the left and right sides of the color points CD_2_1 and CD_2_2 to a horizontal buried electrode extension distance HEEED1. Similarly, the buried discrete field amplifier EFFA_2 extends beyond the top of the color point CD_2_1 and the bottom of the color point CD_2_2 to a vertical buried electrode extension distance VEEED1. Therefore, the edges of the color points CD_2_1 and CD_2_2 are located in front of the portion of the buried discrete field amplifier EFFA_2. In addition, the buried discrete field amplifier EFFA_2 is vertically aligned with the buried discrete field amplifier EFFA_1 and spaced apart from the buried discrete field amplifier EFFA_1 by a horizontal buried electrode pitch HEES1.
相似地,埋置離散場放大器EFFA_3係被放置成使色點CD_3_1及色點CD_3_2以及切換元件SE_3位於埋置離散場放大器EFFA_3前面。然而,埋置離散場放大器EFFA_3延伸超過色點CD_3_1及CD_3_2之左側及右側達一水平埋置電極延伸距離HEEED1。相似地,埋置離散場放大器EFFA_3延伸超過色點CD_3_1之頂部及色點CD_3_2之底部達一垂直埋置電極延伸距離VEEED1。因此,色點CD_3_1及CD_3_2之邊緣係位於埋置離散場放大器EFFA_3之部分前面。此外,埋置離散場放大器EFFA_3係與埋置離散場放大器EFFA_2垂直地配向,並以一水平埋置電極間距HEES1與埋置離散場放大器EFFA_2間隔開。一電極1116係用於將埋置離散場放大器EFFA_1耦接至一電壓源。 Similarly, the buried discrete field amplifier EFFA_3 is placed such that the color point CD_3_1 and the color point CD_3_2 and the switching element SE_3 are located in front of the buried discrete field amplifier EFFA_3. However, the buried discrete field amplifier EFFA_3 extends beyond the left and right sides of the color points CD_3_1 and CD_3_2 to a horizontal buried electrode extension distance HEEED1. Similarly, the buried discrete field amplifier EFFA_3 extends beyond the top of the color point CD_3_1 and the bottom of the color point CD_3_2 to a vertical buried electrode extension distance VEEED1. Therefore, the edges of the color points CD_3_1 and CD_3_2 are located in front of the portion of the buried discrete field amplifier EFFA_3. In addition, the buried discrete field amplifier EFFA_3 is vertically aligned with the buried discrete field amplifier EFFA_2 and spaced apart from the buried discrete field amplifier EFFA_2 by a horizontal buried electrode pitch HEES1. An electrode 1116 is used to couple the buried discrete field amplifier EFFA_1 to a voltage source.
使用「+」及「-」符號來顯示色點、埋置離散場放大器、及切換元件之極性。因此,在其中顯示畫素設計1110+之正的點極性圖案之圖11(a)中,所有切換元件(即,切換元件SE_1、SE_2及SE_3)及所有色點(即,色點CD_1_1、CD_1_2、CD_2_1、CD_2_2、CD_3_1、及CD_3_2)具有正極性。然而,埋置離散場放大器EFFA_1、EFFA_2、及EFFA_3具有負極性。因此,埋置極性區域EPR_1_1、EPR_2_1、及EPR_3_1亦具有負極性(由於空間限制,在圖11(a)及圖11(b)中未表示埋置極性區域之極性)。 Use the "+" and "-" symbols to display the color point, the embedded discrete field amplifier, and the polarity of the switching components. Therefore, in Fig. 11(a) in which the dot pattern of the pixel design 1110+ is displayed, all the switching elements (i.e., switching elements SE_1, SE_2, and SE_3) and all the color points (i.e., color points CD_1_1, CD_1_2) , CD_2_1, CD_2_2, CD_3_1, and CD_3_2) have positive polarity. However, the buried discrete field amplifiers EFFA_1, EFFA_2, and EFFA_3 have negative polarity. Therefore, the buried polar regions EPR_1_1, EPR_2_1, and EPR_3_1 also have a negative polarity (the polarity of the buried polar region is not shown in FIGS. 11(a) and 11(b) due to space limitations).
圖11(b)顯示具有負的點極性圖案之畫素設計1110。對於負的點極性圖案,所有切換元件(即,切換元件SE_1、SE_2及SE_3)及所有色點(即,色點CD_1_1、CD_1_2、CD_2_1、CD_2_2、CD_3_1、及3_2)具有負極 性。然而,埋置離散場放大器EFFA_1、EFFA_2、及EFFA_3具有正極性。因此,埋置極性區域EPR_1_1、EPR_2_1、及EPR_3_1亦具有正極性。 Figure 11 (b) shows a pixel design 1110 with a negative dot polarity pattern. For a negative dot polarity pattern, all switching elements (ie, switching elements SE_1, SE_2, and SE_3) and all color points (ie, color points CD_1_1, CD_1_2, CD_2_1, CD_2_2, CD_3_1, and 3_2) have negative poles Sex. However, the buried discrete field amplifiers EFFA_1, EFFA_2, and EFFA_3 have positive polarity. Therefore, the buried polar regions EPR_1_1, EPR_2_1, and EPR_3_1 also have positive polarity.
每一色點中之離散場皆被放大,乃因色點之邊緣附近存在不同電壓。畫素設計1110利用埋置離散場放大器來增強並穩定液晶結構中之多區域之形成。具體而言,一色點之邊緣係位於一埋置離散場放大器之一部分前面。當埋置離散場放大器EFFA_1上之電壓不同於色點之電壓時,色點與埋置離散場放大器之交疊放置會放大色點之離散場。若色點與埋置離散場放大器具有相反極性,則會更大程度地放大離散場。然而,若埋置離散場放大器係被保持於共同電壓(即,中性極性),亦可良好地放大色點之離散場。一般而言,偏極化組件之極性係被指定成使一第一極性之一色點位於一第二極性之一埋置離散場放大器前面,該第二極性之埋置離散場放大器延伸超過色點之邊緣。舉例而言,對於畫素設計1110(圖11(a))之正的點極性圖案,色點CD_2_2具有正極性。然而,埋置離散場放大器EFFA_2具有一負極性。因此,色點CD_2_2之離散場被放大。 The discrete fields in each color point are magnified because of the different voltages near the edges of the color points. The pixel design 1110 utilizes a buried discrete field amplifier to enhance and stabilize the formation of multiple regions in the liquid crystal structure. Specifically, the edge of a color point is located in front of a portion of a buried discrete field amplifier. When the voltage across the buried discrete field amplifier EFFA_1 is different from the voltage at the color point, the overlap of the color point and the buried discrete field amplifier amplifies the discrete field of the color point. If the color point has the opposite polarity to the buried discrete field amplifier, the discrete field will be amplified to a greater extent. However, if the buried discrete field amplifier is maintained at a common voltage (ie, neutral polarity), the discrete fields of the color points can be well magnified. In general, the polarity of the polarization component is specified such that a color point of a first polarity is in front of a buried discrete field amplifier of a second polarity, and the buried discrete field amplifier of the second polarity extends beyond the color point. The edge. For example, for the positive dot polarity pattern of the pixel design 1110 (Fig. 11(a)), the color point CD_2_2 has a positive polarity. However, the buried discrete field amplifier EFFA_2 has a negative polarity. Therefore, the discrete field of the color point CD_2_2 is amplified.
因畫素設計1110中之所有切換元件具有相同極性且埋置離散場放大器應具有一不同極性,故離散場放大器係由一外部極性源(即,來自畫素設計1110之特定畫素外之一極性源)驅動。可依據本發明之不同實施例來使用各種相反極性源。舉例而言,可使用特定的埋置離散場放大器切換元件或亦可使用鄰近畫素之具有一相反點極性之切換元件來驅動埋置離散場放大器。在圖11(a)-11(b)之實施例中,亦可使用鄰近畫素之具有一相反點極性之切換元件來驅動離散場放大區域。因此,畫素設計1110包含導體1112、1114、及1116,以幫助離散場放大區域耦接至其他畫素中之切換元件。一電極1112係用於將埋置離散場放大器EFFA_1耦接至一電壓源。一般而言,在切換元件列反轉驅動模式顯示器中,電極1112係耦接至位於當前畫素上方之一畫素之色點CD_1_2(參見圖11(d))。一電極1114係用於將埋置離散場放大器EFFA_2耦接至一電壓源。一般而言,在切換元件列反轉驅動模式顯示器中,電極1114係耦接至位於當前畫素上方之一畫素之色點CD_2_2(參見圖11(d))。一電極1116係用於將埋置離散場放大器EFFA_1耦接至一電壓源。一般而言,在切換元件列反轉驅動模式顯示器中,電極1116係耦接至位於當前畫素上方之一畫素之色點CD_3_2(參見圖11(d))。 Since all of the switching elements in the pixel design 1110 have the same polarity and the buried discrete field amplifier should have a different polarity, the discrete field amplifier is comprised of an external polar source (ie, one of the specific pixels from the pixel design 1110). Polar source) drive. Various sources of opposite polarity can be used in accordance with various embodiments of the present invention. For example, a particular buried discrete field amplifier switching element can be used or a buried pixel with a reverse polarity can be used to drive the buried discrete field amplifier. In the embodiment of Figures 11(a)-11(b), the discrete field amplification regions can also be driven using switching elements of adjacent pixels having opposite polarity. Thus, the pixel design 1110 includes conductors 1112, 1114, and 1116 to assist in coupling the discrete field amplification regions to the switching elements in other pixels. An electrode 1112 is used to couple the buried discrete field amplifier EFFA_1 to a voltage source. In general, in the switching element column inversion driving mode display, the electrode 1112 is coupled to a color point CD_1_2 located at a pixel above the current pixel (see FIG. 11(d)). An electrode 1114 is used to couple the buried discrete field amplifier EFFA_2 to a voltage source. In general, in the switching element column inversion driving mode display, the electrode 1114 is coupled to a color point CD_2_2 located at a pixel above the current pixel (see FIG. 11(d)). An electrode 1116 is used to couple the buried discrete field amplifier EFFA_1 to a voltage source. In general, in the switching element column inversion driving mode display, the electrode 1116 is coupled to a color point CD_3_2 located at a pixel above the current pixel (see FIG. 11(d)).
圖11(c)顯示沿A-A線(圖11(b))截取之畫素設計1110之橫截面,其包含色點CD_1_1、CD_2_1、CD_3_1、埋置極性區域EPR_1_1、EPR_2_1、及EPR_3_1、以及埋置離散場放大器EFFA_1、EFFA_2、及EFFA_3。圖11(c)係用以說明色點與埋置離散場放大器之相對放置。因此,為清楚起見,可能存在於本發明各實施例中之某些層及組件未顯示於圖11(c)中。此外,使用畫素設計1110之一顯示器中之其他層及組件可能不存在於圖11(c)所示畫素設計1110之區域中。如圖11(c)所示,使用畫素設計1110之一顯示器包含一下伏透明基板1121。透明基板1121上形成有一第一鈍化層1123。儘管圖未示出,然而一第一金屬層常常形成於基板1121上且通常由第一鈍化層1123覆蓋。然而,第一金屬層未用於圖11(c)所示畫素設計1110之部分中。鈍化層1123係使用一透明鈍化材料(例如,介電層SiNx)製成。一般而言,一層透明導電材料(例如ITO、或ZnO)係形成於鈍化層1123之上並被蝕刻以形成埋置離散場放大器EFFA_1、EFFA_2、及EFFA_3。在本發明之某些實施例中,可在鈍化層1123上形成一第二金屬層。一第二鈍化層1127係形成於埋置離散場放大器EFFA_1之上且亦填充由用於形成埋置離散場放大器EFFA_1、EFFA_2、及EFFA_3之蝕刻製造所留下之間隙。圖11(c)所示畫素設計1110之特定部分包含埋置極性區域EPR_1_1、EPR_2_1、及EPR_3_1,埋置極性區域EPR_1_1、EPR_2_1、及EPR_3_1係藉由蝕刻穿過色點及鈍化層1127之中間而形成。因此,在圖11(c)中,鈍化層1127顯現為多個部分。色點係形成於鈍化層1127之頂部上。通常,色點係藉由在第二鈍化層1127上沈積一層導電材料(例如,ITO或IZO)而形成。隨後,圖案化並蝕刻導電層以形成色點。因此,如圖11(c)所示,色點CD_1_1、CD_2_1、及CD_3_1係位於第二鈍化層1127之頂部上。因圖11(c)之透視圖係於埋置極性區域所在之處截取,故在圖11(c)中色點CD_1_1、CD_2_1、及CD_3_1係顯現為二分開之部分。然而,色點之實際形狀係為一正方形形狀,該正方形形狀於中心處具有一正方形孔,如圖11(a)所示。在本發明之某些實施例中,埋置離散場放大器係形成於透明基板1121上。 Figure 11 (c) shows a cross section of the pixel design 1110 taken along line AA (Figure 11 (b)), including color points CD_1_1, CD_2_1, CD_3_1, buried polarity regions EPR_1_1, EPR_2_1, and EPR_3_1, and embedding Discrete field amplifiers EFFA_1, EFFA_2, and EFFA_3. Figure 11 (c) is used to illustrate the relative placement of color points and buried discrete field amplifiers. Thus, for clarity, certain layers and components that may be present in various embodiments of the invention are not shown in Figure 11(c). In addition, other layers and components in the display using one of the pixel design 1110 may not be present in the region of the pixel design 1110 shown in Figure 11(c). As shown in FIG. 11(c), one of the displays using the pixel design 1110 includes a lower transparent substrate 1121. A first passivation layer 1123 is formed on the transparent substrate 1121. Although not shown, a first metal layer is often formed on the substrate 1121 and is typically covered by the first passivation layer 1123. However, the first metal layer is not used in the portion of the pixel design 1110 shown in Fig. 11(c). Passivation layer 1123 is made using a transparent passivation material (eg, dielectric layer SiNx). In general, a layer of transparent conductive material (eg, ITO, or ZnO) is formed over passivation layer 1123 and etched to form buried discrete field amplifiers EFFA_1, EFFA_2, and EFFA_3. In some embodiments of the invention, a second metal layer can be formed over passivation layer 1123. A second passivation layer 1127 is formed over the buried discrete field amplifier EFFA_1 and also fills the gap left by the etch fabrication used to form the buried discrete field amplifiers EFFA_1, EFFA_2, and EFFA_3. A specific portion of the pixel design 1110 shown in FIG. 11(c) includes buried polarity regions EPR_1_1, EPR_2_1, and EPR_3_1, and the buried polarity regions EPR_1_1, EPR_2_1, and EPR_3_1 are etched through the middle of the color point and the passivation layer 1127. And formed. Therefore, in FIG. 11(c), the passivation layer 1127 appears as a plurality of portions. A color dot is formed on top of the passivation layer 1127. Generally, the color point is formed by depositing a layer of a conductive material (for example, ITO or IZO) on the second passivation layer 1127. Subsequently, the conductive layer is patterned and etched to form a color point. Therefore, as shown in FIG. 11(c), the color points CD_1_1, CD_2_1, and CD_3_1 are located on the top of the second passivation layer 1127. Since the perspective view of Fig. 11(c) is taken at the place where the buried polar region is located, the color points CD_1_1, CD_2_1, and CD_3_1 appear as two separate portions in Fig. 11(c). However, the actual shape of the color point is a square shape having a square hole at the center as shown in Fig. 11(a). In some embodiments of the invention, a buried discrete field amplifier is formed on a transparent substrate 1121.
圖11(d)示出顯示器1140之一部分,顯示器1140之該部分具有畫素設計1110之畫素P(0,0)、P(1,0)、P(0,1)、及P(1,1)。顯示器1140使用 一切換元件列反轉驅動模式。顯示器1140可具有數千列,且每一列上具有數千畫素。列與行將以圖11(d)所示之方式從圖11(d)所示之部分連續排列。為清楚起見,在圖11(d)中省略了用於控制切換元件之閘極線及源極線。在顯示器1140中,同一列上之畫素係以一水平畫素間距HPS間隔開,且鄰近列中之畫素係以一垂直畫素間距VPS間隔開。顯示器1140之畫素被設置成使位於一列中之所有畫素具有相同之點極性圖案(正的或負的),且每一連續列應在正的點極性圖案與負的點極性圖案之間交替。因此,第一列(即,列0)中之畫素P(0,0)及P(1,0)具有正的點極性圖案,且第二列(即,列1)中之畫素P(0,1)及P(1,1)具有負的點極性圖案。然而,在下一頁框中,畫素將切換點極性圖案。因此,一般而言,一畫素P(x,y)在y為偶數時具有一第一點極性圖案,而在y為奇數時具有一第二點極性圖案。畫素設計1110之內部導體1112提供極性至埋置離散場放大器。具體而言,一第一畫素之埋置離散場放大器係自一第二畫素接收電壓極性及電壓大小。更具體而言,該第二畫素係為位於該第一畫素上方之畫素。舉例而言,畫素P(0,0)之埋置離散場放大器EFFA_1係經由畫素P(0,1)之色點CD_1_2之電極而耦接至畫素P(0,1)之切換元件SE_1。 Figure 11 (d) shows a portion of the display 1140 having the pixels P10, 0, P(0, 1) ,1). Display 1140 use A switching element column inversion driving mode. Display 1140 can have thousands of columns with thousands of pixels on each column. The columns and rows will be successively arranged from the portion shown in Fig. 11(d) in the manner shown in Fig. 11(d). For the sake of clarity, the gate lines and source lines for controlling the switching elements are omitted in FIG. 11(d). In display 1140, the pixels on the same column are spaced apart by a horizontal pixel spacing HPS, and the pixels in adjacent columns are spaced apart by a vertical pixel spacing VPS. The pixels of display 1140 are arranged such that all pixels in a column have the same point polarity pattern (positive or negative), and each successive column should be between a positive dot polarity pattern and a negative dot polarity pattern. alternately. Therefore, the pixels P(0,0) and P(1,0) in the first column (ie, column 0) have a positive dot polarity pattern, and the pixel P in the second column (ie, column 1) (0, 1) and P (1, 1) have a negative dot polarity pattern. However, in the next page box, the pixels will switch the dot polarity pattern. Therefore, in general, a pixel P(x, y) has a first dot polarity pattern when y is an even number and a second dot polarity pattern when y is an odd number. The inner conductor 1112 of the pixel design 1110 provides a polarity to buried discrete field amplifier. Specifically, a buried discrete field amplifier of a first pixel receives voltage polarity and voltage from a second pixel. More specifically, the second pixel is a pixel located above the first pixel. For example, the embedded discrete field amplifier EFFA_1 of the pixel P(0,0) is coupled to the switching element of the pixel P(0,1) via the electrode of the color point CD_1_2 of the pixel P(0,1). SE_1.
作為另一選擇,在本發明之另一實施例中,一顯示器可針對每一列畫素具有埋置離散場放大器切換元件。相似地,埋置極性區域切換元件係用於圖7(d)中。然而,每一列畫素僅需要一個埋置離散場放大器切換元件。 Alternatively, in another embodiment of the invention, a display can have embedded discrete field amplifier switching elements for each column of pixels. Similarly, the buried polar region switching element is used in Figure 7(d). However, only one buried discrete field amplifier switching element is required for each column of pixels.
由於在顯示器1140中每一列上存在極性切換,故若一色點具有第一極性,則圍繞該色點之埋置離散場放大器將具有第二極性。舉例而言,畫素P(0,0)之色點CD_3_2具有正極性,而畫素P(0,0)之埋置離散場放大器EFFA_1具有負極性(來自畫素P(0,1)之切換元件SE_1)。在本發明之一特定實施例中,每一色點具有30微米之一寬度及35微米之一高度。每一埋置極性區域具有6微米之一寬度及6微米之一高度。每一埋置離散場放大器具有105微米之一寬度及105微米之一高度。水平點間距HDS1係為10微米,垂直點間距VDS1係為30微米,水平埋置電極延伸距離係為6微米,且垂直埋置電極延伸距離係為6微米。此外,水平畫素間距HPS係為微米,且垂直畫素間距VPS係為微米。 Since there is polarity switching on each column in display 1140, if a color point has a first polarity, the buried discrete field amplifier surrounding the color point will have a second polarity. For example, the color point CD_3_2 of the pixel P(0,0) has a positive polarity, and the buried discrete field amplifier EFFA_1 of the pixel P(0,0) has a negative polarity (from the pixel P(0,1) Switching element SE_1). In a particular embodiment of the invention, each color point has a width of one of 30 microns and a height of one of 35 microns. Each buried polar region has a width of one of 6 microns and a height of one of 6 microns. Each buried discrete field amplifier has a width of one of 105 microns and a height of one of 105 microns. The horizontal dot pitch HDS1 is 10 micrometers, the vertical dot pitch VDS1 is 30 micrometers, the horizontal buried electrode extends 6 micrometers, and the vertical buried electrode extends 6 micrometers. In addition, the horizontal pixel spacing HPS is micrometers and the vertical pixel spacing VPS is micrometers.
可輕易地修改畫素設計1110以用於具有切換元件行反轉驅動模式及切 換元件點反轉驅動模式之顯示器。圖11(e)及圖11(f)顯示一畫素設計1120(被標示為1120+及1120-)之不同點極性圖案。在實際操作中,一畫素將在每一影像頁框之間在一第一點極性圖案與一第二點極性圖案之間切換。畫素設計1120幾乎完全相同於畫素設計1110,因此不再予以贅述,而僅闡述其不同之處。具體而言,畫素設計1120與畫素設計1110之不同之處在於,切換元件SE_2、色點CD_2_1、色點CD_2_2之極性對於正的點極性係為負的且對於負的點極性係為正的。此外,埋置離散場放大器EFFA_2之極性對於正的點極性係為正的且對於負的點極性係為負的。 The pixel design 1110 can be easily modified for use with a switching element row inversion driving mode and cutting Change the display of the component dot inversion drive mode. Figures 11(e) and 11(f) show different dot polarity patterns for a pixel design 1120 (labeled 1120+ and 1120-). In actual operation, a pixel will switch between a first dot polarity pattern and a second dot polarity pattern between each image frame. The pixel design 1120 is almost identical to the pixel design 1110, so it will not be described again, but only the differences. Specifically, the pixel design 1120 is different from the pixel design 1110 in that the polarity of the switching element SE_2, the color point CD_2_1, and the color point CD_2_2 is negative for a positive point polarity and positive for a negative point polarity. of. Furthermore, the polarity of the buried discrete field amplifier EFFA_2 is positive for positive point polarities and negative for negative point polarities.
因此,在其中顯示畫素設計1120+之正的點極性圖案之圖11(e)中,切換元件SE_1及SE_3、色點CD_1_1、CD_1_2、CD_3_1、及CD_3_2、以及埋置離散場放大器EFFA_2具有正極性。然而,切換元件SE_2、色點CD_2_1及CD_2_2、以及埋置離散場放大器EFFA_1及EFFA_3具有負極性。圖11(f)顯示具有負的點極性圖案之畫素設計1120。對於負的點極性圖案,切換元件SE_1及SE_3、色點CD_1_1、CD_1_2、CD_3_1、及CD_3_2、以及埋置離散場放大器EFFA_2具有負極性。然而,切換元件SE_2、色點CD_2_1及CD_2_2、以及埋置離散場放大器EFFA_1及EFFA_3具有正極性。亦可將畫素設計1120修改成對於埋置離散場放大器使用中性極性。 Therefore, in FIG. 11(e) in which the dot polarity pattern of the pixel design 1120+ is displayed, the switching elements SE_1 and SE_3, the color points CD_1_1, CD_1_2, CD_3_1, and CD_3_2, and the buried discrete field amplifier EFFA_2 have positive electrodes. Sex. However, the switching element SE_2, the color points CD_2_1 and CD_2_2, and the buried discrete field amplifiers EFFA_1 and EFFA_3 have negative polarity. Figure 11 (f) shows a pixel design 1120 having a negative dot polarity pattern. For the negative dot polarity pattern, the switching elements SE_1 and SE_3, the color points CD_1_1, CD_1_2, CD_3_1, and CD_3_2, and the buried discrete field amplifier EFFA_2 have negative polarity. However, the switching element SE_2, the color points CD_2_1 and CD_2_2, and the buried discrete field amplifiers EFFA_1 and EFFA_3 have positive polarity. The pixel design 1120 can also be modified to use a neutral polarity for the buried discrete field amplifier.
除極性變化之外,亦可相較於畫素設計1110修改電極1112、1114及1116。一般而言,在切換元件點反轉驅動模式顯示器中,電極1112係耦接至位於當前畫素上方之一畫素之色點CD_1_2(參見圖11(g))。然而,在切換元件行反轉驅動模式顯示器中,電極1112係耦接至當前畫素之色點CD_2_1(參見圖11(h))。然而,在本發明之其他實施例中,在切換元件行反轉驅動模式顯示器中,電極1112係耦接至位於當前畫素左上方之一畫素之色點CD_3_2。一般而言,在切換元件點反轉驅動模式顯示器中,電極1114係耦接至位於當前畫素上方之一畫素之色點CD_2_2(參見圖11(g))。然而,在切換元件行反轉驅動模式顯示器中,電極1114係耦接至當前畫素之色點CD_3_1(參見圖11(h))。然而,在本發明之其他實施例中,在切換元件行反轉驅動模式顯示器中,電極1114係耦接至位於當前畫素左上方之一畫素之色點CD_1_2。一般而言,在切換元件點反轉驅動模式顯示器中,電極1116係耦接至位於當前畫素上方之一畫素之色點CD_3_2(參見圖11(g))。然而, 在切換元件行反轉驅動模式顯示器中,電極1116係耦接至位於當前畫素右側之一畫素之色點CD_1_1(參見圖11(h))。然而,在本發明之使用切換元件行反轉驅動模式顯示器之其他實施例中,電極1116係耦接至位於當前畫素左上方之一畫素之色點CD_2_2。 In addition to the polarity change, the electrodes 1112, 1114, and 1116 can also be modified as compared to the pixel design 1110. In general, in the switching element dot inversion driving mode display, the electrode 1112 is coupled to a color point CD_1_2 located at a pixel above the current pixel (see FIG. 11(g)). However, in the switching element row inversion driving mode display, the electrode 1112 is coupled to the color point CD_2_1 of the current pixel (see FIG. 11(h)). However, in other embodiments of the present invention, in the switching element row inversion driving mode display, the electrode 1112 is coupled to a color point CD_3_2 located at one of the left pixels of the current pixel. In general, in the switching element dot inversion driving mode display, the electrode 1114 is coupled to a color point CD_2_2 located at a pixel above the current pixel (see FIG. 11(g)). However, in the switching element row inversion driving mode display, the electrode 1114 is coupled to the color point CD_3_1 of the current pixel (see FIG. 11(h)). However, in other embodiments of the present invention, in the switching element row inversion driving mode display, the electrode 1114 is coupled to the color point CD_1_2 of one pixel located at the upper left of the current pixel. In general, in the switching element dot inversion driving mode display, the electrode 1116 is coupled to a color point CD_3_2 located at a pixel above the current pixel (see FIG. 11(g)). however, In the switching element row inversion driving mode display, the electrode 1116 is coupled to a color point CD_1_1 located at one of the pixels on the right side of the current pixel (see FIG. 11(h)). However, in other embodiments of the present invention using a switching element row inversion driving mode display, the electrode 1116 is coupled to a color point CD_2_2 located at a pixel on the upper left of the current pixel.
圖11(g)示出顯示器1160之一部分,顯示器1160之該部分具有畫素設計1120之畫素P(0,0)、P(1,0)、P(0,1)、及P(1,1)。顯示器1160使用一切換元件點反轉驅動模式。顯示器1160可具有數千列,且每一列上具有數千畫素。在顯示器1160中,同一列上之畫素係以一水平畫素間距HPS間隔開,且鄰近列中之畫素係以一垂直畫素間距VPS間隔開。列與行將以圖11(g)所示之方式從圖11(g)所示之部分連續排列。為清楚起見,在圖11(g)中省略了用於控制切換元件之閘極線及源極線。在顯示器1160中,畫素係被設置成使位於一列中之畫素交替地具有點極性圖案(正的或負的),且位於一行中之畫素亦在正的點極性圖案與負的點極性圖案之間交替。因此,畫素P(0,0)及P(1,1)具有正的點極性圖案,且畫素P(0,1)及P(1,0)具有負的點極性圖案。然而,在下一頁框中,畫素將切換點極性圖案。因此,一般而言,一畫素P(x,y)在x+y為偶數時具有一第一點極性圖案,而在x+y為奇數時具有一第二點極性圖案。 Figure 11 (g) shows a portion of the display 1160, which has pixels of the pixel design 1120 P(0,0), P(1,0), P(0,1), and P(1). ,1). Display 1160 uses a switching element dot inversion drive mode. Display 1160 can have thousands of columns with thousands of pixels on each column. In display 1160, the pixels on the same column are spaced apart by a horizontal pixel spacing HPS, and the pixels in adjacent columns are spaced apart by a vertical pixel spacing VPS. The columns and rows will be successively arranged from the portion shown in Fig. 11(g) in the manner shown in Fig. 11(g). For the sake of clarity, the gate lines and source lines for controlling the switching elements are omitted in FIG. 11(g). In the display 1160, the pixels are arranged such that the pixels located in one column alternately have a dot polarity pattern (positive or negative), and the pixels in one row are also at a positive dot polarity pattern and a negative point. The polarity patterns alternate between each other. Therefore, the pixels P(0, 0) and P(1, 1) have a positive dot polarity pattern, and the pixels P(0, 1) and P(1, 0) have a negative dot polarity pattern. However, in the next page box, the pixels will switch the dot polarity pattern. Therefore, in general, a pixel P(x, y) has a first dot polarity pattern when x+y is even, and a second dot polarity pattern when x+y is odd.
畫素設計1120亦可用於使用切換元件行反轉驅動模式之顯示器中。圖11(h)示出顯示器1180之一部分,顯示器1180之該部分具有畫素設計1120之畫素P(0,0)、P(1,0)、P(0,1)、及P(1,1)。顯示器1180可具有數千列,且每一列上具有數千畫素。在顯示器1180中,同一列上之畫素係以一水平畫素間距HPS間隔開,且鄰近列中之畫素係以一垂直畫素間距VPS間隔開。列與行將以圖11(h)所示之方式從圖11(h)所示之部分連續排列。為清楚起見,在圖11(h)中省略了用於控制切換元件之閘極線及源極線。在顯示器1180中,畫素係被設置成使位於一列中之畫素交替地具有點極性圖案(正的或負的),且位於一行中之畫素具有相同之點極性圖案。因此,畫素P(0,0)及P(0,1)具有正的點極性圖案,且畫素P(1,0)及P(1,1)具有負的點極性圖案。然而,在下一頁框中,畫素將切換點極性圖案。因此,一般而言,一畫素P(x,y)在x為偶數時具有一第一點極性圖案,而在x為奇數時具有一第二點極性圖案。 The pixel design 1120 can also be used in a display that uses a switching element row inversion driving mode. Figure 11 (h) shows a portion of the display 1180 having the pixels P (0, 0), P (1, 0), P (0, 1), and P (1) of the pixel design 1120. ,1). Display 1180 can have thousands of columns with thousands of pixels on each column. In display 1180, the pixels on the same column are spaced apart by a horizontal pixel spacing HPS, and the pixels in adjacent columns are spaced apart by a vertical pixel spacing VPS. The columns and rows will be successively arranged from the portion shown in Fig. 11(h) in the manner shown in Fig. 11(h). For the sake of clarity, the gate lines and source lines for controlling the switching elements are omitted in FIG. 11(h). In the display 1180, the pixels are arranged such that the pixels located in one column alternately have a dot polarity pattern (positive or negative), and the pixels located in one row have the same dot polarity pattern. Therefore, the pixels P(0, 0) and P(0, 1) have a positive dot polarity pattern, and the pixels P(1, 0) and P(1, 1) have a negative dot polarity pattern. However, in the next page box, the pixels will switch the dot polarity pattern. Therefore, in general, a pixel P(x, y) has a first dot polarity pattern when x is an even number and a second dot polarity pattern when x is an odd number.
埋置離散場放大器之使用並不限於具有埋置極性區域之畫素設計。此外,本發明之許多實施例使用多個埋置離散場放大器一畫素。舉例而言,圖12(a)及圖12(b)顯示一畫素設計1210(被標示為1210+及1210-)之不同點極性圖案,畫素設計1210包含三個埋置離散場放大器但不包含位於色點中之埋置極性區域。畫素設計1210常常用於具有一切換元件點反轉驅動模式或切換元件行反轉驅動模式之顯示器中。在實際操作中,一畫素將在每一影像頁框之間在一第一點極性圖案與一第二點極性圖案之間切換。 The use of buried discrete field amplifiers is not limited to pixel designs with buried polar regions. Moreover, many embodiments of the present invention use a plurality of buried discrete field amplifiers one pixel. For example, Figures 12(a) and 12(b) show different dot polarity patterns for a pixel design 1210 (labeled 1210+ and 1210-), and the pixel design 1210 includes three buried discrete field amplifiers but Does not contain buried polar regions located in the color point. The pixel design 1210 is often used in displays having a switching element dot inversion driving mode or a switching element row inversion driving mode. In actual operation, a pixel will switch between a first dot polarity pattern and a second dot polarity pattern between each image frame.
畫素設計1210具有三個色分量CC_1、CC_2及CC_3(在圖12(a)-11(b)中未標示出)。該三個色分量其中每一者包含二色點。為清楚起見,該等色點被表示成CD_X_Y,其中X係為一色分量(在圖12(a)-12(b)中係從1至3),且Y係為一色點編號(在圖12(a)-12(b)中係從1至2)。畫素設計1210亦針對每一色分量包含一切換元件(被表示為SE_1、SE_2、及SE_3),且針對每一色分量包含一埋置離散場放大器(被表示為EFFA_1、EFFA_2、及EFFA_3)。切換元件SE_1、SE_2及SE_3係排列成一列。埋置離散場放大器EFFA_1、EFFA_2、及EFFA_3亦排列成一列。 The pixel design 1210 has three color components CC_1, CC_2, and CC_3 (not shown in Figures 12(a)-11(b)). Each of the three color components includes a two color point. For the sake of clarity, the color points are represented as CD_X_Y, where X is a one-color component (from 1 to 3 in Figures 12(a)-12(b)), and Y is a color point number (in the figure) 12(a)-12(b) is from 1 to 2). The pixel design 1210 also includes a switching element (denoted as SE_1, SE_2, and SE_3) for each color component and a buried discrete field amplifier (denoted EFFA_1, EFFA_2, and EFFA_3) for each color component. The switching elements SE_1, SE_2 and SE_3 are arranged in a row. The buried discrete field amplifiers EFFA_1, EFFA_2, and EFFA_3 are also arranged in a column.
畫素設計1210之第一色分量CC_1具有二色點CD_1_1及CD_1_2。色點CD_1_1與CD_1_2形成一行,並以一垂直點間距VDS1間隔開。換言之,色點CD_1_1與CD_1_2係水平地配向並由垂直點間距VDS1垂直地間隔開。此外,色點CD_1_1與CD_1_2係垂直地錯開垂直點偏移量VDO1,垂直點偏移量VDO1係等於垂直點間距VDS1加上色點高度CDH。切換元件SE_1係位於色點CD_1_1上方。切換元件SE_1係耦接至色點CD_1_1及CD_1_2之電極,以控制色點CD_1_1及CD_1_2之電壓極性及電壓大小。 The first color component CC_1 of the pixel design 1210 has two color points CD_1_1 and CD_1_2. The color points CD_1_1 and CD_1_2 form a line and are spaced apart by a vertical dot pitch VDS1. In other words, the color points CD_1_1 and CD_1_2 are horizontally aligned and vertically spaced by the vertical dot pitch VDS1. Further, the color point CD_1_1 and the CD_1_2 are vertically shifted by the vertical dot offset VDO1, and the vertical dot offset VDO1 is equal to the vertical dot pitch VDS1 plus the color point height CDH. The switching element SE_1 is located above the color point CD_1_1. The switching element SE_1 is coupled to the electrodes of the color points CD_1_1 and CD_1_2 to control the voltage polarity and voltage of the color points CD_1_1 and CD_1_2.
相似地,畫素設計1210之第二色分量CC_2具有二色點CD_2_1及CD_2_2。色點CD_2_1與CD_2_2形成一第二行,並以一垂直點間距VDS1間隔開。因此,色點CD_2_1與CD_2_2係水平地配向並以垂直點間距VDS1垂直地間隔開。切換元件SE_2係位於色點CD_2_1上方。切換元件SE_2係耦接至色點CD_2_1及CD_2_2之電極,以控制色點CD_2_1及CD_2_2之電壓極性及電壓大小。第二色分量CC_2係與第一色分量CC_1垂直地配向,並以一水平點間距HDS1與色分量CC_1間隔開,因此色分量CC_2與CC_1係水平地錯開一水平點偏移量HDO1,水平點偏移量HDO1係等於水 平點間距HDS1加上色點寬度CDW。具體關於色點而言,色點CD_2_1與色點CD_1_1係垂直地配向並以水平點間距HDS1水平地間隔開。相似地,色點CD_2_2與色點CD_2_1係垂直地配向並以水平點間距HDS1水平地間隔開。因此,色點CD_1_1與色點CD_2_1形成一第一列色點,且色點CD_1_2與色點CD_2_2形成一第二列色點。 Similarly, the second color component CC_2 of the pixel design 1210 has two color points CD_2_1 and CD_2_2. The color points CD_2_1 and CD_2_2 form a second line and are spaced apart by a vertical dot pitch VDS1. Therefore, the color points CD_2_1 and CD_2_2 are horizontally aligned and vertically spaced apart by the vertical dot pitch VDS1. The switching element SE_2 is located above the color point CD_2_1. The switching element SE_2 is coupled to the electrodes of the color points CD_2_1 and CD_2_2 to control the voltage polarity and voltage of the color points CD_2_1 and CD_2_2. The second color component CC_2 is vertically aligned with the first color component CC_1, and is spaced apart by a horizontal dot pitch HDS1 and the color component CC_1. Therefore, the color components CC_2 and CC_1 are horizontally shifted by a horizontal point offset HDD1, the horizontal point. Offset HDO1 is equal to water Flat dot spacing HDS1 plus color point width CDW. Specifically, regarding the color point, the color point CD_2_1 and the color point CD_1_1 are vertically aligned and horizontally spaced by the horizontal dot pitch HDS1. Similarly, the color point CD_2_2 is vertically aligned with the color point CD_2_1 and horizontally spaced by the horizontal dot pitch HDS1. Therefore, the color point CD_1_1 and the color point CD_2_1 form a first column color point, and the color point CD_1_2 and the color point CD_2_2 form a second column color point.
相似地,畫素1210之第三色分量CC_3具有二色點CD_3_1及CD_3_2。色點CD_3_1與CD_3_2形成一第三行,並以一垂直點間距VDS1間隔開。因此,色點CD_3_1與CD_3_2係水平地配向並以垂直點間距VDS1垂直地間隔開。切換元件SE_3係位於色點CD_3_1上方。切換元件SE_3係耦接至色點CD_3_1及CD_3_2之電極,以控制色點CD_3_1及CD_3_2之電壓極性及電壓大小。第三色分量CC_3係與第二色分量CC_2垂直地配向,並以水平點間距HDS1與色分量CC_2間隔開,因此色分量CC_3與CC_2係水平地錯開一水平點偏移量HDO1。具體關於色點而言,色點CD_3_1與色點CD_2_1係垂直地配向並以水平點間距HDS1水平地間隔開。相似地,色點CD_3_2與色點CD_2_2係垂直地配向並以水平點間距HDS1水平地間隔開。因此,色點CD_3_1係位於第一列色點上,且色點CD_3_2係位於第二列色點上。 Similarly, the third color component CC_3 of the pixel 1210 has two color points CD_3_1 and CD_3_2. The color points CD_3_1 and CD_3_2 form a third line and are spaced apart by a vertical dot pitch VDS1. Therefore, the color points CD_3_1 and CD_3_2 are horizontally aligned and vertically spaced apart by the vertical dot pitch VDS1. The switching element SE_3 is located above the color point CD_3_1. The switching element SE_3 is coupled to the electrodes of the color points CD_3_1 and CD_3_2 to control the voltage polarity and voltage of the color points CD_3_1 and CD_3_2. The third color component CC_3 is vertically aligned with the second color component CC_2, and is spaced apart from the color component CC_2 by the horizontal dot pitch HDS1, so that the color components CC_3 and CC_2 are horizontally shifted by a horizontal dot offset amount HDO1. Specifically, regarding the color point, the color point CD_3_1 and the color point CD_2_1 are vertically aligned and horizontally spaced by the horizontal dot pitch HDS1. Similarly, the color point CD_3_2 is vertically aligned with the color point CD_2_2 and horizontally spaced by the horizontal dot pitch HDS1. Therefore, the color point CD_3_1 is located on the first column color point, and the color point CD_3_2 is located on the second column color point.
為清楚起見,以具有相同色點高度CDH之色點來例示畫素設計1210之各色點。然而,本發明之某些實施例可包含具有不同色點高度之色點。舉例而言,在本發明之一實施例(其為畫素設計1210之一變體)中,色點CD_1_1、CD_2_1、及CD_3_1之色點高度小於色點CD_1_2、CD_2_2、及CD_3_2之色點高度。此外,在本發明之許多實施例中,色點可具有不同形狀。 For the sake of clarity, the various color points of the pixel design 1210 are illustrated with color points having the same color point height CDH. However, certain embodiments of the invention may include color points having different color point heights. For example, in one embodiment of the present invention, which is a variant of the pixel design 1210, the color point heights of the color points CD_1_1, CD_2_1, and CD_3_1 are smaller than the color point heights of the color points CD_1_2, CD_2_2, and CD_3_2. . Moreover, in many embodiments of the invention, the color points can have different shapes.
畫素設計1210亦包含埋置離散場放大器EFFA_1、EFFA_2、及EFFA_3。如圖12(a)所示,埋置離散場放大器EFFA_1、EFFA_2、及EFFA_3係被放置於畫素設計1210之色點後面。具體而言,埋置離散場放大器EFFA_1係被放置成使色點CD_1_1及色點CD_1_2及切換元件SE_1位於埋置離散場放大器EFFA_1前面。然而,埋置離散場放大器EFFA_1延伸超過色點CD_1_1及CD_1_2之左側及右側達一水平埋置電極延伸距離HEEED1。相似地,埋置離散場放大器EFFA_1延伸超過切換元件SE_1之 頂部及色點CD_1_2之底部達一垂直埋置電極延伸距離VEEED1。因此,色點CD_1_1及CD_1_2之邊緣係位於埋置離散場放大器EFFA_1之部分前面。一電極1212係用於將埋置離散場放大器EFFA_1耦接至一電壓源。一般而言,在切換元件點反轉驅動模式顯示器中,電極1212係耦接至位於當前畫素上方之一畫素之色點CD_1_2(參見圖12(c))。然而,在切換元件行反轉驅動模式顯示器中,電極1212係耦接至位於當前畫素左上方之一畫素之色點CD_3_2(參見圖12(d),畫素P(1,0))。 The pixel design 1210 also includes embedded discrete field amplifiers EFFA_1, EFFA_2, and EFFA_3. As shown in FIG. 12(a), the buried discrete field amplifiers EFFA_1, EFFA_2, and EFFA_3 are placed behind the color point of the pixel design 1210. Specifically, the buried discrete field amplifier EFFA_1 is placed such that the color point CD_1_1 and the color point CD_1_2 and the switching element SE_1 are located in front of the buried discrete field amplifier EFFA_1. However, the buried discrete field amplifier EFFA_1 extends beyond the left and right sides of the color points CD_1_1 and CD_1_2 to a horizontal buried electrode extension distance HEEED1. Similarly, the buried discrete field amplifier EFFA_1 extends beyond the switching element SE_1 The top of the top and the color point CD_1_2 reaches a vertical buried electrode extending distance VEEED1. Therefore, the edges of the color points CD_1_1 and CD_1_2 are located in front of the portion of the buried discrete field amplifier EFFA_1. An electrode 1212 is used to couple the buried discrete field amplifier EFFA_1 to a voltage source. In general, in the switching element dot inversion driving mode display, the electrode 1212 is coupled to a color point CD_1_2 located at a pixel above the current pixel (see FIG. 12(c)). However, in the switching element row inversion driving mode display, the electrode 1212 is coupled to a color point CD_3_2 located at the upper left of the current pixel (see FIG. 12(d), pixel P(1, 0)). .
相似地,埋置離散場放大器EFFA_2係被放置成使色點CD_2_1及色點CD_2_2及切換元件SE_2位於埋置離散場放大器EFFA_2前面。然而,埋置離散場放大器EFFA_2延伸超過色點CD_2_1及CD_2_2之左側及右側達一水平埋置電極延伸距離HEEED1。相似地,埋置離散場放大器EFFA_2延伸超過切換元件SE_2之頂部及色點CD_2_2之底部達一垂直埋置電極延伸距離VEEED1。因此,色點CD_2_1及CD_2_2之邊緣係位於埋置離散場放大器EFFA_2之部分前面。此外,埋置離散場放大器EFFA_2係與埋置離散場放大器EFFA_1垂直地配向,並以一水平埋置電極間距HEES1與埋置離散場放大器EFFA_1間隔開。一電極1214係用於將埋置離散場放大器EFFA_1耦接至一電壓源。一般而言,在切換元件點反轉驅動模式顯示器中,電極1214係耦接至位於當前畫素上方之一畫素之色點CD_2_2(參見圖12(c))。然而,在切換元件行反轉驅動模式顯示器中,電極1214係耦接至位於當前畫素上方之一畫素之色點CD_1_2(參見圖12(d),畫素P(1,0))。 Similarly, the buried discrete field amplifier EFFA_2 is placed such that the color point CD_2_1 and the color point CD_2_2 and the switching element SE_2 are located in front of the buried discrete field amplifier EFFA_2. However, the buried discrete field amplifier EFFA_2 extends beyond the left and right sides of the color points CD_2_1 and CD_2_2 to a horizontal buried electrode extension distance HEEED1. Similarly, the buried discrete field amplifier EFFA_2 extends beyond the top of the switching element SE_2 and the bottom of the color point CD_2_2 to a vertical buried electrode extension distance VEEED1. Therefore, the edges of the color points CD_2_1 and CD_2_2 are located in front of the portion of the buried discrete field amplifier EFFA_2. In addition, the buried discrete field amplifier EFFA_2 is vertically aligned with the buried discrete field amplifier EFFA_1 and spaced apart from the buried discrete field amplifier EFFA_1 by a horizontal buried electrode pitch HEES1. An electrode 1214 is used to couple the buried discrete field amplifier EFFA_1 to a voltage source. In general, in the switching element dot inversion driving mode display, the electrode 1214 is coupled to a color point CD_2_2 located at a pixel above the current pixel (see FIG. 12(c)). However, in the switching element row inversion driving mode display, the electrode 1214 is coupled to the color point CD_1_2 of one pixel above the current pixel (see FIG. 12(d), pixel P(1, 0)).
相似地,埋置離散場放大器EFFA_3係被放置成使色點CD_3_1及色點CD_3_2及切換元件SE_3位於埋置離散場放大器EFFA_3前面。然而,埋置離散場放大器EFFA_3延伸超過色點CD_3_1及CD_3_2之左側及右側達一水平埋置電極延伸距離HEEED1。相似地,埋置離散場放大器EFFA_3延伸超過切換元件SE_3之頂部及色點CD_3_2之底部達一垂直埋置電極延伸距離VEEED1。因此,色點CD_3_1及CD_3_2之邊緣係位於埋置離散場放大器EFFA_3之部分前面。此外,埋置離散場放大器EFFA_3係與埋置離散場放大器EFFA_2垂直地配向,並以一水平埋置電極間距HEES1與埋置離散場放大器EFFA_2間隔開。一電極1216係用於將埋置離散場放大器EFFA_1耦接至一電壓源。一般而言,在切換元件點反轉驅動模式顯示器 中,電極1216係耦接至位於當前畫素上方之一畫素之色點CD_3_2(參見圖12(c))。然而,在切換元件行反轉驅動模式顯示器中,電極1216係耦接至位於當前畫素上方之一畫素之色點CD_2_2(參見圖12(d),畫素P(1,0))。 Similarly, the buried discrete field amplifier EFFA_3 is placed such that the color point CD_3_1 and the color point CD_3_2 and the switching element SE_3 are located in front of the buried discrete field amplifier EFFA_3. However, the buried discrete field amplifier EFFA_3 extends beyond the left and right sides of the color points CD_3_1 and CD_3_2 to a horizontal buried electrode extension distance HEEED1. Similarly, the buried discrete field amplifier EFFA_3 extends beyond the top of the switching element SE_3 and the bottom of the color point CD_3_2 to a vertical buried electrode extension distance VEEED1. Therefore, the edges of the color points CD_3_1 and CD_3_2 are located in front of the portion of the buried discrete field amplifier EFFA_3. In addition, the buried discrete field amplifier EFFA_3 is vertically aligned with the buried discrete field amplifier EFFA_2 and spaced apart from the buried discrete field amplifier EFFA_2 by a horizontal buried electrode pitch HEES1. An electrode 1216 is used to couple the buried discrete field amplifier EFFA_1 to a voltage source. In general, in the switching element point inversion drive mode display The electrode 1216 is coupled to a color point CD_3_2 located at a pixel above the current pixel (see FIG. 12(c)). However, in the switching element row inversion driving mode display, the electrode 1216 is coupled to the color point CD_2_2 of one pixel above the current pixel (see FIG. 12(d), pixel P(1, 0)).
使用「+」及「-」符號來顯示色點、埋置離散場放大器、及切換元件之極性。因此,在其中顯示畫素設計1210+之正的點極性圖案之圖12(a)中,切換元件SE_1及SE_3、色點CD_1_1、CD_1_2、CD_3_1、及CD_3_2、以及埋置離散場放大器EFFA_2具有正極性。然而,切換元件SE_2、色點CD_2_1及CD_2_2、以及埋置離散場放大器EFFA_1及EFFA_3具有負極性。圖12(b)顯示具有負的點極性圖案之畫素設計1210。對於負的點極性圖案,切換元件SE_1及SE_3、色點CD_1_1、CD_1_2、CD_3_1、及CD_3_2、以及埋置離散場放大器EFFA_2具有負極性。然而,切換元件SE_2、色點CD_2_1及CD_2_2、以及埋置離散場放大器EFFA_1及EFFA_3具有正極性。本發明之其他實施例可對於埋置離散場放大器EFFA_1、EFFA_2、及EFFA_3使用一中性極性。舉例而言,在本發明之一特定實施例中,埋置離散場放大器EFFA_1、EFFA_2、及EFFA_3係耦接至共同電壓V_com。 Use the "+" and "-" symbols to display the color point, the embedded discrete field amplifier, and the polarity of the switching components. Therefore, in FIG. 12(a) in which the dot polarity pattern of the pixel design 1210+ is displayed, the switching elements SE_1 and SE_3, the color points CD_1_1, CD_1_2, CD_3_1, and CD_3_2, and the buried discrete field amplifier EFFA_2 have positive electrodes. Sex. However, the switching element SE_2, the color points CD_2_1 and CD_2_2, and the buried discrete field amplifiers EFFA_1 and EFFA_3 have negative polarity. Figure 12(b) shows a pixel design 1210 with a negative dot polarity pattern. For the negative dot polarity pattern, the switching elements SE_1 and SE_3, the color points CD_1_1, CD_1_2, CD_3_1, and CD_3_2, and the buried discrete field amplifier EFFA_2 have negative polarity. However, the switching element SE_2, the color points CD_2_1 and CD_2_2, and the buried discrete field amplifiers EFFA_1 and EFFA_3 have positive polarity. Other embodiments of the invention may use a neutral polarity for the buried discrete field amplifiers EFFA_1, EFFA_2, and EFFA_3. For example, in a particular embodiment of the invention, the buried discrete field amplifiers EFFA_1, EFFA_2, and EFFA_3 are coupled to a common voltage V_com.
圖12(c)示出顯示器1220之一部分,顯示器1220之該部分具有畫素設計1010之畫素P(0,0)、P(1,0)、P(0,1)、及P(1,1)。顯示器1220使用一切換元件點反轉驅動模式。顯示器1220可具有數千列,且每一列上具有數千畫素。在顯示器1220中,同一列上之畫素係以一水平畫素間距HPS間隔開,且鄰近列中之畫素係以一垂直畫素間距VPS間隔開。列與行將以圖12(c)所示之方式從圖12(c)所示之部分連續排列。為清楚起見,在圖12(c)中省略了用於控制切換元件之閘極線及源極線。在顯示器1220中,畫素係被設置成使位於一列中之畫素交替地具有點極性圖案(正的或負的),且位於一行中之畫素亦於正的點極性圖案與負的點極性圖案之間交替。因此,畫素P(0,0)及P(1,1)具有正的點極性圖案,且畫素P(0,1)及P(1,0)具有負的點極性圖案。然而,在下一頁框中,畫素將切換點極性圖案。因此,一般而言,一畫素P(x,y)在x+y為偶數時具有一第一點極性圖案,而在x+y為奇數時具有一第二點極性圖案。 Figure 12 (c) shows a portion of display 1220 having pixels of pixel design 1010 P(0,0), P(1,0), P(0,1), and P(1). ,1). Display 1220 uses a switching element dot inversion drive mode. Display 1220 can have thousands of columns with thousands of pixels on each column. In display 1220, the pixels on the same column are spaced apart by a horizontal pixel spacing HPS, and the pixels in adjacent columns are spaced apart by a vertical pixel spacing VPS. The columns and rows will be successively arranged from the portion shown in Fig. 12(c) in the manner shown in Fig. 12(c). For the sake of clarity, the gate lines and source lines for controlling the switching elements are omitted in Figure 12(c). In the display 1220, the pixels are arranged such that the pixels located in one column alternately have a dot polarity pattern (positive or negative), and the pixels in one row are also in a positive dot polarity pattern and a negative point. The polarity patterns alternate between each other. Therefore, the pixels P(0, 0) and P(1, 1) have a positive dot polarity pattern, and the pixels P(0, 1) and P(1, 0) have a negative dot polarity pattern. However, in the next page box, the pixels will switch the dot polarity pattern. Therefore, in general, a pixel P(x, y) has a first dot polarity pattern when x+y is even, and a second dot polarity pattern when x+y is odd.
畫素設計1210亦可用於使用切換元件行反轉驅動模式之顯示器中。圖12(d)示出顯示器1230之一部分,顯示器1230之該部分具有畫素設計1210 之畫素P(0,0)、P(1,0)、P(0,1)、及P(1,1)。顯示器1230可具有數千列,且每一列上具有數千畫素。在顯示器1230中,同一列上之畫素係以一水平畫素間距HPS間隔開,且鄰近列中之畫素係以一垂直畫素間距VPS間隔開。列與行將以圖12(d)所示之方式從圖12(d)所示之部分連續排列。為清楚起見,在圖12(d)中省略了用於控制切換元件之閘極線及源極線。在顯示器1230中,畫素係被設置成使位於一列中之畫素交替地具有點極性圖案(正的或負的),且位於一行中之畫素具有相同之點極性圖案。因此,畫素P(0,0)及P(0,1)具有正的點極性圖案,且畫素P(1,0)及P(1,1)具有負的點極性圖案。然而,在下一頁框中,畫素將切換點極性圖案。因此,一般而言,一畫素P(x,y)在x為偶數時具有一第一點極性圖案,而在x為奇數時具有一第二點極性圖案。 The pixel design 1210 can also be used in a display that uses a switching element row inversion driving mode. Figure 12 (d) shows a portion of display 1230, which has a pixel design 1210 The pixels P(0,0), P(1,0), P(0,1), and P(1,1). Display 1230 can have thousands of columns with thousands of pixels on each column. In display 1230, the pixels on the same column are spaced apart by a horizontal pixel spacing HPS, and the pixels in adjacent columns are spaced apart by a vertical pixel spacing VPS. The columns and rows will be successively arranged from the portion shown in Fig. 12(d) in the manner shown in Fig. 12(d). For the sake of clarity, the gate lines and source lines for controlling the switching elements are omitted in Figure 12(d). In display 1230, the pixels are arranged such that pixels located in a column alternately have a dot polarity pattern (positive or negative), and pixels located in one row have the same dot polarity pattern. Therefore, the pixels P(0, 0) and P(0, 1) have a positive dot polarity pattern, and the pixels P(1, 0) and P(1, 1) have a negative dot polarity pattern. However, in the next page box, the pixels will switch the dot polarity pattern. Therefore, in general, a pixel P(x, y) has a first dot polarity pattern when x is an even number and a second dot polarity pattern when x is an odd number.
圖13(a)及圖13(b)顯示一畫素設計1310(被標示為1310+及1310-)之不同點極性圖案,畫素設計1310可與具有切換元件列反轉驅動模式之顯示器一起使用。畫素設計1310之佈局與畫素設計1210相同,因此將不再予以贅述。然而,畫素設計1310中之埋置離散場放大器EFFA_2、切換元件SE_2、以及色點CD_2_1及CD_2_2之極性相較於畫素設計1210反轉。因此,在其中顯示畫素設計1310+之正的點極性圖案之圖13(a)中,切換元件SE_1、SE_2及SE_3、色點CD_1_1、CD_1_2、CD_2_1、CD_2_2、CD_3_1、及CD_3_2具有正極性。然而,埋置離散場放大器EFFA_1、EFFA_2、及EFFA_3具有負極性。圖13(b)顯示具有負的點極性圖案之畫素設計1310。對於負的點極性圖案,切換元件SE_1、SE_2、及SE_3、色點CD_1_1、CD_1_2、CD_2_1、CD_2_2、CD_3_1、及CD_3_2具有負極性。然而,埋置離散場放大器EFFA_1、EFFA_2及EFFA_3具有正極性。在本發明之其他實施例中,埋置離散場放大器EFFA_1、EFFA_2及EFFA_3具有中性極性。 Figures 13(a) and 13(b) show different dot polarity patterns for a pixel design 1310 (labeled 1310+ and 1310-), and the pixel design 1310 can be used with a display having a switching element column inversion driving mode. use. The layout of the pixel design 1310 is the same as the pixel design 1210 and will not be described again. However, the polarity of the buried discrete field amplifier EFFA_2, the switching element SE_2, and the color points CD_2_1 and CD_2_2 in the pixel design 1310 is reversed compared to the pixel design 1210. Therefore, in FIG. 13(a) in which the dot polarity pattern of the pixel design 1310+ is displayed, the switching elements SE_1, SE_2, and SE_3, the color points CD_1_1, CD_1_2, CD_2_1, CD_2_2, CD_3_1, and CD_3_2 have positive polarity. However, the buried discrete field amplifiers EFFA_1, EFFA_2, and EFFA_3 have negative polarity. Figure 13 (b) shows a pixel design 1310 having a negative dot polarity pattern. For the negative dot polarity pattern, the switching elements SE_1, SE_2, and SE_3, the color points CD_1_1, CD_1_2, CD_2_1, CD_2_2, CD_3_1, and CD_3_2 have negative polarity. However, the buried discrete field amplifiers EFFA_1, EFFA_2, and EFFA_3 have positive polarity. In other embodiments of the invention, the buried discrete field amplifiers EFFA_1, EFFA_2, and EFFA_3 have a neutral polarity.
圖13(c)示出顯示器1320之一部分,顯示器1320之該部分具有畫素設計1310之畫素P(0,0)、P(1,0)、P(0,1)、及P(1,1)。顯示器1320使用一切換元件列反轉驅動模式。顯示器1320可具有數千列,且每一列上具有數千畫素。在顯示器1320中,同一列上之畫素係以一水平畫素間距HPS間隔開,且鄰近列中之畫素係以一垂直畫素間距VPS間隔開。列與行將以 圖13(c)所示之方式從圖13(c)所示之部分連續排列。為清楚起見,在圖13(c)中省略了用於控制切換元件之閘極線及源極線。顯示器1320之畫素被設置成使位於一列中之所有畫素具有相同之點極性圖案(正的或負的),且每一連續列應在正的點極性圖案與負的點極性圖案之間交替。因此,第一列(即,列0)中之畫素P(0,0)及P(1,0)具有正的點極性圖案,且第二列(即,列1)中之畫素P(0,1)及P(1,1)具有負的點極性圖案。然而,在下一頁框中,畫素將切換點極性圖案。因此,一般而言,一畫素P(x,y)在y為偶數時具有一第一點極性圖案,而在y為奇數時具有一第二點極性圖案。 Figure 13 (c) shows a portion of the display 1320, which has pixels of the pixel design 1310 P(0,0), P(1,0), P(0,1), and P(1). ,1). Display 1320 uses a switching element column inversion drive mode. Display 1320 can have thousands of columns with thousands of pixels on each column. In display 1320, the pixels on the same column are spaced apart by a horizontal pixel spacing HPS, and the pixels in adjacent columns are spaced apart by a vertical pixel spacing VPS. Columns and rows will be The mode shown in Fig. 13(c) is continuously arranged from the portion shown in Fig. 13(c). For the sake of clarity, the gate lines and source lines for controlling the switching elements are omitted in FIG. 13(c). The pixels of display 1320 are arranged such that all pixels in a column have the same point polarity pattern (positive or negative), and each successive column should be between a positive dot polarity pattern and a negative dot polarity pattern. alternately. Therefore, the pixels P(0,0) and P(1,0) in the first column (ie, column 0) have a positive dot polarity pattern, and the pixel P in the second column (ie, column 1) (0, 1) and P (1, 1) have a negative dot polarity pattern. However, in the next page box, the pixels will switch the dot polarity pattern. Therefore, in general, a pixel P(x, y) has a first dot polarity pattern when y is an even number and a second dot polarity pattern when y is an odd number.
包含埋置離散場放大器之一缺點係為:需要額外能量來使埋置離散場放大器偏極化。此額外能量需要量係與埋置離散場放大器之尺寸成正比。因此,本發明之許多實施例使用具有一更小面積之埋置離散場放大器來取代矩形埋置離散場放大器。因埋置離散場放大器係用於在色點之邊緣處放大離散場,故埋置離散場放大器之最大程度地放大離散場之部分係為靠近色點邊緣之部分。因此,可去除埋置離散場放大器之位於色點之中間後面之部分。因此,舉例而言,本發明之一實施例使用圖14所示埋置離散場放大器來取代以上所示之矩形埋置離散場放大器。 One of the disadvantages of including a buried discrete field amplifier is that additional energy is required to bias the buried discrete field amplifier. This additional energy requirement is proportional to the size of the buried discrete field amplifier. Thus, many embodiments of the present invention use a buried discrete field amplifier having a smaller area instead of a rectangular buried discrete field amplifier. Since the buried discrete field amplifier is used to amplify the discrete field at the edge of the color point, the portion of the discrete field amplifier that is buried to maximize the discrete field is near the edge of the color point. Therefore, the portion of the buried discrete field amplifier located behind the middle of the color point can be removed. Thus, for example, one embodiment of the present invention replaces the rectangular buried discrete field amplifier shown above with the buried discrete field amplifier shown in FIG.
圖14顯示一埋置離散場放大器1400。為清楚起見,將埋置離散場放大器1400在概念上劃分成垂直埋置部及水平埋置部。具體而言,埋置離散場放大器1400包含二垂直埋置部VEP_1及VEP_2以及三個水平埋置部HEP_1、HEP_2、及HEP_3。針對其中使用埋置離散場放大器1400取代畫素設計13(a)之埋置離散場放大器EFFA_1之情形來闡述垂直埋置部及水平埋置部之位置。垂直埋置部VEP_1係位於色點CD_1_1及CD_1_2之右邊緣後面(圖13(a))。垂直埋置部VEP_2係位於色點CD_1_1及CD_1_2之左邊緣後面(圖13(a))。水平埋置部HEP_1係位於色點CD_1_2之底部邊緣後面;水平埋置部HEP_2係位於色點CD_1_2之上邊緣及色點CD_1_1之下邊緣後面;且水平埋置部HEP_3係位於色點CD_1_1之上邊緣後面。如圖14所示,水平埋置部HEP_2係寬於水平埋置部HEP_1及HEP_3。水平埋置部HEP_2之額外寬度係用於兩個目的。首先,水平埋置部HEP_2較寬之原因係僅因其位於色點CD_1_2之上邊緣及色點CD_1_1之下邊緣二者後面,以放大色點CD_1_1與CD_1_2二者之離散場。其次,水平埋置部 HEP_2可用作色點CD_1_1及CD_1_2之一儲存電容器。面積愈大便會提供愈大之電荷儲存容量。在本發明之一特定實施例中,色點CD_1_1具有28微米之一寬度(水平)及30微米之一長度(垂直),色點CD_1_2具有28微米之一寬度及30微米之一高度,水平埋置部HEP_1具有30微米之一寬度及3微米之一高度;水平埋置部HEP_2具有28微米之一寬度及5微米之一高度;水平埋置部HEP_3具有15微米之一寬度及3微米之一高度;垂直埋置部VEP_1具有3微米之一寬度及95微米之一高度;且垂直埋置部VEP_2具有3微米之一寬度及80微米之一高度。 Figure 14 shows a buried discrete field amplifier 1400. For the sake of clarity, the buried discrete field amplifier 1400 is conceptually divided into a vertical buried portion and a horizontal buried portion. Specifically, the buried discrete field amplifier 1400 includes two vertical buried portions VEP_1 and VEP_2 and three horizontal buried portions HEP_1, HEP_2, and HEP_3. The position of the vertical embedding portion and the horizontal embedding portion will be described for the case where the buried discrete field amplifier 1400 is used instead of the buried discrete field amplifier EFFA_1 of the pixel design 13(a). The vertical embedding portion VEP_1 is located behind the right edges of the color points CD_1_1 and CD_1_2 (Fig. 13(a)). The vertical embedding portion VEP_2 is located behind the left edges of the color points CD_1_1 and CD_1_2 (Fig. 13(a)). The horizontal embedding portion HEP_1 is located behind the bottom edge of the color point CD_1_2; the horizontal embedding portion HEP_2 is located at the upper edge of the color point CD_1_2 and behind the lower edge of the color point CD_1_1; and the horizontal embedding portion HEP_3 is located above the color point CD_1_1 Behind the edge. As shown in FIG. 14, the horizontal embedding portion HEP_2 is wider than the horizontal embedding portions HEP_1 and HEP_3. The extra width of the horizontal buried portion HEP_2 is used for two purposes. First, the reason why the horizontal embedding portion HEP_2 is wider is because it is located behind the upper edge of the color point CD_1_2 and the lower edge of the color point CD_1_1 to enlarge the discrete fields of the color points CD_1_1 and CD_1_2. Second, the horizontal embedding department HEP_2 can be used as a storage capacitor for one of the color points CD_1_1 and CD_1_2. The larger the area, the larger the charge storage capacity. In a particular embodiment of the invention, the color point CD_1_1 has a width (horizontal) of 28 microns and a length (vertical) of 30 microns, and the color point CD_1_2 has a width of 28 microns and a height of 30 microns, horizontally buried The portion HEP_1 has a width of one micron and a height of three micrometers; the horizontal embedding portion HEP_2 has a width of one of 28 micrometers and a height of one micrometer; the horizontal embedding portion HEP_3 has one width of 15 micrometers and one of three micrometers. The height; the vertical embedding portion VEP_1 has a width of one micrometer and a height of 95 micrometers; and the vertical embedding portion VEP_2 has a width of one micrometer and one height of 80 micrometers.
使用僅沿色點之邊緣延伸之埋置離散場放大器之另一優點係為:埋置離散場放大器不需要使用一透明導電材料形成。因此,可使用用於顯示器之其他部件(例如,切換元件、源極線、及資料線)之非透明材料(例如,金屬層)來形成埋置離散場放大器1400(以及以下所述之其他埋置離散場放大器)。因此,可使用單一ITO層而非二ITO層來製成本發明之實施例。減少層之數目會降低一顯示器之製造成本,乃因製造步驟之數目及掩模之數目會減少。 Another advantage of using a buried discrete field amplifier that extends only along the edges of the color point is that the buried discrete field amplifier does not need to be formed using a transparent conductive material. Thus, a non-transparent material (eg, a metal layer) for other components of the display (eg, switching elements, source lines, and data lines) can be used to form the buried discrete field amplifier 1400 (and other buried as described below) Set the discrete field amplifier). Thus, embodiments of the invention can be made using a single ITO layer rather than a two ITO layer. Reducing the number of layers reduces the manufacturing cost of a display because the number of manufacturing steps and the number of masks are reduced.
如上所述,在本發明之某些實施例中,用於形成埋置離散場放大器之層亦用於一切換元件中。因此,對於該等實施例,埋置離散場放大器未延伸至切換元件。圖15顯示一埋置離散場放大器1500,其未延伸至切換元件。為清楚起見,將埋置離散場放大器1500在概念上劃分成垂直埋置部及水平埋置部。具體而言,埋置離散場放大器1500包含二垂直埋置部VEP_1及VEP_2、三個水平埋置部HEP_1、HEP_2、及HEP_3、以及一可選之第四水平埋置部HEP_4。針對其中使用埋置離散場放大器1500取代畫素設計13(a)之埋置離散場放大器EFFA_1之情形來闡述垂直埋置部及水平埋置部之位置。垂直埋置部VEP_1係位於色點CD_1_1及CD_1_2之右邊緣後面(圖13(a))。垂直埋置部VEP_2係位於色點CD_1_2之左邊緣後面及色點CD_1_1之左邊緣之一部分後面(圖13(a))。具體而言,垂直埋置部VEP_2未延伸至色點CD_1_1之左上角之切換元件SE_1所定位處。水平埋置部HEP_1係位於色點CD_1_2之底部邊緣後面;水平埋置部HEP_2係位於色點CD_1_2之上邊緣及色點CD_1_1之下邊緣後面;且水平埋置部HEP_3係位於色點CD_1_1之上邊緣之一部分後面。具體而言,水平埋置部HEP_3 未延伸至色點CD_1_1之左上角之切換元件SE_1所定位處。與上述關於埋置離散場放大器1400之水平埋置部HEP_3所述之原因相同,埋置離散場放大器1500之水平埋置部HEP_2係寬於水平埋置部HEP_1及HEP_3。埋置離散場放大器1500顯示有可選之水平埋置部HEP_4,水平埋置部HEP_4係自垂直埋置部VEP_1之右邊緣向右延伸一段小的距離。水平埋置部HEP_4係垂直地居中於水平埋置部HEP_2上。水平埋置部HEP_4係用於將一第一埋置離散場放大器耦接至位於該第一埋置離散場放大器右側之一第二埋置離散場放大器。因此,水平埋置部HEP_4係僅在第一埋置離散場放大器與第二埋置離散場放大器具有相同極性時使用。舉例而言,在對於埋置離散場放大器使用一中性極性之畫素中,包含水平埋置部HEP_4將輕易地為所有埋置離散場放大器提供中性極性。在本發明之一特定實施例中,色點CD_1_1具有28微米之一寬度(水平)及30微米之一長度(垂直),色點CD_1_2具有28微米之一寬度及30微米之一高度,水平埋置部HEP_1具有28微米之一寬度及3微米之一高度;水平埋置部HEP_2具有28微米之一寬度及5微米之一高度;水平埋置部HEP_3具有15微米之一寬度及3微米之一高度;水平埋置部HEP_4具有15微米之一寬度及12微米之一高度;垂直埋置部VEP_1具有3微米之一寬度及95微米之一高度;且垂直埋置部VEP_2具有3微米之一寬度及80微米之一高度。 As noted above, in some embodiments of the invention, the layers used to form the buried discrete field amplifier are also used in a switching element. Thus, for these embodiments, the buried discrete field amplifier does not extend to the switching element. Figure 15 shows a buried discrete field amplifier 1500 that does not extend to the switching element. For the sake of clarity, the buried discrete field amplifier 1500 is conceptually divided into a vertical buried portion and a horizontal buried portion. Specifically, the buried discrete field amplifier 1500 includes two vertical buried portions VEP_1 and VEP_2, three horizontal buried portions HEP_1, HEP_2, and HEP_3, and an optional fourth horizontal buried portion HEP_4. The position of the vertical embedding portion and the horizontal embedding portion will be described for the case where the buried discrete field amplifier 1500 is used instead of the buried discrete field amplifier EFFA_1 of the pixel design 13(a). The vertical embedding portion VEP_1 is located behind the right edges of the color points CD_1_1 and CD_1_2 (Fig. 13(a)). The vertical embedding portion VEP_2 is located behind the left edge of the color point CD_1_2 and behind one of the left edges of the color point CD_1_1 (Fig. 13(a)). Specifically, the vertical embedding portion VEP_2 does not extend to the position where the switching element SE_1 at the upper left corner of the color point CD_1_1 is positioned. The horizontal embedding portion HEP_1 is located behind the bottom edge of the color point CD_1_2; the horizontal embedding portion HEP_2 is located at the upper edge of the color point CD_1_2 and behind the lower edge of the color point CD_1_1; and the horizontal embedding portion HEP_3 is located above the color point CD_1_1 Behind one of the edges. Specifically, the horizontal embedding unit HEP_3 The position of the switching element SE_1 that is not extended to the upper left corner of the color point CD_1_1 is not extended. The horizontal embedding portion HEP_2 of the buried discrete field amplifier 1500 is wider than the horizontal embedding portions HEP_1 and HEP_3, as described above with respect to the horizontal embedding portion HEP_3 in which the discrete field amplifier 1400 is buried. The buried discrete field amplifier 1500 is shown with an optional horizontal buried portion HEP_4 that extends a small distance to the right from the right edge of the vertical buried portion VEP_1. The horizontal embedding portion HEP_4 is vertically centered on the horizontal embedding portion HEP_2. The horizontal buried portion HEP_4 is for coupling a first buried discrete field amplifier to a second buried discrete field amplifier located on the right side of the first buried discrete field amplifier. Therefore, the horizontal buried portion HEP_4 is used only when the first buried discrete field amplifier and the second buried discrete field amplifier have the same polarity. For example, in a pixel that uses a neutral polarity for a buried discrete field amplifier, including the horizontal buried portion HEP_4 will easily provide a neutral polarity for all buried discrete field amplifiers. In a particular embodiment of the invention, the color point CD_1_1 has a width (horizontal) of 28 microns and a length (vertical) of 30 microns, and the color point CD_1_2 has a width of 28 microns and a height of 30 microns, horizontally buried The portion HEP_1 has a width of 28 microns and a height of 3 microns; the horizontal buried portion HEP_2 has a width of 28 microns and a height of 5 microns; the horizontal buried portion HEP_3 has a width of 15 microns and one of 3 microns Height; the horizontal embedding portion HEP_4 has a width of one of 15 microns and a height of 12 microns; the vertical embedding portion VEP_1 has a width of one micron and a height of 95 microns; and the vertical embedding portion VEP_2 has a width of one micron And one of the heights of 80 microns.
除放大離散場之外,埋置離散場放大器亦可用於改善單元間隙均勻性及降低顯示器之其他部件(例如,光間隔片)之液晶影響。圖16顯示依據本發明另一實施例之一埋置離散場放大器1600,埋置離散場放大器1600亦改善單元間隙均勻性並降低光間隔片對液晶之影響。為清楚起見,將埋置離散場放大器1600在概念上劃分成垂直埋置部及水平埋置部。具體而言,埋置離散場放大器1600包含四個垂直埋置部VEP_1、VEP_2、VEP_3、及VEP_4以及四個水平埋置部HEP_1、HEP_2、HEP_3、及HEP_4。針對其中使用埋置離散場放大器1600取代畫素設計13(a)之埋置離散場放大器EFFA_1之情形來闡述垂直埋置部及水平埋置部之位置。垂直埋置部VEP_1係位於色點CD_1_2之右邊緣後面(圖13(a))。垂直埋置部VEP_2係位於色點CD_1_2之左邊緣後面(圖13(a))。垂直埋置部VEP_3係位於色點CD_1_1之右邊緣後面(圖13(a))。垂直埋置部VEP_4係位於色點CD_1_1 之左邊緣後面(圖13(a))。水平埋置部HEP_1係位於色點CD_1_2之底部邊緣後面且亦略微地延伸至垂直埋置部VEP_1右側及略微地延伸至垂直埋置部VEP_2左側。水平埋置部HEP_1之延伸超過垂直埋置部VEP_1及VEP_2之部分會提高單元間隙均勻性。水平埋置部HEP_2係位於色點CD_1_2之上邊緣及色點CD_1_1之下邊緣後面。水平埋置部HEP_2延伸至垂直埋置部VEP_2及VEP_4左側,以改善單元間隙均勻性。水平埋置部HEP_3係位於色點CD_1_1之上邊緣之一部分後面。具體而言,水平埋置部HEP_3未延伸至色點CD_1_1之左上角之切換元件SE_1所定位處。水平埋置部HEP_4係被包含用以改善單元間隙均勻性,其延伸之垂直埋置部VEP_4左側並與水平埋置部HEP_3近似垂直地配向。與上述關於埋置離散場放大器1400之水平埋置部HEP_2所述之原因相同,埋置離散場放大器1600之水平埋置部HEP_2係寬於水平埋置部HEP_1、HEP_3、HEP_4。在本發明之一特定實施例中,色點CD_1_1具有28微米之一寬度(水平)及30微米之一長度(垂直),色點CD_1_2具有28微米之一寬度及30微米之一高度,水平埋置部HEP_1具有32微米之一寬度及3微米之一高度;水平埋置部HEP_2具有32微米之一寬度及5微米之一高度;水平埋置部HEP_3具有15微米之一寬度及3微米之一高度;水平埋置部HEP_4具有15微米之一寬度及3微米之一高度;垂直埋置部VEP_1具有3微米之一寬度及28微米之一高度;垂直埋置部VEP_2具有3微米之一寬度及28微米之一高度;垂直埋置部VEP_3具有3微米之一寬度及28微米之一高度;垂直埋置部VEP_4具有3微米之一寬度及28微米之一高度。 In addition to amplifying discrete fields, buried discrete field amplifiers can also be used to improve cell gap uniformity and reduce the liquid crystal effects of other components of the display (eg, photo spacers). 16 shows a buried discrete field amplifier 1600 in accordance with another embodiment of the present invention. The buried discrete field amplifier 1600 also improves cell gap uniformity and reduces the effect of the optical spacer on the liquid crystal. For the sake of clarity, the buried discrete field amplifier 1600 is conceptually divided into a vertical buried portion and a horizontal buried portion. Specifically, the buried discrete field amplifier 1600 includes four vertical buried portions VEP_1, VEP_2, VEP_3, and VEP_4 and four horizontal buried portions HEP_1, HEP_2, HEP_3, and HEP_4. The position of the vertical embedding portion and the horizontal embedding portion will be described for the case where the buried discrete field amplifier 1600 is used instead of the buried discrete field amplifier EFFA_1 of the pixel design 13(a). The vertical embedding portion VEP_1 is located behind the right edge of the color point CD_1_2 (Fig. 13(a)). The vertical embedding portion VEP_2 is located behind the left edge of the color point CD_1_2 (Fig. 13(a)). The vertical embedding portion VEP_3 is located behind the right edge of the color point CD_1_1 (Fig. 13(a)). The vertical embedding part VEP_4 is located at the color point CD_1_1 Behind the left edge (Fig. 13(a)). The horizontal embedding portion HEP_1 is located behind the bottom edge of the color point CD_1_2 and also slightly extends to the right side of the vertical embedding portion VEP_1 and slightly extends to the left side of the vertical embedding portion VEP_2. The extension of the horizontal embedding portion HEP_1 beyond the portions of the vertical embedding portions VEP_1 and VEP_2 improves the cell gap uniformity. The horizontal embedding portion HEP_2 is located at the upper edge of the color point CD_1_2 and behind the lower edge of the color point CD_1_1. The horizontal embedding portion HEP_2 extends to the left side of the vertical embedding portions VEP_2 and VEP_4 to improve cell gap uniformity. The horizontal embedding portion HEP_3 is located behind one of the upper edges of the color point CD_1_1. Specifically, the horizontal embedding portion HEP_3 does not extend to the position where the switching element SE_1 at the upper left corner of the color point CD_1_1 is positioned. The horizontal embedding portion HEP_4 is included to improve cell gap uniformity, and extends to the left side of the vertical embedding portion VEP_4 and is aligned approximately perpendicularly to the horizontal embedding portion HEP_3. The horizontal embedding portion HEP_2 of the buried discrete field amplifier 1600 is wider than the horizontal embedding portions HEP_1, HEP_3, and HEP_4, as described above with respect to the horizontal embedding portion HEP_2 in which the discrete field amplifier 1400 is buried. In a particular embodiment of the invention, the color point CD_1_1 has a width (horizontal) of 28 microns and a length (vertical) of 30 microns, and the color point CD_1_2 has a width of 28 microns and a height of 30 microns, horizontally buried The portion HEP_1 has a width of one of 32 micrometers and a height of one micrometer; the horizontal buried portion HEP_2 has a width of one of 32 micrometers and a height of one micrometer; the horizontal embedded portion HEP_3 has one width of 15 micrometers and one of three micrometers. Height; horizontal embedding portion HEP_4 has a width of one of 15 microns and a height of one micron; the vertical embedding portion VEP_1 has a width of one micron and a height of 28 microns; the vertical embedding portion VEP_2 has a width of one micron and One of 28 microns in height; the vertical buried portion VEP_3 has a width of one of 3 microns and a height of 28 microns; the vertical buried portion VEP_4 has a width of one of 3 microns and a height of one of 28 microns.
亦可修改上述畫素設計以用於半透半反射顯示器中,半透半反射顯示器在明亮環境(例如,在一晴天之室外)中提供更佳之效能。依據本發明之某些實施例,一色點子集係使用一反射性材料而非一透明材料製成。圖17顯示一畫素設計1710,畫素設計1710係設計用於半透半反射顯示器。畫素設計1710幾乎與畫素設計1210相同。因此,將僅闡述其不同之處。具體而言,在畫素設計1210中,色點CD_1_1、CD_2_2、及CD_3_1係被形成為反射性色點,如在色點CD_1_1、CD_2_2、及CD_3_1中使用陰影所示。反射性色點使用一反射性材料(例如,鋁)而非一透明材料。其他色點、切換元件、埋置極性區域(包括偏極化組件之極性)則與畫素設計 1210相同。因此,畫素設計1710可用於上述使用畫素設計1210之各種顯示器中。在本發明之其他實施例中,一不同之色點子集係被選擇成反射性色點。舉例而言,色點CD_1_2、CD_2_1、及色點CD_3_2可係為反射性色點,而色點CD_1_1、CD_2_2、及CD_3_1可係為透射性色點。一般而言,反射性色點應被均勻地分散於整個顯示器中,以在顯示器中提供均勻之效能。相似地,上述其他畫素設計亦可被修改成使用反射性色點。 The above pixel design can also be modified for use in a transflective display that provides better performance in a bright environment (eg, outdoors on a clear day). In accordance with some embodiments of the present invention, a subset of color points is made using a reflective material rather than a transparent material. Figure 17 shows a pixel design 1710, which is designed for a transflective display. The pixel design 1710 is almost identical to the pixel design 1210. Therefore, only the differences will be explained. Specifically, in the pixel design 1210, the color points CD_1_1, CD_2_2, and CD_3_1 are formed as reflective color points, as indicated by hatching in the color points CD_1_1, CD_2_2, and CD_3_1. Reflective dots use a reflective material (eg, aluminum) rather than a transparent material. Other color points, switching elements, buried polar regions (including the polarity of polarized components) and pixel design The same as 1210. Thus, the pixel design 1710 can be used in the various displays described above using the pixel design 1210. In other embodiments of the invention, a different subset of color points is selected as a reflective color point. For example, the color points CD_1_2, CD_2_1, and the color point CD_3_2 may be reflective color dots, and the color points CD_1_1, CD_2_2, and CD_3_1 may be transmissive color points. In general, reflective color dots should be evenly dispersed throughout the display to provide uniform performance in the display. Similarly, the other pixel designs described above can also be modified to use reflective color points.
圖18例示依據本發明一實施例之一半透半反射性色點1800。可使用半透半反射性色點來取代普通透射性色點,以將一普通透射顯示器轉換成一半透半反射顯示器。因此,此處所述半透半反射性色點可用以修改上述畫素設計其中之任一種。具體而言,半透半反射性色點1800包含二矩形透射部TP_1及TP_2,該二矩形透射部TP_1及TP_2係由一反射部RP_1間隔開。為清楚起見,使用陰影來繪製反射部RP_1。透射部係使用一透明導電材料(例如,ITO)製成。反射部係使用一反射導電材料(例如,鋁)製成。在本發明之某些實施例中,透明部TP_1及TP_2及反射部RP_1具有相同尺寸。在本發明之其他實施例中,反射部RP_1大於透明部TP_1及TP_2。在本發明之其他實施例中,使用其他半透半反射性色點。一般而言,一半透半反射性色點將具有一或多個透明部及一或多個反射部。透明部與反射部之面積比率通常係介於3:1與1:1之間。一般而言,當周圍光照明亮時(例如,白天在室外環境中),反射面積之比率愈高便提供愈佳之效能。 Figure 18 illustrates a transflective color dot 1800 in accordance with one embodiment of the present invention. A transflective color dot can be used in place of a normal transmissive color point to convert a conventional transmissive display into a transflective display. Thus, the transflective color points described herein can be used to modify any of the above pixel designs. Specifically, the transflective color point 1800 includes two rectangular transmissive portions TP_1 and TP_2 which are spaced apart by a reflecting portion RP_1. For the sake of clarity, the reflections RP_1 are drawn using shading. The transmissive portion is made using a transparent conductive material such as ITO. The reflective portion is made using a reflective conductive material such as aluminum. In some embodiments of the invention, the transparent portions TP_1 and TP_2 and the reflective portion RP_1 have the same size. In other embodiments of the invention, the reflecting portion RP_1 is larger than the transparent portions TP_1 and TP_2. In other embodiments of the invention, other transflective color dots are used. In general, a half transflective color dot will have one or more transparent portions and one or more reflective portions. The area ratio of the transparent portion to the reflective portion is usually between 3:1 and 1:1. In general, when the ambient light is bright (for example, in an outdoor environment during the day), the higher the ratio of the reflective areas, the better the performance.
可對使用反射性色點或半透半反射性色點之顯示器作出其他修改以改善顯示器之效能。舉例而言,可減少位於反射性色點之上之濾色片以及半透半反射性色點之反射部,乃因反射光兩次穿過濾色片(一次係在至反射性色點之途中,一次係在向外返回至顯示器之觀察者之途中)。舉例而言,在本發明之一實施例中,位於一反射性色點之上之濾色片之厚度僅係為位於一透射性色點之上之濾色片之厚度之一半。在本發明之其他實施例中,位於反射性色點之上之濾色片(或半透半反射性色點之反射部)被減少50%以上以改善亮度。 Other modifications can be made to displays that use reflective color dots or transflective color points to improve the performance of the display. For example, the color filter above the reflective color point and the reflective portion of the transflective color point can be reduced, because the reflected light passes through the filter color twice (once on the way to the reflective color point) , once on the way back to the viewer of the display). For example, in one embodiment of the invention, the thickness of the color filter above a reflective color point is only one-half the thickness of the color filter above a transmissive color point. In other embodiments of the invention, the color filter (or the reflective portion of the transflective color point) above the reflective color point is reduced by more than 50% to improve brightness.
在本發明之各種實施例中,已闡述了無需使用基板上之物理特徵便會產生一多區域垂直配向液晶顯示器之新穎結構及方法。上述本發明之結構及方法之各種實施例係僅用於說明本發明之原理,而非旨在將本發明之範 圍限制於所述特定實施例。舉例而言,就本揭露內容而言,熟習此項技藝者可界定其他畫素定義、埋置極性區域、埋置離散場放大器、場減少層、絕緣層、鈍化層、導電層、空隙、點極性圖案、畫素設計、色分量、極性延伸區域、極性、離散場、電極、基板、膜、色點、反射性色點、半透半反射性色點等等,並依據本發明之原理使用此等替代特徵來產生一種方法或系統。因此,本發明僅由以下申請專利範圍限定。 In various embodiments of the present invention, a novel structure and method for producing a multi-region vertical alignment liquid crystal display without the use of physical features on the substrate has been described. The various embodiments of the present invention are merely illustrative of the principles of the invention and are not intended to be a It is limited to the specific embodiment. For example, in the context of the present disclosure, those skilled in the art can define other pixel definitions, buried polar regions, buried discrete field amplifiers, field reduction layers, insulating layers, passivation layers, conductive layers, voids, and dots. Polarity pattern, pixel design, color component, polar extension region, polarity, discrete field, electrode, substrate, film, color point, reflective color point, transflective color point, etc., and are used in accordance with the principles of the present invention These alternative features result in a method or system. Accordingly, the invention is limited only by the scope of the following claims.
302‧‧‧第一偏光片 302‧‧‧First polarizer
305‧‧‧第一基板 305‧‧‧First substrate
307‧‧‧第一配向層 307‧‧‧First alignment layer
310‧‧‧畫素 310‧‧‧ pixels
311‧‧‧第一電極 311‧‧‧First electrode
312‧‧‧液晶 312‧‧‧LCD
313‧‧‧液晶 313‧‧‧LCD
315‧‧‧第二電極 315‧‧‧second electrode
320‧‧‧畫素 320‧‧‧ pixels
321‧‧‧第一電極 321‧‧‧first electrode
322‧‧‧液晶 322‧‧‧LCD
323‧‧‧液晶 323‧‧‧LCD
325‧‧‧第二電極 325‧‧‧second electrode
327‧‧‧電場 327‧‧‧ electric field
330‧‧‧畫素 330‧‧‧ pixels
331‧‧‧第一電極 331‧‧‧First electrode
332‧‧‧液晶 332‧‧‧LCD
333‧‧‧液晶 333‧‧‧LCD
335‧‧‧第二電極 335‧‧‧second electrode
352‧‧‧第二配向層 352‧‧‧Second alignment layer
355‧‧‧第二基板 355‧‧‧second substrate
357‧‧‧第二偏光片 357‧‧‧Second polarizer
410‧‧‧畫素設計 410‧‧‧ pixel design
500‧‧‧色點 500‧‧‧ color point
510‧‧‧電極 510‧‧‧electrode
512‧‧‧埋置極性區域 512‧‧‧ buried polar area
514‧‧‧鈍化層 514‧‧‧ Passivation layer
516‧‧‧埋置電極 516‧‧‧ embedded electrode
518‧‧‧改變導電性區域 518‧‧‧Change the conductivity area
600‧‧‧色點 600‧‧‧ color point
610‧‧‧電極 610‧‧‧electrode
612‧‧‧埋置極性區域 612‧‧‧ Buried polar area
614‧‧‧鈍化層 614‧‧‧ Passivation layer
616‧‧‧埋置電極 616‧‧‧ buried electrode
710‧‧‧畫素設計 710‧‧‧ pixel design
712‧‧‧導體 712‧‧‧Conductor
714‧‧‧導體 714‧‧‧Conductor
716‧‧‧導體 716‧‧‧Conductor
720‧‧‧顯示器 720‧‧‧ display
730‧‧‧顯示器 730‧‧‧ display
740‧‧‧顯示器 740‧‧‧ display
810‧‧‧畫素設計 810‧‧‧ pixel design
812‧‧‧導體 812‧‧‧Conductor
820‧‧‧顯示器 820‧‧‧ display
821‧‧‧透明基板 821‧‧‧Transparent substrate
823‧‧‧鈍化層 823‧‧‧ Passivation layer
827‧‧‧鈍化層 827‧‧‧ Passivation layer
840‧‧‧顯示器 840‧‧‧ display
910‧‧‧畫素設計 910‧‧ ‧ pixel design
920‧‧‧顯示器 920‧‧‧ display
1010‧‧‧畫素設計 1010‧‧‧ pixel design
1020‧‧‧顯示器 1020‧‧‧ display
1030‧‧‧顯示器 1030‧‧‧ display
1110‧‧‧畫素設計 1110‧‧‧ pixel design
1112‧‧‧電極 1112‧‧‧Electrode
1114‧‧‧電極 1114‧‧‧electrode
1116‧‧‧電極 1116‧‧‧electrode
1121‧‧‧透明基板 1121‧‧‧Transparent substrate
1123‧‧‧鈍化層 1123‧‧‧ Passivation layer
1127‧‧‧鈍化層 1127‧‧‧ Passivation layer
1140‧‧‧顯示器 1140‧‧‧ display
1160‧‧‧顯示器 1160‧‧‧ display
1210‧‧‧畫素設計 1210‧‧‧ pixel design
1214‧‧‧電極 1214‧‧‧electrode
1216‧‧‧電極 1216‧‧‧ electrodes
1220‧‧‧顯示器 1220‧‧‧ display
1230‧‧‧顯示器 1230‧‧‧ display
1310‧‧‧畫素設計 1310‧‧‧ pixel design
1320‧‧‧顯示器 1320‧‧‧ display
1400‧‧‧埋置離散場放大器 1400‧‧‧ embedded discrete field amplifier
1500‧‧‧埋置離散場放大器 1500‧‧‧ embedded discrete field amplifier
1600‧‧‧埋置離散場放大器 1600‧‧‧ embedded discrete field amplifier
1710‧‧‧畫素設計 1710‧‧‧ pixel design
1800‧‧‧色點 1800‧‧‧ color point
CC_1‧‧‧色分量 CC_1‧‧‧ color component
CC_2‧‧‧色分量 CC_2‧‧‧ color component
CC_3‧‧‧色分量 CC_3‧‧‧ color component
CD_1_1‧‧‧色點 CD_1_1‧‧‧ color point
CD_1_2‧‧‧色點 CD_1_2‧‧‧ color point
CD_1_3‧‧‧色點 CD_1_3‧‧‧ color point
CD_2_1‧‧‧色點 CD_2_1‧‧‧ color point
CD_2_2‧‧‧色點 CD_2_2‧‧‧ color point
CD_2_3‧‧‧色點 CD_2_3‧‧‧ color point
CD_3_1‧‧‧色點 CD_3_1‧‧‧ color point
CD_3_2‧‧‧色點 CD_3_2‧‧‧ color point
CDH‧‧‧色點高度 CDH‧‧‧ color point height
CDW‧‧‧色點寬度 CDW‧‧‧ color point width
DCA_1‧‧‧裝置元件區域 DCA_1‧‧‧ device component area
DCA_2‧‧‧裝置元件區域 DCA_2‧‧‧ device component area
DCA_3‧‧‧裝置元件區域 DCA_3‧‧‧ device component area
EPR_1_1‧‧‧埋置極性區域 EPR_1_1‧‧‧ buried polar area
EPR_1_2‧‧‧埋置極性區域 EPR_1_2‧‧‧ buried polar area
EPR_2_1‧‧‧埋置極性區域 EPR_2_1‧‧‧ buried polar area
EPR_2_2‧‧‧埋置極性區域 EPR_2_2‧‧‧ buried polar area
EPR_3_1‧‧‧埋置極性區域 EPR_3_1‧‧‧ buried polar area
EPR_3_2‧‧‧埋置極性區域 EPR_3_2‧‧‧ buried polar area
EPR_SE_0_1‧‧‧埋置極性區域切換元件 EPR_SE_0_1‧‧‧ Buried Polar Area Switching Element
EPR_SE_0_2‧‧‧埋置極性區域切換元件 EPR_SE_0_2‧‧‧ Buried Polar Area Switching Element
EPR_SE_1_1‧‧‧埋置極性區域切換元件 EPR_SE_1_1‧‧‧ Buried Polar Area Switching Element
EPR_SE_1_2‧‧‧埋置極性區域切換元件 EPR_SE_1_2‧‧‧ Buried Polar Region Switching Element
FFAR_1‧‧‧離散場放大區域 FFAR_1‧‧‧Discrete field magnification area
FFAR_2‧‧‧離散場放大區域 FFAR_2‧‧‧Discrete field magnification area
FFAR_3‧‧‧離散場放大區域 FFAR_3‧‧‧Discrete field magnification area
HAP‧‧‧水平放大部 HAP‧‧‧Horizontal Zoom Department
HAP_H‧‧‧水平放大部高度 HAP_H‧‧‧Horizontal magnification
HAP_W‧‧‧水平放大部寬度 HAP_W‧‧‧ horizontal magnification
HDO1‧‧‧水平點偏移 HDO1‧‧‧ horizontal point offset
HDS1‧‧‧水平點間距 HDS1‧‧‧ horizontal point spacing
HFFARS‧‧‧水平離散場放大區域間距 HFFARS‧‧‧ horizontal discrete field amplification area spacing
HPS‧‧‧水平畫素間距 HPS‧‧‧ horizontal pixel spacing
SE_1‧‧‧切換元件 SE_1‧‧‧Switching components
SE_2‧‧‧切換元件 SE_2‧‧‧Switching element
SE_3‧‧‧切換元件 SE_3‧‧‧Switching components
VDO1‧‧‧垂直點偏移 VDO1‧‧‧ vertical point offset
VDS1‧‧‧垂直點間距 VDS1‧‧‧ vertical point spacing
VFFARS‧‧‧垂直離散場放大區域間距 VFFARS‧‧‧Vertical discrete field amplification area spacing
VPS‧‧‧垂直畫素間距 VPS‧‧‧ vertical pixel spacing
圖1(a)-1(c) 係為一習知單區域垂直配向液晶顯示器之一畫素之三個圖示。 1(a)-1(c) are three diagrams of one of the pixels of a conventional single-region vertical alignment liquid crystal display.
圖2 係為一習知多區域垂直配向液晶顯示器之一畫素之一圖示。 Figure 2 is an illustration of one of the pixels of a conventional multi-region vertical alignment liquid crystal display.
圖3(a)-3(b) 例示依據本發明一實施例之一多區域垂直配向液晶顯示器。 3(a)-3(b) illustrate a multi-region vertical alignment liquid crystal display according to an embodiment of the present invention.
圖4(a)-4(b) 例示依據本發明一實施例之一畫素設計。 4(a)-4(b) illustrate a pixel design in accordance with an embodiment of the present invention.
圖5(a)-5(c) 例示依據本發明一實施例之一色點。 Figures 5(a)-5(c) illustrate a color point in accordance with an embodiment of the present invention.
圖6(a)-6(b) 例示依據本發明一實施例之一色點。 6(a)-6(b) illustrate a color point in accordance with an embodiment of the present invention.
圖7(a)-7(c) 例示依據本發明一實施例之一畫素設計。 7(a)-7(c) illustrate a pixel design in accordance with an embodiment of the present invention.
圖7(d) 例示依據本發明一實施例之一顯示器之一部分。 Figure 7 (d) illustrates a portion of a display in accordance with an embodiment of the present invention.
圖7(e) 例示依據本發明一實施例之一顯示器之一部分。 Figure 7 (e) illustrates a portion of a display in accordance with an embodiment of the present invention.
圖7(f) 例示依據本發明一實施例之一顯示器之一部分。 Figure 7 (f) illustrates a portion of a display in accordance with an embodiment of the present invention.
圖8(a)-8(c) 例示依據本發明一實施例之一畫素設計。 8(a)-8(c) illustrate a pixel design in accordance with an embodiment of the present invention.
圖8(d) 例示依據本發明一實施例之一顯示器之一部分。 Figure 8 (d) illustrates a portion of a display in accordance with an embodiment of the present invention.
圖9(a)-9(b) 例示依據本發明一實施例之一畫素設計。 Figures 9(a)-9(b) illustrate a pixel design in accordance with an embodiment of the present invention.
圖9(c) 例示依據本發明一實施例之一顯示器之一部分。 Figure 9 (c) illustrates a portion of a display in accordance with an embodiment of the present invention.
圖10(a)-10(b) 例示依據本發明一實施例之一畫素設計。 Figures 10(a)-10(b) illustrate a pixel design in accordance with an embodiment of the present invention.
圖10(c) 例示依據本發明一實施例之一顯示器之一部分。 Figure 10 (c) illustrates a portion of a display in accordance with an embodiment of the present invention.
圖10(d) 例示依據本發明一實施例之一顯示器之一部分。 Figure 10 (d) illustrates a portion of a display in accordance with an embodiment of the present invention.
圖11(a)-11(c) 例示依據本發明一實施例之一畫素設計。 11(a)-11(c) illustrate a pixel design in accordance with an embodiment of the present invention.
圖11(d) 例示依據本發明一實施例之一顯示器之一部分。 Figure 11 (d) illustrates a portion of a display in accordance with an embodiment of the present invention.
圖11(e)-11(f) 例示依據本發明一實施例之一畫素設計。 11(e)-11(f) illustrate a pixel design in accordance with an embodiment of the present invention.
圖11(g) 例示依據本發明一實施例之一顯示器之一部分。 Figure 11 (g) illustrates a portion of a display in accordance with an embodiment of the present invention.
圖11(h) 例示依據本發明一實施例之一顯示器之一部分。 Figure 11 (h) illustrates a portion of a display in accordance with an embodiment of the present invention.
圖12(a)-12(b) 例示依據本發明一實施例之一畫素設計。 12(a)-12(b) illustrate a pixel design in accordance with an embodiment of the present invention.
圖12(c) 例示依據本發明一實施例之一顯示器之一部分。 Figure 12 (c) illustrates a portion of a display in accordance with an embodiment of the present invention.
圖12(d) 例示依據本發明一實施例之一顯示器之一部分。 Figure 12 (d) illustrates a portion of a display in accordance with an embodiment of the present invention.
圖13(a)-13(b) 例示依據本發明一實施例之一畫素設計。 Figures 13(a)-13(b) illustrate a pixel design in accordance with an embodiment of the present invention.
圖13(c) 例示依據本發明一實施例之一顯示器之一部分。 Figure 13 (c) illustrates a portion of a display in accordance with an embodiment of the present invention.
圖14 例示一埋置離散場放大器。 Figure 14 illustrates a buried discrete field amplifier.
圖15 例示一埋置離散場放大器。 Figure 15 illustrates a buried discrete field amplifier.
圖16 例示一埋置離散場放大器。 Figure 16 illustrates a buried discrete field amplifier.
圖17 例示依據本發明一實施例之一半透半反射性畫素設計。 Figure 17 illustrates a transflective pixel design in accordance with one embodiment of the present invention.
圖18 例示依據本發明一實施例之一半透半反射性色點。 Figure 18 illustrates a transflective color dot in accordance with one embodiment of the present invention.
1110‧‧‧畫素設計 1110‧‧‧ pixel design
1112‧‧‧電極 1112‧‧‧Electrode
1114‧‧‧電極 1114‧‧‧electrode
1116‧‧‧電極 1116‧‧‧electrode
CD_1_1‧‧‧色點 CD_1_1‧‧‧ color point
CD_1_2‧‧‧色點 CD_1_2‧‧‧ color point
CD_2_1‧‧‧色點 CD_2_1‧‧‧ color point
CD_2_2‧‧‧色點 CD_2_2‧‧‧ color point
CD_3_1‧‧‧色點 CD_3_1‧‧‧ color point
CD_3_1‧‧‧色點 CD_3_1‧‧‧ color point
CDH‧‧‧色點高度 CDH‧‧‧ color point height
CDW‧‧‧色點寬度 CDW‧‧‧ color point width
EFFA_1‧‧‧埋置離散場放大器 EFFA_1‧‧‧ embedded discrete field amplifier
EPR_1_1‧‧‧埋置極性區域 EPR_1_1‧‧‧ buried polar area
EPR_2_1‧‧‧埋置極性區域 EPR_2_1‧‧‧ buried polar area
EPR_3_1‧‧‧埋置極性區域 EPR_3_1‧‧‧ buried polar area
HDO1‧‧‧水平點偏移 HDO1‧‧‧ horizontal point offset
HDS1‧‧‧水平點間距 HDS1‧‧‧ horizontal point spacing
VDO1‧‧‧垂直點偏移 VDO1‧‧‧ vertical point offset
VDS1‧‧‧垂直點間距 VDS1‧‧‧ vertical point spacing
Claims (31)
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US13/341,819 US20120236242A1 (en) | 2005-09-15 | 2011-12-30 | Liquid Crystal Displays Having Pixels with Embedded Fringe Field Amplifiers |
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TW201329570A true TW201329570A (en) | 2013-07-16 |
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TW101149516A TW201329570A (en) | 2011-12-30 | 2012-12-24 | Liquid crystal displays having pixels with embedded fringe field amplifiers |
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