TW201318174A - Semiconductor device - Google Patents

Abstract

Provided is a semiconductor device wherein transistor size is reduced without causing narrow channel effects. An MOS transistor (1) has, in a well-forming region, an active region (11) for forming a drain region, an active region (12) for forming a channel region, and an active region (13) for forming a source region, which are partitioned by means of element isolating films, and the active regions are formed by being separated from each other with the element isolating films among the regions. A width (B) of the active region (11) for forming the drain region is set narrower than a width (A) of the active region (12) for forming the channel region.

Description

Semiconductor device

The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a MOS (Metal-Oxide-Semiconductor) transistor for high withstand voltage applications.

In the conventional semiconductor device, as a configuration of the MOS transistor 10 for high withstand voltage use, for example, those shown in FIGS. 7 and 8 are provided.

Fig. 7 shows the layout on the substrate surface of the MOS transistor 10, and Fig. 8 shows the cross-sectional structural view in the X direction of Fig. 7. As shown in FIGS. 7 and 8, the MOS transistor 10 has three active regions 11, 12, and 13 divided by an element separation film in the formation region 15 of the well 25. Further, a drain region 21 is formed in the active region 11, a channel region 22 is formed in the active region 12, and a source region 23 is formed in the active region 13.

A drain side drift region 24a is formed in the region 14a of FIG. 7 so as to cover the drain region 21, and a source-side drain region is formed in the region 14b of FIG. 7 so as to cover the source region 23. 24b. Further, above the channel region 22, the gate electrode 17 is formed in the region 17 of Fig. 7 via the gate insulating film 26. Further, the well 25 functions as a field inversion preventing layer at the boundary portion of the well forming region 15.

Here, the width A of each of the active regions 12, 13 forming the channel region 22 and the source region 23 of the MOS transistor 10 is the same as the width B of the active region 11 forming the drain region. In this case, in order to miniaturize the transistor, it is necessary to simultaneously shorten the widths A and B. However, as the channel width A of the transistor is narrowed, The narrow channel effect becomes a problem. This narrow channel effect is caused by the diffusion of impurities in the element separation film and intrusion into the channel region.

Further, the transistor can be made smaller by narrowing the width C of the region in the drift region 24a that is not overlapped with the drain region 21. However, in this case, the drain voltage is generally a problem.

As a method of preventing the above-described narrow channel effect, Patent Document 1 discloses a method of forming a tantalum nitride film and light in a device formation region when forming an element separation film by LOCOS (Local Oxidation of Silicon). After the mask is blocked, impurities such as boron are implanted to block the impurities, and then one portion of the tantalum nitride film is removed by isotropic etching, thereby preventing the channel stop region from intruding into the element formation region by thermal oxidation thereafter. The element separation film is formed. According to this method, the semiconductor device can be manufactured without bringing the element formation region into contact with the channel stopper region. Therefore, variation in device characteristics due to deterioration of the narrow channel effect or the drain contact withstand voltage can be prevented.

[Previous Technical Literature] [Patent Literature]

[Patent Document 1] Japanese Patent Laid-Open No. Hei 6-53316

The narrow channel effect of the same channel width can be prevented by using this method, but the final channel width needs to be reduced in order to reduce the size of the transistor. Further, unevenness in line width is liable to occur due to the isotropic etching of the tantalum nitride film.

Further, when the MOS transistor 10 shown in the layout of FIG. 7 is arranged in parallel, for example, the layout shown in FIG. 9 is obtained. In this case, the MOS transistors 10 are mutually The interval is defined by the distance D between the formation regions 14a of the drain side drift regions 24a of the MOS transistors 10. In order to ensure the withstand voltage, the separation distance D needs to be a fixed distance depending on the withstand voltage, and it is not easy to shorten.

In view of the above circumstances, an object of the present invention is to realize a semiconductor device which can reduce the size of a transistor without causing a narrow channel effect.

A semiconductor device according to the present invention for achieving the above object is characterized by comprising: an MOS transistor having at least two adjacent to each other in a first direction parallel to the substrate and partitioned by the element isolation film on the well of the first conductivity type a first active region and a second active region; wherein the MOS electrification system has a second conductivity type bungee formed on the surface layer of the well and opposite to the well in the first active region a region in the second active region having a surface layer of the well, that is, a channel region; and the channel in the second active region or in the active region different from the first and second active regions a second source-type source region formed on the surface layer of the well, and a region separating the first active region and the second active region a drain-side drift region having a conductivity type lower than that of the drain region and having a lower concentration than the drain region; The width of the drain region parallel to the substrate and perpendicular to the second direction of the first direction is formed to be narrower than the width of the channel region in the second direction.

In the semiconductor device according to the first aspect of the invention, preferably, the MOS electro-crystal system is formed such that the source region is formed in the first direction in a direction in which the second active region is opposed to the first active region. In the active region, a source-side drift region connecting the source region and the channel region and having the same conductivity type as the source region and having a lower concentration than the source region is formed in the third active region and the first region 2 Below the element separation membrane between the active regions.

Preferably, the semiconductor device according to the first aspect described above further includes a plurality of the MOS transistors that share the well.

In the semiconductor device of the present invention having the above characteristics, by making the width of the active region forming the drain region narrower than the active region forming the channel region, it is possible to realize a small and highly durable MOS device without generating a narrow channel effect and without reducing the withstand voltage. Crystal.

(First embodiment)

Hereinafter, a semiconductor device (hereinafter referred to as "the device of the present invention" as appropriate) and a method of manufacturing the same according to an embodiment of the present invention will be described in detail. Fig. 1 shows the layout on the substrate surface of the MOS transistor 1 constituting the device of the present invention. As shown in FIG. 1, the MOS transistor 1 has a component separation in the well formation region 15. The membrane is divided into three active regions 11, 12, and 13. Among them, the active region 11 is an active region for forming a drain region, the active region 12 is an active region for forming a channel region, and the active region 13 is an active region for forming a source region. An element separation film is formed in a region other than the active regions 11, 12, and 13.

As shown in Fig. 1, in the present embodiment, the width B of the active region 11 for forming the drain region of the MOS transistor 1 is made narrower than the width A of the active region 12 for forming the channel region. On the other hand, the width C of the region in the formation region 14a of the drift region which is not overlapped with the active region 11 is the same as in the previous example. However, the other components are the same as those of the MOS transistor 10 of the prior art shown in FIGS. 7 and 8.

Therefore, regarding the structure of the transistor 1, the cross-sectional structural view in the X direction of Fig. 1 is substantially the same as that of Fig. 8. Further, in the cross-sectional view shown in Fig. 8, the main portion is appropriately emphasized, and the size ratio of each constituent portion on the drawing does not necessarily coincide with the actual size ratio. This point is also the same in the cross-sectional view shown later.

Regarding the MOS transistor 1, the N-type drain region 21, the channel region (the region of the surface layer of the P-type well 25 directly under the gate electrode 27) 22, and the N-type source region 23 are the drain region 21 and the source. The regions 23 are opposed to each other with the channel region 22 interposed therebetween, and are formed in the surface layer in the P-type well 25 so as to be spaced apart from each other by the element separation film 28.

A drain-side drift region 24a having the same conductivity type and lower concentration as the drain region 21 is formed in the region 14a of FIG. 1 so as to cover the drain region 21, and further covers the source region 23 in FIG. A source-side drift region having the same conductivity type as the source region 23 and having a lower concentration is formed in the region 14b. Domain 24b. Further, above the channel region 22, the gate electrode 27 is formed in the region 17 of Fig. 1 via the gate insulating film 26. Further, although not shown, a drain electrode is formed on the drain region 21 and a source electrode is formed on the source region 23, respectively. Further, the well 25 functions as a field inversion preventing layer at the boundary portion of the well forming region 15.

As described above, in the apparatus of the present invention, the width B of the active region of the MOS transistor 1 for forming the drain region 21 is made narrower than the width A of the active region 12 for forming the channel region 22. However, since the width A of the active region 12 is not changed, the channel width is not narrowed, and a narrow channel effect is not generated.

Further, since the width C of the region of the drift region 24a that is not overlapped with the drain region 21 is not narrowed, the withstand voltage does not decrease.

Further, in the present embodiment, the MOS transistor 1 is a bidirectional transistor and has a symmetrical structure sandwiching the channel region 22. Therefore, the relationship between the drain and the source of the MOS transistor 1 can be reversed. In other words, the source region 23 of FIG. 8 may be connected to the high potential side as a drain, and may be connected to the low potential side so that the drain region 21 of FIG. 8 becomes a source. In the present embodiment, together with the width B of the active region of the MOS transistor 1 for forming the drain region 21, the width (the same as B) for the active region for forming the source region 23 is also made narrower than for Since the width A of the active region 12 of the channel region 22 is formed, even if the relationship between the drain and the source is changed, the withstand voltage drop or the narrow channel effect does not occur and can be operated.

Further, in Fig. 2, the layout in the case where the MOS transistor 1 is arranged in parallel is shown. FIG. 2 is an example of a case where two MOS transistors 1 of the common well 25 are formed.

As shown in FIG. 2, in the device of the present invention, since the drain region 21 is formed Since the width B of the active region is narrowed, it can be disposed as a distance D between the drift regions 14a and maintained at a fixed value or more, and the distance between the transistors 1 is reduced as compared with FIG. Therefore, there is no problem that the withstand voltage is lowered.

Hereinafter, the manufacturing steps of the apparatus of the present invention will be described in detail with reference to the drawings. 3 and 4 are cross-sectional views schematically showing the steps of an embodiment of a method of manufacturing the apparatus of the present invention manufactured in the layout of Fig. 1 or Fig. 2.

First, as shown in FIG. 3(a), an active region 11 for forming a drain region, an active region 12 for forming a channel region, and an active region for forming a source region are used by a known process technique. The surface of the substrate other than the region 13 is thermally oxidized, and the element separation film 28 is formed by the LOCOS method.

Then, as shown in FIG. 3(b), a P-type well is formed by ion implantation of a P-type impurity using a photoresist mask 31 having an opening in the well formation region 15 by a known process technique.

Then, as shown in FIG. 3(c), the photoresist mask 32, which is formed by the formation regions 14a and 14b of the drift region, is formed by a known process technique, and the drain of the drain is formed by ion implantation of the N-type impurity. Region 24a and source side drift region 24b. At this time, according to FIG. 1, since the formation regions 14a and 14b of the drift region overlap with the formation region 12 of the channel region, respectively, the drain side drift region 24a exceeds the element separation film 28 sandwiched between the active region 11 and the active region 12. Below the source side drift region 24b side, the source side drift region 24b extends beyond the element isolation film 28 between the active region 12 and the active region 13 to the drain side drift region 24a side.

Then, as shown in FIG. 4(a), using the well-known process technology, in the active area The domain 12 forms a gate insulating film 26. At this time, the channel region 22 is formed in the surface layer of the well 25 in the active region 12. The channel region 22 is connected to the drain side drift region 24a formed under the element separation film 28 sandwiched between the active region 11 and the active region 12, and the element formed between the active region 12 and the active region 13 The source side drift region 24b below the separation film 28 is connected.

Then, as shown in FIG. 4(b), a gate electrode 27 containing polysilicon is formed in a region 17 of FIG. 1 so as to cover a portion of the gate insulating film 26 and the element isolation film 28 by a known process technique. .

Then, as shown in FIG. 4(c), the drain region 21 and the source region 23 are formed by ion implantation of N-type impurities by a known process technique. Thereafter, although not shown, the apparatus of the present invention is manufactured by forming a drain electrode on the drain region 21 and forming a source electrode on the source region 23.

As described above, according to the present invention, it is possible to reduce the size of the transistor and the size of the wafer in the case where the transistor is arranged side by side without changing the special process.

(Second embodiment)

In the first embodiment described above, the case where the MOS transistor 1 is a bidirectional transistor in which the active region 13 for forming the source region 23 and the active region 12 for forming the channel region 22 are separated is described, but The present invention can also be applied to a unidirectional transistor in which the active region 13 forming the source region 23 is not separated from the active region 12 for forming the channel region 22.

Fig. 5 shows the layout of the substrate surface of the MOS transistor 2 constituting the device of the present invention in the case of constituting a unidirectional transistor. As shown in FIG. 5, the MOS transistor 2 has two active regions divided by the element separation film in the well formation region 15. 11 and 12. The active region 11 is an active region for forming a drain region, and the active region 12 is an active region for forming a channel region and a source region. An element separation film is formed in a region other than the active regions 11 and 12.

Fig. 6 is a view showing the cross-sectional structure of the MOS transistor 2 in the X direction of Fig. 5. The MOS transistor 2 has substantially the same configuration as the MOS transistor 1 except for the passive electrode side drift region 24b and the source region 23 formed in a part of the active region 12.

The MOS transistor 2 is also narrowed by the width A of the active region 12 not formed in the channel region 22, and the width B of the active region 11 used to form the drain region 21 is narrowed, so that a narrow channel effect can be achieved. The MOS transistor for high voltage withstand voltage which does not reduce the withstand voltage.

Further, in the first and second embodiments described above, the case where the MOS transistors 1 and 2 are N-channel MOS transistors has been described as an example. The present invention is not limited to this, and can also be applied to the case of a P-channel MOS transistor. The well 25 may be N-type, and the drain region 21, the source region 23, and the drift regions 24a and 24b may be P-type.

Further, when the method of forming the channel stop region described in Patent Document 1 is applied to the present invention, the element separation film 28 is present between the drain region 21 and the channel region 22 in the MOS transistors 1 and 2, and In the MOS transistor 1, the element isolation film 28 is present between the channel region 22 and the source region 23, but the channel stop region cannot be formed below the element isolation film. In the present invention, in the case where the channel stopper region is formed, for example, before the step of forming the element separation film 28 shown in Fig. 3 (a), it is required to separate the film from the formation of the element. Covering different masks, injecting holes such as boron to block impurities in a specific area to form a channel stop area.

The present invention relates to a layout when forming a high withstand voltage MOS transistor, as long as the width of the active region 11 for forming the drain region 21 is narrower than the width of the active region 12 for forming the channel region 22, the respective semiconductor regions ( The size (depth or area) of the drain region 21, the channel region 22, the source region 23, the drift regions 24a, 24b, and the well 25, etc., the impurity concentration, and the material constituting the transistor are not limited in any way. For example, as a material of the gate electrode 27, a high melting point metal can be used in addition to the polysilicon. As the gate insulating film 26, a high-k (high dielectric) material can be used in addition to the thermal oxide film or the CVD oxide film. The element separation film 28 is not limited to those formed by the LOCOS method.

[Industrial availability]

The present invention can be utilized in a semiconductor device, and can be particularly utilized in a semiconductor device including a MOS transistor for high withstand voltage applications.

1‧‧‧A semiconductor device according to an embodiment of the present invention (the device of the present invention)

2. A semiconductor device according to an embodiment of the present invention (the device of the present invention)

10‧‧‧ previously constructed semiconductor devices

11‧‧‧Active areas used to form the bungee region

12‧‧‧Active areas used to form the channel area

13‧‧‧Active areas for the formation of source regions

14a‧‧‧ Formation area of drift zone

14b‧‧‧ Formation area of drift zone

15‧‧‧ Well formation area

21‧‧‧Bungee area

22‧‧‧Channel area

23‧‧‧Source area

24a‧‧‧汲polar drift zone

24b‧‧‧Source side drift region

25‧‧‧ Well

26‧‧‧Gate insulation film

27‧‧‧ gate electrode

28‧‧‧Component separation membrane

31‧‧‧Light-shielding mask

32‧‧‧Light-shielding mask

A‧‧‧ channel width

B‧‧‧The width of the bungee area

C‧‧‧Width of the area of the drift region that does not overlap with the bungee region

D‧‧‧ spacing distance between drift regions of transistors adjacent in the width direction

Fig. 1 is a view showing a layout on a substrate surface of a semiconductor device (MOS transistor) according to an embodiment of the present invention.

Fig. 2 is a view showing the layout on the substrate surface in the case where the MOS transistor is arranged in parallel in the present invention.

3(a) through 3(c) are schematic cross sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

4(a) to 4(c) are cross-sectional views schematically showing the steps of a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Fig. 5 is a view showing a layout on a substrate surface of a semiconductor device (MOS transistor) according to an embodiment of the present invention.

Fig. 6 is a cross-sectional view showing the structure of an element structure of a semiconductor device (MOS transistor) according to an embodiment of the present invention.

Fig. 7 is a view showing the layout on the substrate surface of the previously constructed MOS transistor.

Fig. 8 is a cross-sectional view schematically showing the structure of the element of the present invention and the previously constructed MOS transistor.

Fig. 9 is a view showing the layout on the substrate surface in the case where the MOS transistors are arranged side by side in the prior configuration.

1‧‧‧A semiconductor device according to an embodiment of the present invention (the device of the present invention)

11‧‧‧Active areas used to form the bungee region

12‧‧‧Active areas used to form the channel area

13‧‧‧Active areas for the formation of source regions

14a‧‧‧ Formation area of drift zone

14b‧‧‧ Formation area of drift zone

15‧‧‧ Well formation area

17‧‧‧Area

A‧‧‧ channel width

B‧‧‧The width of the bungee area

C‧‧‧Width of the area of the drift region that does not overlap with the bungee region

Claims (3)

A semiconductor device comprising: a MOS transistor having a first conductivity type adjacent to a first direction parallel to a substrate and having at least two first active regions divided by an element isolation film; a second active region; wherein the MOS electromorphic system has a second conductivity type drain region formed on the surface layer of the well and opposite to the well in the first active region; a region having a surface layer of the well in the active region, wherein the channel region is in the second active region or in the active region different from the first and second active regions, and the channel region is interposed therebetween a polar region is formed in a source region of the second conductivity type formed on a surface layer of the well; and has a connection under the element isolation film sandwiched between the first active region and the second active region The drain region and the channel region are of the same conductivity type as the drain region and have a concentration lower than a drain drift region of the drain region; and the drain region is parallel to the upper region Substrate and a width perpendicular to the second direction of the first direction, the narrow width of the second direction than the area of said passage. The semiconductor device of claim 1, wherein the MOS electrification system is such that the source region is formed in the first direction and sandwiches the second activity a region in the third active region facing the first active region; and the source region and the channel region are connected to the source region and have a lower conductivity than the source region of the source region The drift region is formed below the element isolation film sandwiched between the third active region and the second active region. A semiconductor device according to claim 1 or 2, wherein a plurality of said MOS transistors sharing said well are provided.