JPWO2013061670A1 - Semiconductor device - Google Patents

Abstract

A semiconductor device capable of reducing the transistor size without causing a narrow channel effect is realized. In the well formation region, there are an active region 11 for forming a drain region partitioned by an element isolation film, an active region 12 for forming a channel region, and an active region 13 for forming a source region, In the MOS transistor 1 in which the active regions are formed with the element isolation film interposed therebetween, the width B of the active region 11 for forming the drain region is larger than the width A of the active region 12 for forming the channel region. Narrow.

Description

  The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including a MOS transistor used for high breakdown voltage applications.

  In the conventional semiconductor device, as a configuration of the MOS transistor 10 used for high withstand voltage applications, for example, there are those shown in FIGS.

  FIG. 7 shows a layout of the MOS transistor 10 on the substrate surface, and FIG. 8 shows a sectional structure view in the X direction of FIG. As shown in FIGS. 7 and 8, the MOS transistor 10 has three active regions 11, 12, and 13 partitioned by an element isolation film in the formation region 15 of the well 25. A drain region 21 is formed in the active region 11, a channel region 22 is formed in the active region 12, and a source region 23 is formed in the active region 13.

  A drain side drift region 24a is formed in the region 14a of FIG. 7 so as to cover the drain region 21, and a source side drain region 24b is further formed in the region 14b of FIG. 7 so as to cover the source region 23. ing. Furthermore, a gate electrode 17 is formed in the region 17 of FIG. 7 above the channel region 22 via a gate insulating film 26. The well 25 also functions as a field inversion prevention layer at the boundary of the well formation region 15.

  Here, the width A of each of the active regions 12 and 13 forming the channel region 22 and the source region 23 of the MOS transistor 10 is the same as the width B of the active region 11 forming the drain region. In this case, in order to reduce the size of the transistor, it is necessary to shorten the widths A and B at the same time. However, the narrow channel effect becomes a problem as the channel width A of the transistor is narrowed. The narrow channel effect is caused by the diffusion of impurities in the element isolation film and entering the channel region.

  The transistor can also be reduced in size by reducing the width C of the region that does not overlap with the drain region 21 in the drift region 24a, but in this case, the drain breakdown voltage is generally a problem.

  As a method for preventing the narrow channel effect, in Patent Document 1, in forming an element isolation film by LOCOS, after forming a silicon nitride film and a resist mask in an element formation region, a channel stopper impurity such as boron is implanted, and thereafter A method of forming an element isolation film by removing a part of the silicon nitride film by isotropic etching and without allowing the channel stopper region to enter the element formation region by subsequent thermal oxidation is disclosed. In Japanese Patent Laid-Open No. 2004-260260, a semiconductor device can be manufactured by this method without bringing the element formation region and the channel stopper region into contact with each other, so that fluctuations in element characteristics due to a narrow channel effect, drain junction breakdown voltage degradation, and the like are prevented. You can do that.

JP-A-6-53316

  By using this method, it is possible to prevent the narrow channel effect with the same channel width, but if it is desired to reduce the size of the transistor, it is necessary to reduce the channel width after all. Further, since the silicon nitride film is isotropically etched, variations in line width are likely to occur.

  Further, when the MOS transistors 10 shown in the layout of FIG. 7 are arranged in parallel, for example, the layout shown in FIG. 9 is obtained. In this case, the interval between the MOS transistors 10 is defined by the separation distance D of the formation region 14 a of the drain side drift region 24 a of each MOS transistor 10. In order to secure the withstand voltage, the separation distance D requires a certain distance depending on the withstand voltage, and is difficult to shorten.

  In view of the above situation, an object of the present invention is to realize a semiconductor device capable of reducing the transistor size without causing a narrow channel effect.

In order to achieve the above object, a semiconductor device according to the present invention provides:
A MOS transistor having at least two first active regions and second active regions adjacent to each other in a first direction parallel to the substrate and partitioned by an element isolation film on the first conductivity type well;
The MOS transistor is
A drain region of a second conductivity type opposite to the well formed in a surface layer of the well in the first active region;
A channel region that is a surface layer region of the well in the second active region;
The second active layer is formed in a surface layer of the well in the second active region or in an active region different from the first and second active regions so as to face the drain region across the channel region. A conductive source region; and
Below the element isolation film sandwiched between the first active region and the second active region, the drain region and the channel region are connected and have the same conductivity type as the drain region and the drain region It has a lower concentration drain side drift region,
A width of the drain region in a second direction parallel to the substrate and perpendicular to the first direction is narrower than a width of the channel region in the second direction.

In the semiconductor device according to the first feature, the MOS transistor further includes:
The source region is formed in a third active region facing the first active region across the second active region in the first direction;
A source-side drift region that connects the source region and the channel region and has the same conductivity type as the source region and has a lower concentration than the source region is sandwiched between the third active region and the second active region. Preferably, it is formed below the device isolation film.

  The semiconductor device of the first feature preferably further includes a plurality of the MOS transistors having the well in common.

  In the semiconductor device according to the present invention having the above characteristics, the width of the active region forming the drain region is narrower than that of the active region forming the channel region, so that the narrow channel effect is not caused and the breakdown voltage is reduced. Therefore, a small MOS transistor for high withstand voltage can be realized.

The figure which shows the layout on the board | substrate surface of the semiconductor device (MOS transistor) which concerns on one Embodiment of this invention. The figure which shows the layout on the board | substrate surface at the time of arranging MOS transistor in parallel in this invention Process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention typically Process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention typically The figure which shows the layout on the board | substrate surface of the semiconductor device (MOS transistor) which concerns on one Embodiment of this invention. 1 is a cross-sectional view schematically showing a device structure of a semiconductor device (MOS transistor) according to an embodiment of the present invention. The figure which shows the layout on the substrate surface of the MOS transistor of the conventional configuration Sectional drawing which shows typically the device structure of this invention and the MOS transistor of a conventional structure The figure which shows the layout on the substrate surface when the MOS transistor of the conventional configuration is arranged in parallel

<First Embodiment>
A semiconductor device according to an embodiment of the present invention (hereinafter referred to as “the present device” as appropriate) and a manufacturing method thereof will be described in detail below. FIG. 1 shows a layout on the substrate surface of a MOS transistor 1 constituting the device of the present invention. As shown in FIG. 1, the MOS transistor 1 has three active regions 11, 12, and 13 partitioned by an element isolation film in a well formation region 15. Of these, the active region 11 is an active region for forming a drain region, the active region 12 is an active region for forming a channel region, and the active region 13 is an active region for forming a source region. An element isolation film is formed in a region excluding the active regions 11, 12, and 13.

  As shown in FIG. 1, in this embodiment, the width B of the active region 11 for forming the drain region is made narrower than the width A of the active region 12 for forming the channel region of the MOS transistor 1. . On the other hand, the width C of the region that does not overlap the active region 11 in the drift region formation region 14a is the same as that of the conventional example. However, other configurations are the same as those of the conventional MOS transistor 10 shown in FIGS.

  Therefore, the cross-sectional structure diagram in the X direction of FIG. 1 of the structure of the transistor 1 is substantially the same as FIG. Note that, in the cross-sectional view shown in FIG. 8, the main parts are appropriately emphasized, and the dimensional ratios of the respective constituent parts on the drawing do not necessarily coincide with the actual dimensional ratios. The same applies to the sectional views shown below.

  In the MOS transistor 1, an N-type drain region 21, a channel region (a surface layer region of the P-type well 25 immediately below the gate electrode 27) 22, and an N-type source region 23 are formed on the surface layer in the P-type well 25. The drain region 21 and the source region 23 are formed so as to face each other with the channel region 22 interposed therebetween, and are separated from each other via the element isolation film 28.

  A drain side drift region 24a having the same conductivity type as that of the drain region 21 and a lower concentration in the region 14a in FIG. 1 so as to cover the drain region 21 and further covering the source region 23 in the region 14b in FIG. Inside, a source-side drift region 24b having the same conductivity type as the source region 23 and a lower concentration is formed. A gate electrode 27 is formed in the region 17 of FIG. 1 above the channel region 22 via a gate insulating film 26. Although not shown, a drain electrode is formed on the drain region 21 and a source electrode is formed on the source region 23, respectively. The well 25 also functions as a field inversion prevention layer at the boundary of the well formation region 15.

  As described above, in the device of the present invention, the width B of the active region for forming the drain region 21 of the MOS transistor 1 is made smaller than the width A of the active region 12 for forming the channel region 22. However, since the width A of the active region 12 is not changed, the channel width is not narrowed and the narrow channel effect does not occur.

  Further, since the width C of the region that does not overlap the drain region 21 in the drift region 24a is not reduced, the breakdown voltage is not lowered.

  In the present embodiment, the MOS transistor 1 is a bidirectional transistor and has a symmetrical structure with the channel region 22 in between. Therefore, the relationship between the drain and the source in the MOS transistor 1 may be reversed. That is, it may be connected to the high potential side so that the source region 23 in FIG. 8 becomes the drain, and connected to the low potential side so that the drain region 21 in FIG. 8 becomes the source. In the present embodiment, in addition to the active region width B for forming the drain region 21 of the MOS transistor 1, the active region width for forming the source region 23 (same as B) is also used for the channel region 22. Since it is narrower than the width A of the active region 12 for formation, even if the relationship between the drain and the source is switched, the operation can be performed without causing a breakdown voltage drop or a narrow channel effect.

  Further, FIG. 2 shows a layout when MOS transistors 1 are arranged in parallel. FIG. 2 shows an example in which two MOS transistors 1 having a common well 25 are formed.

  As shown in FIG. 2, in the device of the present invention, since the width B of the active region forming the drain region 21 is narrowed, the distance D between the drift regions 14a is greater than a certain value compared to FIG. The distance between the transistors 1 can be reduced while being maintained. For this reason, the problem of a pressure | voltage resistant fall does not arise.

  Below, the manufacturing process of this invention apparatus is demonstrated in detail with reference to drawings. 3 and 4 are process cross-sectional views schematically showing an embodiment of a method of manufacturing the device of the present invention manufactured with the layout of FIG. 1 or FIG.

  First, as shown in FIG. 3A, an active region 11 for forming a drain region, an active region 12 for forming a channel region, and an activity for forming a source region by a known process technique. The substrate surface in the region excluding the region 13 is thermally oxidized, and the element isolation film 28 is formed by the LOCOS method.

  Next, as shown in FIG. 3B, ion implantation of P-type impurities is performed by a known process technique using a resist mask 31 opening the well formation region 15 to form a P-type well.

  Next, as shown in FIG. 3C, the drain side drift region 24a and the source side drift region 24b are formed using a resist mask 32 that opens the drift region formation regions 14a and 14b by a known process technique. Are formed by ion implantation of N-type impurities. At this time, from FIG. 1, since the drift region formation regions 14 a and 14 b overlap the channel region formation region 12, the drain side drift region 24 a is between the active region 11 and the active region 12. The source-side drift region 24b extends beyond the sandwiched element isolation film 28 to the source-side drift region 24b side, and the source-side drift region 24b exceeds the lower portion of the element isolation film 28 sandwiched between the active region 12 and the active region 13. Extending toward the drain side drift region 24a.

  Next, as shown in FIG. 4A, a gate insulating film 26 is formed in the active region 12 by a known process technique. At this time, a channel region 22 is formed in the surface layer of the well 25 in the active region 12. The channel region 22 is connected to the drain side drift region 24 a formed below the element isolation film 28 sandwiched between the active region 11 and the active region 12, and is sandwiched between the active region 12 and the active region 13. The source-side drift region 24b formed below the element isolation film 28 is connected.

  Next, as shown in FIG. 4B, by a known process technique, polysilicon is formed in the region 17 of FIG. 1 so as to cover the gate insulating film 26 and a part of the element isolation film 28. A gate electrode 27 is formed.

  Next, as shown in FIG. 4C, the drain region 21 and the source region 23 are formed by ion implantation of N-type impurities by a known process technique. Thereafter, although not shown, the drain electrode is formed on the drain region 21 and the source electrode is formed on the source region 23, whereby the device of the present invention is manufactured.

  As described above, according to the present invention, the transistor size and the chip size when transistors are arranged in parallel can be reduced without any special process change.

Second Embodiment
In the first embodiment, the MOS transistor 1 is described as a bidirectional transistor in which the active region 13 for forming the source region 23 is separated from the active region 12 for forming the channel region 22. The present invention can also be applied to a unidirectional transistor in which the active region 13 for forming the source region 23 is not separated from the active region 12 for forming the channel region 22.

  FIG. 5 shows a layout on the substrate surface of the MOS transistor 2 constituting the device of the present invention when a unidirectional transistor is constructed. As shown in FIG. 5, the MOS transistor 2 has two active regions 11 and 12 partitioned by an element isolation film in the well formation region 15. Of these, the active region 11 is an active region for forming a drain region, and the active region 12 is an active region for forming a channel region and a source region. An element isolation film is formed in a region excluding the active regions 11 and 12.

  FIG. 6 is a schematic diagram of a cross-sectional structure of the MOS transistor 2 in the X direction of FIG. The MOS transistor 2 has substantially the same configuration as the MOS transistor 1 except that there is no source-side drift region 24 b and the source region 23 is formed in a part of the active region 12.

  In the MOS transistor 2 described above, the width A of the active region 12 for forming the channel region 22 is not changed, and the width B of the active region 11 for forming the drain region 21 is narrowed. A small high-breakdown-voltage MOS transistor can be realized without occurring and without lowering the breakdown voltage.

  In the first and second embodiments, the case where the MOS transistors 1 and 2 are N-channel MOS transistors has been described as an example. The present invention is not limited to this, and can also be applied to the case of a P-channel MOS transistor. The well 25 may be N-type, and the drain region 21, the source region 23, and the drift regions 24a and 24b may be P-type.

  Further, when the method for forming the channel stopper region described in Patent Document 1 is applied to the present invention, in the MOS transistors 1 and 2, between the drain region 21 and the channel region 22, and in the MOS transistor 1, An element isolation film 28 exists between the source regions 23, but a channel stopper region cannot be formed below these element isolation films. In the present invention, when forming the channel stopper region, for example, a mask different from the mask necessary for forming the element isolation film is used before the element isolation film 28 forming step shown in FIG. Then, a channel stopper impurity such as boron is implanted into a predetermined region to form a channel stopper region.

  The present invention relates to a layout for forming a high voltage MOS transistor, and the width of the active region 11 for forming the drain region 21 is narrower than the width of the active region 12 for forming the channel region 22. As long as it is, the size (depth and area), impurity concentration, and transistor of each semiconductor region (drain region 21, channel region 22, source region 23, drift regions 24a and 24b, well 25, etc.) are formed. The material is not limited at all. For example, as the material of the gate electrode 27, refractory metal can be used in addition to polysilicon. Also for the gate insulating film 26, a high-k material may be used in addition to the thermal oxide film and the CVD oxide film. The element isolation film 28 is not limited to a film formed by the LOCOS method.

  The present invention can be used for a semiconductor device, and in particular, can be used for a semiconductor device including a MOS transistor used for a high breakdown voltage application.

1, 2: A semiconductor device according to an embodiment of the present invention (device of the present invention)
10: Conventional semiconductor device 11: Active region 12 for forming drain region: Active region 13 for forming channel region 13: Active region 14a, 14b for forming source region 15: Drift region forming region 15: Well region Formation region 21: Drain region 22: Channel region 23: Source region 24a: Drain side drift region 24b: Source side drift region 25: Well 26: Gate insulating film 27: Gate electrode 28: Element isolation films 31, 32: Resist mask A : Channel width B: Width of drain region C: Width of region not overlapping with drain region in drift region D: Distance between drift regions of adjacent transistors in the width direction

Claims (3)

A MOS transistor having at least two first active regions and second active regions adjacent to each other in a first direction parallel to the substrate and partitioned by an element isolation film on the first conductivity type well;
The MOS transistor is
A drain region of a second conductivity type opposite to the well formed in a surface layer of the well in the first active region;
A channel region that is a surface layer region of the well in the second active region;
The second active layer is formed in a surface layer of the well in the second active region or in an active region different from the first and second active regions so as to face the drain region across the channel region. A conductive source region; and
Below the element isolation film sandwiched between the first active region and the second active region, the drain region and the channel region are connected and have the same conductivity type as the drain region and the drain region It has a lower concentration drain side drift region,
2. The semiconductor device according to claim 1, wherein a width of the drain region in a second direction parallel to the substrate and perpendicular to the first direction is narrower than a width of the channel region in the second direction. The MOS transistor is
The source region is formed in a third active region facing the first active region across the second active region in the first direction;
A source-side drift region that connects the source region and the channel region and has the same conductivity type as the source region and has a lower concentration than the source region is sandwiched between the third active region and the second active region. 2. The semiconductor device according to claim 1, wherein the semiconductor device is formed below the element isolation film.   The semiconductor device according to claim 1, further comprising a plurality of the MOS transistors sharing the well.

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