JP2023007739A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

To provide a semiconductor device capable of reducing a leak current due to a parasitic transistor generated in a separation region.SOLUTION: A semiconductor device comprises: a high-side circuit region 18 arranged on a P-type semiconductor substrate 10; a first N-type well 11; a second N-type well 12 arranged in a level shift resurf MOS 19; a separation region 13 located between the high-side circuit region 18 and the level shift resurf MOS 19 and separating between the first N-type well 11 and the second N-type well 12 by the P-type semiconductor substrate; an insulation layer 14 located on the separation region 13; wiring 15 provided on the insulation layer 14 and electrically connected to the second N-type well 12; and a P-type region 16 located below the wiring 15 and arranged on a surface side of the P-type semiconductor substrate in the separation region 13.SELECTED DRAWING: Figure 2

Description

The present invention relates to a semiconductor device and its manufacturing method.

In a conventional semiconductor device, as an example of efficiently laying out a level-shift resurf MOS and a high-side isolation island (high-side circuit area), a level shift to a high-breakdown-voltage termination area arranged around the high-side isolation island in a plan view is performed. There is a layout method in which a resurf MOS is arranged, a section of the high side isolation island is divided, and the level shift resurf MOS is isolated from the high side isolation island by an isolation region in which a narrow region of a P-type semiconductor substrate is interposed. An insulating layer is arranged on the isolation region, the high-side isolation island and the level shift RESURF MOS, and wiring is arranged on the insulating layer. Techniques related to this are disclosed in Patent Documents 1 and 2.

In the above-described layout method, when trying to reduce the chip area, the isolation region (thin region of the P-type semiconductor substrate) between the high-side isolation island and the level shift resurf MOS must be narrowed (during high voltage operation). complete depletion) is required.

However, if the isolation region is narrowed, the region (isolation region) of the P-type semiconductor substrate interposed between the drain region (N-type well) of the level shift resurf MOS and the N-type region of the high-side isolation island will have a large area. When a high voltage is applied to the wiring existing through the insulating layer thereon, an inversion layer may be formed and a leakage current may flow. Especially when the voltage of the high-side isolation island is low and the depletion of the isolation region is incomplete, a parasitic transistor may cause leakage current in the isolation region separating the level shift resurf MOS and the high-side isolation island. .

Therefore, in order to reduce the leakage current due to the parasitic transistor, it is necessary to increase the concentration of the isolation region. There was a problem that it could not be used at the voltage of

JP 2015-170733 A JP-A-9-283716

Various aspects of the present invention provide a semiconductor device capable of reducing leakage current due to a parasitic transistor generated in an isolation region without lowering the breakdown voltage of the level shift resurf MOS and the high side isolation island and without increasing the isolation distance. intended to
Another object of various aspects of the present invention is to provide a method of manufacturing a semiconductor device capable of reducing leak current caused by a parasitic transistor generated in an isolation region without increasing the number of manufacturing steps.

Various aspects of the invention are described below.

[1] A semiconductor substrate of a first conductivity type;
a high side circuit region arranged on the semiconductor substrate in plan view;
a first second conductivity type well arranged on the surface side of the semiconductor substrate and located in the high side circuit region;
a high breakdown voltage termination region arranged on the periphery of the high side circuit region in plan view;
a level shift resurf MOS positioned in the high breakdown voltage termination region in plan view;
a second second conductivity type well arranged on the surface side of the semiconductor substrate and arranged in the level shift resurf MOS;
is positioned between the high side circuit region and the level shift resurf MOS, and the first conductivity type well is provided between the first well of the second conductivity type and the second well of the second conductivity type; a separation region separated by a semiconductor substrate;
an insulating layer overlying the first well of second conductivity type, the isolation region and the second well of second conductivity type;
a wiring disposed on the insulating layer and electrically connected to the second well of the second conductivity type;
a first conductivity type region located under the wiring and arranged on the surface side of the first conductivity type semiconductor substrate of the isolation region;
the first conductivity type region is isolated from each of the first second conductivity type well and the second second conductivity type well by the semiconductor substrate of the first conductivity type in the isolation region;
A semiconductor device, wherein the impurity concentration of the first conductivity type region is higher than the impurity concentration of the semiconductor substrate of the first conductivity type.

[2] In [1] above,
A semiconductor device, wherein the width of the first conductivity type region is 0.5 μm or more and 4 μm or less (preferably 1.5 μm or more and 4 μm or less).

[3] In the above [1] or [2],
A semiconductor device, wherein the distance between the first well of the second conductivity type and the second well of the second conductivity type is 17 μm or more and 27 μm or less (preferably 20 μm or more and 27 μm or less).

[4] In any one of [1] to [3] above,
A semiconductor device, wherein the depth of the first conductivity type region is 0.5 μm or more and 2.5 μm or less.

[5] In any one of [1] to [4] above,
A semiconductor device, wherein the thickness of the insulating layer is 0.6 μm or more and 2 μm or less (preferably 0.85 μm or more and 2 μm or less).

[6] In a semiconductor substrate of a first conductivity type, a first second conductivity type well positioned in a high side circuit region, and a level shift resurf MOS arranged outside the high side circuit region in plan view. a second second conductivity type well located between the high side circuit region and the level shift resurf MOS in a plan view, and connecting the first well of the second conductivity type and the a step (a) of forming an isolation region separating a second second conductivity type well by the semiconductor substrate of the first conductivity type;
step (b) of forming a first first-conductivity-type region having a higher impurity concentration than the semiconductor substrate on the surface side of the first-conductivity-type semiconductor substrate in the isolation region;
forming an insulating layer over the first well of second conductivity type, the first region of first conductivity type, the isolation region and the second well of second conductivity type;
(d) forming a wiring located on the insulating layer and electrically connected to the second well of the second conductivity type;
the wiring is located on the first conductivity type region;
The first conductivity type region is isolated from each of the first second conductivity type well and the second second conductivity type well by the semiconductor substrate of the first conductivity type in the isolation region. A method of manufacturing a semiconductor device characterized by:

[7] In [6] above,
In the step (b), the first conductivity type region is formed on the surface side of the first conductivity type semiconductor substrate in the isolation region, and at the same time, a first conductivity type impurity is diffused into the second second conductivity type well. A method of manufacturing a semiconductor device, comprising: forming a layer.

According to various aspects of the present invention, a semiconductor device capable of reducing leakage current due to a parasitic transistor generated in an isolation region without lowering the breakdown voltage of the level shift resurf MOS and the high side isolation island and without increasing the isolation distance. can be provided.
Further, according to various aspects of the present invention, it is possible to provide a method of manufacturing a semiconductor device capable of reducing leak current caused by a parasitic transistor generated in an isolation region without increasing the number of manufacturing steps.

1 is a plan view showing a semiconductor device according to one embodiment of the present invention; FIG. FIG. 2 is a cross-sectional view taken along line AA' shown in FIG. 1; 3 is a cross-sectional view showing a modification of the semiconductor device shown in FIG. 2; FIG.

Embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art will readily understand that various changes in form and detail may be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the descriptions of the embodiments shown below.

FIG. 1 is a plan view illustrating a semiconductor device according to one embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line AA' shown in FIG.

As shown in FIG. 2, this semiconductor device has a semiconductor substrate (Psub) 10 of a first conductivity type. The first conductivity type is, for example, P-type, and this semiconductor substrate is P-type semiconductor substrate 10 .

As shown in FIG. 1, a high side circuit region (high side isolation island) 18 is formed in a P type semiconductor substrate (corresponding to the P type semiconductor substrate 10 shown in FIG. 2) in plan view.
Further, as shown in FIG. 1, a high breakdown voltage termination region 20 is arranged on the outer periphery of the high side circuit region (high side isolation island) 18 in plan view. A low side circuit area (low side circuit area) (not shown) is arranged outside the high breakdown voltage termination area 20 . A level shift resurf MOS 19 is arranged in the high breakdown voltage termination region 20 in plan view.

As shown in FIG. 1, level shift resurf MOS 19 is separated from high side isolation island 18 by isolation region 13 . This isolation region 13 has a narrow region of the P-type semiconductor substrate 10 dividing a section of the high side isolation island 18 (see FIG. 2).

As shown in FIG. 2, a first second-conductivity-type well 11 located in a high-side circuit region 18 is arranged on the surface side of a P-type semiconductor substrate 10 . The second conductivity type is, for example, N-type, and this well is the first N-type well 11 . An N-type contact layer 31 is formed on the surface side of the first N-type well 11 .

The level shift RESURF MOS 19 is provided with a second second conductivity type well 12 positioned on the surface side of the P-type semiconductor substrate 10 as shown in FIG. This second conductivity type well is the second N-type well 12 .

As shown in FIG. 1, an isolation region 13 is formed between the high side circuit region 18 and the level shift resurf MOS 19 . This isolation region 13 is positioned between the first N-type well 11 and the second N-type well 12, as shown in FIG. are separated by the P-type semiconductor substrate 10 .

As shown in FIG. 2, a P-type impurity diffusion layer (also referred to as a “first conductivity type impurity diffusion layer”) 17 and a P-type well 35 are formed on the surface side of the second N-type well 12 . A first P-type impurity diffusion layer 22 is formed on the surface side of the P-type well 35 , and a gate insulating film 25 is formed on the first P-type impurity diffusion layer 22 . A gate electrode 26 is formed on the gate insulating film 25 .

An N-type source diffusion layer 23 and a second P-type impurity diffusion layer 27 are formed on the surface side of the first P-type impurity diffusion layer 22, and the second P-type impurity diffusion layer 27 is an N-type impurity diffusion layer. It is arranged adjacent to the source diffusion layer 23 . A back gate electrode 24 is formed on the N-type source diffusion layer 23 and the second P-type impurity diffusion layer 27 .

An N-type drain contact layer 28 is formed on the surface side of the second N-type well 12 , and a P-type impurity diffusion layer 17 is positioned between the N-type drain contact layer 28 and the P-type well 35 . are doing. A drain wiring 30 is formed on the N-type drain contact layer 28 and electrically connected to the N-type drain contact layer 28 and the wiring 15 .

An N-type impurity diffusion layer 29 is formed on the P-type impurity diffusion layer 17, the second N-type well 12 and the first N-type well 11, and the N-type impurity diffusion layer 29 serves as an N-type drain. It is arranged adjacent to the contact layer 28 . The N-type impurity diffusion layer 29 is also formed on the first N-type well 11 . Also, the N-type impurity diffusion layer 29 protrudes to the P-type semiconductor substrate 10 in the isolation region 13 .

This N-type impurity diffusion layer 29 is a layer forming a so-called (triple) RESURF structure for uniformizing the surface electric field of the drift portion.

As shown in FIG. 2, an insulating layer 14 is formed on the first N-type well 11, the isolation region 13 and the second N-type well 12. As shown in FIG.

A wiring 15 is formed on the insulating layer 14 and electrically connected to the second N-type well 12 .

The purpose of the wiring 15 is to stabilize the surface of the isolation region 13 . In other words, by forming the wiring 15 on the insulating layer 14, it is possible to prevent the influence of the external electric field and charged particles that affect the isolation region 13 having a low impurity concentration, stabilize the characteristics, and suppress changes over time. can.

A wiring 21 is formed on the insulating layer 14 and electrically connected to the second N-type well 12 via an N-type drain contact layer 28 . The wiring 21 extends in a direction perpendicular to the paper surface of FIG. 2 and forms a ring for the purpose of uniforming the electric field in the drift section. That is, by forming the wiring 21 on the insulating layer 14, the breakdown voltage of the RESURF MOS can be stabilized.

A first conductivity type region 16 is formed on the surface side of the P-type semiconductor substrate (Psub) 10 of the isolation region 13 , and this first conductivity type region is the P-type region 16 . This P-type region 16 is located below the wiring 15 .

The P-type region 16 is isolated from each of the first N-type well 11 and the second N-type well 12 by the P-type semiconductor substrate (Psub) 10 of the isolation region 13 . In other words, the P-type semiconductor substrate 10 exists between the P-type region 16 and the first N-type well 11 , and the P-type semiconductor substrate 10 exists between the P-type region 16 and the second N-type well 12 . A semiconductor substrate 10 is present. Therefore, the P-type region 16 is isolated from each of the first N-type well 11 and the second N-type well 12 .

The impurity concentration of the P-type region 16 is higher than that of the P-type semiconductor substrate 10 (see FIG. 2). As a result, leakage current due to parasitic transistors can be reduced without increasing the chip area.

According to this embodiment, the isolation region 13 is formed to isolate the first N-type well 11 and the second N-type well 12 by the P-type semiconductor substrate 10, and the isolation region 13 is formed on the P-type semiconductor substrate. A P-type region 16 is formed on the surface side of 10 . As a result, even if a high voltage is applied to the wiring 15 located on the insulating layer 14 and electrically connected to the second N-type well 12, the P-type region 16 functions as an anti-inversion layer. 2, leakage current due to parasitic transistors in the isolation region 13 can be reduced. In other words, even if the separation distance between the level shift resurf MOS 19 and the high side isolation island 18 is narrowed to reduce the chip area, the leak current due to the parasitic transistor can be suppressed. Therefore, the leak current due to the parasitic transistor can be reduced without increasing the chip area.

In other words, in the case of the isolation region 13 without the P-type region 16, if the isolation distance between the level shift resurf MOS 19 and the high side isolation island 18 is narrowed, when a high voltage is applied to the wiring 15 on the insulating layer 14, Leakage current due to parasitic transistors in the isolation region 13 increases. Even so, when a high voltage is applied to the wiring 15 on the insulating layer 14, the leakage current due to the parasitic transistor in the isolation region 13 can be reduced. Therefore, the leak current due to the parasitic transistor can be reduced without increasing the chip area.

Also, the width C of the P-type region 16 is preferably 0.5 μm or more and 4 μm or less, more preferably 1.5 μm or more and 4 μm or less. As a result, a power supply voltage Vcc of 20 V to 26 V and a high side drive voltage of about 600 V to 1200 V can be obtained, making it easy to reduce leakage current due to parasitic transistors in the isolation region without increasing the chip area. In other words, it is possible to greatly improve the leakage potential difference while maintaining the withstand voltage of the level shift resurf.

A distance B between the first N-type well 11 and the second N-type well 12 is preferably 17 μm or more and 27 μm or less, more preferably 20 μm or more and 27 μm or less. This makes it easier to reduce the leak current due to the parasitic transistor in the isolation region without increasing the chip area. In other words, it is possible to greatly improve the leakage potential difference while maintaining the withstand voltage of the level shift resurf.

The depth of the P-type region 16 is preferably 0.5 μm or more and 2.5 μm or less, more preferably 1.5 μm or more and 2.5 μm or less. This makes it easier to reduce the leak current due to the parasitic transistor in the isolation region without increasing the chip area.

The thickness of the insulating layer 14 is preferably 0.6 μm or more and 2 μm or less, preferably 0.85 μm or more and 2 μm or less.

A method for manufacturing the above semiconductor device will be described below. This method of manufacturing a semiconductor device has steps (a) to (d).

First, step (a) will be described.
As shown in FIGS. 1 and 2, a first N-type well 11 and a second N-type well 12 are formed in a P-type semiconductor substrate 10, which is a first conductivity type semiconductor substrate (Psub). Thereby, an isolation region 13 is formed between the first N-type well 11 and the second N-type well 12 . The isolation region 13 is a region that isolates the high side isolation island 18 and the level shift resurf MOS 19 by the P-type semiconductor substrate 10 located in the isolation region. That is, the isolation region 13 is located between the high-side isolation island 18 and the level shift RESURF MOS 19, and the gap between the first N-type well 11 and the second N-type well 12 is the P-type semiconductor substrate. 10 separate regions.

The first N-type well 11 is a first second-conductivity-type well located in a high-side circuit region (high-side isolation island) 18 . Also, the second N-type well 12 is a second second conductivity type well and is located in a level shift resurf MOS 19 arranged outside the high side isolation island 18 .

A third N-type well 33 is formed in the P-type semiconductor substrate 10 before forming the first N-type well 11 and the second N-type well 12 in the P-type semiconductor substrate 10 . A third N-type well 33 is located below the first N-type well 11 .

A third N-type well 33 is formed in the P-type semiconductor substrate 10 at the same time as the first N-type well 11 and the second N-type well 12 are formed in the P-type semiconductor substrate 10 . The third N-type well 33 is formed overlapping the first N-type well 11 . That is, impurity ions are introduced into the first and second N-type wells 11 and 12 in the same process, and impurity ions are introduced into the third N-type well 33 in a subsequent process. A third N-type well is formed.

Next, step (b) will be described.
A first conductivity type region (also referred to as “P-type region”) 16 having an impurity concentration higher than that of the P-type semiconductor substrate 10 is formed on the surface side of the P-type semiconductor substrate 10 in the isolation region 13 . The impurity concentration of the P-type semiconductor substrate 10 is preferably 1×10 ¹⁴ /cm ³ or more and 2×10 ¹⁴ /cm ³ or less, and the impurity concentration of the P-type region 16 is 2.3×10 ¹⁶ /cm 3 . ³ or more and 2.8×10 ¹⁶ /cm ³ or less.

Next, step (c) will be described.
An insulating layer 14 is formed over the first N-type well 11 , the P-type region 16 , the isolation region 13 and the second N-type well 12 . The impurity concentration of the first N-type well 11 is preferably 7.5×10 ¹⁶ /cm ³ or more and 8.5×10 ¹⁶ /cm ³ or less, and the impurity concentration of the second N-type well 12 is preferably , 9.5×10 ¹⁵ /cm ³ or more and 1.05×10 ¹⁶ /cm ³ or less.

It is preferable to have the following steps between step (b) and step (c).
A first P-type impurity diffusion layer 22 is formed on the surface side of the P-type well 35 . Next, an N-type impurity diffusion layer 29 is formed on the P-type impurity diffusion layer 17 , the second N-type well 12 and the first N-type well 11 .

Next, an N-type source diffusion layer 23 is formed on the surface side of the first P-type impurity diffusion layer 22 . Also, a second P-type impurity diffusion layer 27 is formed on the surface side of the first P-type impurity diffusion layer 22 . Also, an N-type drain contact layer 28 is formed on the surface side of the second N-type well 12 . Also, an N-type contact layer 31 is formed on the surface side of the first N-type well 11 .

Next, a gate insulating film 25 is formed on the first P-type impurity diffusion layer 22 .

Next, step (d) will be described.
A wiring 15 is formed on the insulating layer 14 . This wiring 15 is electrically connected to the second N-type well 12 . This wiring 15 is located above the P-type region 16 .

Specifically, in step (d), the gate electrode 26 is formed on the gate insulating film 25 and the wiring 15 and the wiring 21 are preferably formed on the insulating layer 14 .

Next, an insulating layer 50 is formed on the wiring 15 , the wiring 21 , the gate electrode 26 and the insulating layer 14 .

Next, the drain wiring 30 is formed on the insulating layer 50 and the back gate electrode 24 is formed on the N-type source diffusion layer 23 and the second P-type impurity diffusion layer 27 .

In the semiconductor device manufactured by the manufacturing method described above, the P-type region 16 is isolated from the first N-type well 11 and the second N-type well 12 by the isolation region 13 of the P-type semiconductor substrate 10 . there is

According to this embodiment, the isolation region 13 is formed to isolate the first N-type well 11 and the second N-type well 12 by the P-type semiconductor substrate 10, and the isolation region 13 is formed on the P-type semiconductor substrate. A P-type region 16 is formed on the surface side of 10 . As a result, even if a high voltage is applied to the wiring 15 located on the insulating layer 14 and electrically connected to the second N-type well 12, the leakage current due to the parasitic transistor in the isolation region 13 shown in FIG. can be reduced. In other words, even if the separation distance between the level shift resurf MOS 19 and the high side isolation island 18 is narrowed to reduce the chip area, the leak current due to the parasitic transistor can be suppressed. Therefore, the leak current due to the parasitic transistor can be reduced without increasing the chip area.

In the step (b), as shown in FIG. 2, the P-type region 16 is formed on the surface side of the P-type semiconductor substrate 10 in the isolation region 13, and at the same time, the second N-type well 12 is formed with the first conductivity type. The step of forming an impurity diffusion layer (also referred to as “P-type impurity diffusion layer”) 17 is preferable. By doing so, the P-type region (P-type impurity diffusion layer) 16 can be formed without increasing the number of resist masks, and an increase in manufacturing cost can be suppressed.

That is, since the P-type impurity diffusion layer 17 is an impurity diffusion layer that is also formed in a conventional semiconductor device, the P-type impurity diffusion layer 16 is removed using a resist mask for forming the P-type impurity diffusion layer 17. If formed, there is no need to add a new resist mask, and the P-type impurity diffusion layer 16 can be formed without increasing the number of resist masks. As a result, an increase in cost can be suppressed. The impurity concentration of the P-type impurity diffusion layer 17 is preferably 1.4×10 ¹⁶ /cm ³ or more and 1.6×10 ¹⁶ /cm ³ or less.

In the above step (b), as shown in FIG. 2, the P-type region 16 is formed on the surface side of the P-type semiconductor substrate 10 in the isolation region 13, and at the same time, the second N-type well 12 is filled with P-type impurities. It may be a step of forming the diffusion layer 17 and the P-type well 35 .

FIG. 3 shows a modification of the semiconductor device shown in FIG. 2, the same parts as those in FIG. 2 are denoted by the same reference numerals, and only different parts will be described.

The semiconductor device shown in FIG. 3 is obtained by removing the N-type impurity diffusion layer 29 from the semiconductor device shown in FIG. Also, the P-type impurity diffusion layer 17 is a layer forming a so-called double RESURF structure.

In the modification shown in FIG. 3 as well, the same effects as in the present embodiment can be obtained.

10 First conductivity type semiconductor substrate (P-type semiconductor substrate, Psub)
11 first second conductivity type well (first N type well)
12 second second conductivity type well (second N type well)
13 Separation region 14 Insulating layer 15 Wiring 16 First conductivity type region (P-type region)
17 First conductivity type impurity diffusion layer (P-type impurity diffusion layer)
18 High-side circuit area (high-side isolated island)
19 level shift resurf MOS
20 High-breakdown-voltage termination region B Distance between first second-conductivity-type well and second second-conductivity-type well (distance between first N-type well and second N-type well)
C Width of first conductivity type region (width of P-type region)

Claims (7)

a first conductivity type semiconductor substrate;
a high side circuit region arranged on the semiconductor substrate in plan view;
a first second conductivity type well arranged on the surface side of the semiconductor substrate and located in the high side circuit region;
a high breakdown voltage termination region arranged on the periphery of the high side circuit region in plan view;
a level shift resurf MOS positioned in the high breakdown voltage termination region in plan view;
a second second conductivity type well arranged on the surface side of the semiconductor substrate and arranged in the level shift resurf MOS;
is positioned between the high side circuit region and the level shift resurf MOS, and the first conductivity type well is provided between the first well of the second conductivity type and the second well of the second conductivity type; a separation region separated by a semiconductor substrate;
an insulating layer overlying the first well of second conductivity type, the isolation region and the second well of second conductivity type;
a wiring disposed on the insulating layer and electrically connected to the second well of the second conductivity type;
a first conductivity type region located under the wiring and arranged on the surface side of the first conductivity type semiconductor substrate of the isolation region;
the first conductivity type region is isolated from each of the first second conductivity type well and the second second conductivity type well by the semiconductor substrate of the first conductivity type in the isolation region;
A semiconductor device, wherein the impurity concentration of the first conductivity type region is higher than the impurity concentration of the semiconductor substrate of the first conductivity type. In claim 1,
A semiconductor device, wherein the width of the first conductivity type region is 0.5 μm or more and 4 μm or less. In claim 1 or 2,
A semiconductor device, wherein the distance between the first well of the second conductivity type and the second well of the second conductivity type is 17 μm or more and 27 μm or less. In any one of claims 1 to 3,
A semiconductor device, wherein the depth of the first conductivity type region is 0.5 μm or more and 2.5 μm or less. In any one of claims 1 to 4,
A semiconductor device, wherein the insulating layer has a thickness of 0.6 μm or more and 2 μm or less. In a semiconductor substrate of a first conductivity type, a first second conductivity type well located in a high side circuit region, and a level shift resurf MOS located outside the high side circuit region in plan view. 2 wells of the second conductivity type are formed, are located between the high side circuit region and the level shift resurf MOS in a plan view, and are located between the first well of the second conductivity type and the second well. a step (a) of forming an isolation region separating from the second conductivity type well by the semiconductor substrate of the first conductivity type;
step (b) of forming a first first-conductivity-type region having a higher impurity concentration than the semiconductor substrate on the surface side of the first-conductivity-type semiconductor substrate in the isolation region;
forming an insulating layer over the first well of the second conductivity type, the first region of the first conductivity type, the isolation region and the second well of the second conductivity type;
(d) forming a wiring located on the insulating layer and electrically connected to the second well of the second conductivity type;
the wiring is located on the first conductivity type region;
The first conductivity type region is isolated from each of the first second conductivity type well and the second second conductivity type well by the semiconductor substrate of the first conductivity type in the isolation region. A method of manufacturing a semiconductor device characterized by: In claim 6,
In the step (b), the first conductivity type region is formed on the surface side of the first conductivity type semiconductor substrate in the isolation region, and at the same time, a first conductivity type impurity is diffused into the second second conductivity type well. A method of manufacturing a semiconductor device, comprising: forming a layer.

Images