TW201316718A - Encoding method, encoding apparatus, decoding method, decoding apparatus, data transmitting apparatus and data receiving apparatus - Google Patents

Abstract

An encoding method includes: detecting a first bitstream to obtain a first detection result; and inserting an identifier bit to the first bitstream according to the first detection result, and accordingly forming a second bitstream, wherein difference between a number of bits in the first bitstream and that in the second bitstream is 1. A decoding method includes: generating a first detection result by detecting a specific bit set in a first bitstream, wherein the specific bit set includes at least one bit; and converting the first bitstream into the second bitstream according to the first detection result, wherein difference between a number of bits in the first bitstream and that in the second bitstream is 1.

Description

Encoding method, encoding device, decoding method, decoding device, data transmitting device, and data receiving device

The present invention relates to data encoding and decoding, and more particularly to a method and apparatus for encoding by inserting a recognized bit to an uncoded data, and a related decoding method, decoding device, data transmitting device and data receiving device.

In general, when transmitting data between the Transmitter (TX) and the Receiver (RX), in addition to the mechanism for transmitting/receiving data, a transmission/reception clock is required. Information mechanism. When transmitting data in the high-speed interface, in order to improve the signal transmission quality, reduce electromagnetic interference (EMI), provide error correction (Error Correction), and save clock circuits, the data to be transmitted is generally encoded to satisfy Above needs. Traditionally, 4B5B and 8B10B coding methods are used. However, both coding methods need to use a coding table (Coding table), that is, directly refer to the correspondence before and after data coding in a table lookup manner, and then encode the data. /Decoding, therefore, the transceiver (ie, the transmitting end and the receiving end) need to provide additional circuitry to store the encoding table, resulting in an increase in the size of the transceiver circuit.

The encoding method of 4B5B requires a 5-bit bandwidth (Bandwidth) to transmit 4-bit data, and the 8B10B encoding method requires 10-bit bandwidth to transmit 8-bit data. The above two encoding methods are sacrificed. The bandwidth ratio is 25% (that is, the transmission of 4 bits will sacrifice 1 bit). Once the bandwidth is sacrificed, the transceiver needs to transmit the same amount of data at a faster transmission speed. However, when the transmission speed is increased (that is, the operation frequency is increased), the transceiver circuit is extra. The current consumed also increases, which in turn increases the loss of energy. Furthermore, since the receiving end must obtain the phase or frequency of the data through the number of conversions of the bits in the data when receiving the data, if the number of bits having the same logical value in the data occurs continuously for too many times The receiving end will not be able to correctly obtain the phase or frequency of the data. For example, by using the 4B5B encoding method to transmit 8-bit data, there may be 8 consecutive logic 0s or logic 1s, thus reducing the encoding quality.

In addition, since the data transmission interface includes a phase-locked loop (PLL) type and a delay-locked loop (DLL) type, the 4B5B and 8B10B only support the data transmission interface of the phase-locked loop type (also That is, the coding elasticity is low), so when the data transmission interface is a delay phase-locked loop type, the transceiver terminal needs an additional circuit mechanism to provide encoding/decoding, thereby increasing the size of the transceiver circuit.

Therefore, there is a need for an innovative coding method that can reduce the bandwidth sacrificed during data transmission, reduce energy loss, improve coding quality, increase coding flexibility, and/or save transceiver circuit size.

In view of the above, an object of the present invention is to provide an encoding method and an encoding apparatus for inserting an identification bit into an uncoded material, an associated decoding method, a decoding apparatus, a data transmission apparatus, and a data receiving apparatus, to solve the above problem. problem.

According to an embodiment of the present invention, an encoding method includes: detecting a first bit stream to obtain a first detection result; and determining a recognition bit according to the first detection result. Inserting into the first bit stream, and forming a second bit stream, wherein the number of bits of the first bit stream is different from the number of bits of the second bit stream by one.

According to an embodiment of the present invention, an encoding method includes: detecting a least significant bit of a first bit stream to obtain a first detection result; and determining, according to the first detection result, An identification bit is inserted after the least significant bit of the first bit stream, and a second bit stream is formed accordingly.

According to an embodiment of the present invention, an encoding method includes: detecting a most significant bit of a first bit stream to obtain a first detection result; and determining, according to the first detection result, A recognition bit is inserted before the most significant bit of the first bit stream, and a second bit stream is formed accordingly.

According to an embodiment of the present invention, an encoding method includes: inserting at least one identification bit into a first bit stream, and forming a second bit stream; determining the second a signal quality of the bit stream; when the signal quality satisfies a criterion, the second bit stream is output; and when the signal quality does not satisfy the criterion, the second bit stream is adjusted to generate and output A third bit stream.

According to an embodiment of the present invention, a decoding method is disclosed. The decoding method includes: detecting a specific bit set in a first bit stream to generate a first detection result, where the specific bit set includes Having at least one bit; and converting the first bit stream into a second bit stream according to the first detection result, wherein the number of bits of the first bit stream and the second bit stream The number of bits differs by 1.

According to an embodiment of the invention, an encoding apparatus is disclosed, the encoding apparatus comprising: a detecting unit and a processing unit. The detecting unit is configured to detect a first bit stream to obtain a first detection result. The processing unit is coupled to the detecting unit, configured to insert a recognition bit into the first bit stream according to the first detection result, and form a second bit stream, wherein the The number of bits in a bit stream differs from the number of bits in the second bit stream by one.

According to an embodiment of the present invention, an encoding apparatus is further disclosed. The encoding apparatus includes: a detecting unit and a processing unit. The detecting unit is configured to detect a least significant bit of a first bit stream to obtain a first detection result. The processing unit is coupled to the detecting unit, configured to insert a recognition bit into the least significant bit of the first bit stream according to the first detection result, and form a second bit accordingly Yuan stream.

According to an embodiment of the present invention, an encoding apparatus is further disclosed. The encoding apparatus includes: a detecting unit and a processing unit. The detecting unit is configured to detect the most significant bit of the first bit stream to obtain a first detection result. The processing unit is coupled to the detecting unit, configured to insert a recognition bit before the most significant bit of the first bit stream according to the first detection result, and form a second bit according to the first detection result. Yuan stream.

According to an embodiment of the invention, an encoding apparatus is further disclosed, the encoding apparatus comprising: a first processing unit and a second processing unit. The first processing unit is configured to insert at least one identification bit into a first bit stream and form a second bit stream accordingly. The second processing unit is coupled to the first processing unit for determining a signal quality of the second bit stream. When the signal quality satisfies a criterion, the second bit stream is output, and when the signal quality does not satisfy the criterion, the second bit stream is adjusted to generate and output a third bit stream.

According to an embodiment of the present invention, a decoding apparatus is disclosed. The encoding apparatus includes: a detecting unit and a processing unit. The detecting unit is configured to detect a specific bit set in a first bit stream to generate a detection result, wherein the specific bit set includes at least one bit. The processing unit is coupled to the detecting unit, configured to convert the first bit stream into a second bit stream according to the detection result, where the number of bits of the first bit stream and the first The number of bits in the binary stream differs by one.

According to an embodiment of the present invention, a data transfer apparatus is disclosed. The data transfer apparatus includes: a phase locked loop unit, a parallel to serial conversion unit, an encoding unit, and a driving unit. The phase locked loop unit is configured to generate the first control signal and the second control signal according to the clock signal. The parallel to serial conversion unit is configured to convert the parallel data into the serial data according to the first control signal. The coding unit is configured to insert a bit into the serial data according to the second control signal, and form an encoded data, wherein the number of bits of the serial data and the number of bits of the encoded data The difference is 1. The driving unit is configured to output the encoded data as an encoded signal.

According to an embodiment of the present invention, a data receiving apparatus is disclosed. The data receiving apparatus includes: a comparing unit, a clock recovery unit, a decoding unit, and a serial-to-parallel conversion unit. The comparison unit is configured to generate an input data based on the encoded data. The clock recovery unit is configured to generate a first control signal, a second control signal, and a clock signal according to the input data. The decoding unit is configured to convert the input data into a decoded data according to the first control signal, wherein the number of bits of the input data is different from the number of bits of the decoded data by one. The serial to parallel conversion unit is configured to convert the decoded data into a parallel data according to the first control signal.

First, please refer to FIG. 1. FIG. 1 is a generalized flowchart of an embodiment of an encoding method of the present invention. In step 110, a first bit stream is first detected to obtain a first detection result, where the first bit stream is an uncoded material, and then, in step 120, it is obtained according to step 110. The first detection result inserts a recognition bit into the first bit stream, and accordingly forms a second bit stream, wherein the number of bits of the first bit stream and the second bit stream The number of bits differs by 1. Please refer to FIG. 1 and FIG. 2 together. FIG. 2 is a flowchart of an embodiment of the encoding method of the present invention. The flow shown in FIG. 2 is based on the generalized flow shown in FIG. In FIG. 2, the step 110 shown in FIG. 1 may include detecting a type of a specific bit set in the first bit stream at a specific bit position as the first detection result ( As shown in step 210), the particular set of bits includes at least one bit located in the first bitstream. In addition, the step 120 shown in FIG. 1 may include inserting the identification bit having a first logic value into the first bit stream when the pattern of the specific bit set is a first type ( As shown in steps 224 and 226 in step 220, and according to the second bit stream, and when the pattern of the particular bit set is different from the second version of the first type, The identification bit having a second logic value is inserted into the first bit stream (as indicated by steps 224 and 228 in step 220) and a second bit stream is formed accordingly.

In step 220, the identification bit can be inserted between one of the adjacent bits immediately adjacent to the particular set of bits and the particular set of bits, however, when detected in the first bitstream When the specific bit position is the most significant bit (MSB) or the least significant bit (LSB) of the first bit stream (that is, the specific bit set is the highest) a valid bit or a least significant bit), except that the identifying bit is inserted between an adjacent bit immediately adjacent to the most significant bit/least significant bit of the first bit stream, The identification bit is inserted before the most significant bit of the first bit stream, or the identification bit is inserted after the least significant bit of the first bit stream. Therefore, in an embodiment, the most significant bit of the first bit stream BS1 can be detected to obtain a first detection result DR1, and then the identification bit IB is inserted according to the first detection result DR1. Before the most significant bit of the first bit stream BS1, a second bit stream BS2 is formed accordingly. In another embodiment, the least significant bit of the first bit stream BS1 may be detected to obtain a first detection result DR1, and then an identification bit IB is obtained according to the first detection result DR1. After being inserted into the least significant bit of the first bit stream BS1, a second bit stream BS2 is formed accordingly.

Please refer to FIG. 3A together with FIG. 2, wherein FIG. 3A is for inserting a recognition bit IB into a first bit stream BS1 having a bit number N (ie, having one of N bits). Schematic diagram of uncoded data). In FIG. 3A, the specific location of the first bit stream BS1 is the bit position of the least significant bit, and the corresponding specific bit set SB is “0” (ie, the first detection described above). result). As described above, in addition to the insertion of the identification bit IB between one of the adjacent bits (i.e., the bit NB) immediately adjacent to the specific bit set SB and the specific bit set SB (as shown in FIG. 3A) P1), it is also possible to insert the identification bit IB after the least significant bit (as in the position P2 shown in Fig. 3A). In addition, since the pattern of the specific bit set SB is “0”, the identification bit IB having different logic values can be inserted according to different design requirements/measurements. For example, when the pattern of the specific bit set SB is "0" (for example, the first type described above), the identification bit IB having the logical value "1" (for example, the first logical value described above) is inserted. To position P2; conversely, when the pattern of the specific bit set SB is "1" (for example, the second pattern described above), the identification bit having the logical value "0" (for example, the second logical value described above) The element IB is inserted to position P2. Therefore, in this embodiment, the identification bit IB having the logical value "1" is inserted into the right position P2 of the least significant bit of the first bit stream BS1, thereby forming a one having the number of bits N+1. The second bit stream BS2 (i.e., has one of N+1 bits of encoded material).

In a design change, step 220 shown in FIG. 2 further includes converting the particular set of bits to the second pattern when the pattern of the particular set of bits is the first pattern. Please refer to FIG. 4, which is a flow chart of another embodiment of the encoding method of the present invention, wherein the steps shown in FIG. 4 are based on the flow shown in FIG. Step 420 includes inserting the identification bit having a first logic value into the first bit stream (as shown in steps 224 and 226) and when the pattern of the particular bit set is a first pattern Converting the particular set of bits into a second pattern (as shown in step 425), and thereby forming a second bit stream, and when the pattern of the particular bit set is different from the first type In the case of the second type, the identification bit having a second logic value is inserted into the first bit stream (as shown in steps 224 and 228), and a second bit stream is formed accordingly. It is worth noting that if the results obtained are substantially the same, the order of steps 425 and 226 can be reversed.

Please refer to FIG. 3B together with FIG. 4, wherein FIG. 3B is to insert a recognition bit IB into a first bit stream BS1 having a bit number N (ie, having one of N bits). Schematic diagram of uncoded data). As shown in FIG. 3B, the specific location of the first bit stream BS1 is the bit position of the first two bits calculated by the most significant bit, and the corresponding specific bit set SB is of the type "00" (that is, the first detection result described above), and the position at which the recognition bit IB is inserted is after the least significant bit (ie, position P3). It should be noted that after inserting the identification bit IB into the first bit stream BS1, the identification bit IB does not have to be in close proximity to the specific bit set SB, that is, the identification bit IB can be inserted into the first Between any two bits in the bit stream BS1, before the most significant bit or after the least significant bit.

In this embodiment (but the invention is not limited thereto), when the type of the specific bit set SB is "00" or "11" (for example, the first type described above), it will have a logical value of "1". The identification bit IB of (for example, the first logical value described above) is inserted to the position P3; conversely, when the pattern of the specific bit set SB is "01" or "10" (for example, the second type described above), then The identification bit IB having a logical value of "0" (e.g., the second logical value described above) is inserted into the position P3. Further, when the type of the specific bit set SB is "00" or "11", the pattern of the specific bit set SB is converted to "01" or "10". Therefore, in this embodiment, the identification bit IB having the logical value "1" is inserted into the right position P3 of the least significant bit of the first bit stream BS1, thereby forming a one having the number of bits N+1. The second bit stream BS2 (i.e., has one of N+1 bits of encoded material).

Please note that the above description is for illustrative purposes only and is not intended to be a limitation of the present invention, that is, the location of a particular set of bits, the number of bits contained in a particular set of bits, and the identified bits are uncoded. The position of the data inserted and/or the logical value of the identified bit corresponding to a different type of particular bit set can be appropriately adjusted depending on actual design requirements/measurements.

When the embodiment of the above-described encoding method of the present invention is applied to a transmission interface that does not need to consider the number of consecutive bits having the same logical value in the transmitted data (for example, a delay-locked loop type (DLL-based) In the case of the transmission interface, in the flowchart shown in FIG. 2 (or FIG. 4), the second bit stream BS2 generated in step 226 or step 228 is directly output as the desired coded data. However, when the above-described embodiment of the encoding method of the present invention is applied to a transmission interface (e.g., phase-locked loop type (PLL-based) transmission) that requires consideration of the number of consecutive bits having the same logical value in the transmitted data. In the case of the interface, the second bit stream BS2 generated in step 226 or step 228 shown in FIG. 2 (or FIG. 4) may need to be appropriately adjusted based on the signal quality to satisfy the coding quality. Requirements.

Please refer to FIG. 5, which is a flow chart of another embodiment of the encoding method of the present invention. In step 510, at least one identification bit is inserted into a first bit stream, and a second bit stream is formed, and then, in step 520, a signal quality of the second bit stream is determined. . When the signal quality satisfies a criterion, the second bit stream is output (as shown in step 530), and when the signal quality does not satisfy the criterion, the second bit stream is adjusted to generate and output a The third bit stream (as shown in step 540). For example, when the signal quality meets the encoding quality requirement, the second bit stream is directly outputted as an encoded data. However, when the signal quality does not meet the encoding quality requirement, the second bit stream is adjusted. The signal quality is used to generate and output a third bit stream as an encoded material. In addition, the above criterion includes that the same logical value continuously appears in the second bit stream does not exceed a predetermined number of consecutive times, and/or a first logic value and a second logic value are in the second bit stream. The number of conversions is not less than a predetermined number of conversions. For example (but the invention is not limited thereto), when the logic "0" or the logic "1" continuously appears in the second bit stream more than 6 bits, the second bit needs to be adjusted. The stream, or when the number of transitions of logic "0" and logic "1" in the second bit stream is less than 3 times, the second bit stream needs to be adjusted. Moreover, step 510 can be implemented using steps 110 and 120 shown in FIG. 1 (but the invention is not limited thereto).

In an embodiment, step 540 can include performing a logical operation on a plurality of bits in the second bit stream to generate the third bit stream. Please refer to FIG. 6. FIG. 6 is an exemplary flow chart of an implementation of the step 540 shown in FIG. 5. In step 652, at least one first bit in the second bit stream is inverted to satisfy the determination criterion; in step 654, a plurality of bits in the second bit stream are detected to generate a first And detecting, in step 656, inverting at least one second bit in the second bit stream according to the second detection result to generate the third bit stream. For example, step 652 is for interrupting the case where the same logical value continuously appears in the second bit stream exceeds the predetermined number of consecutive times, however, at least the second bit stream is inverted. After a bit, the second bit stream at this time may be repeated with the second bit stream output directly via step 540 shown in FIG. 5, so step 654 and step 656 are used for the first bit stream. The binary stream detects and inverts at least the second bit to avoid duplicate encoded data.

Please refer to FIG. 7. FIG. 7 is a flow chart showing an embodiment of the transmission method applied to the phase-locked loop type of the coding method of the present invention. In this embodiment, the step 654 may include performing a logical exclusive exclusion (XOR) operation on the plurality of bits to generate the second detection result. For example (but the invention is not limited thereto), the first bit stream BS1 is "00000001", and the specific bit set SB is the least significant bit "1", and then the bit IB is recognized. After being inserted into the least significant bit of the first bit stream BS1, the second bit stream BS2 "000000010" is formed (that is, step 510 shown in FIG. 5). Since the number of consecutive occurrences of logic "0" in the second bit stream BS2 "000000010" exceeds 5 times (that is, the predetermined number of consecutive times), the signal quality of the second bit stream BS2 does not satisfy the criterion. Therefore, the second bit stream BS2 needs to be adjusted to generate and output the third bit stream BS3 (that is, step 530 and step 540 shown in FIG. 5). First, the fourth bit from the most significant bit in the second bit stream BS2 is inverted. At this time, the second bit stream BS2 becomes "000100010" (that is, step 652 of FIG. 6). Next, for the second and third bits of the second bit stream BS2 calculated by the least significant bit, a logical mutual exclusion operation is performed to generate the second detection result (ie, the sixth Step 654). In this embodiment, when the logical mutual exclusion operation is 1, the third bit and the least significant bit calculated by the most significant bit are inverted, and when the logical mutually exclusive operation is 0, the inversion is performed. The second bit from the least significant bit, so that the second bit stream BS2 is converted from "000100010" to the third bit stream BS3 "001100011" (ie, the steps of Figure 6) 656). It is worth noting that when encoding in the above implementation manner, all the last two bits of the plurality of second bit streams satisfying the criterion (that is, the first two bits from the least significant bit) The type of the code is "01" or "10" after the encoding process, and all the last two bits of the plurality of second bit streams that do not satisfy the criterion are "00" after the encoding process. "11", therefore, the subsequent decoding process can easily know whether or not one of the encoded data to be processed has a conversion process of the enhanced signal quality in the encoding process.

Please note that the above description is for illustrative purposes only and is not intended to be a limitation of the present invention. That is, the adjustment operation performed for the signal quality is not limited to the above. As long as at least one identification bit is inserted into a first bit stream to form a second bit stream, and the signal quality of the bit stream is determined to directly output or adjust the bit stream, and then output, and And the encoding method for distinguishing whether or not an encoded material has been subjected to the conversion processing of the enhanced signal quality by using the adjustment operation performed is in accordance with the inventive spirit of the present invention and falls within the scope of the present invention.

Please refer to FIG. 8A, which is an example flow diagram of another implementation of step 540 shown in FIG. 5. In step 852, at least one first bit in the second bit stream is inverted to satisfy the criterion; in step 854, at least one of the first bit streams is detected in the first bit stream a last at least one bit to generate a second detection result; and in step 856, inverting at least one second bit in the second bit stream according to the second detection result to generate the third Bit stream. For example, step 852 can be used to interrupt the case where the same logical value continuously appears in the second bit stream exceeds the predetermined number of consecutive times, and steps 854 and 856 can be used to perform the second bit stream. Detecting and inverting at least the second bit to avoid duplicate encoded data. Please refer to FIG. 8B, which is an example flow chart of still another implementation of step 540 shown in FIG. 5. In this embodiment, the foregoing manner of generating the second detection result may include detecting a last one of the last bit stream and a complex number of the first bit stream The bits are generated to generate the second detection result (as shown in step 855). In short, in this embodiment, the bit stream of the bit stream to be encoded and the bit stream adjacent to the bit stream to be encoded are considered for dynamic coding.

Please refer to FIG. 9. FIG. 9 is a flow chart showing another embodiment of the transmission method applied to the phase-locked loop type of the coding method of the present invention. In this embodiment (but the invention is not limited thereto), a first bit stream BS1 is "00000000", and a specific bit set SB is the first two bits from the most significant bit. 00", next, after inserting a recognition bit IB "1" into the least significant bit of the first bit stream BS1 according to the pattern "00" of the specific bit set SB, the pattern of the specific bit set SB "00" is converted to another type "01" to form a second bit stream BS2 "010000001" (i.e., step 510 shown in Fig. 5). Since the number of consecutive occurrences of logic "0" in the second bit stream BS2 "010000001" exceeds 5 times (that is, the predetermined number of consecutive times), the quality of the signal of the second bit stream BS2 does not satisfy a judgment. The criterion is that the second bit stream BS2 needs to be adjusted to generate and output a third bit stream BS3 (ie, step 530 and step 540 shown in FIG. 5). First, the fifth bit from the most significant bit in the second bit stream BS2 is inverted. At this time, the second bit stream BS2 becomes "010010001" (that is, step 852 of FIG. 8A). Next, detecting the last one of the previous bit stream (for example, "1") and the first two bits of the second bit stream BS2 (ie, "01") (ie, step 854 of Figure 8A). In this embodiment, when the last bit of the previous bit stream and the first two bits of the first bit stream BS2 are "1" and "01", respectively, The first two bits in the first bit stream BS2 are converted to "00"; when the last bit in the previous bit stream and the first two bits in the second bit stream BS2 When the patterns of the elements are "0" and "01", the first two bits in the second bit stream BS2 are converted to "11", and the least significant bit in the second bit stream BS2 is inverted. The third bit from the first bit; the last bit in the previous bit stream and the first two bits in the second bit stream BS2 are "1" and "10" respectively. Converting the first two bits from the beginning of the second bit stream BS2 to "00" and inverting the third bit from the least significant bit in the second bit stream BS2; When the last bit of the previous bit stream and the first two bits of the first bit stream BS2 are respectively "0" and "10", the second bit stream BS2 is used. In the beginning Two bits is converted to "11" (ie, step 856 of Figure 8A). As a result, the generated third bit stream BS3 is "000010001". It is worth noting that, when encoding in the above implementation manner, all of the plurality of second bit streams satisfying the criterion are preceded by two bits (ie, the first two bits from the most significant bit). The type of the code is "01" or "10" after the encoding process, and all the two bits before the plurality of second bit streams that do not satisfy the criterion are "00" or after the encoding process. "11", therefore, the subsequent decoding process can easily know whether or not one of the encoded data to be processed has a conversion process of the upgraded signal quality in the encoding process. Please note that the above is for illustrative purposes only and is not intended to be a limitation of the present invention. That is to say, the dynamic adjustment operation performed on the signal quality is not limited to the above. For example, the first bit of the second bit stream BS2 may be adjusted according to other plural bits of the previous bit stream, and the encoded data outputted by the other plurality of bits may be distinguished. Original signal quality (ie, signal quality before unencoding). In short, as long as at least one identification bit is inserted into a first bit stream to form a second bit stream, the signal quality of the bit stream is determined to directly output the bit stream or via adjustment processing. After the output, the bit stream is dynamically adjusted according to a bit stream before the bit stream, and/or the adjusted operation is used to distinguish whether the encoded data is encoded by the upgrade signal quality. The method is in accordance with the spirit of the invention and falls within the scope of the invention.

Please refer to FIG. 10, which is a generalized flowchart of another embodiment of the encoding method of the present invention. In step 1010, at least one identification bit is inserted into a first bit stream, and a second bit stream is formed accordingly. In step 1020, the type of the transmission interface to be transmitted by the second bit stream is checked, if it is not necessary to consider the transmission interface of the number of consecutive bits having the same logical value in the transmitted data (for example, the delay phase locked loop type) Step 1030 is performed; otherwise, step 1040 is performed. In step 1030, the second bit stream is output. In step 1040, the signal quality of the second bit stream is determined. If the signal quality is good, step 1050 is performed; otherwise, step 1060 is performed. In step 1050, the second bit stream is output. In step 1060, the second bit stream is adjusted to generate and output a third bit stream. In short, the coding method of the present invention can implement a dual mode coding mode, that is, the coding method proposed by the present invention can be dynamically switched by different data transmission interfaces. In addition, step 1010 can be utilized (but the invention is not limited thereto) by step 110 and step 120 shown in FIG. 1, and steps 1040, 1050, and 1060 are available (but the invention is not limited thereto) Steps 520, 530, and 540 shown in FIG. 5 are implemented. It should be noted that, in a design change, after performing step 1010, the signal quality may be first determined (step 1040), and then the type of the data transmission interface is determined (step 1020) to perform the corresponding processing. In another design change, the user can manually switch the encoding mode of the data transmission according to the type of the data transmission interface. Therefore, step 1020 can be omitted.

Please refer to FIG. 11A, which is a functional block diagram of an embodiment of an encoding apparatus of the present invention. The encoding device 1100 includes (but is not limited to) a detecting unit 1110 and a processing unit 1120. The detecting unit 1110 is configured to detect a first bit stream BS1 to obtain a first detection result DR1. The processing unit 1120 is coupled to the detecting unit 1110, for inserting a identifying bit IB into the first bit stream BS1 according to the first detecting result DR1, and forming a second bit stream BS2, wherein The number of bits of the first bit stream BS1 differs from the number of bits of the second bit stream BS2 by one. In a design change, the detecting unit 1110 is further configured to detect the least significant bit of the first bit stream BS1 to obtain the first detection result DR1, and the processing unit 1120 is further configured to use the first detection result DR1. An identification bit IB is inserted after the least significant bit of the first bit stream BS1, and a second bit stream BS2 is formed accordingly. In another design change, the detecting unit 1110 is further configured to detect the most significant bit of the first bit stream BS1 to obtain the first detection result DR1, and the processing unit 1120 is further configured to use the first detection result DR1. An identification bit IB is inserted before the most significant bit of the first bit stream BS1, and a second bit stream BS2 is formed accordingly. Since the skilled artisan can easily understand the related operations of the encoding device 1100 by reading the related descriptions of FIGS. 1 to 4, further description will not be repeated here.

Please refer to FIG. 11B, which is a functional block diagram of another embodiment of the encoding apparatus of the present invention. The encoding device 1101 includes, but is not limited to, a first processing unit 1111 and a second processing unit 1121. The first processing unit 1111 is configured to insert at least one identification bit IB into a first bit stream BS1, and thereby form a second bit stream BS2. The second processing unit 1121 is coupled to the first processing unit 1111 for determining a signal quality of the second bit stream BS2, wherein when the signal quality satisfies a criterion, the second bit stream BS2 is output, and when When the signal quality does not satisfy the criterion, the second bit stream BS2 is adjusted to generate and output a third bit stream BS3. Since the skilled artisan can easily understand the related operations of the encoding device 1200 by reading the related descriptions of FIGS. 5 to 9, the further description will not be repeated here.

Please refer to FIG. 11C, which is a functional block diagram of still another embodiment of the encoding apparatus of the present invention. The encoding device 1102 includes, but is not limited to, a first processing unit 1112, a switching unit 1122, and a second processing unit 1132. The first processing unit 1112 is configured to insert at least one identification bit IB into a first bit stream BS1, and thereby form a second bit stream BS2. The switching unit 1122 is coupled to the first processing unit 1111 for checking the type of the transmission interface to be transmitted by the second bit stream BS2. If the type of the transmission interface to be transmitted does not need to consider the same logical value in the transmitted data. The number of consecutive bits (for example, the transmission interface of the delay phase-locked loop type) directly outputs the second bit stream BS2; otherwise, the second bit stream BS2 is transmitted to the second processing unit 1132 for signal quality. Judge. The second processing unit 1121 is coupled to the switching unit 1122 for determining a signal quality of the second bit stream BS2, wherein when the signal quality satisfies a criterion, the second bit stream BS2 is output, and when the signal is When the quality does not satisfy the criterion, the second bit stream BS2 is adjusted to generate and output a third bit stream BS3.

Please note that the description of FIG. 10 shows that the switching unit 1122 can be omitted in the case where the user manually switches the encoding mode of the data transmission in advance. In addition, the switching unit 1122 can also be combined/integrated into the second processing unit 1132. Therefore, the second processing unit 1132 is a common circuit that performs different encoding modes according to different transmission interface types, thereby reducing the circuit size of the encoding device, and An encoding device is implemented that has at least dual mode (eg, a data transfer interface for a delayed phase locked loop type and a phase locked loop type). It is to be noted that the encoding devices 1100, 1101, and 1102 perform encoding operations by inserting only one bit into an uncoded material, and thus the sacrificed bandwidth is much reduced compared to conventional encoding devices, especially when operating frequencies. At higher times, the reduced energy loss will be more significant.

Please refer to FIG. 12, which is a generalized flowchart of an embodiment of the decoding method of the present invention. In step 1210, a specific bit set in a first bit stream (eg, an encoded data) is first detected to generate a first detection result, wherein the specific bit set includes at least one bit. And then, in step 1220, converting the first bit stream to a second bit stream according to the first detection result, wherein the number of bits of the first bit stream and the second bit The number of bits in the stream differs by one. In an embodiment, when the specific bit set is a recognized bit, step 1220 may include directly outputting all remaining bits in the first bit stream except the recognized bit as the The second bit stream. For example, when a first bit stream BS1 (eg, an encoded data) is received from a transmission interface that does not require consideration of the number of consecutive bits having the same logical value in the transmitted data (eg, delay) In the case of a phase-locked loop type transmission interface, the first bit stream BS1 has a bit pattern "001000101" and its specific bit set SB is the least significant bit "1" (also an identification bit IB). a receiving end performs decoding according to the detection result DR performed for the first bit stream BS1, that is, the receiving end directly outputs all of the first bit stream BS1 except the identification bit IB. The remaining bit "00100010" is used as the second bit stream BS2.

As described above, when an uncoded material is transferred to a transmission interface (for example, a phase-locked loop type transmission interface) that requires consideration of the number of consecutive bits of the same logical value in the transmitted data, since the uncoded The data may be subject to an improved signal quality adjustment, and therefore, will be received from a transmission interface that has a number of consecutive bits of the same logical value in the data to be transmitted (eg, a phase-locked loop type transmission interface). When an encoded data is decoded, it may be necessary to make judgments and conversions for the adjustment of the quality of the signal. Referring to FIG. 13, FIG. 13 is a flowchart of an embodiment of a decoding method of the present invention, wherein the flow shown in FIG. 13 is based on the flow shown in FIG. In FIG. 13 , the step 1220 shown in FIG. 12 may include: outputting the first bit when the first detection result indicates that the plurality of bits included in the specific bit set have a first coding pattern. All remaining bits in the meta stream except a recognized bit are used as the second bit stream (ie, steps 1322 and 1324); and when the first detection result shows the particular bit set When the plurality of bits included have a second encoding pattern different from the first encoding pattern, converting the first bit stream into a third bit stream, and outputting the third bit stream except one All remaining bits except the bit are identified as the second bit stream (i.e., steps 1322 and 1326).

In an embodiment, step 1326 may include converting the first bit stream according to a conversion operation to generate a plurality of conversion results, and selecting one of the plurality of conversion results according to a determination criterion as the one. The third bit stream. The above criterion may include that the same logical value appears consecutively the most, and/or a first logical value and a second logical value are converted the least. Please refer to FIG. 14, which is an example flow diagram of an implementation of step 1326 shown in FIG. In step 1426, the first bit stream is converted according to a conversion operation to generate a plurality of conversion results, wherein the plurality of conversion results include a first conversion result and a second conversion result, and in step 1427, A criterion is used to select one of the plurality of conversion results as the third bit stream. Step 1426 can include a step 1428 and a step 1429. In step 1428, inverting a first bit set of the first bit stream that includes a specific bit to generate the first conversion result, wherein the specific bit It is one of a contiguous number of bits having the same logical value. In step 1429, a second set of bits in the first bitstream containing the particular bit is inverted to generate the second conversion result. Step 1428 and step 1429 are both for restoring at least one bit of the first bit stream that was inverted during the encoding process.

It can be seen from the foregoing embodiments that when encoding an uncoded data, when the signal quality of the uncoded data is not good, at least one bit needs to be inverted to improve the same logical value continuously appearing in the In the case where the number of times of encoding the data is excessive, and the inversion is performed again to avoid the occurrence of repetition in the plurality of encoded data; furthermore, it can be seen from the plurality of embodiments disclosed above that the performance of the enhanced signal can be utilized. Converting processing to distinguish the original signal quality of the plurality of encoded data (that is, the signal quality before encoding), therefore, in this embodiment, the bit that may be inverted during the encoding process needs to be inverted (including the Specific bits) to correctly obtain the uncoded material with poor signal quality. It is to be noted that since the decoding method is adjusted according to the encoding method, the above description is for illustrative purposes only and is not intended to be a limitation of the present invention. For example, the resulting multiple conversion results are not limited to two.

Please refer to FIG. 15 together with FIG. 7, wherein FIG. 15 is a flowchart of an embodiment of a transmission interface applied to a phase-locked loop type of the decoding method of the present invention, and the decoding process shown in FIG. 15 corresponds to The encoding process shown in Figure 7. In this embodiment (but the invention is not limited thereto), the first bit stream BS1 is "001100011" (that is, the bit stream of the completed encoding shown in FIG. 7), and the specific bit thereof The set SB is the first two bits "11" counted by the least significant bit. As can be seen from the description of FIG. 7, if the coding pattern of the specific bit set SB is "01" or "10", the original data of the first bit stream BS1 (that is, the bit stream before the unencoding) has Good signal quality; conversely, if the coding pattern of the specific bit set SB is "00" or "11", the signal quality of the original data of the first bit stream BS1 is poor. Therefore, the first bit stream BS1 needs to be converted according to a conversion operation to restore a plurality of possible patterns of the first bit stream BS1 before encoding (that is, generating a plurality of conversion results), and then selecting a bit with poor signal quality. The stream is used as a third bit stream BS3. Since the encoding process shown in FIG. 7 uses a logical mutual exclusion operation, the first bit stream BS1 "001100011" is first converted into a first conversion result "000000010" (that is, the inversion is performed by the most significant bit). The fourth and third bits counted, and the least significant bit), and then the first bit stream BS1 "001100011" is converted into a second conversion result "001000001" (ie, inverted by The fourth most significant bit, and the second bit from the least significant bit). Since the same logical value occurs most frequently in the first conversion result "000000010", the first conversion result is selected as the third bit stream BS3. Next, all the remaining bits except the one identifying bit (ie, the least significant bit "0") in the third bit stream BS3 are output as a second bit stream BS2 (ie, Step 1326) shown in Fig. 13, in other words, the obtained uncoded material is "00000001".

Referring to FIG. 16, FIG. 16 is a flowchart of an embodiment of a decoding method of the present invention, wherein the steps shown in FIG. 16 are based on the flow shown in FIG. In FIG. 16, the step 1220 shown in FIG. 12 may include: detecting the first when the first detection result indicates that the plurality of bits included in the specific bit set have a first coding pattern. An identification bit of the bitstream generates a second detection result, and converts the first bitstream into the second bitstream according to the second detection result (as in steps 1621, 1622, and 1623) And when the first detection result indicates that the plurality of bits included in the specific bit set have a second coding pattern different from the first coding pattern, converting the first bit stream to A third bit stream is generated according to the third bit stream (as shown in steps 1621, 1624, and 1625). In an embodiment, step 1624 can include converting the first bit stream according to a conversion operation to generate a plurality of conversion results, and selecting one of the plurality of conversion results according to a criterion to serve as the The third bit stream. The above criterion may include that the same logical value appears consecutively the most, and/or a first logical value and a second logical value are converted the least.

In addition, step 1625 can include identifying a bit in accordance with one of the first bitstreams to convert the set of bits in the third bitstream corresponding to the particular set of bits into the second encoding pattern, and All remaining bits except the one identifying bit in the third bit stream are output as the second bit stream. In a design change, step 1625 may include identifying a bit according to one of the first bit streams, and directly outputting all remaining bits except the one identifying bit in the third bit stream as the first Two bit stream. In addition, since the step 1623 is to detect the second detection result obtained by identifying the bit in the first bit stream, the first bit stream is converted into the second bit stream, and therefore, In a design change, step 1625 can be implemented using steps 1623 and 1624.

Please refer to FIG. 17, which is an exemplary flow chart of an implementation of steps 1624 and 1625 shown in FIG. In step 1724, the first bit stream is converted according to a conversion operation to generate a plurality of conversion results, wherein the plurality of conversion results include a first conversion result and a second conversion result, and in step 1725, A criterion is used to select one of the plurality of conversion results as the third bit stream. Step 1724 can include a step 1726 and a step 1727. In step 1726, inverting a first bit set of the first bit stream that includes a specific bit to generate the first conversion result, where the specific bit is generated. It is one of a contiguous number of bits having the same logical value. In step 1727, a second set of bits of the first bit stream containing the particular bit is inverted to generate the second conversion result. Step 1726 and step 1727 are both used to restore at least one bit of the first bit stream that was inverted during the encoding process. In addition, in step 1723, one of the first bitstreams is detected to identify the bit to generate a second detection result. Then, according to the second detection result, the set of bits in the third bit stream corresponding to the specific bit set is converted into the second coding type, and the third bit stream is output. A remaining bit other than the identified bit is used as the second bit stream (as shown in steps 1724 and 1728). In another embodiment, according to the second detection result, all remaining bits except the one of the identification bits in the third bit stream are directly output as the second bit stream (step 1724). And 1729)).

Please refer to FIG. 18 together with FIG. 9, wherein FIG. 18 is a flowchart of another embodiment of the transmission interface applied to the phase-locked loop type of the decoding method of the present invention, and the decoding process shown in FIG. The encoding process shown in Figure 9. In this embodiment (but the present invention is not limited thereto), a first bit stream BS1 is "000010001" (that is, the bit stream of the completed encoding shown in FIG. 9), and its specific bit The metaset SB is the first two bits counted by the most significant bit and has an encoding pattern "00". As can be seen from the description of FIG. 9, if the coding pattern of the specific bit set SB is "01" or "10", the original data of the first bit stream BS1 (that is, the bit stream before unencoding) has Good signal quality; conversely, if the coding pattern of the specific bit set SB is "00" or "11", the signal quality of the original data of the first bit stream BS1 is poor. Therefore, the first bit stream BS1 needs to be converted according to a conversion operation to restore a plurality of possible patterns of the first bit stream BS1 before encoding (that is, generating a plurality of conversion results), and then selecting a bit with poor signal quality. The meta stream is converted into a third bit stream BS3. According to the encoding process shown in FIG. 9, first converting the first bit stream BS1 "000010001" into a first conversion result "010000001" (that is, inverting the fifth bit from the most significant bit) And converting the first two bits from "00" to "01"), and converting the first bit stream BS1 "000010001" into a second conversion result "100000101" (ie, the inversion is highest) The fifth bit from the valid bit, converts the first two bits from "00" to "10", and inverts the third bit from the least significant bit). Since the same logical value appears the most frequently in the first conversion result "010000001", the first conversion result is selected as the third bit stream BS3.

Since the type of the third bit stream BS3 is "010000001", and one of the first bit stream BS1 recognizes that the bit system is "1", the two bits before the third bit stream BS3 are converted into " 00", and outputting all remaining bits of the bit "1" except one of the third bit stream BS3 as a second bit stream BS2, in other words, the decoded data outputted is "00000000".

Please refer to FIG. 19, which is a generalized flowchart of another embodiment of the encoding method of the present invention. In step 1910, a specific bit set in a first bit stream is detected to generate a first detection result, wherein the specific bit set is a recognition bit. In step 1920, the type of the interface to be transmitted by the first bit stream is checked, if it is not necessary to consider the transmission interface of the number of consecutive bits having the same logical value in the transmitted data (for example, a delay phase locked loop) a type of transmission interface), or a transmission interface (for example, a phase-locked loop type transmission interface) having a number of consecutive bits of the same logical value in the transmitted data, but the first detection result indication If the identification bit of the first bit stream has a first coding pattern (for example, an encoding pattern representing a good signal quality), step 1930 is performed; otherwise, step 1940 is performed. In step 2030, all remaining bits in the first bit stream except the identification bit are directly output as the second bit stream. In step 1940, the first bit stream is converted in accordance with a conversion operation to produce a plurality of conversion results. In step 1950, one of the plurality of conversion results is selected according to a criterion to be the third bit stream. In step 1960, all remaining bits of the third bit stream except one recognition bit are directly output as the second bit stream. In short, the decoding method of the present invention can implement a dual mode encoding mode, that is, the decoding method proposed by the present invention can be dynamically switched by different data transmission interfaces. In a design change, the user can manually switch the decoding mode of the data transmission according to the type of the data transmission interface. Therefore, step 1920 can be omitted.

Please refer to FIG. 20, which is a functional block diagram of an embodiment of a decoding apparatus of the present invention. The encoding device 2000 includes (but is not limited to) a detecting unit 2010 and a processing unit 2020. The detecting unit 2010 is configured to detect a specific bit set SB in a first bit stream BS1 to generate a first detecting result DR, wherein the specific bit set SB includes at least one bit. The processing unit 2020 is coupled to the detecting unit 2010 for converting the first bit stream BS1 into a second bit stream BS2 according to the first detection result DR, wherein the number of bits of the first bit stream BS1 It differs from the number of bits of the second bit stream BS2 by one. In an embodiment, when the first detection result DR1 shows that the plurality of bits included in the specific bit set SB have a first coding pattern, the processing unit 2020 outputs a recognition bit in the first bit stream BS1. All remaining bits except IB1 are used as the second bit stream BS2, and when the first detection result DR1 shows that the plurality of bits included in the specific bit set SB are different from the first coding type In a second coding mode, the processing unit 2020 converts the first bit stream BS1 into a third bit stream BS3, and outputs all remaining bits in the third bit stream BS3 except one identification bit IB3. As the second bit stream BS2. In another embodiment, when the first detection result DR1 indicates that the plurality of bits included in the specific bit set SB have a first coding pattern, the 2020 processing unit detects a recognition bit of the first bit stream BS1. The element IB1 generates a second detection result DR2, and converts the first bit stream BS1 into the second bit stream BS2 according to the second detection result DR2, and when the first detection result DR1 displays the specific bit set When the plurality of bits included in the SB have a second coding pattern different from the first coding pattern, the processing unit 2020 converts the first bit stream BS1 into a third bit stream BS3, and according to the BS3 third. The bit stream is generated to generate a second bit stream BS2. Since the skilled artisan can easily understand the related operations of the encoding device 2000 by reading the related descriptions of Figs. 12 to 19, further description will not be repeated here.

Referring to FIG. 21, FIG. 21 is a functional block diagram of an embodiment of a data transfer apparatus 2100 implemented in accordance with the encoding apparatus of the present invention, wherein the data transfer apparatus 2100 includes (but the invention is not limited thereto) A phase-locked loop unit 2110, a parallel-to-serial conversion unit 2120, an encoding unit 2130, and a driving unit 2140. The phase-locked loop unit 2110 is configured to generate a first control signal C1 and a second control signal C2 according to a clock signal CS. The parallel-to-serial conversion unit 2120 is configured to convert a parallel data PD into a serial data SD according to the first control signal C1. The encoding unit 2130 is configured to insert a bit into the serial data SD according to the second control signal C2, and form an encoded data CD, wherein the number of bits of the serial data SD and the bit of the encoded data CD The difference between the numbers is 1. The driving unit 2140 outputs the encoded material CD as an encoded signal ECS. In this embodiment, the encoding unit 2130 can be implemented by the encoding device 1102 shown in FIG. 11C. Therefore, the encoding unit 2130 has low energy loss, small circuit size, good encoding quality, at least dual encoding mode switching, and The data transfer device 2100 can be applied to the transmission interface of high-speed and high-volume data transmission devices (for example, high-resolution displays) because of the advantages of less sacrifice of bandwidth. Moreover, in practical applications, the encoding unit 2130 can selectively encode the serial data PD in a delayed phase locked loop encoding mode or a phase locked loop encoding mode. In another embodiment, the encoding unit 2130 can also be implemented by the encoding device 1102 shown in the drawing device 1100 or 11B shown in FIG. 11A. Since the skilled artisan should readily understand the conventional data transfer device (e.g., other circuit components that do not include the encoding unit 2130) and the associated operations of the encoding unit 2130 disclosed herein, further description will not be repeated herein.

Referring to FIG. 22, FIG. 22 is a functional block diagram of an embodiment of a data receiving apparatus 2200 implemented in accordance with the encoding apparatus of the present invention, wherein the data receiving apparatus 2200 includes (but the invention is not limited thereto) A comparison unit 2210, a clock recovery unit 2220, a decoding unit 2230, and a serial-to-parallel conversion unit 2240. The comparing unit 2210 is configured to generate an input material ID according to an encoded signal ECS. The clock recovery unit 2220 is configured to generate a first control signal C1, a second control signal C2, and a clock signal CS according to the input data ID. The decoding unit 2230 is configured to convert the input data ID into a decoded data CD according to the first control signal C1, wherein the number of bits of the input material ID is different from the number of bits of the decoded data CD by one. The serial-to-parallel conversion unit 2240 is configured to convert the decoded data CD into a parallel data PD according to the first control signal C1. In addition, in this embodiment, the decoding unit 2230 can be implemented by the decoding device 2000 shown in FIG. 20, and therefore, the encoding unit 2230 has low energy loss, small circuit size, good decoding quality, and at least double decoding mode switching. As well as the advantages of less bandwidth, the data receiving device 2200 can be applied to the transmission interface of high-speed and high-volume transmission devices (for example, high-resolution displays). Moreover, in practical applications, the decoding unit 2230 can selectively decode the parallel data SD in a delay locked loop decoding mode or a phase locked loop decoding mode. Since the skilled artisan should be able to readily understand the conventional data receiving device (e.g., other circuit components that do not include decoding unit 2230) and the associated operations of encoding unit 2230 disclosed herein, further description is not repeated herein.

Briefly, the present invention proposes an innovative coding method that encodes data by inserting only one identification bit to reduce the bandwidth and energy loss at the time of data transmission, and to utilize simple logic circuits. Different coding modes can be shared, thereby reducing the size of the transceiver circuit and increasing the coding flexibility. In addition, based on this innovative coding method, the present invention also provides a corresponding decoding method and associated encoding/decoding apparatus, data transmission apparatus and data receiving apparatus for application to today's high speed and large amount of data transmission and reception.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

1100, 1101, 1102. . . Coding device

1110, 2010. . . Detection unit

1111, 1112, 1121, 1120, 1132, 2020. . . Processing unit

1122. . . Switching unit

2000. . . Decoding device

2100. . . Data transfer device

2110. . . Phase-locked loop unit

2120. . . Parallel to serial conversion unit

2130. . . Coding unit

2140. . . Drive unit

2200. . . Data receiving device

2210. . . Comparison unit

2220. . . Clock recovery unit

2230. . . Decoding unit

2240. . . Tandem to parallel conversion unit

1 is a generalized flow chart of an embodiment of an encoding method of the present invention.

2 is a flow chart of an embodiment of an encoding method of the present invention.

Figure 3A is a schematic diagram of inserting a recognition bit into a first bit stream with a number of bits N.

Figure 3B is a schematic diagram of inserting a recognition bit into a first bit stream with a number of bits N.

Figure 4 is a flow chart of another embodiment of the encoding method of the present invention.

Figure 5 is a flow chart of another embodiment of the encoding method of the present invention.

Figure 6 is a flow chart showing an example of an implementation of the steps shown in Figure 5.

Figure 7 is a flow diagram of one embodiment of a transmission interface of the inventive encoding method applied to a phase locked loop type.

Figure 8A is an example flow diagram of another implementation of the steps shown in Figure 5.

Figure 8B is a flow chart showing an example of another implementation of the steps shown in Figure 5.

Figure 9 is a flow diagram of another embodiment of the transmission interface of the inventive encoding method applied to a phase locked loop type.

Figure 10 is a generalized flow chart of another embodiment of the encoding method of the present invention.

Figure 11A is a functional block diagram of an embodiment of an encoding apparatus of the present invention.

Figure 11B is a functional block diagram of another embodiment of the encoding apparatus of the present invention.

Figure 11C is a functional block diagram of still another embodiment of the encoding apparatus of the present invention.

Figure 12 is a generalized flow chart of an embodiment of a decoding method of the present invention.

Figure 13 is a flow chart of an embodiment of a decoding method of the present invention.

Figure 14 is a flow chart showing an example of an implementation of the steps shown in Figure 13.

Figure 15 is a flow chart showing an embodiment of a transmission interface of the decoding method applied to a phase-locked loop type of the present invention.

Figure 16 is a flow chart of an embodiment of a decoding method of the present invention.

Figure 17 is a flow chart showing an example of an implementation of the steps shown in Figure 16.

Figure 18 is a flow diagram of another embodiment of a transmission interface of the present invention for a decoding method applied to a phase locked loop type.

Figure 19 is a generalized flow chart of another embodiment of the encoding method of the present invention.

Figure 20 is a functional block diagram of an embodiment of a decoding apparatus of the present invention.

Figure 21 is a functional block diagram of an embodiment of a data transfer apparatus implemented in accordance with the encoding apparatus of the present invention.

Figure 22 is a functional block diagram of an embodiment of a data receiving apparatus implemented in accordance with the encoding apparatus of the present invention.

1010, 1020, 1030, 1040, 1050, 1060. . . step

Claims (40)

An encoding method includes: detecting a first bit stream to obtain a first detection result; and inserting a recognition bit into the first bit stream according to the first detection result, and forming according to the first detection result a second bit stream, wherein the number of bits of the first bit stream differs from the number of bits of the second bit stream by one. The encoding method of claim 1, wherein detecting the first bit stream to obtain the first detection result comprises: detecting a specific bit in the first bit stream at a specific bit position A type of the metaset is used as the first detection result, wherein the specific set of bits includes at least one bit located in the first bitstream. The encoding method of claim 2, wherein the identifying bit is inserted between one of the adjacent bits immediately adjacent to the particular set of bits and the particular set of bits. The encoding method of claim 2, wherein the step of inserting the identification bit into the first bit stream according to the first detection result comprises: when the specific bit set is a first type, the identification bit having a first logic value being inserted into the first bit stream; and when the pattern of the particular bit set is different from the second pattern of the first type The identification bit having a second logic value is inserted into the first bit stream. The encoding method of claim 4, wherein the step of inserting the identification bit into the first bit stream according to the first detection result further comprises: when the type of the specific bit set is For the first version, the particular set of bits is converted to the second version. An encoding method includes: detecting a least significant bit of a first bit stream to obtain a first detection result; and inserting a recognition bit into the first bit stream according to the first detection result After the least significant bit, a second bit stream is formed accordingly. An encoding method includes: detecting a most significant bit of a first bit stream to obtain a first detection result; and inserting a recognition bit into the first bit stream according to the first detection result Before the most significant bit, a second bit stream is formed accordingly. An encoding method includes: inserting at least one identification bit into a first bit stream, and forming a second bit stream; determining a signal quality of the second bit stream; when the signal quality satisfies a When the criterion is judged, the second bit stream is output; and when the signal quality does not satisfy the judgment criterion, the second bit stream is adjusted to generate and output a third bit stream. The encoding method of claim 8, wherein the judging criterion is that the number of consecutive occurrences of the same logical value in the second bit stream does not exceed a predetermined number of consecutive times. The encoding method of claim 8, wherein the determining criterion is that a first logical value and a second logical value are converted in the second bit stream by a predetermined number of conversions. The encoding method of claim 8, wherein the step of adjusting the second bit stream to generate and output the third bit stream comprises: logic for a plurality of bits in the second bit stream An operation to generate the third bit stream. The encoding method of claim 8, wherein the step of adjusting the second bit stream to generate and output the third bit stream comprises: inverting at least a first bit in the second bit stream And satisfying the criterion; detecting a plurality of bits in the second bit stream to generate a second detection result; and inverting at least one of the second bit stream according to the second detection result The second bit is to generate the third bit stream. The encoding method of claim 12, wherein the detecting the plurality of bits in the second bit stream to generate the second detection result comprises: performing a logic on the plurality of bits A mutually exclusive operation produces the second detection result. The encoding method of claim 8, wherein the step of adjusting the second bit stream to generate and output the third bit stream comprises: inverting at least a first bit in the second bit stream The element satisfies the criterion; at least the last at least one element of the previous one of the second bit streams is detected to generate a second detection result; and the second detection result is reversed Transducing at least one second bit of the second bit stream to generate the third bit stream. The encoding method of claim 14, wherein the step of generating the second detection result comprises: detecting a last one of the last one of the previous meta streams and the second bit stream The first plurality of bits are initially generated to generate the second detection result. A decoding method includes: detecting a specific bit set in a first bit stream to generate a first detection result, wherein the specific bit set includes at least one bit; and according to the first detection As a result, the first bit stream is converted to a second bit stream, wherein the number of bits of the first bit stream differs from the number of bits of the second bit stream by one. The decoding method of claim 16, wherein the specific bit set is a recognition bit, and the first bit stream is converted into the second bit stream according to the first detection result. The step includes: directly outputting all remaining bits in the first bit stream except the identification bit as the second bit stream. The decoding method of claim 16, wherein the converting the first bit stream to the second bit stream according to the first detection result comprises: when the first detection result shows the When a plurality of bits included in a specific bit set have a first coding pattern, all remaining bits except the one recognized bit in the first bit stream are output as the second bit stream; And converting the first bit stream to a third when the first detection result indicates that the plurality of bits included in the specific bit set have a second coding pattern different from the first coding pattern. The bit stream is output, and all remaining bits except the one identifying bit in the third bit stream are output as the second bit stream. The decoding method of claim 18, wherein the converting the first bit stream to the third bit stream comprises: converting the first bit stream according to a conversion operation to generate a plurality of conversions a result; and selecting one of the plurality of conversion results according to a criterion to be the third bit stream. The decoding method of claim 19, wherein the criterion is that the same logical value appears consecutively the most. The decoding method of claim 19, wherein the determining criterion is that the number of conversions of a first logical value and a second logical value is the least. The decoding method of claim 19, wherein the plurality of conversion results include a first conversion result and a second conversion result, and converting the first bit stream according to the conversion operation to generate the plurality of The step of converting the result includes: inverting a first bit set of the first bit stream including a specific bit to generate the first conversion result, wherein the specific bit is a continuous complex number having the same logical value One of the bits; and inverting a second set of bits of the first bitstream containing the particular bit to produce the second conversion result. The decoding method of claim 16, wherein the converting the first bit stream to the second bit stream according to the first detection result comprises: when the first detection result shows the Detecting a certain bit of the first bit stream to generate a second detection result, and Converting the first bit stream to the second bit stream; and when the first detection result indicates that the plurality of bits included in the specific bit set have a second difference from the first coding pattern When encoding the pattern, the first bit stream is converted into a third bit stream, and the second bit stream is generated according to the third bit stream. The decoding method of claim 23, wherein converting the first bit stream to the third bit stream comprises: converting the first bit stream according to a conversion operation to generate a plurality of conversions a result; and selecting one of the plurality of conversion results according to a criterion to be the third bit stream. The decoding method of claim 24, wherein the criterion is that the same logical value appears consecutively the most. The decoding method of claim 24, wherein the determining criterion is that the number of conversions of a first logical value and a second logical value is the least. The decoding method of claim 24, wherein the plurality of conversion results include a first conversion result and a second conversion result, and converting the first bit stream according to the conversion operation to generate the plurality of The step of converting the result includes: inverting a first bit set of the first bit stream including a specific bit to generate the first conversion result, wherein the specific bit is a continuous complex number having the same logical value One of the bits; and inverting a second set of bits of the first bitstream containing the particular bit to produce the second conversion result. The decoding method of claim 23, wherein the generating the second bit stream according to the third bit stream comprises: identifying a bit according to one of the first bit streams, to Converting a bit set corresponding to the specific bit set into the second coding pattern, and outputting all remaining bits except the one identifying bit in the third bit stream as The second bit stream. The decoding method of claim 23, wherein the generating the second bit stream according to the third bit stream comprises: identifying the bit according to one of the first bit streams, directly outputting the first The remaining bits in the three-bit stream except one identifying the bit are used as the second bit stream. An encoding device includes: a detecting unit for detecting a first bit stream to obtain a first detecting result; and a processing unit coupled to the detecting unit for using the first detecting The measurement result inserts a recognition bit into the first bit stream, and accordingly forms a second bit stream, wherein the number of bits of the first bit stream and the number of bits of the second bit stream The difference is 1. An encoding device includes: a detecting unit for detecting a least significant bit of a first bit stream to obtain a first detecting result; and a processing unit coupled to the detecting unit for Inserting a recognition bit into the least significant bit of the first bit stream according to the first detection result, and forming a second bit stream accordingly. An encoding device includes: a detecting unit for detecting a most significant bit of a first bit stream to obtain a first detecting result; and a processing unit coupled to the detecting unit for And inserting a recognition bit before the most significant bit of the first bit stream according to the first detection result, and forming a second bit stream accordingly. An encoding device includes: a first processing unit, configured to insert at least one identification bit into a first bit stream, and thereby form a second bit stream; and a second processing unit coupled to The first processing unit is configured to determine a signal quality of the second bit stream; wherein when the signal quality satisfies a criterion, the second bit stream is output, and when the signal quality does not satisfy the criterion The second bit stream is adjusted to generate and output a third bit stream. A decoding device includes: a detecting unit, configured to detect a specific bit set in a first bit stream to generate a first detecting result, wherein the specific bit set includes at least one bit; And a processing unit coupled to the detecting unit, configured to convert the first bit stream into a second bit stream according to the first detection result, where the number of bits of the first bit stream The number of bits of the second bit stream differs by one. The decoding device of claim 34, wherein the processing unit outputs the first bit when the first detection result indicates that the plurality of bits included in the specific bit set have a first coding pattern All remaining bits in the meta stream except for a recognized bit are used as the second bit stream, and when the first detection result shows that the plurality of bits included in the specific bit set are different In the second coding mode of the first coding type, the processing unit converts the first bit stream into a third bit stream, and outputs the third bit stream except for one identification bit. All remaining bits are used as the second bit stream. The decoding device of claim 34, wherein the processing unit detects the first when the first detection result indicates that the plurality of bits included in the specific bit set have a first coding pattern And identifying a bit of the bit stream to generate a second detection result, and converting the first bit stream to the second bit stream according to the second detection result, and when the first detection result When the plurality of bits included in the specific bit set are different from the second coding pattern of the first coding pattern, the processing unit converts the first bit stream into a third bit stream, and The second bit stream is generated according to the third bit stream. A data transmission device includes: a phase locked loop unit for generating a first control signal and a second control signal according to a clock signal; and a parallel to the serial conversion unit for using the first control signal according to the first control signal Converting a side-by-side data into a series of data; a coding unit for inserting a bit into the serial data according to the second control signal, and thereby forming an encoded data, wherein the serial data The number of bits differs from the number of bits of the encoded data by one; and a driving unit for outputting the encoded data as an encoded signal. The data transfer device of claim 37, wherein the coding unit selectively encodes the serial data in a delayed phase locked loop coding mode or a phase locked loop coding mode. A data receiving device includes: a comparing unit configured to generate an input data according to an encoded data; a clock recovery unit configured to generate a first control signal, a second control signal according to the input data, and a decoding unit, configured to convert the input data into a decoded data according to the first control signal, wherein a number of bits of the input data is different from a number of bits of the decoded data; The serial to parallel conversion unit is configured to convert the decoded data into a parallel data according to the first control signal. The data receiving device of claim 39, wherein the decoding unit selectively decodes the input data in a delay locked loop decoding mode or a phase locked loop decoding mode.