CN109309548B

CN109309548B - Encoding method, apparatus and readable storage medium

Info

Publication number: CN109309548B
Application number: CN201810450407.2A
Authority: CN
Inventors: 张玮; 黄卫东; 秦达; 王拂依; 徐枫程
Original assignee: Shenzhen China Star Optoelectronics Technology Co Ltd
Current assignee: TCL Huaxing Photoelectric Technology Co Ltd
Priority date: 2018-05-11
Filing date: 2018-05-11
Publication date: 2020-01-03
Anticipated expiration: 2038-05-11
Also published as: CN109309548A; WO2019214138A1

Abstract

The invention discloses a coding method, which comprises the following steps: acquiring a first bit stream, wherein the first bit stream is an 8-bit stream; performing quality judgment on the first bit stream; wherein the first bit stream is determined to meet the quality criterion if the first bit stream simultaneously meets the following conditions: at least two bits of the 4 th bit to the 7 th bit in the first bit stream have different logic values; at least two bits of the 1 st bit to the 6 th bit in the first bit stream have different logic values; at least two bits of the 0 th bit to the 5 th bit in the first bit stream have different logic values; the logical values of the 6 th bit and the 7 th bit in the first bit stream are different, the logical values of the 0 th bit to the 4 th bit are different, or the logical values of the 6 th bit and the 7 th bit are the same, and the logical values of the 0 th bit to the 4 th bit are the same and are the same as the logical values of the 6 th bit and the 7 th bit. The invention also discloses a coding device and a readable storage medium. By the method, the coding quality of the third bit stream can be guaranteed.

Description

Encoding method, apparatus and readable storage medium

Technical Field

The present invention relates to the field of data transmission, and in particular, to an encoding method, an encoding apparatus, and a readable storage medium.

Background

In serial data transmission, transmitted data can be encoded into a code stream containing a clock frequency component, so that a receiving end can extract clock synchronization information from the code stream, and the clock synchronization information can ensure that the receiving end can regenerate original data from received signals according to correct time sequence.

4B5B is a common code, and converts input 4-bit data into 5 bits and outputs the 5 bits. Generally, the encoding and decoding operations are completed by searching a designed code table, so that additional memories are required for storing the code table at both the transmitting end and the receiving end. 4B5B encoding may also degrade the encoding quality, i.e., the number of consecutive bits with the same logical value is excessive, for example, when 8 bits of data are transmitted using 4B5B encoding. The low-quality codes are not beneficial to a receiving end to extract clock synchronization information, larger direct current components are brought, and the error rate is improved.

Disclosure of Invention

The invention mainly solves the technical problem of providing an encoding method, an encoding device and a readable storage medium, which can solve the problem that encoding quality is possibly reduced in the prior art.

In order to solve the above technical problem, the present invention provides an encoding method, including: acquiring a first bit stream, wherein the first bit stream is an 8-bit stream; performing quality judgment on the first bit stream; wherein the first bit stream is determined to meet the quality criterion if the first bit stream simultaneously meets the following conditions: at least two bits of the 4 th bit to the 7 th bit in the first bit stream have different logic values; at least two bits of the 1 st bit to the 6 th bit in the first bit stream have different logic values; at least two bits of the 0 th bit to the 5 th bit in the first bit stream have different logic values; and at least one of the following sub-conditions is satisfied: the logical values of the 6 th bit and the 7 th bit in the first bitstream are different, the logical values of the 0 th bit to the 4 th bit in the first bitstream are different, or the logical values of the 6 th bit and the 7 th bit in the first bitstream are the same, the logical values of the 0 th bit to the 4 th bit are the same, and the logical values of the 6 th bit and the 7 th bit are the same.

In order to solve the above technical problem, the present invention provides an encoding device, which includes a processor for executing instructions to implement the foregoing method.

In order to solve the above technical problem, the present invention provides a readable storage medium storing instructions which, when executed, implement the foregoing method.

The invention has the beneficial effects that: in the encoding process, whether the first bit stream meets a preset quality standard or not is judged, the first bit stream which does not meet the quality standard is converted, a second bit stream is output, the output first bit stream or the output second bit stream is combined with an identification bit to form a third bit stream, the encoding quality of the second bit stream compared with the first bit stream after conversion is improved, and the encoding quality of the third bit stream is guaranteed.

Drawings

FIG. 1 is a flow chart of an embodiment of the encoding method of the present invention;

FIG. 2 is a flowchart illustrating the step S3 in FIG. 1 according to an embodiment of the encoding method of the present invention;

FIG. 3 is a flowchart illustrating the step S3 in FIG. 1 according to another embodiment of the encoding method of the present invention;

FIG. 4 is a flowchart illustrating the step S4 in FIG. 1 according to another embodiment of the encoding method of the present invention;

FIG. 5 is a flow chart illustrating an encoding method according to another embodiment of the present invention;

FIG. 6 is a flow chart illustrating an encoding method according to another embodiment of the present invention;

FIG. 7 is a flowchart illustrating an encoding method according to another embodiment of the present invention;

FIG. 8 is a flowchart illustrating an encoding method according to another embodiment of the present invention;

FIG. 9 is a schematic structural diagram of an embodiment of the encoding apparatus of the present invention;

FIG. 10 is a schematic structural diagram of an embodiment of a readable storage medium of the present invention.

Detailed Description

The present invention will be described in detail below with reference to the accompanying drawings and examples. Non-conflicting ones of the following embodiments may be combined with each other.

As shown in fig. 1, an embodiment of the encoding method of the present invention includes:

s1: and carrying out quality judgment on the first bit stream.

The first bit stream may be uncoded data, and the number of bits may be determined according to actual transmission requirements, for example, 8 bits, 16 bits, and the like. The quality determination may be to determine whether the quality of the first bitstream meets a preset quality criterion. The quality criterion may relate to consecutive bits of the first bit stream having the same logical value. Generally, the number of consecutive bits of the first bit stream that satisfy the quality criterion, having the same logical value, does not exceed a threshold value, which may be related to the number of bits of the first bit stream, e.g. half the number of bits of the first bit stream plus a positive integer.

In an embodiment of the present invention, when the first bit stream is an 8-bit stream, if the first bit stream satisfies at least one of the following conditions a, b, c, and d, it is determined that the first bit stream does not satisfy the quality criterion:

a. the logic values of the 4 th bit to the 7 th bit in the first bit stream are the same;

b. the logical values of the 1 st bit to the 6 th bit in the first bit stream are the same;

c. the logical values of the 0 th bit to the 5 th bit in the first bit stream are the same;

d. the 6 th and 7 th bits in the first bitstream have the same logic value, and the 0 th to 4 th bits have the same logic value and are opposite to the logic values of the 6 th and 7 th bits.

Optionally, the above determination manner may be converted into a determination of a calculation result of the following logical expression:

NAND(NAND(bm[4～7]),NAND(bm[1～6]),NAND(bm[0～5]),OR(NAND(bm[6～7]),OR(bm[0～4])),OR(OR(bm[6～7]),NAND(bm[0～4])),OR(bm[4～7]),OR(bm[1～6]),OR(bm[0～5])) (1)

where NAND is NAND operation, OR is OR operation, bm [ i-j ] is the ith to jth bits of the first bitstream, i and j are integers from 0 to 7 and i < j.

In the formula (1), when the 4 th bit to the 7 th bit of the first bit stream are all 1, NAND (bm [ 4-7 ]) is 0.

When the 1 st bit to the 6 th bit of the first bit stream are all 1, NAND (bm [ 1-6 ]) is 0.

When the 0 th bit to the 5 th bit of the first bit stream are all 1, NAND (bm [0 ~ 5]) is 0.

When the 6 th bit to the 7 th bit of the first bit stream are all 1 and the 0 th bit to the 4 th bit of the first bit stream are all 0, NAND (bm 6-7) is 0, OR (bm 0-4) is 0, OR (NAND (bm 6-7), OR (bm 0-4)) is 0.

When the 6 th bit to the 7 th bit of the first bit stream are all 0 and the 0 th bit to the 4 th bit of the first bit stream are all 1, OR (bm 6-7) is 0, NAND (bm 0-4) is 0, OR (OR (bm 6-7), NAND (bm 0-4)) is 0.

When the 4 th bit to the 7 th bit of the first bit stream are all 0, OR (bm 4-7) is 0.

When the 1 st bit to the 6 th bit of the first bit stream are all 0, OR (bm [ 1-6 ]) is 0.

When the 0 th bit to the 5 th bit of the first bit stream are all 0, OR (bm [ 0-5 ]) is 0.

If the calculation result of the formula (1) is 1, it means that at least one of NAND (bm 4-7), NAND (bm 1-6), NAND (bm 0-5), OR (NAND (bm 6-7), OR (bm 0-4), OR (OR (bm 6-7), NAND (bm 0-4), OR (bm 4-7), OR (bm 1-6), OR (bm 0-5) is 0, and the first bitstream satisfies at least one of the conditions a, b, c, and d in combination with the condition that each of the above logical expressions is 0, the first bitstream does not satisfy the quality standard. If the calculation result of equation (1) is 0, the first bit stream satisfies the quality criterion.

In another embodiment of the present invention, in the case that the first bit stream is an 8-bit stream, if the first bit stream simultaneously satisfies all of the following conditions e, f, g, and h, it is determined that the first bit stream satisfies the quality criterion:

e. at least two bits of the 4 th bit to the 7 th bit in the first bit stream have different logic values;

f. at least two bits of the 1 st bit to the 6 th bit in the first bit stream have different logic values;

g. at least two bits of the 0 th bit to the 5 th bit in the first bit stream have different logic values;

h. at least one of the following sub-conditions is satisfied:

h1. the 6 th bit and the 7 th bit in the first bitstream have different logical values.

h2. The logical values of the 0 th bit to the 4 th bit in the first bit stream are different.

h3. The 6 th and 7 th bits in the first bitstream have the same logic value, and the 0 th to 4 th bits have the same logic value as the 6 th and 7 th bits.

AND(XOR(bm[4～7]),XOR(bm[1～6]),XOR(bm[0～5]),OR(NAND(bm[6～7]),OR(bm[0～4])),OR(OR(bm[6～7]),NAND(bm[0～4]))) (2)

wherein, AND is AND operation, NAND is NAND operation, OR is OR operation, XOR is XOR operation; bm [ i-j ] is the ith to jth bit of the first bitstream, i and j are integers from 0 to 7 and i < j.

In equation (2), when the logical values of the 4 th bit to the 7 th bit of the first bitstream are different (i.e., the logical values of at least two bits thereof are different), XOR (bm 4 to 7) is 1.

When the logical values of the 1 st bit to the 6 th bit of the first bit stream are different, XOR (bm [1 ~ 6]) is 1.

When the logical values of the 0 th bit to the 5 th bit of the first bit stream are different, XOR (bm [0 ~ 5]) is 1.

bm 6-7 and bm 0-4 can be discussed in combination.

When the logical values of the 6 th bit and the 7 th bit of the first bit stream are different, NAND (bm 6 to 7) and OR (bm 6 to 7) are both 1, OR (NAND (bm 6 to 7), OR (bm 0 to 4)) and OR (OR (bm 6 to 7), NAND (bm 0 to 4)) are both 1 regardless of whether the logical values of the 0 th bit to the 4 th bit of the first bit stream are the same.

When the logical values of the 0 th bit to the 4 th bit of the first bit stream are different, NAND (bm [ 0-4 ]) and OR (bm [ 0-4 ]) are both 1, OR (NAND (bm [ 6-7 ]), OR (bm [ 0-4 ])) and OR (OR (bm [ 6-7 ])), NAND (bm [ 0-4 ])) are both 1 regardless of whether the logical values of the 6 th bit and the 7 th bit of the first bit stream are the same.

In the case where the logical values of the 6 th bit and the 7 th bit of the first bit stream are the same and the logical values of the 0 th bit to the 4 th bit of the first bit stream are the same: when the 6 th bit and the 7 th bit of the first bitstream are both 0, NAND (bm 6-7) is 1, OR (NAND (bm 6-7), OR (bm 0-4) is 1, and OR (bm 6-7) is 0, and OR (OR (bm 6-7) is 1, NAND (bm 0-4) should be 1, that is, the 0 th bit to the 4 th bit of the first bitstream are all 0; when the 6 th bit and the 7 th bit of the first bitstream are both 1, OR (bm 6-7) is 1, OR (OR (bm 6-7), NAND (bm 0-4) is 1, and NAND (bm 6-7) is 0, the OR (OR (bm 6-7), OR (bm 0-4) is 1, OR (bm 0-4) should be 1, that is, the 0 th bit to the 4 th bit of the first bitstream are all 1.

If the calculation result of the formula (2) is 1, it means that XOR (bm 4-7), XOR (bm 1-6), XOR (bm 0-5), OR (NAND (bm 6-7), OR (bm 0-4), OR (OR (bm 6-7), NAND (bm 0-4)) are all 1, and the first bit stream can be obtained by combining the description of the previous section and simultaneously satisfies all the conditions e, f, g and h, then the first bit stream satisfies the quality standard. If the calculation result of equation (2) is 0, the first bit stream does not satisfy the quality standard.

After the quality judgment, if the first bit stream meets the quality standard, the step goes to S2; if the first bitstream does not meet the quality criterion, it jumps to S3.

S2: outputting the first bit stream.

And under the condition that the first bit stream meets the preset quality standard, the coding quality of the first bit stream does not need to be improved, and the first bit stream can be directly output.

A jump is made to S4.

S3: the first bit stream is converted and a second bit stream is output.

The purpose of the conversion is to improve the coding quality of the first bit stream. In general, the second bitstream obtained after the conversion may satisfy a preset quality criterion. The second bit stream is output and then the process proceeds to S4.

As shown in fig. 2, in an embodiment of the present invention, the step may specifically include:

s31: a logical operation is performed on a first set of bits in a first bit stream.

The result of the logical operation may be a first result or a second result, the first result being different from the second result.

If the result of the logical operation is the first result, go to S32; if the result of the logical operation is the second result, the process proceeds to S33.

S32: a second set of bits in the first bit stream is inverted.

S33: a third set of bits in the first bit stream is inverted.

The first specific bit set, the second specific bit set and the third specific bit set comprise at least one bit. Generally, at least some of the bits in the second particular set of bits and the third particular set of bits are different.

The first bit stream after the inversion is completed can be output as a second bit stream.

For example, when the first bit stream is an 8-bit stream, the 0 th bit and the 1 st bit in the first bit stream may be subjected to an exclusive or operation. If the result of the exclusive-or operation is 1, which means that the 0 th bit and the 1 st bit in the first bit stream are different, and the probability that the logic values of the continuous multiple bits in the high bits in the first bit stream are the same is high, inverting the 4 th bit, the 5 th bit and the 7 th bit in the first bit stream; if the result of the exclusive or operation is 0, meaning that the 0 th bit and the 1 st bit in the first bit stream are the same and there is a high possibility that the logical values of consecutive bits in the lower bits in the first bit stream are the same, the 0 th bit, the 3 rd bit, the 5 th bit, and the 6 th bit in the first bit stream are inverted.

In another embodiment of the present invention, as shown in fig. 3, the method may comprise:

s35: and assigning a value to the third bit stream by using the first bit stream or the second bit stream.

S36: and performing logic operation or inversion on bits corresponding to at least part of the first specific bit set, the second specific bit set or the third specific bit set in the assigned third bit stream.

The main difference between this embodiment and the embodiment corresponding to fig. 2 is that a logical operation or an inversion operation is performed on the third bit stream. For example, a logical operation may be performed on a first set of bits in the first bitstream, then the first bitstream is assigned to the third bitstream, and then the third bitstream is inverted. Or firstly carrying out logic operation on the first specific bit set in the first bit stream, then carrying out inversion on one part of the second/third specific bit sets in the first bit stream to obtain a second bit stream, then assigning the second bit stream to the third bit stream, and then carrying out inversion on bits corresponding to the rest parts of the second/third specific bit sets in the third bit stream. In the last case, the inversion operation is divided into two steps, performed separately for the first and third bit streams. In other embodiments, the inversion operation may be performed on the first bit stream and the second bit stream, or the first, second, and third bit streams.

For example, when the first bit stream is an 8-bit stream, the 0 th bit and the 1 st bit in the first bit stream may be subjected to an exclusive or operation. If the result of the exclusive-or operation is 1, which means that the 0 th bit and the 1 st bit in the first bit stream are different, and the possibility that the logic values of the continuous multiple bits in the high bits in the first bit stream are the same is high, inverting the 4 th bit and the 7 th bit in the first bit stream; if the result of the exclusive or operation is 0, meaning that the 0 th bit and the 1 st bit in the first bit stream are the same and there is a high possibility that the logical values of consecutive bits in the lower bits in the first bit stream are the same, the 0 th bit, the 3 rd bit, and the 6 th bit in the first bit stream are inverted. The first bit stream is inverted for the first time to obtain a second bit stream, then the second bit stream is assigned to a third bit stream, and the 6 th bit (equivalent to the 5 th bit in the first/second bit streams) in the third bit stream is inverted (no matter whether the result of the exclusive-or operation is 0 or 1).

S4: and combining the output first bit stream or the second bit stream with the identification bits to form a third bit stream.

The number of bits of the flag bit may be 1 or more. Specifically, the identification bits may be directly inserted before, during, or after the first/second bit streams to form the third bit stream, or the identification bits may be inserted after at least a part of bits of the first/second bit streams are subjected to logic operation, or other combination manners may be adopted, which is not limited herein. In general, the combination of the identification bits and the first/second bit stream should not affect the encoding quality, i.e. the third bit stream still meets the preset quality criterion. To achieve this, the logical value of the identification bit may be different from the logical value of at least one of its adjacent bits (one or two bits) after its insertion. For example, an identification bit is inserted before the 0 th bit of the first/second bitstream, and a logical value of the identification bit is different from a logical value of the 0 th bit of the first/second bitstream.

As shown in fig. 4, in another embodiment of the present invention, the step may specifically include:

s41: if the output is the first bit stream, assigning the identification bits by using the bit bits of the first bit stream in a second assignment mode and combining the identification bits with the first bit stream; and if the output is the second bit stream, assigning the identification bit by utilizing the specific bit of the second bit stream in a first assignment mode, and combining the identification bit and the second bit stream.

The identification bits may be any bits in the first/second bit stream. In the third bit stream after combination, the identification bits may or may not be adjacent to the bits corresponding to the specific bits. The first assignment pattern is different from the second assignment pattern so that whether the third bit stream is quality-adjusted can be distinguished by the identification bit and the specific bit. For example, the first assignment manner may be one of direct assignment and reciprocal assignment, and the second assignment manner may be the other of direct assignment and reciprocal assignment. The receiving end can judge whether the received third bit stream is subjected to quality adjustment through the exclusive or result of the identification bit and the specific bit, so that different decoding modes can be selected.

In practical applications, the specific bit of the first/second bitstream may be directly assigned to the flag bit or assigned to the flag bit after being inverted, or other equivalent manners may be adopted, such as determining whether the logical value of the specific bit is 0/1, and setting the logical value of the flag bit according to the determination result and whether inversion is required.

For example, if the first bitstream is outputted, the logical value of the 0 th bit (i.e. the identification bit) of the third bitstream can be set to be equal to the inverted result of the 0 th bit of the first bitstream, wherein the 1 st bit and the subsequent bits of the third bitstream are obtained by assigning values to the 0 th bit and the subsequent bits of the first bitstream. The order between assignment and flag bit setting is not limited, and the negation result of the 0 th bit of the first bit stream can be assigned to the flag bit, and then the 0 th bit and the subsequent bits of the first bit stream are assigned to the 1 st bit and the subsequent bits of the third bit stream; or assigning the 0 th bit and the subsequent bits of the first bit stream to the 1 st bit and the subsequent bits of the third bit stream, and then assigning the inversion result of the 0 th bit of the first bit stream or the inversion result of the 1 st bit of the third bit stream to the identification bit.

If the output is the second bit stream, the logical value of the 0 th bit (i.e. the identification bit) of the third bit stream may be set to be equal to the 0 th bit of the second bit stream, wherein the 1 st bit and the subsequent bits of the third bit stream are obtained by assigning values to the 0 th bit and the subsequent bits of the second bit stream. The order between assignment and flag setting is not limited, and the 0 th bit of the second bit stream can be assigned to the flag first, and then the 0 th bit and the following bits of the second bit stream are assigned to the 1 st bit and the following bits of the third bit stream; or assigning the 0 th bit and the subsequent bits of the second bit stream to the 1 st bit and the subsequent bits of the third bit stream, and then assigning the 0 th bit of the second bit stream or the 1 st bit of the third bit stream to the identification bit.

In the above example, the logical value of the identification bit is set equal to the inverted result of the 0 th bit of the first bitstream or equal to the 0 th bit of the second bitstream. The opposite may actually be true, i.e. the logical value of the identification bit is set equal to bit 0 of the first bit stream or equal to the inverted result of bit 0 of the second bit stream.

By implementing the embodiment, in the encoding process, whether the first bit stream meets the preset quality standard is judged, the first bit stream which does not meet the quality standard is converted, the second bit stream is output, then the output first bit stream or the output second bit stream is combined with the identification bit to form the third bit stream, and the encoding quality of the second bit stream compared with the first bit stream after conversion is improved, so that the encoding quality of the third bit stream is ensured.

The complete encoding process is illustrated below with reference to the accompanying drawings.

As shown in fig. 5, in another embodiment of the present invention, the encoding method includes:

s101: a first bit stream bm [ 0-7 ] is obtained.

S102: it is judged whether or not the calculation result of the logical expression (1) is 1.

In the drawings, the term "equals" means "assigns.

If the calculation result of the logic expression (1) is 1, jumping to S103; if the calculation result of the logical expression (1) is 0, the process jumps to S107.

S103: judging whether the calculation result of XOR (bm [0 ~ 1]) is 1.

If the calculation result of XOR (bm [ 0-1 ]) is 1, jumping to S104; if the calculation result of XOR (bm [0 ~ 1]) is 0, then jump to S105.

S104: negating bm 4 and bm 7.

bm [ ] or bn [ ] front-represents the negation.

The remaining bits are unchanged to obtain a second bit stream, and jumping to S106.

S105: the values of bm < 0 >, bm < 3 > and bm < 6 > are inverted.

S106: the second bit stream is assigned to bits 1 to 8 of the third bit stream, the bit 6 (bn 6, equal to the bit 5 of the first and second bit streams) of the third bit stream is inverted, and the bit 0 of the second bit stream is assigned to the bit 0 (bn 0, as an identification bit) of the third bit stream.

Obtaining a third bit stream bn [0 ~ 8 ].

S107: and assigning the first bit stream to bits 1-8 of the third bit stream.

S108: the negation of the 0 th bit of the first bitstream (equal to the 1 st bit of the third bitstream) is assigned to the 0 th bit of the third bitstream (i.e., the identification bit).

Obtaining a third bit stream bn [0 ~ 8 ].

As shown in fig. 6, in another embodiment of the present invention, the encoding method includes:

s201: a first bit stream bm [ 0-7 ] is obtained.

S202: it is judged whether or not the calculation result of the logical expression (2) is 1.

In the drawings, the term "equals" means "assigns.

If the calculation result of the logic expression (2) is 1, jumping to S203; if the calculation result of the logical expression (2) is 0, the process jumps to S207.

S203: and assigning the first bit stream to bits 1-8 of the third bit stream.

S204: the negation of the 0 th bit of the first bitstream (equal to the 1 st bit of the third bitstream) is assigned to the 0 th bit of the third bitstream (i.e., the identification bit).

Obtaining a third bit stream bn [0 ~ 8 ].

S205: judging whether the calculation result of XOR (bm [0 ~ 1]) is 1.

If the calculation result of XOR (bm [ 0-1 ]) is 1, then S206 is skipped; if the calculation result of XOR (bm [0 ~ 1]) is 0, then jump to S207.

S206: negating bm 4 and bm 7.

bm [ ] or bn [ ] front-represents the negation.

The remaining bits are unchanged to obtain a second bit stream, and the process jumps to S208.

S207: the values of bm < 0 >, bm < 3 > and bm < 6 > are inverted.

S208: the second bit stream is assigned to bits 1 to 8 of the third bit stream, the bit 6 (bn 6, equal to the bit 5 of the first and second bit streams) of the third bit stream is inverted, and the bit 0 of the second bit stream is assigned to the bit 0 (bn 0, as an identification bit) of the third bit stream.

Obtaining a third bit stream bn [0 ~ 8 ].

As shown in fig. 7, in another embodiment of the present invention, the encoding method includes:

s301: a first bit stream bm [ 0-7 ] is obtained.

S302: it is judged whether or not the calculation result of the logical expression (1) is 1.

In the drawings, the term "equals" means "assigns.

If the calculation result of the logic expression (1) is 1, jumping to S303; if the calculation result of the logical expression (1) is 0, the process goes to S308.

S303: judging whether the calculation result of XOR (bm [0 ~ 1]) is 1.

If the calculation result of XOR (bm [ 0-1 ]) is 1, jumping to S304; if the calculation result of XOR (bm [0 ~ 1]) is 0, then S305 is skipped.

S304: negating bm 4 and bm 7.

bm [ ] or bn [ ] front-represents the negation.

Jumping to S306.

S305: the values of bm < 0 >, bm < 3 > and bm < 6 > are inverted.

Jumping to S306.

S306: negating bm 5.

The remaining bits are unchanged, resulting in a second bit stream.

S307: and assigning the negation result of the 0 th bit of the second bit stream to the 0 th bit (bn [0] as the identification bit) of the third bit stream, and assigning the second bit stream to the 1 st to 8 th bits of the third bit stream.

Obtaining a third bit stream bn [0 ~ 8 ].

S308: and assigning the first bit stream to bits 1-8 of the third bit stream.

S309: it is determined whether the 1 st bit of the third bitstream (equal to the 0 th bit of the first bitstream) is 1.

If the 1 st bit of the third bitstream is 1, jumping to S310; if the 1 st bit of the third bitstream is 0, the process jumps to S311.

S310: the 0 th bit (i.e., identification bit) of the third bitstream is set to 1.

Obtaining a third bit stream bn [0 ~ 8 ].

S311: the 0 th bit (i.e., identification bit) of the third bitstream is set to 0.

Obtaining a third bit stream bn [0 ~ 8 ].

As shown in fig. 8, in another embodiment of the present invention, the encoding method includes:

s401: a first bit stream bm [ 0-7 ] is obtained.

In the drawings, the term "equals" means "assigns.

S402: it is judged whether or not the calculation result of the logical expression (1) is 1.

If the calculation result of the logic expression (1) is 1, jumping to S403; if the calculation result of the logical expression (1) is 0, the process goes to S407.

S403: judging whether the calculation result of XOR (bm [0 ~ 1]) is 1.

If the calculation result of XOR (bm [ 0-1 ]) is 1, jumping to S404; if the calculation result of XOR (bm [0 ~ 1]) is 0, then S405 is skipped.

S404: the bm 4, bm 5 and bm 7 are inverted.

bm [ ] or bn [ ] front-represents the negation.

The remaining bits are unchanged to obtain a second bit stream, and the process jumps to S406.

S405: the inverses of bm < 0 >, bm < 3 >, bm < 5 > and bm < 6 >.

S406: and assigning the negation result of the 0 th bit of the second bit stream to the 0 th bit (bn [0] as the identification bit) of the third bit stream, and assigning the second bit stream to the 1 st to 8 th bits of the third bit stream.

Obtaining a third bit stream bn [0 ~ 8 ].

S407: and assigning the first bit stream to bits 1-8 of the third bit stream.

S408: it is determined whether the 1 st bit of the third bitstream (equal to the 0 th bit of the first bitstream) is 1.

If the 1 st bit of the third bit stream is 1, jumping to S409; if the 1 st bit of the third bitstream is 0, the process jumps to S410.

S409: the 0 th bit (i.e., identification bit) of the third bitstream is set to 1.

Obtaining a third bit stream bn [0 ~ 8 ].

S410: the 0 th bit (i.e., identification bit) of the third bitstream is set to 0.

Obtaining a third bit stream bn [0 ~ 8 ].

As shown in fig. 9, an embodiment of the encoding apparatus of the present invention includes: a processor 110. In addition, the encoding apparatus may further include a memory (not shown).

The processor 110 controls the operation of the encoding device, and the processor 110 may also be referred to as a Central Processing Unit (CPU). The processor 110 may be an integrated circuit chip having the processing capability of signal sequences. The processor 110 may also be a general purpose processor, a digital signal sequence processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

The processor 110 is used to execute instructions to implement the methods provided by any embodiment and possible combinations of the encoding methods of the present invention.

As shown in fig. 10, an embodiment of the storage medium readable by the present invention includes a memory 210, and the memory 210 stores instructions that, when executed, implement the method provided by any embodiment and possible combination of the encoding method of the present invention.

The Memory 210 may include a Read-Only Memory (ROM), a Random Access Memory (RAM), a Flash Memory (Flash Memory), a hard disk, an optical disk, and the like.

In the embodiments provided in the present invention, it should be understood that the disclosed method and apparatus can be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the modules or units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may be physically included alone, or two or more units may be integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, a network device, or the like) or a processor (processor) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes performed by the present specification and drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.

Claims

1. A method of encoding, the method comprising:

obtaining a first bit stream, wherein the first bit stream is an 8-bit stream;

performing quality judgment on the first bit stream; wherein the first bitstream is determined to meet the quality criterion if the first bitstream meets the following conditions simultaneously:

at least two bits of the 4 th bit to the 7 th bit in the first bit stream have different logic values;

at least two bits of the 1 st bit to the 6 th bit in the first bit stream have different logic values;

at least two bits of the 0 th bit to the 5 th bit in the first bit stream have different logic values;

and at least one of the following sub-conditions is satisfied:

the 6 th bit and the 7 th bit in the first bit stream have different logic values;

the logical values of the 0 th bit to the 4 th bit in the first bit stream are different; or

The logic values of the 6 th bit and the 7 th bit in the first bit stream are the same, and the logic values of the 0 th bit to the 4 th bit are the same and are the same as the logic values of the 6 th bit and the 7 th bit;

if the first bit stream meets a preset quality standard, outputting the first bit stream;

if the first bit stream does not meet the preset quality standard, converting the first bit stream, and outputting a second bit stream, specifically including: performing a logical operation on a first bit set in the first bit stream, and if a result of the logical operation is a first result, performing an inversion on a second bit set in the first bit stream to form and output the second bit stream; if the result of the logical operation is a second result, inverting a third bit set in the first bit stream to form and output the second bit stream;

combining the output first bit stream or the output second bit stream with identification bits to form a third bit stream, specifically including: assigning a value to the third bit stream by using the first bit stream or the second bit stream, and negating bits corresponding to at least part of the first bit set, the second bit set, or the third bit set in the assigned third bit stream; if the output is the second bit stream, assigning the identification bit by using a specific bit of the second bit stream in a first assignment mode, and combining the identification bit and the second bit stream; if the output is the first bit stream, assigning the identification bits by using the bit bits of the first bit stream in a second assignment mode and combining the identification bits and the first bit stream;

the first assignment mode is one of direct assignment and inverse assignment, and the second assignment mode is the other of direct assignment and inverse assignment, so that whether the third bit stream is subjected to quality adjustment can be distinguished through the identification bit and the specific bit.

2. The method of claim 1, wherein the step of determining the quality of the first bit stream comprises:

the first bitstream satisfies the quality criterion if a calculation of the following logical expression is equal to 1:

AND(XOR(bm[4～7]),XOR(bm[1～6]),XOR(bm[0～5]),OR(NAND(bm[6～7]),OR(bm[0～4])),OR(OR(bm[6～7]),NAND(bm[0～4])))

wherein, AND is AND operation, NAND is NAND operation, OR is OR operation, XOR is XOR operation; bm [ i-j ] is the ith through jth bits of the first bitstream.

3. The method of claim 1, wherein the first bit stream is an 8-bit stream;

the converting the first bit stream and outputting a second bit stream includes:

performing an exclusive-or operation on a 0 th bit and a 1 st bit in the first bit stream;

if the result of the exclusive-or operation is 1, inverting the 4 th bit, the 5 th bit and the 7 th bit in the first bit stream;

and if the result of the exclusive-or operation is 0, inverting the 0 th bit, the 3 rd bit, the 5 th bit and the 6 th bit in the first bit stream.

4. The method of claim 3, wherein the step of assigning the value to the third bit stream using the first bit stream or the second bit stream further comprises:

assigning the 1 st bit and the subsequent bits of the third bit stream by using the 0 th bit and the subsequent bits of the second bit stream;

wherein inverting the 0 th bit, the 3 rd bit, the 4 th bit, the 6 th bit, and the 7 th bit of the first bitstream is to operate on the first bitstream, and inverting the 5 th bit of the first bitstream is to operate on the 6 th bit of the third bitstream.

5. The method of claim 1, wherein the step of applying the coating comprises applying a coating to the substrate

If the output is the second bit stream, the step of assigning the identification bit by using the specific bit of the second bit stream in a first assignment mode comprises the following steps:

setting the logic value of the 0 th bit of the third bit stream to be equal to the 0 th bit of the second bit stream, wherein the 1 st bit and the subsequent bits of the third bit stream are obtained by converting and assigning the 0 th bit and the subsequent bits of the second bit stream.

6. The method of claim 5, wherein the step of applying the coating comprises applying a coating to the substrate

If the output is the first bit stream, the step of assigning the identification bits by using the bit bits of the first bit stream in a second assignment mode comprises the following steps:

and setting the logic value of the 0 th bit of the third bit stream to be equal to the inverted result of the 0 th bit of the first bit stream, wherein the 1 st bit and the subsequent bits of the third bit stream are obtained by assigning the 0 th bit and the subsequent bits of the first bit stream.

7. An encoding device, comprising a processor to execute instructions to implement the method of any one of claims 1-6.

8. A readable storage medium storing instructions that, when executed, implement the method of any one of claims 1-6.