CN108777606B - Decoding method, apparatus and readable storage medium - Google Patents
Decoding method, apparatus and readable storage medium Download PDFInfo
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- CN108777606B CN108777606B CN201810539654.XA CN201810539654A CN108777606B CN 108777606 B CN108777606 B CN 108777606B CN 201810539654 A CN201810539654 A CN 201810539654A CN 108777606 B CN108777606 B CN 108777606B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0041—Arrangements at the transmitter end
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
- H04L1/0033—Systems modifying transmission characteristics according to link quality, e.g. power backoff arrangements specific to the transmitter
Abstract
The invention discloses a decoding method, which comprises the following steps: carrying out XOR logic operation on the specific bit and the identification bit in the first bit stream to judge whether the original bit stream is subjected to quality adjustment; if the operation result indicates that the original bit stream is subjected to quality adjustment, converting the first bit stream into a third bit stream, and if the operation result indicates that the original bit stream is not subjected to quality adjustment, directly outputting the first bit stream; and ignoring the identification bits in the output first bit stream or the output third bit stream to form a second bit stream. The invention also discloses a decoding device and a readable storage medium. By the mode, the invention can reduce the error rate and save a memory for storing the code table.
Description
Technical Field
The present invention relates to the field of data transmission, and in particular, to a decoding method, device and readable storage medium.
Background
In serial data transmission, transmitted data can be encoded into a code stream containing a clock frequency component, so that a receiving end can extract clock synchronization information from the code stream, and the clock synchronization information can ensure that the receiving end can regenerate original data from a received signal according to a correct time sequence, namely successful decoding.
4B5B is a common code, and converts input 4-bit data into 5 bits and outputs the 5 bits. Generally, the encoding and decoding operations are completed by searching a designed code table, so that additional memories are required for storing the code table at both the transmitting end and the receiving end. 4B5B encoding may also degrade the encoding quality, i.e., the number of consecutive bits with the same logical value is excessive, for example, when 8 bits of data are transmitted using 4B5B encoding. The low-quality codes are not beneficial to a receiving end to extract clock synchronization information, larger direct current components are brought, and the error rate is improved.
Disclosure of Invention
The invention mainly solves the technical problem of providing a decoding method, a decoding device and a readable storage medium, which can solve the problem that encoding quality is possibly reduced in encoding in the prior art.
In order to solve the above technical problem, the present invention provides a decoding method, including: carrying out XOR logic operation on the specific bit and the identification bit in the first bit stream to judge whether the original bit stream is subjected to quality adjustment; if the operation result indicates that the original bit stream is subjected to quality adjustment, converting the first bit stream into a third bit stream, and if the operation result indicates that the original bit stream is not subjected to quality adjustment, directly outputting the first bit stream; and ignoring the identification bits in the output first bit stream or the output third bit stream to form a second bit stream.
In order to solve the above technical problem, the present invention provides a decoding apparatus, which includes a processor for executing instructions to implement the foregoing method.
In order to solve the above technical problem, the present invention provides a readable storage medium storing instructions which, when executed, implement the foregoing method.
The invention has the beneficial effects that: carrying out XOR logic operation on the specific bit and the identification bit in the first bit stream to judge whether the original bit stream is subjected to quality adjustment; if the operation result indicates that the original bit stream is subjected to quality adjustment, converting the first bit stream into a third bit stream, and if the operation result indicates that the original bit stream is not subjected to quality adjustment, directly outputting the first bit stream; and ignoring the identification bits in the output first bit stream or the output third bit stream to form a second bit stream. The first bit stream is a received decoded bit stream, whether the original bit stream is subjected to quality adjustment needs to be judged in the decoding process, and the quality adjustment is carried out on the original bit stream with the coding quality not meeting the requirement in the coding process so as to guarantee the quality of the first bit stream, so that the error rate is reduced; meanwhile, the decoding is finished without a code table, and a memory for storing the code table is saved.
Drawings
FIG. 1 is a flow chart of an embodiment of a decoding method of the present invention;
FIG. 2 is a flowchart illustrating the step S2 in FIG. 1 according to an embodiment of the decoding method of the present invention;
FIG. 3 is a flowchart illustrating a decoding method according to another embodiment of the present invention;
FIG. 4 is a flowchart illustrating a decoding method according to another embodiment of the present invention;
FIG. 5 is a schematic structural diagram of an embodiment of a decoding apparatus according to the present invention;
FIG. 6 is a schematic structural diagram of an embodiment of a readable storage medium of the present invention.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and examples. Non-conflicting ones of the following embodiments may be combined with each other.
As shown in fig. 1, an embodiment of the decoding method of the present invention includes:
s1: and carrying out exclusive-or logic operation on the bit and the identification bit in the first bit stream to judge whether the original bit stream is subjected to quality adjustment.
The first bit stream may be undecoded data, and the number of bits may depend on actual transmission requirements, e.g., 9 bits, 17 bits, etc. The first bit stream has a greater number of bits than the original bit stream. In the encoding process, it is necessary to determine whether the quality of the original bit stream meets the quality standard, and if not, the quality of the original bit stream needs to be adjusted. The quality criterion may relate to consecutive bits of the original bit stream having the same logical value. Generally, the number of consecutive bits in the original bitstream that satisfy the quality criterion that have the same logical value does not exceed a threshold, which may be related in size to the number of bits in the original bitstream, e.g., half the number of bits in the original bitstream plus a positive integer.
The first bit stream includes identification bits and specific bits for distinguishing whether the original bit stream has been quality-adjusted. The number of identification bits and specific bits and the position in the first bit stream are not limited. For example, the first bit stream is a 9-bit stream, the specific bit may be a 1 st bit, and the identification bit may be a 0 th bit. The xor logic operation may be performed on the specific bit and the identification bit in the first bit stream to obtain an operation result, and then whether the original bit stream is subjected to the quality adjustment is determined according to the operation result.
Specifically, if the operation result is not equal to 1 (i.e., equal to 0), which means that the specific bit and the flag bit are the same, it is determined that the original bitstream has undergone quality adjustment, and if the operation result is equal to 1, which means that the specific bit and the flag bit are different, it is determined that the original bitstream has not undergone quality adjustment.
Of course, the other way around is that if the operation result is equal to 1, the original bitstream is determined to have undergone quality adjustment, and if the operation result is not equal to 1, the original bitstream is determined not to have undergone quality adjustment.
In practical application, the corresponding relationship between which operation result is selected and the judgment result of whether the quality is adjusted or not can be determined by the assignment mode of the identification bit selected by the sending end in the encoding process.
If the operation result indicates that the original bit stream is subjected to quality adjustment, jumping to S2; if the operation result indicates that the original bitstream has not been quality-adjusted, the process goes to S3.
S2: the first bitstream is converted into a third bitstream.
Generally, the conversion process corresponds to a quality adjustment process in the encoding process of the transmitting end, so that a part of bits in the quality-adjusted first bit stream is restored to the original bit stream.
As shown in fig. 2, in an embodiment of the present invention, the step may specifically include:
s21: and performing first conversion on the first bit stream to obtain a first conversion result.
The first conversion may include inverting a first set of bits in the first bit stream.
S22: and judging whether the first conversion result meets the data conversion standard or not.
If the first conversion result meets the data conversion standard, jumping to S23; if the first conversion result does not satisfy the data conversion criterion, it jumps to S24.
S23: the first conversion result is directly output as the third bit stream.
S24: and performing second conversion on the first conversion result to obtain a second conversion result, and outputting the second conversion result as a third bit stream.
The second conversion may include inverting a second set of bits in the first conversion result, the first set of bits being different from the second set of bits. The first set of bits and the second set of bits being different means that at least one of the bits comprised by the two sets of bits is different. And then jumps to S4.
A specific conversion process is illustrated. The first bit stream is a 9-bit stream, and a first set of bits in the first bit stream is inverted to obtain a first conversion result, wherein the first set of bits includes bits 5, 6 and 8. And then judging whether the first conversion result meets the data conversion standard.
Specifically, if the first conversion result satisfies at least one of the following conditions, it is determined that the first conversion result satisfies the data conversion criterion:
a. the logic values of the 5 th bit to the 8 th bit in the first conversion result are the same;
b. the logic values of the 2 nd bit to the 7 th bit in the first conversion result are the same;
c. the logical values of the 1 st bit to the 6 th bit in the first conversion result are the same.
Optionally, the above determination manner may be converted into a determination of a calculation result of the following logical expression:
NAND(NAND(bn[5～8]),NAND(bn[2～7]),NAND(bn[1～6]),OR(bn[5～8]),OR(bn[2～7]),OR(bn[1～6]))
where NAND is NAND operation, OR is OR operation, and bn [ i-j ] are ith to jth bits of the first conversion result.
In the formula (1), when the 5 th bit to the 8 th bit of the first conversion result are all 1, NAND (bn [ 5-8 ]) is 0.
When the 2 nd bit to the 7 th bit of the first conversion result are all 1, NAND (bn 2-7) is 0.
When the 1 st bit to the 6 th bit of the first conversion result are all 1, NAND (bn [ 1-6 ]) is 0.
When the 5 th bit to the 8 th bit of the first conversion result are all 0, OR (bn 5-8) is 0.
When the 2 nd bit to the 7 th bit of the first conversion result are all 0, OR (bn 2-7) is 0.
When the 1 st bit to the 6 th bit of the first conversion result are all 0, OR (bn [ 1-6 ]) is 0.
If the calculation result of the formula (1) is 1, it means that at least one of NAND (bn [ 5-8 ]), NAND (bn [ 2-7 ]), NAND (bn [ 1-6 ]), OR (bn [ 5-8 ]), OR (bn [ 2-7 ]), OR (bn [ 1-6 ]) is 0, and the first conversion result satisfies at least one of the conditions a, b, c, and d in combination with the above condition that each logical expression is 0, the first conversion result satisfies the data conversion standard. If the calculation result of the equation (1) is 0, the first conversion result does not satisfy the data conversion criterion.
Other equivalent logic formulas may be used for the determination, such as determining whether the operation result of AND (XOR (bn 5-8, XOR (bn 2-7, or XOR (bn 1-6)) is 1, if so, the first conversion result does not satisfy the data conversion criterion, AND if so, the first conversion result satisfies the data conversion criterion.
If the first conversion result meets the data conversion standard, directly outputting the first conversion result as a third bit stream; and if the first conversion result meets the data conversion standard, inverting a second bit set in the first conversion result to obtain a second conversion result, wherein the second bit set comprises 1 st, 4 th, 5 th, 7 th and 8 th bits, and outputting the second conversion result as a third bit stream. The third bit stream is still a 9-bit stream and the flag bit is still the 0 th bit.
S3: the first bit stream is directly output.
A jump is made to S4.
S4: and ignoring the identification bits in the output first bit stream or the output third bit stream to form a second bit stream.
If the original bit stream is not subjected to quality adjustment, the directly output first bit stream is a combination of the original bit stream and the identification bit; and if the original bit stream is subjected to quality adjustment, converting the first bit stream and outputting a third bit stream which is a combination of the original bit stream and the identification bit. The second bit stream, i.e. the original bit stream, can be formed by ignoring the identification bits in the output first bit stream or third bit stream, thereby completing the decoding.
By implementing the embodiment, the xor logical operation is performed on the specific bit and the identification bit in the first bit stream to determine whether the original bit stream is subjected to quality adjustment; if the operation result indicates that the original bit stream is subjected to quality adjustment, converting the first bit stream into a third bit stream, and if the operation result indicates that the original bit stream is not subjected to quality adjustment, directly outputting the first bit stream; and ignoring the identification bits in the output first bit stream or the output third bit stream to form a second bit stream. The first bit stream is a received bit stream after encoding, whether the original bit stream is subjected to quality adjustment needs to be judged in the decoding process, and the quality adjustment is carried out on the original bit stream with the encoding quality not meeting the requirement in the encoding process so as to guarantee the quality of the first bit stream, so that the error rate is reduced; meanwhile, the decoding is finished without a code table, and a memory for storing the code table is saved.
The complete decoding process is illustrated below with reference to the figures.
In another embodiment of the present invention, as shown in fig. 3, the decoding method includes:
s101: a first bit stream bn [ 0-8 ] is obtained.
S102: it is determined whether the result of the exclusive or operation of the 0 th bit (identification bit) and the 1 st bit (specific bit) in the first bit stream is 1.
In the drawings, the term "equals" means "assigns.
If the operation result is 0, jumping to S103; if the operation result is 1, the process proceeds to S106.
S103: the negation of bn 5, bn 6 and bn 8 is performed.
bn before indicates negation. A first conversion result is obtained.
S104: it is judged whether or not the calculation result of the logical expression (1) is 1.
If the calculation result of the logic expression (1) is 1, outputting the first conversion result as a third bit stream, and jumping to S106; if the calculation result of the logical expression (1) is 0, the process jumps to S105.
S105: the inverses of bn 1, bn 4, bn 5, bn 7 and bn 8.
The other bits are unchanged, and a second conversion result is obtained and is output as a third bit stream, and S106 is skipped.
S106: the bn 0 (identification bit) is ignored, and the bn 1-8 are assigned to the second bit stream bm 0-7.
The obtained second bit stream bm [ 0-7 ] is the original bit stream, and the decoding is completed.
As shown in fig. 4, in another embodiment of the present invention, the decoding method includes:
s201: a first bit stream bn [ 0-8 ] is obtained.
S202: it is determined whether the result of the exclusive or operation of the 0 th bit (identification bit) and the 1 st bit (specific bit) in the first bit stream is 1.
In the drawings, the term "equals" means "assigns.
If the operation result is 1, jumping to S203; if the operation result is 0, the process proceeds to S206.
S203: the negation of bn 5, bn 6 and bn 8 is performed.
bn before indicates negation. A first conversion result is obtained.
S204: it is judged whether or not the calculation result of the logical expression (1) is 1.
If the calculation result of the logic expression (1) is 1, outputting the first conversion result as a third bit stream, and jumping to S206; if the calculation result of the logical expression (1) is 0, the process jumps to S205.
S205: the inverses of bn 1, bn 4, bn 5, bn 7 and bn 8.
The remaining bits are unchanged, and a second conversion result is obtained and output as a third bit stream, and the process jumps to S206.
S206: the bn 0 (identification bit) is ignored, and the bn 1-8 are assigned to the second bit stream bm 0-7.
The obtained second bit stream bm [ 0-7 ] is the original bit stream, and the decoding is completed.
As shown in fig. 5, an embodiment of the decoding apparatus of the present invention includes: a processor 110. In addition, the decoding apparatus may further include a memory (not shown).
The processor 110 controls the operation of the decoding apparatus, and the processor 110 may also be referred to as a CPU (Central Processing Unit). The processor 110 may be an integrated circuit chip having the processing capability of signal sequences. The processor 110 may also be a general purpose processor, a digital signal sequence processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The processor 110 is used to execute instructions to implement the methods provided by any embodiment and possible combinations of the decoding methods of the present invention.
As shown in fig. 6, an embodiment of the storage medium readable by the present invention includes a memory 210, and the memory 210 stores instructions that, when executed, implement the method provided by any embodiment and possible combination of the decoding method of the present invention.
The Memory 210 may include a Read-Only Memory (ROM), a Random Access Memory (RAM), a Flash Memory (Flash Memory), a hard disk, an optical disk, and the like.
In the embodiments provided in the present invention, it should be understood that the disclosed method and apparatus can be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the modules or units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may be physically included alone, or two or more units may be integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, a network device, or the like) or a processor (processor) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes performed by the present specification and drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (9)
1. A method of decoding, the method comprising:
carrying out XOR logic operation on the specific bit and the identification bit in the first bit stream to judge whether the original bit stream is subjected to quality adjustment;
if the operation result indicates that the original bit stream is subjected to the quality adjustment, converting the first bit stream into a third bit stream, and if the operation result indicates that the original bit stream is not subjected to the quality adjustment, directly outputting the first bit stream;
ignoring the identification bits in the outputted first or third bit stream to form a second bit stream;
wherein the converting the first bitstream into a third bitstream comprises: performing a first conversion on the first bit stream to obtain a first conversion result; judging whether the first conversion result meets a data conversion standard or not; if the data conversion standard is met, directly outputting the first conversion result as the third bit stream, and if the data conversion standard is not met, performing second conversion on the first conversion result to obtain a second conversion result, and outputting the second conversion result as the third bit stream;
wherein the number of bits of the first conversion result is 9, and the determining whether the first conversion result satisfies a data conversion criterion includes: determining that the first conversion result satisfies the data conversion criterion if the first conversion result satisfies at least one of the following conditions: the logic values of the 5 th bit to the 8 th bit in the first conversion result are the same; the logic values of the 2 nd bit to the 7 th bit in the first conversion result are the same; the logic values of the 1 st bit to the 6 th bit in the first conversion result are the same.
2. The method of claim 1, wherein performing an exclusive-or operation on the bit and the identification bit in the first bit stream to determine whether the original bit stream is quality-adjusted comprises:
performing the exclusive-or logic operation on the bit and the identification bit in the first bit stream to obtain the operation result;
and if the operation result is not equal to 1, determining that the original bit stream is subjected to the quality adjustment, and if the operation result is equal to 1, determining that the original bit stream is not subjected to the quality adjustment.
3. The method of claim 1, wherein performing an exclusive-or operation on the bit and the identification bit in the first bit stream to determine whether the original bit stream is quality-adjusted comprises:
performing the exclusive-or logic operation on the bit and the identification bit in the first bit stream to obtain the operation result;
and if the operation result is equal to 1, determining that the original bit stream is subjected to the quality adjustment, and if the operation result is not equal to 1, determining that the original bit stream is not subjected to the quality adjustment.
4. The method of claim 1,
the first converting comprises inverting a first set of bits in the first bitstream, the second converting comprises inverting a second set of bits in the first conversion result, the first set of bits being different from the second set of bits.
5. The method of claim 4, wherein the first bit stream and the first conversion result each have 9 bits, wherein the first set of bits comprises 5 th, 6 th, and 8 th bits, and wherein the second set of bits comprises 1 st, 4 th, 5 th, 7 th, and 8 th bits.
6. The method of claim 1, wherein the first conversion result has a bit number of 9, and wherein the determining whether the first conversion result satisfies a data conversion criterion comprises:
determining that the first conversion result satisfies the data conversion criterion if the calculation result of the following logical expression is equal to 1:
NAND(NAND(bn[5~8]),NAND(bn[2~7]),NAND(bn[1~6]),OR(bn[5~8]),OR(bn[2~7]),OR(bn[1~6]))
wherein NAND is NAND operation, OR is OR operation, bn [ i-j ] is ith to jth bits of the first conversion result.
7. The method of claim 1, wherein the first bit stream and the third bit stream are both 9-bit streams, wherein the bit in the first bit stream is a 1 st bit, and wherein the identification bit in the first bit stream and the third bit stream is a 0 th bit.
8. A decoding device comprising a processor for executing instructions to implement the method of any of claims 1-7.
9. A readable storage medium storing instructions that, when executed, implement the method of any one of claims 1-7.
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| CN110086575B (en) * | 2019-05-06 | 2021-10-08 | Tcl华星光电技术有限公司 | Encoding method, decoding method, related device and storage medium |
| CN112492386A (en) * | 2020-11-09 | 2021-03-12 | Tcl华星光电技术有限公司 | Decoding method, decoding device and readable storage medium |
| CN112929673B (en) * | 2021-01-19 | 2022-04-01 | Tcl华星光电技术有限公司 | Decoding method, decoding apparatus, and readable storage medium |
| CN112953681B (en) * | 2021-02-20 | 2022-03-29 | Tcl华星光电技术有限公司 | Decoding method, decoding apparatus, and computer-readable storage medium |
| WO2023028966A1 (en) * | 2021-09-02 | 2023-03-09 | 北京精雕科技集团有限公司 | Single-code channel absolute position measurement apparatus |
| CN113447051B (en) * | 2021-09-02 | 2021-12-07 | 北京精雕科技集团有限公司 | Single code channel absolute position measuring device |
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Address after: No.9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Applicant after: TCL Huaxing Photoelectric Technology Co.,Ltd. Address before: No.9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Applicant before: Shenzhen China Star Optoelectronics Technology Co.,Ltd. |
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| GR01 | Patent grant | ||
| GR01 | Patent grant |